On Fri, 2020-03-20 at 16:17 +1100, Jordan Niethe wrote:
> Currently unsigned ints are used to represent instructions on powerpc.
> This has worked well as instructions have always been 4 byte words.
> However, a future ISA version will introduce some changes to
> instructions that mean this scheme
This completes the move of the stray hunk. Also fixes an irq tracer
bug, returning to irqs-disabled context should not trace_hardirqs_on().
Signed-off-by: Nicholas Piggin
---
arch/powerpc/include/asm/asm-prototypes.h | 2 ++
arch/powerpc/kernel/syscall_64.c | 1 -
2 files changed, 2
Jordan Niethe's on March 20, 2020 3:18 pm:
> In preparation for an instruction data type that can not be directly
> used with the '==' operator use functions for checking equality and
> nullity.
>
> Signed-off-by: Jordan Niethe
> ---
> arch/powerpc/kernel/optprobes.c | 2 +-
>
Jordan Niethe's on March 20, 2020 3:18 pm:
> For powerpc64, redefine the ppc_inst type so both word and prefixed
> instructions can be represented. On powerpc32 the type will remain the
> same. Update places which had assumed instructions to be 4 bytes long.
>
> Signed-off-by: Jordan Niethe
>
Haren Myneni writes:
> On power9, userspace can send GZIP compression requests directly to NX
> once kernel establishes NX channel / window with VAS. This patch provides
> user space API which allows user space to establish channel using open
> VAS_TX_WIN_OPEN ioctl, mmap and close operations.
>
On Mon, Mar 23, 2020 at 09:37:05AM +0100, Christoph Hellwig wrote:
> > > + /*
> > > + * Allows IOMMU drivers to bypass dynamic translations if the DMA mask
> > > + * is large enough.
> > > + */
> > > + if (dev->dma_ops_bypass) {
> > > + if (min_not_zero(dev->coherent_dma_mask,
On Fri, 2020-03-20 at 16:18 +1100, Jordan Niethe wrote:
> This adds emulation support for the following prefixed integer
> load/stores:
> * Prefixed Load Byte and Zero (plbz)
> * Prefixed Load Halfword and Zero (plhz)
> * Prefixed Load Halfword Algebraic (plha)
> * Prefixed Load Word and
On Mon, Mar 23, 2020 at 5:27 PM Nicholas Piggin wrote:
>
> Jordan Niethe's on March 20, 2020 3:17 pm:
> > Currently unsigned ints are used to represent instructions on powerpc.
> > This has worked well as instructions have always been 4 byte words.
> > However, a future ISA version will introduce
On Mon, Mar 23, 2020 at 5:05 PM Balamuruhan S wrote:
>
> On Fri, 2020-03-20 at 16:17 +1100, Jordan Niethe wrote:
> > To execute an instruction out of line after a breakpoint, the NIP is
> > set
> > to the address of struct bpt::instr. Here a copy of the instruction
> > that
> > was replaced with
On Mon, Mar 23, 2020 at 6:09 PM Nicholas Piggin wrote:
>
> Jordan Niethe's on March 20, 2020 3:18 pm:
> > Alignment interrupts can be caused by prefixed instructions accessing
> > memory. Prefixed instructions are not permitted to cross 64-byte
> > boundaries. If they do the alignment interrupt
Jordan Niethe's on March 20, 2020 3:17 pm:
> To execute an instruction out of line after a breakpoint, the NIP is set
> to the address of struct bpt::instr. Here a copy of the instruction that
> was replaced with a breakpoint is kept, along with a trap so normal flow
> can be resumed after XOLing.
On Sun, Mar 22, 2020 at 09:05:37PM -0700, Haren Myneni wrote:
>
> Changes to probe GZIP device-tree nodes, open RX windows and setup
> GZIP compression type. No plans to provide GZIP usage in kernel right
> now, but this patch enables GZIP for user space usage.
>
> Signed-off-by: Haren Myneni
>
Jordan Niethe's on March 20, 2020 3:18 pm:
> Alignment interrupts can be caused by prefixed instructions accessing
> memory. Prefixed instructions are not permitted to cross 64-byte
> boundaries. If they do the alignment interrupt is invoked with SRR1
> BOUNDARY bit set. If this occurs send a
At the moment IODA2 systems do 64bit DMA by bypassing IOMMU which
allows mapping PCI space to system space at fixed offset (1<<59).
The bypass is controlled via the "iommu" kernel parameter.
This adds a "iommu_bypass" mode which maps PCI space to system space
using an actual TCE table with the
This moves code to make the next patches look simpler. In particular:
1. Separate locals declaration as we will be allocating a smaller DMA
window if a TVE1_4GB option (allows a huge DMA windows at 4GB) is enabled;
2. Pass the bypass offset directly to pnv_pci_ioda2_create_table()
as it is the
Now the minimum allocation size for a TCE table level is PAGE_SIZE (64k)
as this is the minimum for alloc_pages(). The limit was set in POWER8
where we did not have sparse RAM so we did not need sparse TCE tables.
On POWER9 we have gaps in the phys address space for which using multi
level TCE
We are about to allow another location for the second DMA window and
we will need to advertise it outside of the powernv platform code.
This moves bypass base address to iommu_table_group so drivers such as
VFIO SPAPR TCE can see it.
Signed-off-by: Alexey Kardashevskiy
---
On Mon, Mar 23, 2020 at 12:28:34PM +1100, Alexey Kardashevskiy wrote:
[full quote deleted, please follow proper quoting rules]
> > +static bool dma_alloc_direct(struct device *dev, const struct dma_map_ops
> > *ops)
> > +{
> > + if (!ops)
> > + return true;
> > +
> > + /*
> > +
On Mon, Mar 23, 2020 at 5:40 PM Nicholas Piggin wrote:
>
> Jordan Niethe's on March 20, 2020 3:17 pm:
> > In preparation for using an instruction data type that can not be used
> > directly with the '&' operator, use a function to mask instructions.
>
> Hmm. ppc_inst_mask isn't such a good
Jordan Niethe's on March 20, 2020 3:17 pm:
> Currently unsigned ints are used to represent instructions on powerpc.
> This has worked well as instructions have always been 4 byte words.
> However, a future ISA version will introduce some changes to
> instructions that mean this scheme will no
Jordan Niethe's on March 20, 2020 3:18 pm:
> From: Alistair Popple
>
> Prefix instructions have their own FSCR bit which needs to enabled via
> a CPU feature. The kernel will save the FSCR for problem state but it
> needs to be enabled initially.
>
> If prefixed instructions are made
Jordan Niethe's on March 20, 2020 3:18 pm:
> Add the BOUNDARY SRR1 bit definition for when the cause of an alignment
> exception is a prefixed instruction that crosses a 64-byte boundary.
> Add the PREFIXED SRR1 bit definition for exceptions caused by prefixed
> instructions.
>
> Bit 35 of SRR1
Jordan Niethe's on March 20, 2020 3:18 pm:
> For powerpc64, redefine the ppc_inst type so both word and prefixed
> instructions can be represented. On powerpc32 the type will remain the
> same. Update places which had assumed instructions to be 4 bytes long.
>
> Signed-off-by: Jordan Niethe
>
IODA2 systems (POWER8/9) allow DMA windows at 2 fixed locations - 0 and
0x800...==1<<59, stored in TVT as TVE0/1. PHB4 on POWER9 has
a "TVT Select 'GTE4GB' Option" which allows mapping both windows at 0 and
selecting one based on IOBA address - accesses below 4GB go via TVE0 and
above
On 23/03/2020 19:37, Christoph Hellwig wrote:
> On Mon, Mar 23, 2020 at 12:28:34PM +1100, Alexey Kardashevskiy wrote:
>
> [full quote deleted, please follow proper quoting rules]
>
>>> +static bool dma_alloc_direct(struct device *dev, const struct dma_map_ops
>>> *ops)
>>> +{
>>> + if
On Sun, Mar 22, 2020 at 09:03:00PM -0700, Haren Myneni wrote:
>
> coproc entry is initialized during NX probe on power9, but not on P8.
> nx842_delete_coprocs() is used for both and frees receive window if it
> is allocated. Getting crash for rmmod on P8 since coproc->vas.rxwin
> is not
On Sun, Mar 22, 2020 at 09:03:50PM -0700, Haren Myneni wrote:
>
> Rename nx-842-powernv.c to nx-common-powernv.c to add code for setup
> and enable new GZIP compression type. The actual functionality is not
> changed in this patch.
>
> Signed-off-by: Haren Myneni
> ---
>
Jordan Niethe's on March 20, 2020 3:17 pm:
> In preparation for using an instruction data type that can not be used
> directly with the '&' operator, use a function to mask instructions.
Hmm. ppc_inst_mask isn't such a good interface I think. It takes a
ppc_inst and a mask, you would expect it to
On Sun, Mar 22, 2020 at 09:06:17PM -0700, Haren Myneni wrote:
>
> When window is opened, pid reference is taken for user space
> windows. Not needed for kernel windows. So remove 'pid' in
> vas_tx_win_attr struct.
>
> Signed-off-by: Haren Myneni
> ---
> arch/powerpc/include/asm/vas.h|
Here is an attempt to support bigger DMA space for devices
supporting DMA masks less than 59 bits (GPUs come into mind
first). POWER9 PHBs have an option to map 2 windows at 0
and select a windows based on DMA address being below or above
4GB.
This adds the "iommu=iommu_bypass" kernel parameter
On 3/19/20 7:14 AM, Haren Myneni wrote:
>
> Alloc IRQ and get trigger port address for each VAS instance. Kernel
> register this IRQ per VAS instance and sets this port for each send
> window. NX interrupts the kernel when it sees page fault.
I don't understand why this is not done by the OPAL
On Mon, Mar 23, 2020 at 5:46 PM Nicholas Piggin wrote:
>
> Jordan Niethe's on March 20, 2020 3:18 pm:
> > In preparation for an instruction data type that can not be directly
> > used with the '==' operator use functions for checking equality and
> > nullity.
> >
> > Signed-off-by: Jordan Niethe
Jordan Niethe's on March 23, 2020 7:28 pm:
> On Mon, Mar 23, 2020 at 5:27 PM Nicholas Piggin wrote:
>>
>> Jordan Niethe's on March 20, 2020 3:17 pm:
>> > Currently unsigned ints are used to represent instructions on powerpc.
>> > This has worked well as instructions have always been 4 byte words.
On Fri, 2020-03-20 at 16:17 +1100, Jordan Niethe wrote:
> To execute an instruction out of line after a breakpoint, the NIP is
> set
> to the address of struct bpt::instr. Here a copy of the instruction
> that
> was replaced with a breakpoint is kept, along with a trap so normal
> flow
> can be
Jordan Niethe's on March 20, 2020 3:17 pm:
> For modifying instructions in xmon, patch_instruction() can serve the
> same role that store_inst() is performing with the advantage of not
> being specific to xmon. In some places patch_instruction() is already
> being using followed by store_inst().
Jordan Niethe's on March 20, 2020 3:17 pm:
> A future revision of the ISA will introduce prefixed instructions. A
> prefixed instruction is composed of a 4-byte prefix followed by a
> 4-byte suffix.
>
> All prefixes have the major opcode 1. A prefix will never be a valid
> word instruction. A
Jordan Niethe's on March 20, 2020 3:17 pm:
> In preparation for instructions having a more complex data type start
> using a macro, PPC_INST(), for making an instruction out of a u32.
> Currently this does nothing, but it will allow for creating a data type
> that can represent prefixed
On Sun, Mar 22, 2020 at 09:04:47PM -0700, Haren Myneni wrote:
>
> Make setup and enable code generic to support new GZIP compression type.
> Changed nx842 reference to nx and moved some code to new functions.
> Functionality is not changed except sparse warning fix - setting NULL
> instead of 0
Jordan Niethe's on March 20, 2020 3:18 pm:
> Prefixed instructions will mean there are instructions of different
> length. As a result dereferencing a pointer to an instruction will not
> necessarily give the desired result. Introduce a function for reading
> instructions from memory into the
We are about to add an additional offset within a TCE table which is
going to increase the size of the window, prepare for this.
This should cause no behavioral change.
Signed-off-by: Alexey Kardashevskiy
---
arch/powerpc/include/asm/iommu.h | 1 +
arch/powerpc/platforms/powernv/pci.h
Haren Myneni's on March 7, 2020 10:39 am:
>
> Power9 introduced Virtual Accelerator Switchboard (VAS) which allows
> userspace to communicate with Nest Accelerator (NX) directly. But
> kernel has to establish channel to NX for userspace. This document
> describes user space API that application
On Mon, 2020-03-23 at 18:00 +1000, Nicholas Piggin wrote:
> Jordan Niethe's on March 20, 2020 3:18 pm:
> > Prefixed instructions will mean there are instructions of different
> > length. As a result dereferencing a pointer to an instruction will not
> > necessarily give the desired result.
On 3/19/20 7:12 AM, Haren Myneni wrote:
>
> This function allocates IRQ on a specific chip. VAS needs per chip
> IRQ allocation and will have IRQ handler per VAS instance.
The pool of generic interrupt source (IPI) numbers is generally used
by user space application which generally do not care
On 3/19/20 7:13 AM, Haren Myneni wrote:
>
> pnv_ocxl_alloc_xive_irq() in ocxl.c allocates IRQ and gets trigger port
> address. VAS also needs this function, but based on chip ID. So moved
> this common function to xive/native.c.
We now have two drivers using the lowlevel routines of the machine
On Mon, Mar 23, 2020 at 5:22 PM Nicholas Piggin wrote:
>
> Jordan Niethe's on March 20, 2020 3:17 pm:
> > A future revision of the ISA will introduce prefixed instructions. A
> > prefixed instruction is composed of a 4-byte prefix followed by a
> > 4-byte suffix.
> >
> > All prefixes have the
On Mon, Mar 23, 2020 at 5:54 PM Balamuruhan S wrote:
>
> On Fri, 2020-03-20 at 16:17 +1100, Jordan Niethe wrote:
> > In preparation for using a data type for instructions that can not be
> > directly used with the '>>' operator use a function for getting the op
> > code of an instruction.
>
> we
On Fri, 2020-03-20 at 16:18 +1100, Jordan Niethe wrote:
> This adds emulation support for the following prefixed Fixed-Point
> Arithmetic instructions:
> * Prefixed Add Immediate (paddi)
>
> Signed-off-by: Jordan Niethe
Reviewed-by: Balamuruhan S
> ---
> v3: Since we moved the prefixed
On Fri, 2020-03-20 at 16:17 +1100, Jordan Niethe wrote:
> To execute an instruction out of line after a breakpoint, the NIP is
> set
> to the address of struct bpt::instr. Here a copy of the instruction
> that
> was replaced with a breakpoint is kept, along with a trap so normal
> flow
> can be
On Fri, 2020-03-20 at 16:17 +1100, Jordan Niethe wrote:
> In preparation for using a data type for instructions that can not be
> directly used with the '>>' operator use a function for getting the op
> code of an instruction.
we need to adopt this in sstep.c and vecemu.c
-- Bala
>
>
So far the only option for a big 64big DMA window was a window located
at 0x800... (1<<59) which creates problems for devices
supporting smaller DMA masks.
This exploits a POWER9 PHB option to allow the second DMA window to map
at 0 and advertises it with a 4GB offset to avoid overlap
On 3/19/20 7:08 AM, Haren Myneni wrote:
>
> On power9, Virtual Accelerator Switchboard (VAS) allows user space or
> kernel to communicate with Nest Accelerator (NX) directly using COPY/PASTE
> instructions. NX provides various functionalities such as compression,
> encryption and etc. But only
On Mon, Mar 23, 2020 at 5:30 PM Nicholas Piggin wrote:
>
> Jordan Niethe's on March 20, 2020 3:17 pm:
> > In preparation for instructions having a more complex data type start
> > using a macro, PPC_INST(), for making an instruction out of a u32.
> > Currently this does nothing, but it will allow
On Mon, Mar 23, 2020 at 7:03 PM Nicholas Piggin wrote:
>
> Jordan Niethe's on March 20, 2020 3:18 pm:
> > Prefixed instructions will mean there are instructions of different
> > length. As a result dereferencing a pointer to an instruction will not
> > necessarily give the desired result.
Jordan Niethe's on March 23, 2020 7:25 pm:
> On Mon, Mar 23, 2020 at 5:22 PM Nicholas Piggin wrote:
>>
>> Jordan Niethe's on March 20, 2020 3:17 pm:
>> > A future revision of the ISA will introduce prefixed instructions. A
>> > prefixed instruction is composed of a 4-byte prefix followed by a
>>
Ganesh's on March 23, 2020 8:19 pm:
>
>
> On 3/20/20 8:58 PM, Nicholas Piggin wrote:
>> rtas_call allocates and uses memory in failure paths, which is
>> not safe for RMA. It also calls local_irq_save() which may not be safe
>> in all real mode contexts.
>>
>> Particularly machine check may run
On 2020-03-20 2:16 pm, Christoph Hellwig wrote:
Several IOMMU drivers have a bypass mode where they can use a direct
mapping if the devices DMA mask is large enough. Add generic support
to the core dma-mapping code to do that to switch those drivers to
a common solution.
Hmm, this is
On Mon, Mar 23, 2020 at 12:14:08PM +, Robin Murphy wrote:
> On 2020-03-20 2:16 pm, Christoph Hellwig wrote:
>> Several IOMMU drivers have a bypass mode where they can use a direct
>> mapping if the devices DMA mask is large enough. Add generic support
>> to the core dma-mapping code to do
On 03/03/2020 02:54 AM, Christophe Leroy wrote:
> Anshuman Khandual a écrit :
>
>> On 02/27/2020 04:59 PM, Christophe Leroy wrote:
>>>
>>>
>>> Le 27/02/2020 à 11:33, Anshuman Khandual a écrit :
This adds new tests validating arch page table helpers for these following
core memory
On Fri, 2020-03-20 at 16:18 +1100, Jordan Niethe wrote:
> In preparation for prefixed instructions where all instructions are no
> longer words, use an accessor for getting a word instruction as a u32
> from the instruction data type.
>
> Signed-off-by: Jordan Niethe
> ---
> v4: New to series
>
Nicholas Piggin writes:
> Haren Myneni's on March 19, 2020 4:13 pm:
>>
>> Kernel sets fault address and status in CRB for NX page fault on user
>> space address after processing page fault. User space gets the signal
>> and handles the fault mentioned in CRB by bringing the page in to
>> memory
On Mon, Mar 23, 2020 at 04:55:48PM +0530, Balamuruhan S wrote:
> Data Cache Block Invalidate (dcbi) instruction implemented in 32-bit
> designs prior to PowerPC architecture version 2.01 and got obsolete
> from version 2.01.
It was added back in 2.03. It also exists in 64-bit designs (using
Daniel Axtens writes:
> Haren Myneni writes:
>
>> On power9, userspace can send GZIP compression requests directly to NX
>> once kernel establishes NX channel / window with VAS. This patch provides
>> user space API which allows user space to establish channel using open
>> VAS_TX_WIN_OPEN
Jordan Niethe's on March 23, 2020 8:09 pm:
> On Mon, Mar 23, 2020 at 7:03 PM Nicholas Piggin wrote:
>>
>> Jordan Niethe's on March 20, 2020 3:18 pm:
>> > Prefixed instructions will mean there are instructions of different
>> > length. As a result dereferencing a pointer to an instruction will not
Data Cache Block Invalidate (dcbi) instruction implemented in 32-bit
designs prior to PowerPC architecture version 2.01 and got obsolete
from version 2.01. Attempt to use of this illegal instruction results
in a hypervisor emulation assistance interrupt. So, drop the option
`i` in cacheflush xmon
On 03/23/2020 04:52 AM, Christopher M. Riedl wrote:
When compiled with CONFIG_STRICT_KERNEL_RWX, the kernel must create
temporary mappings when patching itself. These mappings temporarily
override the strict RWX text protections to permit a write. Currently,
powerpc allocates a per-CPU VM
On 3/23/20 10:06 AM, Cédric Le Goater wrote:
> On 3/19/20 7:14 AM, Haren Myneni wrote:
>>
>> Alloc IRQ and get trigger port address for each VAS instance. Kernel
>> register this IRQ per VAS instance and sets this port for each send
>> window. NX interrupts the kernel when it sees page fault.
>
>
Segher Boessenkool wrote:
On Mon, Mar 23, 2020 at 04:55:48PM +0530, Balamuruhan S wrote:
Data Cache Block Invalidate (dcbi) instruction implemented in 32-bit
designs prior to PowerPC architecture version 2.01 and got obsolete
from version 2.01.
It was added back in 2.03. It also exists in
Michael Ellerman writes:
> Daniel Axtens writes:
>> Haren Myneni writes:
>>
>>> On power9, userspace can send GZIP compression requests directly to NX
>>> once kernel establishes NX channel / window with VAS. This patch provides
>>> user space API which allows user space to establish channel
On 3/18/20 6:22 PM, Ravi Bangoria wrote:
On 3/16/20 8:35 PM, Christophe Leroy wrote:
Le 09/03/2020 à 09:57, Ravi Bangoria a écrit :
So far, powerpc Book3S code has been written with an assumption of only
one watchpoint. But future power architecture is introducing second
watchpoint
The core device API performs extra housekeeping bits that are missing
from directly calling cpu_up/down.
See commit a6717c01ddc2 ("powerpc/rtas: use device model APIs and
serialization during LPM") for an example description of what might go
wrong.
This also prepares to make cpu_up/down a
Le 23/03/2020 à 15:17, Joakim Tjernlund a écrit :
In __die(), see below, there is this call to notify_send() with SIGSEGV
hardcoded, this seems odd
to me as the variable "err" holds the true signal(in my case SIGBUS)
Should not SIGSEGV be replaced with the true signal no.?
As far as I can
This is a note to let you know that I've just added the patch titled
mm, slub: prevent kmalloc_node crashes and memory leaks
to the 5.5-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
This is a note to let you know that I've just added the patch titled
mm, slub: prevent kmalloc_node crashes and memory leaks
to the 4.4-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
This is a note to let you know that I've just added the patch titled
mm, slub: prevent kmalloc_node crashes and memory leaks
to the 4.9-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
Laurent Dufour writes:
> When the call to UV_REGISTER_MEM_SLOT is failing, for instance because
> there is not enough free secured memory, the Hypervisor (HV) has to call
> UV_RETURN to report the error to the Ultravisor (UV). Then the UV will call
> H_SVM_INIT_ABORT to abort the securing phase
In __die(), see below, there is this call to notify_send() with SIGSEGV
hardcoded, this seems odd
to me as the variable "err" holds the true signal(in my case SIGBUS)
Should not SIGSEGV be replaced with the true signal no.?
Jocke
static int __die(const char *str, struct pt_regs *regs, long
This is a note to let you know that I've just added the patch titled
mm, slub: prevent kmalloc_node crashes and memory leaks
to the 4.14-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
On Mon, Mar 23, 2020 at 01:50:54PM +, Qais Yousef wrote:
> The new functions use device_{online,offline}() which are userspace
> safe.
>
> This is in preparation to move cpu_{up, down} kernel users to use
> a safer interface that is not racy with userspace.
>
> Suggested-by: "Paul E.
The warning was intended to spot complete_all() users from hardirq
context on PREEMPT_RT. The warning as-is will also trigger in interrupt
handlers, which are threaded on PREEMPT_RT, which was not intended.
Use lockdep_assert_RT_in_threaded_ctx() which triggers in non-preemptive
context on
On 03/23/2020 11:30 AM, Christophe Leroy wrote:
On 03/23/2020 04:52 AM, Christopher M. Riedl wrote:
When compiled with CONFIG_STRICT_KERNEL_RWX, the kernel must create
temporary mappings when patching itself. These mappings temporarily
override the strict RWX text protections to permit a
Le 23/03/2020 à 16:08, Joakim Tjernlund a écrit :
On Mon, 2020-03-23 at 15:45 +0100, Christophe Leroy wrote:
CAUTION: This email originated from outside of the organization. Do not click
links or open attachments unless you recognize the sender and know the content
is safe.
Le 23/03/2020
Le 23/03/2020 à 15:43, Christophe Leroy a écrit :
Le 23/03/2020 à 15:17, Joakim Tjernlund a écrit :
In __die(), see below, there is this call to notify_send() with
SIGSEGV hardcoded, this seems odd
to me as the variable "err" holds the true signal(in my case SIGBUS)
Should not SIGSEGV be
On Mon, 2020-03-23 at 15:45 +0100, Christophe Leroy wrote:
> CAUTION: This email originated from outside of the organization. Do not click
> links or open attachments unless you recognize the sender and know the
> content is safe.
>
>
> Le 23/03/2020 à 15:43, Christophe Leroy a écrit :
> >
>
=
Changes in v4
=
* Split arm and arm64 patches so that the change to use reboot_cpu goes
into its own separate patch (Russell)
* Collected new Acked-by
* Rebased on top of v5.6-rc6
* Trimmed the CC list on the cover letter as
The new functions use device_{online,offline}() which are userspace
safe.
This is in preparation to move cpu_{up, down} kernel users to use
a safer interface that is not racy with userspace.
Suggested-by: "Paul E. McKenney"
Signed-off-by: Qais Yousef
CC: Thomas Gleixner
CC: "Paul E. McKenney"
This is a note to let you know that I've just added the patch titled
mm, slub: prevent kmalloc_node crashes and memory leaks
to the 4.19-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
This is a note to let you know that I've just added the patch titled
mm, slub: prevent kmalloc_node crashes and memory leaks
to the 5.4-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
Christoph Hellwig writes:
> On Mon, Mar 23, 2020 at 09:37:05AM +0100, Christoph Hellwig wrote:
>> > > +/*
>> > > + * Allows IOMMU drivers to bypass dynamic translations if the
>> > > DMA mask
>> > > + * is large enough.
>> > > + */
>> > > +if
On Mon, Mar 23, 2020 at 07:58:01PM +1100, Alexey Kardashevskiy wrote:
> >> 0x100.. .. 0x101..
> >>
> >> 2x4G, each is 1TB aligned. And we can map directly only the first 4GB
> >> (because of the maximum IOMMU table size) but not the other. And 1:1 on
> >> that "pseries" is done
Le 23/03/2020 à 17:49, Christopher M Riedl a écrit :
On March 23, 2020 9:04 AM Christophe Leroy wrote:
On 03/23/2020 11:30 AM, Christophe Leroy wrote:
On 03/23/2020 04:52 AM, Christopher M. Riedl wrote:
When compiled with CONFIG_STRICT_KERNEL_RWX, the kernel must create
temporary
On Mon, 2020-03-23 at 16:31 +0100, Christophe Leroy wrote:
>
> Le 23/03/2020 à 16:08, Joakim Tjernlund a écrit :
> > On Mon, 2020-03-23 at 15:45 +0100, Christophe Leroy wrote:
> > > CAUTION: This email originated from outside of the organization. Do not
> > > click links or open attachments
On Mon, Mar 23, 2020 at 09:07:38PM +0530, Aneesh Kumar K.V wrote:
>
> This is what I was trying, but considering I am new to DMA subsystem, I
> am not sure I got all the details correct. The idea is to look at the
> cpu addr and see if that can be used in direct map fashion(is
> bus_dma_limit the
On Fri, Mar 20, 2020 at 11:41 AM Lubomir Rintel wrote:
>
> There are separate compatible strings for ns16550 and ns16550a and the
> Freescale serial port is compatible with the latter one, with working
> FIFO.
I don't think changing this is right. First, 'ns16550' is what's
documented in the DT
On Fri, Mar 20, 2020 at 11:41 AM Lubomir Rintel wrote:
>
> Hi,
>
> this series aims to make it possible to validate NS 8250 compatible serial
> port
> nodes in Device Tree. It ultimately ends up converting the 8250.txt binding
> specification to YAML for json-schema.
>
> It starts by fixing up a
On Mon, 2020-03-23 at 22:32 +1100, Michael Ellerman wrote:
> Nicholas Piggin writes:
> > Haren Myneni's on March 19, 2020 4:13 pm:
> >>
> >> Kernel sets fault address and status in CRB for NX page fault on user
> >> space address after processing page fault. User space gets the signal
> >> and
On Sun, Mar 22, 2020 at 08:51:15AM +0200, Kalle Valo wrote:
> "Joel Fernandes (Google)" writes:
>
> > Reword and clarify better about the rwsem non-owner release issue.
> >
> > Link: https://lore.kernel.org/linux-pci/20200321212144.ga6...@google.com/
> >
> > Signed-off-by: Joel Fernandes
On Fri, Mar 20, 2020 at 11:41 AM Lubomir Rintel wrote:
>
> Some fixes were done during the conversion:
Thanks for doing this!
>
> Slightly better examples. The original example was for an OMAP serial
> port, which is not even described by this binding, but by
> omap_serial.txt instead.
>
>
On Mon, 2020-03-23 at 10:27 +0100, Cédric Le Goater wrote:
> On 3/23/20 10:06 AM, Cédric Le Goater wrote:
> > On 3/19/20 7:14 AM, Haren Myneni wrote:
> >>
> >> Alloc IRQ and get trigger port address for each VAS instance. Kernel
> >> register this IRQ per VAS instance and sets this port for each
On Fri, Mar 20, 2020 at 11:32:13AM -0600, Rob Herring wrote:
> On Mon, Mar 09, 2020 at 02:19:44PM -0700, Nicolin Chen wrote:
> > On Mon, Mar 09, 2020 at 11:58:28AM +0800, Shengjiu Wang wrote:
> > > In order to support new EASRC and simplify the code structure,
> > > We decide to share the common
On 3/20/20 8:58 PM, Nicholas Piggin wrote:
rtas_call allocates and uses memory in failure paths, which is
not safe for RMA. It also calls local_irq_save() which may not be safe
in all real mode contexts.
Particularly machine check may run with interrupts not "reconciled",
and it may have hit
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