[llvm-branch-commits] [llvm] [SPARC][IAS] Add definitions for OSA 2011 instructions (PR #138403)

https://github.com/s-barannikov approved this pull request. https://github.com/llvm/llvm-project/pull/138403 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [SPARC][IAS] Add definitions for OSA 2011 instructions (PR #138403)

@@ -102,6 +102,49 @@ class F2_4 pattern = [], InstrItinClass itin = NoItinerary> + : InstSP { + bits<10> imm10; + bits<5> rs1; + bits<5> rs2; + bits<4> cond; + + let op = 0; // op = 0 + + let Inst{29}= cond{3}; + let Inst{28}= 1; + let Inst{27-25} = c

[llvm-branch-commits] [SPARC][IAS] Add definitions for OSA 2011 instructions (PR #138403)

@@ -0,0 +1,267 @@ +! RUN: llvm-mc -triple=sparcv9 -mattr=+osa2011 -filetype=obj %s | llvm-objdump --mattr=+osa2011 --no-print-imm-hex -d - | FileCheck %s --check-prefix=BIN + +!! SPARCv9/SPARC64 BPr branches have different offset encoding from the others, ---

[llvm-branch-commits] [SPARC][IAS] Add definitions for OSA 2011 instructions (PR #138403)

@@ -408,6 +427,46 @@ defm : reg_cond_alias<"ne", 0b101>; defm : reg_cond_alias<"gz", 0b110>; defm : reg_cond_alias<"gez", 0b111>; +defm : cwb_cond_alias<"ne", 0b1001>; +defm : cwb_cond_alias<"e",0b0001>; +defm : cwb_cond_alias<"g",0b1010>; +defm : cwb_cond_alias

[llvm-branch-commits] [SPARC][IAS] Add definitions for OSA 2011 instructions (PR #138403)

@@ -102,6 +102,49 @@ class F2_4 pattern = [], InstrItinClass itin = NoItinerary> + : InstSP { s-barannikov wrote: ```suggestion : InstSP { ``` https://github.com/llvm/llvm-project/pull/138403 ___ llvm-branch-comm

[llvm-branch-commits] [SPARC][IAS] Add definitions for OSA 2011 instructions (PR #138403)

@@ -141,6 +147,26 @@ getMachineOpValue(const MCInst &MI, const MCOperand &MO, return 0; } +unsigned SparcMCCodeEmitter::getSImm5OpValue(const MCInst &MI, unsigned OpNo, + SmallVectorImpl &Fixups, +

[llvm-branch-commits] [SPARC][IAS] Add definitions for OSA 2011 instructions (PR #138403)

@@ -331,6 +331,25 @@ multiclass reg_cond_alias { Requires<[Is64Bit]>; } +// Instruction aliases for compare-and-branch. +multiclass cwb_cond_alias { + def : InstAliashttps://github.com/llvm/llvm-project/pull/138403 _

[llvm-branch-commits] [SPARC][IAS] Add definitions for OSA 2011 instructions (PR #138403)

@@ -665,3 +724,9 @@ def : InstAlias<"signx $rs1, $rd", (SRArr IntRegs:$rd, IntRegs:$rs1, G0), 0>, Re // sir -> sir 0 def : InstAlias<"sir", (SIR 0), 0>; + +// pause reg_or_imm -> wrasr %g0, reg_or_imm, %asr27 +let Predicates = [HasOSA2011] in { +def : InstAlias<"pause $rs2",

[llvm-branch-commits] [SPARC][IAS] Add definitions for OSA 2011 instructions (PR #138403)

@@ -217,6 +243,18 @@ unsigned SparcMCCodeEmitter::getBranchOnRegTargetOpValue( return 0; } +unsigned SparcMCCodeEmitter::getCompareAndBranchTargetOpValue( +const MCInst &MI, unsigned OpNo, SmallVectorImpl &Fixups, +const MCSubtargetInfo &STI) const { + const MCOpera

[llvm-branch-commits] [SPARC][IAS] Add definitions for OSA 2011 instructions (PR #138403)

@@ -50,6 +50,15 @@ static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) { return (d16hi << 20) | d16lo; } + case ELF::R_SPARC_WDISP10: { +// 7.17 Compare and Branch +// Inst{20-19} = d10hi; +// Inst{12-5} = d10lo; +unsigned d10hi = (Value >>

[llvm-branch-commits] [SPARC][IAS] Add definitions for UA 2007 instructions (PR #138401)

https://github.com/s-barannikov approved this pull request. https://github.com/llvm/llvm-project/pull/138401 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [SPARC][IAS] Add definitions for UA 2005 instructions (PR #138400)

@@ -0,0 +1,28 @@ +//=== SparcInstrUAOSA.td - UltraSPARC/Oracle SPARC Architecture extensions ===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apa

[llvm-branch-commits] [llvm] [SPARC][IAS] Add definitions for UA 2005 instructions (PR #138400)

https://github.com/s-barannikov approved this pull request. https://github.com/llvm/llvm-project/pull/138400 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [SPARC][IAS] Add definitions for OSA 2011 instructions (PR #138403)

@@ -38,3 +53,92 @@ def FNMADDD : FourOp<"fnmaddd", 0b110111, 0b1110, DFPRegs>; def FNMSUBS : FourOp<"fnmsubs", 0b110111, 0b1001, FPRegs>; def FNMSUBD : FourOp<"fnmsubd", 0b110111, 0b1010, DFPRegs>; } // Predicates = [HasUA2007] + +// Oracle SPARC Architecture 2011 Instructions

[llvm-branch-commits] [SPARC][IAS] Add definitions for UA 2007 instructions (PR #138401)

@@ -19,3 +25,16 @@ def ALLCLEAN : InstSP<(outs), (ins), "allclean", []> { let Inst{18-0} = 0; } } // Predicates = [HasUA2005] + +// UltraSPARC Architecture 2007 Instructions +let Predicates = [HasUA2007] in { +def FMADDS : FourOp<"fmadds", 0b110111, 0b0001, FPRegs>; +def FM

[llvm-branch-commits] [llvm] [SPARC][IAS] Add definitions for UA 2005 instructions (PR #138400)

@@ -152,13 +155,15 @@ def : Proc<"ultrasparc3", [FeatureV9, FeatureV8Deprecated, FeatureVIS, FeatureVIS2], [TuneSlowRDPC]>; def : Proc<"niagara", [FeatureV9, FeatureV8Deprecated, FeatureVIS, -

[llvm-branch-commits] [llvm] [SPARC][IAS] Add definitions for UA 2005 instructions (PR #138400)

@@ -0,0 +1,36 @@ +//=== SparcInstrUAOSA.td - UltraSPARC/Oracle SPARC Architecture extensions ===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apa

[llvm-branch-commits] [SPARC][IAS][NFC] Rename CBCOND -> CPBCOND (PR #138402)

https://github.com/s-barannikov approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/138402 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commit

[llvm-branch-commits] [SPARC][IAS] Add definitions for UA 2005 instructions (PR #138400)

@@ -0,0 +1,21 @@ +//=== SparcInstrVIS.td - Visual Instruction Set extensions (VIS) -===// s-barannikov wrote: Copy&paste bug https://github.com/llvm/llvm-project/pull/138400 ___ llvm-branch-commits mailing list

[llvm-branch-commits] [SPARC][IAS] Add definitions for UA 2005 instructions (PR #138400)

https://github.com/s-barannikov edited https://github.com/llvm/llvm-project/pull/138400 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [SPARC][IAS] Add definitions for UA 2005 instructions (PR #138400)

https://github.com/s-barannikov commented: What about other instructions? (OTHERW, NORMALW, INVALWP) https://github.com/llvm/llvm-project/pull/138400 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bi

[llvm-branch-commits] [SPARC][IAS] Add definitions for UA 2005 instructions (PR #138400)

@@ -0,0 +1,21 @@ +//=== SparcInstrVIS.td - Visual Instruction Set extensions (VIS) -===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apach

[llvm-branch-commits] [SPARC] Mark Niagara3 as VIS3-capable (PR #138399)

https://github.com/s-barannikov approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/138399 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commit

[llvm-branch-commits] [SPARC] Promote i32 CTTZ when we have VIS3 (PR #135894)

s-barannikov wrote: Is something blocking this PR? https://github.com/llvm/llvm-project/pull/135894 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [SPARC] Promote i32 CTTZ when we have VIS3 (PR #135894)

@@ -1,70 +1,438 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -mtriple=sparc -mcpu=v9 | FileCheck %s +; RUN: llc < %s -mtriple=sparc | FileCheck %s -check-prefix=SPARC +; RUN: llc < %s -mtriple=sparc -mattr=popc | FileCheck %s

[llvm-branch-commits] [SPARC] Promote i32 CTTZ when we have VIS3 (PR #135894)

https://github.com/s-barannikov approved this pull request. LGTM with one note https://github.com/llvm/llvm-project/pull/135894 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm

[llvm-branch-commits] [SPARC] Promote i32 CTTZ when we have VIS3 (PR #135894)

@@ -1,70 +1,438 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -mtriple=sparc -mcpu=v9 | FileCheck %s +; RUN: llc < %s -mtriple=sparc | FileCheck %s -check-prefix=SPARC +; RUN: llc < %s -mtriple=sparc -mattr=popc | FileCheck %s

[llvm-branch-commits] [SPARC] Promote i32 CTTZ when we have VIS3 (PR #135894)

https://github.com/s-barannikov edited https://github.com/llvm/llvm-project/pull/135894 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [SimplifyLibCalls] Add initial support for non-8-bit bytes (PR #106542)

https://github.com/s-barannikov updated https://github.com/llvm/llvm-project/pull/106542 >From bb76990f184c59abfcaa7c5f9409ec8d9b309636 Mon Sep 17 00:00:00 2001 From: Sergei Barannikov Date: Wed, 28 Aug 2024 16:09:44 +0300 Subject: [PATCH] [SimplifyLibCalls] Add initial support for non-8-bit by

[llvm-branch-commits] [clang] [llvm] [ValueTracking] Add CharWidth argument to getConstantStringInfo (NFC) (PR #106541)

https://github.com/s-barannikov updated https://github.com/llvm/llvm-project/pull/106541 >From 24ff5d64d01e02e2d3641fad6b72ddab6bb32eea Mon Sep 17 00:00:00 2001 From: Sergei Barannikov Date: Wed, 28 Aug 2024 23:51:13 +0300 Subject: [PATCH] [ValueTracking] Add CharWidth argument to getConstantS

[llvm-branch-commits] [llvm] [IR] Account for byte width in m_PtrAdd (PR #106540)

https://github.com/s-barannikov updated https://github.com/llvm/llvm-project/pull/106540 >From 5604e7a7d06d4b367f765e15a929b9dd7760d6f8 Mon Sep 17 00:00:00 2001 From: Sergei Barannikov Date: Thu, 29 Aug 2024 00:54:20 +0300 Subject: [PATCH] [IR] Account for byte width in m_PtrAdd The method has

[llvm-branch-commits] [llvm] [IRBuilder] Add getByteTy and use it in CreatePtrAdd (PR #106539)

https://github.com/s-barannikov updated https://github.com/llvm/llvm-project/pull/106539 >From c335952171cd7907e38c8a12b4b50ea1fb384bb0 Mon Sep 17 00:00:00 2001 From: Sergei Barannikov Date: Thu, 22 Aug 2024 15:10:58 +0300 Subject: [PATCH] [IRBuilder] Add getByteTy and use it in CreatePtrAdd T

[llvm-branch-commits] [llvm] [ValueTracking] Make isBytewiseValue byte width agnostic (PR #106538)

https://github.com/s-barannikov updated https://github.com/llvm/llvm-project/pull/106538 >From 3036dfc0ddfad4aeee1b5bd23627ad1949875489 Mon Sep 17 00:00:00 2001 From: Sergei Barannikov Date: Fri, 2 Aug 2024 13:14:49 +0300 Subject: [PATCH] [ValueTracking] Make isBytewiseValue byte width agnostic

[llvm-branch-commits] [llvm] [mlir] [IR] Make @llvm.memset prototype byte width dependent (PR #106537)

https://github.com/s-barannikov updated https://github.com/llvm/llvm-project/pull/106537 >From 0bf73e36bee4838ec17742b123f7e5b97c4550b8 Mon Sep 17 00:00:00 2001 From: Sergei Barannikov Date: Thu, 1 Aug 2024 23:47:25 +0300 Subject: [PATCH] [IR] Make @llvm.memset prototype byte width dependent T

[llvm-branch-commits] [llvm] [SPARC] Use lzcnt to implement CTLZ when we have VIS3 (PR #135715)

@@ -0,0 +1,183 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s -mtriple=sparcv9 | FileCheck %s -check-prefix=V9 +; RUN: llc < %s -mtriple=sparcv9 -mattr=popc | FileCheck %s -check-prefix=POPC +; RUN: llc < %s -mtriple=sparcv9 -mat

[llvm-branch-commits] [SPARC] Promote i32 CTTZ when we have VIS3 (PR #135894)

@@ -3599,6 +3615,15 @@ bool SparcTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT, bool SparcTargetLowering::isCtlzFast() const { return Subtarget->isVIS3(); } +bool SparcTargetLowering::isCheapToSpeculateCttz(Type *Ty) const { + // We lack native cttz, however, + /

[llvm-branch-commits] [SPARC] Promote i32 CTTZ when we have VIS3 (PR #135894)

@@ -3599,6 +3615,15 @@ bool SparcTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT, bool SparcTargetLowering::isCtlzFast() const { return Subtarget->isVIS3(); } +bool SparcTargetLowering::isCheapToSpeculateCttz(Type *Ty) const { + // We lack native cttz, however, + /

[llvm-branch-commits] [llvm] [SPARC] Use lzcnt to implement CTLZ when we have VIS3 (PR #135715)

@@ -303,4 +303,10 @@ def : Pat<(i64 (mulhs i64:$lhs, i64:$rhs)), (SUBrr (UMULXHI $lhs, $rhs), (ADDrr (ANDrr (SRAXri $lhs, 63), $rhs), (ANDrr (SRAXri $rhs, 63), $lhs)))>; + +def : Pat<(i64 (ctlz i64:$src)), (LZCNT $src)>; +// 32-bit LZCNT.

[llvm-branch-commits] [llvm] [SPARC] Use lzcnt to implement CTLZ when we have VIS3 (PR #135715)

@@ -303,4 +303,10 @@ def : Pat<(i64 (mulhs i64:$lhs, i64:$rhs)), (SUBrr (UMULXHI $lhs, $rhs), (ADDrr (ANDrr (SRAXri $lhs, 63), $rhs), (ANDrr (SRAXri $rhs, 63), $lhs)))>; + +def : Pat<(i64 (ctlz i64:$src)), (LZCNT $src)>; +// 32-bit LZCNT.

[llvm-branch-commits] [llvm] [SPARC] Use lzcnt to implement CTLZ when we have VIS3 (PR #135715)

@@ -0,0 +1,183 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s -mtriple=sparcv9 | FileCheck %s -check-prefix=V9 +; RUN: llc < %s -mtriple=sparcv9 -mattr=popc | FileCheck %s -check-prefix=POPC +; RUN: llc < %s -mtriple=sparcv9 -mat

[llvm-branch-commits] [llvm] [SPARC] Use lzcnt to implement CTLZ when we have VIS3 (PR #135715)

https://github.com/s-barannikov edited https://github.com/llvm/llvm-project/pull/135715 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [SPARC] Use lzcnt to implement CTLZ when we have VIS3 (PR #135715)

@@ -0,0 +1,183 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s -mtriple=sparcv9 | FileCheck %s -check-prefix=V9 +; RUN: llc < %s -mtriple=sparcv9 -mattr=popc | FileCheck %s -check-prefix=POPC +; RUN: llc < %s -mtriple=sparcv9 -mat

[llvm-branch-commits] [llvm] [SPARC] Use lzcnt to implement CTLZ when we have VIS3 (PR #135715)

https://github.com/s-barannikov approved this pull request. Looks great, I left some final comments (few of them are actionable). There is also a couple of methods in TargetLoweringBase that should be implemented: `isCheapToSpeculateCtlz()`, `isCtlzFast()`. I think they could improve codegen a

[llvm-branch-commits] [llvm] [SPARC] Use lzcnt to implement CTLZ when we have VIS3 (PR #135715)

@@ -0,0 +1,183 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s -mtriple=sparcv9 | FileCheck %s -check-prefix=V9 s-barannikov wrote: Would be nice to check V8 as well. https://github.com/llvm/llvm-project/pull/13

[llvm-branch-commits] [SPARC] Use lzcnt to implement CTLZ when we have VIS3 (PR #135715)

@@ -1815,7 +1817,8 @@ SparcTargetLowering::SparcTargetLowering(const TargetMachine &TM, setOperationAction(ISD::FREM , MVT::f32, Expand); setOperationAction(ISD::FMA , MVT::f32, Expand); setOperationAction(ISD::CTTZ , MVT::i32, Expand); - setOperationAction(ISD::CTLZ ,

[llvm-branch-commits] [SPARC] Use lzcnt to implement CTLZ when we have VIS3 (PR #135715)

@@ -1815,7 +1817,8 @@ SparcTargetLowering::SparcTargetLowering(const TargetMachine &TM, setOperationAction(ISD::FREM , MVT::f32, Expand); setOperationAction(ISD::FMA , MVT::f32, Expand); setOperationAction(ISD::CTTZ , MVT::i32, Expand); - setOperationAction(ISD::CTLZ ,

[llvm-branch-commits] [SPARC] Use op-then-neg instructions when we have VIS3 (PR #135717)

@@ -316,4 +316,17 @@ def : Pat<(i64 (sext (i32 (bitconvert f32:$src, (MOVSTOSW $src)>; def : Pat<(f32 (bitconvert i32:$src)), (MOVWTOS $src)>; def : Pat<(i64 (bitconvert f64:$src)), (MOVDTOX $src)>; def : Pat<(f64 (bitconvert i64:$src)), (MOVXTOD $src)>; + +// OP-then-neg

[llvm-branch-commits] [SPARC] Use lzcnt to implement CTLZ when we have VIS3 (PR #135715)

https://github.com/s-barannikov edited https://github.com/llvm/llvm-project/pull/135715 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [SPARC] Use lzcnt to implement CTLZ when we have VIS3 (PR #135715)

@@ -1815,7 +1817,8 @@ SparcTargetLowering::SparcTargetLowering(const TargetMachine &TM, setOperationAction(ISD::FREM , MVT::f32, Expand); setOperationAction(ISD::FMA , MVT::f32, Expand); setOperationAction(ISD::CTTZ , MVT::i32, Expand); - setOperationAction(ISD::CTLZ ,

[llvm-branch-commits] [SPARC] Promote i32 CTTZ when we have VIS3 (PR #135894)

@@ -1,70 +1,195 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -mtriple=sparc -mcpu=v9 | FileCheck %s +; RUN: llc < %s -mtriple=sparcv9 | FileCheck %s -check-prefix=V9 +; RUN: llc < %s -mtriple=sparcv9 -mattr=popc | FileCheck %s

[llvm-branch-commits] [SPARC] Use lzcnt to implement CTLZ when we have VIS3 (PR #135715)

@@ -0,0 +1,313 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s -mtriple=sparcv9 | FileCheck %s -check-prefix=V9 +; RUN: llc < %s -mtriple=sparcv9 -mattr=popc | FileCheck %s -check-prefix=POPC +; RUN: llc < %s -mtriple=sparcv9 -mat

[llvm-branch-commits] [SPARC] Use umulxhi to do extending 64x64->128 multiply when we have VIS3 (PR #135714)

@@ -294,4 +294,13 @@ def : Pat<(f32 fpnegimm0), (FNEGS (FZEROS))>; // VIS3 instruction patterns. let Predicates = [HasVIS3] in { def : Pat<(i64 (adde i64:$lhs, i64:$rhs)), (ADDXCCC $lhs, $rhs)>; + +def : Pat<(i64 (mulhu i64:$lhs, i64:$rhs)), (UMULXHI $lhs, $rhs)>; +// Signed "M

[llvm-branch-commits] [SPARC] Use umulxhi to do extending 64x64->128 multiply when we have VIS3 (PR #135714)

https://github.com/s-barannikov edited https://github.com/llvm/llvm-project/pull/135714 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [SPARC] Use umulxhi to do extending 64x64->128 multiply when we have VIS3 (PR #135714)

https://github.com/s-barannikov approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/135714 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commit

[llvm-branch-commits] [SPARC] Use native bitcast instructions when we have VIS3 (PR #135716)

https://github.com/s-barannikov approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/135716 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commit

[llvm-branch-commits] [SPARC] Use lzcnt to implement CTLZ when we have VIS3 (PR #135715)

https://github.com/s-barannikov edited https://github.com/llvm/llvm-project/pull/135715 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [SPARC] Use lzcnt to implement CTLZ when we have VIS3 (PR #135715)

https://github.com/s-barannikov edited https://github.com/llvm/llvm-project/pull/135715 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [SPARC] Use lzcnt to implement CTLZ when we have VIS3 (PR #135715)

https://github.com/s-barannikov edited https://github.com/llvm/llvm-project/pull/135715 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [SPARC] Use lzcnt to implement CTLZ when we have VIS3 (PR #135715)

@@ -0,0 +1,315 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s -mtriple=sparcv9 | FileCheck %s -check-prefix=V9 +; RUN: llc < %s -mtriple=sparcv9 -mattr=popc | FileCheck %s -check-prefix=POPC +; RUN: llc < %s -mtriple=sparcv9 -mat

[llvm-branch-commits] [SPARC] Use lzcnt to implement CTLZ when we have VIS3 (PR #135715)

@@ -303,4 +303,10 @@ def : Pat<(i64 (mulhs i64:$lhs, i64:$rhs)), (SUBrr (UMULXHI $lhs, $rhs), (ADDrr (ANDrr (SRAXri $lhs, 63), $rhs), (ANDrr (SRAXri $rhs, 63), $lhs)))>; + +def : Pat<(i64 (ctlz i64:$src)), (LZCNT $src)>; +// 32-bit LZCNT.

[llvm-branch-commits] [SPARC] Use addxccc to do multiword addition when we have VIS3 (PR #135713)

https://github.com/s-barannikov approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/135713 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commit

[llvm-branch-commits] [SPARC] Use addxccc to do multiword addition when we have VIS3 (PR #135713)

@@ -1737,6 +1737,11 @@ SparcTargetLowering::SparcTargetLowering(const TargetMachine &TM, setOperationAction(ISD::SUBC, MVT::i32, Legal); setOperationAction(ISD::SUBE, MVT::i32, Legal); + if (Subtarget->isVIS3()) { +setOperationAction(ISD::ADDC, MVT::i64, Legal); +

[llvm-branch-commits] [SPARC] Use umulxhi to do extending 64x64->128 multiply when we have VIS3 (PR #135714)

https://github.com/s-barannikov edited https://github.com/llvm/llvm-project/pull/135714 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [SPARC] Use umulxhi to do extending 64x64->128 multiply when we have VIS3 (PR #135714)

@@ -294,4 +294,13 @@ def : Pat<(f32 fpnegimm0), (FNEGS (FZEROS))>; // VIS3 instruction patterns. let Predicates = [HasVIS3] in { def : Pat<(i64 (adde i64:$lhs, i64:$rhs)), (ADDXCCC $lhs, $rhs)>; + +def : Pat<(i64 (mulhu i64:$lhs, i64:$rhs)), (UMULXHI $lhs, $rhs)>; +// Signed "M

[llvm-branch-commits] [SPARC] Use umulxhi to do extending 64x64->128 multiply when we have VIS3 (PR #135714)

@@ -294,4 +294,13 @@ def : Pat<(f32 fpnegimm0), (FNEGS (FZEROS))>; // VIS3 instruction patterns. let Predicates = [HasVIS3] in { def : Pat<(i64 (adde i64:$lhs, i64:$rhs)), (ADDXCCC $lhs, $rhs)>; + +def : Pat<(i64 (mulhu i64:$lhs, i64:$rhs)), (UMULXHI $lhs, $rhs)>; +// Signed "M

[llvm-branch-commits] [SPARC] Use lzcnt to implement CTLZ when we have VIS3 (PR #135715)

@@ -0,0 +1,171 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s -mtriple=sparcv9 | FileCheck %s -check-prefix=V9 +; RUN: llc < %s -mtriple=sparcv9 -mattr=popc | FileCheck %s -check-prefix=POPC +; RUN: llc < %s -mtriple=sparcv9 -mat

[llvm-branch-commits] [SPARC] Use lzcnt to implement CTLZ when we have VIS3 (PR #135715)

@@ -303,4 +303,10 @@ def : Pat<(i64 (mulhs i64:$lhs, i64:$rhs)), (SUBrr (UMULXHI $lhs, $rhs), (ADDrr (ANDrr (SRAXri $lhs, 63), $rhs), (ANDrr (SRAXri $rhs, 63), $lhs)))>; + +def : Pat<(i64 (ctlz i64:$src)), (LZCNT $src)>; +// 32-bit LZCNT.

[llvm-branch-commits] [SPARC] Use lzcnt to implement CTLZ when we have VIS3 (PR #135715)

@@ -0,0 +1,171 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s -mtriple=sparcv9 | FileCheck %s -check-prefix=V9 +; RUN: llc < %s -mtriple=sparcv9 -mattr=popc | FileCheck %s -check-prefix=POPC +; RUN: llc < %s -mtriple=sparcv9 -mat

[llvm-branch-commits] [SPARC] Use lzcnt to implement CTLZ when we have VIS3 (PR #135715)

@@ -0,0 +1,171 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s -mtriple=sparcv9 | FileCheck %s -check-prefix=V9 +; RUN: llc < %s -mtriple=sparcv9 -mattr=popc | FileCheck %s -check-prefix=POPC +; RUN: llc < %s -mtriple=sparcv9 -mat

[llvm-branch-commits] [llvm] [IRBuilder] Add getByteTy and use it in CreatePtrAdd (PR #106539)

https://github.com/s-barannikov updated https://github.com/llvm/llvm-project/pull/106539 >From b8c20416dc61604cae2d0ec6bce1632ae54ed96d Mon Sep 17 00:00:00 2001 From: Sergei Barannikov Date: Thu, 22 Aug 2024 15:10:58 +0300 Subject: [PATCH] [IRBuilder] Add getByteTy and use it in CreatePtrAdd T

[llvm-branch-commits] [llvm] [IR] Account for byte width in m_PtrAdd (PR #106540)

https://github.com/s-barannikov updated https://github.com/llvm/llvm-project/pull/106540 >From e75ad5f9a08f81feecf19f0f1c6f0067c24f2faf Mon Sep 17 00:00:00 2001 From: Sergei Barannikov Date: Thu, 29 Aug 2024 00:54:20 +0300 Subject: [PATCH] [IR] Account for byte width in m_PtrAdd The method has

[llvm-branch-commits] [llvm] [SimplifyLibCalls] Add initial support for non-8-bit bytes (PR #106542)

https://github.com/s-barannikov updated https://github.com/llvm/llvm-project/pull/106542 >From 76b45538d3117532e74dedd9bb2c4e75261702e0 Mon Sep 17 00:00:00 2001 From: Sergei Barannikov Date: Wed, 28 Aug 2024 16:09:44 +0300 Subject: [PATCH] [SimplifyLibCalls] Add initial support for non-8-bit by

[llvm-branch-commits] [clang] [llvm] [ValueTracking] Add CharWidth argument to getConstantStringInfo (NFC) (PR #106541)

https://github.com/s-barannikov updated https://github.com/llvm/llvm-project/pull/106541 >From fe95d6435fd4b964f96351c6fc564cbd853ae8f0 Mon Sep 17 00:00:00 2001 From: Sergei Barannikov Date: Wed, 28 Aug 2024 23:51:13 +0300 Subject: [PATCH] [ValueTracking] Add CharWidth argument to getConstantS

[llvm-branch-commits] [llvm] [ValueTracking] Make isBytewiseValue byte width agnostic (PR #106538)

https://github.com/s-barannikov updated https://github.com/llvm/llvm-project/pull/106538 >From 555e531fdeb40bd54d6eecfed41421546ba9025b Mon Sep 17 00:00:00 2001 From: Sergei Barannikov Date: Fri, 2 Aug 2024 13:14:49 +0300 Subject: [PATCH] [ValueTracking] Make isBytewiseValue byte width agnostic

[llvm-branch-commits] [llvm] [mlir] [IR] Make @llvm.memset prototype byte width dependent (PR #106537)

https://github.com/s-barannikov updated https://github.com/llvm/llvm-project/pull/106537 >From 97cce999ea0e569bbf7863316d8fc3e9c653041e Mon Sep 17 00:00:00 2001 From: Sergei Barannikov Date: Thu, 1 Aug 2024 23:47:25 +0300 Subject: [PATCH] [IR] Make @llvm.memset prototype byte width dependent T

[llvm-branch-commits] [llvm] [SPARC][MC] Add tests for VIS family instructions (PR #130967)

@@ -0,0 +1,55 @@ +! RUN: not llvm-mc %s -triple=sparcv9 -show-encoding 2>&1 | FileCheck %s --check-prefixes=NO-VIS2 +! RUN: llvm-mc %s -triple=sparcv9 -mattr=+vis2 -show-encoding | FileCheck %s --check-prefixes=VIS2 + +!! VIS 2 instructions. + +! NO-VIS2: error: instruction requ

[llvm-branch-commits] [llvm] [SPARC][MC] Add tests for VIS family instructions (PR #130967)

@@ -7,76 +7,96 @@ //===--===// // // This file contains instruction formats, definitions and patterns needed for -// VIS, VIS II, VIS II instructions on SPARC. +// VIS, VIS II, VIS III instructions on SPARC.

[llvm-branch-commits] [llvm] [SPARC][MC] Add tests for VIS family instructions (PR #130967)

@@ -82,6 +82,8 @@ def UseDeprecatedInsts : Predicate<"Subtarget->useV8DeprecatedInsts()">; // Instruction Pattern Stuff //===--===// +def siam_mode : PatLeaf<(imm), [{ return isUInt<3>(N->getZExtValue()); }]

[llvm-branch-commits] [llvm] [SPARC][MC] Add tests for VIS family instructions (PR #130967)

https://github.com/s-barannikov approved this pull request. https://github.com/llvm/llvm-project/pull/130967 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [SPARC][MC] Add tests for VIS family instructions (PR #130967)

@@ -7,76 +7,96 @@ //===--===// // // This file contains instruction formats, definitions and patterns needed for -// VIS, VIS II, VIS II instructions on SPARC. +// VIS, VIS II, VIS III instructions on SPARC.

[llvm-branch-commits] [llvm] [SimplifyLibCalls] Add initial support for non-8-bit bytes (PR #106542)

https://github.com/s-barannikov updated https://github.com/llvm/llvm-project/pull/106542 >From 931d15e69f7c57a7c0a0708853ee50be1e27c769 Mon Sep 17 00:00:00 2001 From: Sergei Barannikov Date: Wed, 28 Aug 2024 16:09:44 +0300 Subject: [PATCH] [SimplifyLibCalls] Add initial support for non-8-bit by

[llvm-branch-commits] [clang] [llvm] [ValueTracking] Add CharWidth argument to getConstantStringInfo (NFC) (PR #106541)

https://github.com/s-barannikov updated https://github.com/llvm/llvm-project/pull/106541 >From 57104d137fdb6e7c9add7ed3fcff37f1dcf56a7f Mon Sep 17 00:00:00 2001 From: Sergei Barannikov Date: Wed, 28 Aug 2024 23:51:13 +0300 Subject: [PATCH] [ValueTracking] Add CharWidth argument to getConstantS

[llvm-branch-commits] [llvm] [IRBuilder] Add getByteTy and use it in CreatePtrAdd (PR #106539)

https://github.com/s-barannikov updated https://github.com/llvm/llvm-project/pull/106539 >From 6d95f98f2de990ff8971400966de74f62ef339bb Mon Sep 17 00:00:00 2001 From: Sergei Barannikov Date: Thu, 22 Aug 2024 15:10:58 +0300 Subject: [PATCH] [IRBuilder] Add getByteTy and use it in CreatePtrAdd T

[llvm-branch-commits] [llvm] [IR] Account for byte width in m_PtrAdd (PR #106540)

https://github.com/s-barannikov updated https://github.com/llvm/llvm-project/pull/106540 >From 26dc400bb3e62f33c245082b9d29811d1444560c Mon Sep 17 00:00:00 2001 From: Sergei Barannikov Date: Thu, 29 Aug 2024 00:54:20 +0300 Subject: [PATCH] [IR] Account for byte width in m_PtrAdd The method has

[llvm-branch-commits] [llvm] [ValueTracking] Make isBytewiseValue byte width agnostic (PR #106538)

https://github.com/s-barannikov updated https://github.com/llvm/llvm-project/pull/106538 >From 67765a6e3e4c8e0475cd6baccb801cad1498b36e Mon Sep 17 00:00:00 2001 From: Sergei Barannikov Date: Fri, 2 Aug 2024 13:14:49 +0300 Subject: [PATCH] [ValueTracking] Make isBytewiseValue byte width agnostic

[llvm-branch-commits] [llvm] [mlir] [IR] Make @llvm.memset prototype byte width dependent (PR #106537)

https://github.com/s-barannikov updated https://github.com/llvm/llvm-project/pull/106537 >From 65a421f56e7e7bb9a72d0b5cc70f8cc7b4348c9b Mon Sep 17 00:00:00 2001 From: Sergei Barannikov Date: Thu, 1 Aug 2024 23:47:25 +0300 Subject: [PATCH] [IR] Make @llvm.memset prototype byte width dependent T

[llvm-branch-commits] [SPARC][IAS] Add support for `setsw` pseudoinstruction (PR #125150)

https://github.com/s-barannikov approved this pull request. https://github.com/llvm/llvm-project/pull/125150 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [SPARC][IAS] Add support for `setsw` pseudoinstruction (PR #125150)

@@ -734,6 +737,69 @@ bool SparcAsmParser::expandSET(MCInst &Inst, SMLoc IDLoc, return false; } +bool SparcAsmParser::expandSETSW(MCInst &Inst, SMLoc IDLoc, + SmallVectorImpl &Instructions) { + MCOperand MCRegOp = Inst.getOperand(0); + MCOper

[llvm-branch-commits] [SPARC][IAS] Add support for `setsw` pseudoinstruction (PR #125150)

@@ -734,6 +737,69 @@ bool SparcAsmParser::expandSET(MCInst &Inst, SMLoc IDLoc, return false; } +bool SparcAsmParser::expandSETSW(MCInst &Inst, SMLoc IDLoc, + SmallVectorImpl &Instructions) { + MCOperand MCRegOp = Inst.getOperand(0); + MCOper

[llvm-branch-commits] [SPARC][IAS] Add support for `setsw` pseudoinstruction (PR #125150)

@@ -734,6 +737,69 @@ bool SparcAsmParser::expandSET(MCInst &Inst, SMLoc IDLoc, return false; } +bool SparcAsmParser::expandSETSW(MCInst &Inst, SMLoc IDLoc, + SmallVectorImpl &Instructions) { + MCOperand MCRegOp = Inst.getOperand(0); + MCOper

[llvm-branch-commits] [SPARC][IAS] Add support for `setsw` pseudoinstruction (PR #125150)

@@ -450,6 +450,10 @@ def : InstAlias<"save", (SAVErr G0, G0, G0)>; // def : InstAlias<"set $val, $rd", (ORri IntRegs:$rd, (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>; def SET : AsmPseudoInst<(outs IntRegs:$rd), (ins i32imm:$val), "set $val, $rd">; +// setsw value, rd +// (tu

[llvm-branch-commits] [SPARC][IAS] Add support for `setsw` pseudoinstruction (PR #125150)

@@ -734,6 +737,69 @@ bool SparcAsmParser::expandSET(MCInst &Inst, SMLoc IDLoc, return false; } +bool SparcAsmParser::expandSETSW(MCInst &Inst, SMLoc IDLoc, + SmallVectorImpl &Instructions) { + MCOperand MCRegOp = Inst.getOperand(0); + MCOper

[llvm-branch-commits] [llvm] [SimplifyLibCalls] Add initial support for non-8-bit bytes (PR #106542)

https://github.com/s-barannikov updated https://github.com/llvm/llvm-project/pull/106542 >From 9859c07861131607e36d3de2ee0d2a9980b8d6da Mon Sep 17 00:00:00 2001 From: Sergei Barannikov Date: Wed, 28 Aug 2024 16:09:44 +0300 Subject: [PATCH] [SimplifyLibCalls] Add initial support for non-8-bit by

[llvm-branch-commits] [llvm] [IR] Account for byte width in m_PtrAdd (PR #106540)

https://github.com/s-barannikov updated https://github.com/llvm/llvm-project/pull/106540 >From 222a3b7f2ea2d730fdfb9b35a392af5078a17ad4 Mon Sep 17 00:00:00 2001 From: Sergei Barannikov Date: Thu, 29 Aug 2024 00:54:20 +0300 Subject: [PATCH] [IR] Account for byte width in m_PtrAdd The method has

[llvm-branch-commits] [llvm] [ValueTracking] Make isBytewiseValue byte width agnostic (PR #106538)

https://github.com/s-barannikov updated https://github.com/llvm/llvm-project/pull/106538 >From 9a1fad3a367f1ee9f26fc0792d3f8e63ae2d7aef Mon Sep 17 00:00:00 2001 From: Sergei Barannikov Date: Fri, 2 Aug 2024 13:14:49 +0300 Subject: [PATCH] [ValueTracking] Make isBytewiseValue byte width agnostic

[llvm-branch-commits] [llvm] [SimplifyLibCalls] Add initial support for non-8-bit bytes (PR #106542)

https://github.com/s-barannikov updated https://github.com/llvm/llvm-project/pull/106542 >From baf49339251099659d0d78881147c3a1f0407402 Mon Sep 17 00:00:00 2001 From: Sergei Barannikov Date: Wed, 28 Aug 2024 16:09:44 +0300 Subject: [PATCH] [SimplifyLibCalls] Add initial support for non-8-bit by

[llvm-branch-commits] [clang] [llvm] [ValueTracking] Add CharWidth argument to getConstantStringInfo (NFC) (PR #106541)

https://github.com/s-barannikov updated https://github.com/llvm/llvm-project/pull/106541 >From deca69bea2a9624ba5d12515f2919d88200a5eee Mon Sep 17 00:00:00 2001 From: Sergei Barannikov Date: Wed, 28 Aug 2024 23:51:13 +0300 Subject: [PATCH] [ValueTracking] Add CharWidth argument to getConstantS

[llvm-branch-commits] [llvm] [SimplifyLibCalls] Add initial support for non-8-bit bytes (PR #106542)

https://github.com/s-barannikov updated https://github.com/llvm/llvm-project/pull/106542 >From c640baf7c091c9142983c2785ded7ba8ce3cbe46 Mon Sep 17 00:00:00 2001 From: Sergei Barannikov Date: Wed, 28 Aug 2024 16:09:44 +0300 Subject: [PATCH] [SimplifyLibCalls] Add initial support for non-8-bit by

[llvm-branch-commits] [llvm] [IR] Account for byte width in m_PtrAdd (PR #106540)

https://github.com/s-barannikov updated https://github.com/llvm/llvm-project/pull/106540 >From 61be980d13607425cfb38a3ad73ae36dc794bde2 Mon Sep 17 00:00:00 2001 From: Sergei Barannikov Date: Thu, 29 Aug 2024 00:54:20 +0300 Subject: [PATCH] [IR] Account for byte width in m_PtrAdd The method has

[llvm-branch-commits] [clang] [llvm] [ValueTracking] Add CharWidth argument to getConstantStringInfo (NFC) (PR #106541)

https://github.com/s-barannikov updated https://github.com/llvm/llvm-project/pull/106541 >From d27bc3081184f9cb967c74abea62b696347f1fa5 Mon Sep 17 00:00:00 2001 From: Sergei Barannikov Date: Wed, 28 Aug 2024 23:51:13 +0300 Subject: [PATCH] [ValueTracking] Add CharWidth argument to getConstantS

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