@@ -230,8 +230,15 @@ bool DataSharingProcessor::needBarrier() {
return false;
}
-void DataSharingProcessor::insertBarrier() {
- if (needBarrier())
+void DataSharingProcessor::insertBarrier(
+mlir::omp::PrivateClauseOps *clauseOps) {
luporl wrote:
```su
https://github.com/luporl approved this pull request.
LGTM, thanks!
https://github.com/llvm/llvm-project/pull/140092
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@@ -717,6 +716,466 @@ SrcSafetyAnalysis::create(BinaryFunction &BF,
RegsToTrackInstsFor);
}
+/// A state representing which registers are safe to be used as the destination
+/// operand of an authentication instruction.
+/
@@ -985,6 +985,26 @@ inst_pacnbibsppc:
ret
.size inst_pacnbibsppc, .-inst_pacnbibsppc
+// Test that write-back forms of LDRA(A|B) instructions are handled properly.
+
+.globl inst_ldraa_wb
+.type inst_ldraa_wb,@function
+inst_ldraa_wb:
+// CH
@@ -292,13 +311,23 @@ void RegBankLegalizeHelper::lower(MachineInstr &MI,
case Ext32To64: {
const RegisterBank *RB = MRI.getRegBank(MI.getOperand(0).getReg());
MachineInstrBuilder Hi;
-
-if (MI.getOpcode() == AMDGPU::G_ZEXT) {
+switch (MI.getOpcode()) {
+c
@@ -133,6 +133,43 @@ void RegBankLegalizeHelper::widenLoad(MachineInstr &MI,
LLT WideTy,
MI.eraseFromParent();
}
+void RegBankLegalizeHelper::lowerVccExtToSel(MachineInstr &MI) {
+ Register Dst = MI.getOperand(0).getReg();
+ LLT Ty = MRI.getType(Dst);
+ Register Src = MI
@@ -70,14 +70,29 @@ define i8 @v_ashr_i8_7(i8 %value) {
}
define amdgpu_ps i8 @s_ashr_i8(i8 inreg %value, i8 inreg %amount) {
-; GCN-LABEL: s_ashr_i8:
-; GCN: ; %bb.0:
-; GCN-NEXT:s_sext_i32_i8 s0, s0
-; GCN-NEXT:s_ashr_i32 s0, s0, s1
-; GCN-NEXT:; return to
@@ -292,13 +311,23 @@ void RegBankLegalizeHelper::lower(MachineInstr &MI,
case Ext32To64: {
const RegisterBank *RB = MRI.getRegBank(MI.getOperand(0).getReg());
MachineInstrBuilder Hi;
-
-if (MI.getOpcode() == AMDGPU::G_ZEXT) {
+switch (MI.getOpcode()) {
+c
@@ -286,6 +287,25 @@ void RegBankLegalizeHelper::lowerSplitTo32(MachineInstr
&MI) {
MI.eraseFromParent();
}
+void RegBankLegalizeHelper::lowerSplitTo32Sel(MachineInstr &MI) {
+ Register Dst = MI.getOperand(0).getReg();
+ LLT DstTy = MRI.getType(Dst);
+ assert(DstTy == V4
@@ -717,6 +716,466 @@ SrcSafetyAnalysis::create(BinaryFunction &BF,
RegsToTrackInstsFor);
}
+/// A state representing which registers are safe to be used as the destination
+/// operand of an authentication instruction.
+/
@@ -562,35 +562,55 @@ class MCPlusBuilder {
return {};
}
- virtual ErrorOr getAuthenticatedReg(const MCInst &Inst) const {
-llvm_unreachable("not implemented");
-return getNoRegister();
- }
-
- virtual bool isAuthenticationOfReg(const MCInst &Inst,
-
@@ -787,19 +794,20 @@ shouldReportSigningOracle(const BinaryContext &BC, const
MCInstReference &Inst,
const SrcState &S) {
static const GadgetKind SigningOracleKind("signing oracle found");
- MCPhysReg SignedReg = BC.MIB->getSignedReg(Inst);
- if
kbeyls wrote:
> @kbeyls Looks like something went wrong with the UI, and only the "cover
> letter" was sent instead of the full review.
Ah yes, my apologies... Hopefully you can see the inline comments now...
https://github.com/llvm/llvm-project/pull/136147
OCHyams wrote:
Thanks @jmorse, that should be all nits/questions addressed now.
https://github.com/llvm/llvm-project/pull/134637
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petar-avramovic wrote:
ping. Btw there are some changes in ll tests due to
https://github.com/llvm/llvm-project/pull/131308, some instructions come to
regbankselect as s16 (used to come as s32). Probably could be fixed with some
combine in post reg bank combine (s16 AND + ZEXT to s32 -> AND s3
@@ -286,6 +287,25 @@ void RegBankLegalizeHelper::lowerSplitTo32(MachineInstr
&MI) {
MI.eraseFromParent();
}
+void RegBankLegalizeHelper::lowerSplitTo32Sel(MachineInstr &MI) {
arsenm wrote:
Spell out Select
https://github.com/llvm/llvm-project/pull/132384
@@ -372,6 +392,8 @@ void RegBankLegalizeHelper::lower(MachineInstr &MI,
return lowerS_BFE(MI);
case SplitTo32:
return lowerSplitTo32(MI);
+ case SplitTo32Sel:
arsenm wrote:
Spell out select
https://github.com/llvm/llvm-project/pull/132384
@@ -485,7 +504,8 @@ LLT
RegBankLegalizeHelper::getBTyFromID(RegBankLLTMappingApplyID ID, LLT Ty) {
case UniInVgprB64:
if (Ty == LLT::scalar(64) || Ty == LLT::fixed_vector(2, 32) ||
Ty == LLT::fixed_vector(4, 16) || Ty == LLT::pointer(0, 64) ||
-Ty == LLT:
@@ -133,6 +133,43 @@ void RegBankLegalizeHelper::widenLoad(MachineInstr &MI,
LLT WideTy,
MI.eraseFromParent();
}
+void RegBankLegalizeHelper::lowerVccExtToSel(MachineInstr &MI) {
+ Register Dst = MI.getOperand(0).getReg();
+ LLT Ty = MRI.getType(Dst);
+ Register Src = MI
@@ -133,6 +133,43 @@ void RegBankLegalizeHelper::widenLoad(MachineInstr &MI,
LLT WideTy,
MI.eraseFromParent();
}
+void RegBankLegalizeHelper::lowerVccExtToSel(MachineInstr &MI) {
+ Register Dst = MI.getOperand(0).getReg();
+ LLT Ty = MRI.getType(Dst);
+ Register Src = MI
@@ -133,6 +133,43 @@ void RegBankLegalizeHelper::widenLoad(MachineInstr &MI,
LLT WideTy,
MI.eraseFromParent();
}
+void RegBankLegalizeHelper::lowerVccExtToSel(MachineInstr &MI) {
+ Register Dst = MI.getOperand(0).getReg();
+ LLT Ty = MRI.getType(Dst);
+ Register Src = MI
https://github.com/arsenm approved this pull request.
https://github.com/llvm/llvm-project/pull/132382
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@@ -231,6 +232,23 @@ void RegBankLegalizeHelper::lowerS_BFE(MachineInstr &MI) {
MI.eraseFromParent();
}
+void RegBankLegalizeHelper::lowerSplitTo32(MachineInstr &MI) {
+ Register Dst = MI.getOperand(0).getReg();
+ LLT DstTy = MRI.getType(Dst);
+ assert(DstTy == V4S16 || D
@@ -310,7 +310,7 @@ bool
AMDGPURegBankLegalize::runOnMachineFunction(MachineFunction &MF) {
// Opcodes that support pretty much all combinations of reg banks and LLTs
// (except S1). There is no point in writing rules for them.
if (Opc == AMDGPU::G_BUILD_VECTOR ||
@@ -70,14 +70,29 @@ define i8 @v_ashr_i8_7(i8 %value) {
}
define amdgpu_ps i8 @s_ashr_i8(i8 inreg %value, i8 inreg %amount) {
-; GCN-LABEL: s_ashr_i8:
-; GCN: ; %bb.0:
-; GCN-NEXT:s_sext_i32_i8 s0, s0
-; GCN-NEXT:s_ashr_i32 s0, s0, s1
-; GCN-NEXT:; return to
@@ -171,6 +171,59 @@ void RegBankLegalizeHelper::lowerVccExtToSel(MachineInstr
&MI) {
MI.eraseFromParent();
}
+std::pair RegBankLegalizeHelper::unpackZExt(Register Reg) {
arsenm wrote:
const?
https://github.com/llvm/llvm-project/pull/132385
_
@@ -171,6 +171,59 @@ void RegBankLegalizeHelper::lowerVccExtToSel(MachineInstr
&MI) {
MI.eraseFromParent();
}
+std::pair RegBankLegalizeHelper::unpackZExt(Register Reg) {
+ auto PackedS32 = B.buildBitcast(SgprRB_S32, Reg);
+ auto Mask = B.buildConstant(SgprRB_S32, 0xf
https://github.com/OCHyams updated
https://github.com/llvm/llvm-project/pull/134637
>From 3b4ca1b09a659e575e022109fd8c607c9df3864f Mon Sep 17 00:00:00 2001
From: Orlando Cazalet-Hyams
Date: Wed, 2 Apr 2025 18:01:48 +0100
Subject: [PATCH 01/11] [KeyInstr][Clang] Assignment atom group
This patch
@@ -5985,6 +5985,15 @@ LValue CodeGenFunction::EmitBinaryOperatorLValue(const
BinaryOperator *E) {
assert(E->getOpcode() == BO_Assign && "unexpected binary l-value");
+ // This covers both LHS and RHS expressions, though nested RHS
+ // expressions may get subsequently s
@@ -0,0 +1,48 @@
+// RUN: %clang_cc1 -gkey-instructions -x c++ %s
-debug-info-kind=line-tables-only -emit-llvm -o - \
+// RUN: | FileCheck %s --implicit-check-not atomGroup --implicit-check-not
atomRank
OCHyams wrote:
Done
https://github.com/llvm/llvm-project/
@@ -5985,6 +5985,15 @@ LValue CodeGenFunction::EmitBinaryOperatorLValue(const
BinaryOperator *E) {
assert(E->getOpcode() == BO_Assign && "unexpected binary l-value");
+ // This covers both LHS and RHS expressions, though nested RHS
+ // expressions may get subsequently s
@@ -5985,6 +5985,15 @@ LValue CodeGenFunction::EmitBinaryOperatorLValue(const
BinaryOperator *E) {
OCHyams wrote:
Yeah that's right - added to the test for better coverage.
https://github.com/llvm/llvm-project/pull/134637
_
@@ -0,0 +1,34 @@
+// RUN: %clang_cc1 -gkey-instructions -x c++ %s
-debug-info-kind=line-tables-only -emit-llvm -o - \
+// RUN: | FileCheck %s --implicit-check-not atomGroup --implicit-check-not
atomRank
+
+// RUN: %clang_cc1 -gkey-instructions -x c %s
-debug-info-kind=line-tabl
@@ -0,0 +1,41 @@
+
+// RUN: %clang -gkey-instructions -x c++ %s -gmlt -gno-column-info -S
-emit-llvm -o - -ftrivial-auto-var-init=pattern \
+// RUN: | FileCheck %s --implicit-check-not atomGroup --implicit-check-not
atomRank
+
+// RUN: %clang -gkey-instructions -x c %s -gmlt -gn
@@ -0,0 +1,41 @@
+
+// RUN: %clang -gkey-instructions -x c++ %s -gmlt -gno-column-info -S
-emit-llvm -o - -ftrivial-auto-var-init=pattern \
+// RUN: | FileCheck %s --implicit-check-not atomGroup --implicit-check-not
atomRank
+
+// RUN: %clang -gkey-instructions -x c %s -gmlt -gn
@@ -5849,6 +5852,7 @@ LValue CodeGenFunction::EmitObjCIsaExpr(const ObjCIsaExpr
*E) {
LValue CodeGenFunction::EmitCompoundAssignmentLValue(
const CompoundAssignOperator *E) {
+ ApplyAtomGroup Grp(getDebugInfo());
O
https://github.com/OCHyams updated
https://github.com/llvm/llvm-project/pull/134637
>From 3b4ca1b09a659e575e022109fd8c607c9df3864f Mon Sep 17 00:00:00 2001
From: Orlando Cazalet-Hyams
Date: Wed, 2 Apr 2025 18:01:48 +0100
Subject: [PATCH 01/12] [KeyInstr][Clang] Assignment atom group
This patch
@@ -1209,6 +1213,7 @@ LValue ComplexExprEmitter::
EmitCompoundAssignLValue(const CompoundAssignOperator *E,
ComplexPairTy (ComplexExprEmitter::*Func)(const BinOpInfo&),
RValue &Val) {
+ ApplyAtomGroup Grp(CGF.getDebugInfo());
@@ -292,13 +311,23 @@ void RegBankLegalizeHelper::lower(MachineInstr &MI,
case Ext32To64: {
const RegisterBank *RB = MRI.getRegBank(MI.getOperand(0).getReg());
MachineInstrBuilder Hi;
-
-if (MI.getOpcode() == AMDGPU::G_ZEXT) {
+switch (MI.getOpcode()) {
+c
https://github.com/arsenm approved this pull request.
https://github.com/llvm/llvm-project/pull/132383
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@@ -1356,6 +1361,7 @@ LValue ComplexExprEmitter::EmitBinAssignLValue(const
BinaryOperator *E,
}
ComplexPairTy ComplexExprEmitter::VisitBinAssign(const BinaryOperator *E) {
+ ApplyAtomGroup Grp(CGF.getDebugInfo());
ComplexPairTy Val;
LValue LV = EmitBinAssignLValue(E, V
https://github.com/rampitec approved this pull request.
https://github.com/llvm/llvm-project/pull/141048
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qinkunbao wrote:
> Make Glob a vector added in parsing order
Yeah, that is needed.
> Make sections a vector added in parsing order
It is not necessary.
> duplicate entries is not a problem as they should not be common
It is not common but we need to iterate all the sections every time to ensu
arsenm wrote:
### Merge activity
* **May 22, 6:57 PM UTC**: A user started a stack merge that includes this pull
request via
[Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/141048).
https://github.com/llvm/llvm-project/pull/141048
_
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/132383
>From 649adb11ef0be72fe30d9752538f2ae1f3ff86e9 Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Thu, 8 May 2025 12:03:28 +0200
Subject: [PATCH] AMDGPU/GlobalISel: add RegBankLegalize rules for extend
Author: Ilia Kuklin
Date: 2025-05-22T17:29:24+05:00
New Revision: b2e110036df39bb33163b5cd6c8dacf9253b6b33
URL:
https://github.com/llvm/llvm-project/commit/b2e110036df39bb33163b5cd6c8dacf9253b6b33
DIFF:
https://github.com/llvm/llvm-project/commit/b2e110036df39bb33163b5cd6c8dacf9253b6b33.diff
L
@@ -310,7 +310,7 @@ bool
AMDGPURegBankLegalize::runOnMachineFunction(MachineFunction &MF) {
// Opcodes that support pretty much all combinations of reg banks and LLTs
// (except S1). There is no point in writing rules for them.
if (Opc == AMDGPU::G_BUILD_VECTOR ||
atrosinenko wrote:
@kbeyls Looks like something went wrong with the UI, and only the "cover
letter" was sent instead of the full review.
https://github.com/llvm/llvm-project/pull/136147
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kbeyls wrote:
Thanks, this mostly looks good to me.
I just left a few nit-picky questions or comments inline
https://github.com/llvm/llvm-project/pull/136147
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https://github.com/nikic closed https://github.com/llvm/llvm-project/pull/138550
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https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/132385
>From 0bc832089bf02e0069f441d70728943de51766c6 Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Mon, 14 Apr 2025 16:35:19 +0200
Subject: [PATCH] AMDGPU/GlobalISel: add RegBankLegalize rules for bit s
https://github.com/jmorse approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/134637
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https://github.com/llvm/llvm-project/pull/132383
>From ffc85074898c43ceb52c1ca458bc0fd844e84a60 Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Thu, 8 May 2025 12:03:28 +0200
Subject: [PATCH] AMDGPU/GlobalISel: add RegBankLegalize rules for extend
nikic wrote:
The LLVM 19 release is no longer supported. You'll have to apply this as a
local patch if you want to build and old LLVM 19 with a new libstdc++.
https://github.com/llvm/llvm-project/pull/138550
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https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/132385
>From 0bc832089bf02e0069f441d70728943de51766c6 Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Mon, 14 Apr 2025 16:35:19 +0200
Subject: [PATCH] AMDGPU/GlobalISel: add RegBankLegalize rules for bit s
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/132383
>From ffc85074898c43ceb52c1ca458bc0fd844e84a60 Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Thu, 8 May 2025 12:03:28 +0200
Subject: [PATCH] AMDGPU/GlobalISel: add RegBankLegalize rules for extend
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/132382
>From c08c9f0916b724d733ea47e944137e0a8952d365 Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Thu, 8 May 2025 12:02:27 +0200
Subject: [PATCH] AMDGPU/GlobalISel: add RegBankLegalize rules for AND OR
https://github.com/karolherbst updated
https://github.com/llvm/llvm-project/pull/140902
>From 19163b472984a6c3f8df599d95763794c8d9e3ec Mon Sep 17 00:00:00 2001
From: Karol Herbst
Date: Wed, 21 May 2025 15:57:38 +0200
Subject: [PATCH] [libclc] Include isnan implementation for SPIR-V targets
The
alsepkow wrote:
Reviewed but don't have approval permissions yet. LGTM!
https://github.com/llvm/llvm-project/pull/140151
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alsepkow wrote:
Reviewed but don't have approval permissions yet. LGTM!
https://github.com/llvm/llvm-project/pull/140152
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qinkunbao wrote:
Hi Vitaly,
Sorry for the late reply. I am thinking about a good solution for
https://github.com/llvm/llvm-project/pull/139772 in the past two days.
At the moment, I am thinking only the order of `Globs` and `RegExes` (Or
`Pattern`) matters. The order of `Section`, `Prefix` a
vitalybuka wrote:
> Hi Vitaly,
>
> Sorry for the late reply. I am thinking about a good solution for #139772 in
> the past two days.
>
> At the moment, I am thinking only the order of `Globs` and `RegExes` (Or
> `Pattern`) matters. The order of `Section`, `Prefix` and `Category` does not
> m
https://github.com/joaosaffran converted_to_draft
https://github.com/llvm/llvm-project/pull/138318
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https://github.com/arsenm approved this pull request.
https://github.com/llvm/llvm-project/pull/132385
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llvmbot wrote:
@llvm/pr-subscribers-hlsl
Author: Finn Plummer (inbelic)
Changes
- Implements serialization of the currently completely defined `RootElement`s,
namely `RootConstants` and `RootFlags`
- Adds unit testing for the serialization methods
Resolves: https://github.com/llvm/llvm-p
https://github.com/inbelic created
https://github.com/llvm/llvm-project/pull/141130
- Implements serialization of the currently completely defined `RootElement`s,
namely `RootConstants` and `RootFlags`
- Adds unit testing for the serialization methods
Resolves: https://github.com/llvm/llvm-pro
@@ -2869,9 +2870,23 @@ static void setLinkageForGV(llvm::GlobalValue *GV, const
NamedDecl *ND) {
GV->setLinkage(llvm::GlobalValue::ExternalWeakLinkage);
}
+static bool hasExistingGeneralizedTypeMD(llvm::Function *F) {
+ llvm::MDNode *MD = F->getMetadata(llvm::LLVMContext
@@ -2869,9 +2870,23 @@ static void setLinkageForGV(llvm::GlobalValue *GV, const
NamedDecl *ND) {
GV->setLinkage(llvm::GlobalValue::ExternalWeakLinkage);
}
+static bool hasExistingGeneralizedTypeMD(llvm::Function *F) {
+ llvm::MDNode *MD = F->getMetadata(llvm::LLVMContext
qinkunbao wrote:
Discussed with @vitalybuka offline. It turns out that Section name can be a
regular expression so the order of Section needs to be tacked (with a vector).
https://github.com/llvm/llvm-project/pull/140821
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https://github.com/llvm/llvm-project/pull/140821
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@@ -2869,9 +2870,23 @@ static void setLinkageForGV(llvm::GlobalValue *GV, const
NamedDecl *ND) {
GV->setLinkage(llvm::GlobalValue::ExternalWeakLinkage);
}
+static bool hasExistingGeneralizedTypeMD(llvm::Function *F) {
+ llvm::MDNode *MD = F->getMetadata(llvm::LLVMContext
https://github.com/ilovepi updated
https://github.com/llvm/llvm-project/pull/138065
>From 2d48537e7a270c0a1c6f463ef1118a65c40a6f27 Mon Sep 17 00:00:00 2001
From: Paul Kirth
Date: Tue, 29 Apr 2025 18:31:54 -0700
Subject: [PATCH] [clang-doc] Update serializer for improved template handling
This
https://github.com/ilovepi updated
https://github.com/llvm/llvm-project/pull/138067
>From 46795349a75a0815041e7ac3038be9c00ce8ad2b Mon Sep 17 00:00:00 2001
From: Paul Kirth
Date: Wed, 30 Apr 2025 14:20:40 -0700
Subject: [PATCH] [clang-doc] Track if a type is a template or builtin
Originally pa
https://github.com/ilovepi updated
https://github.com/llvm/llvm-project/pull/138064
>From 5e56a521547f6e5b309fcfd65f5ad459a03f9abc Mon Sep 17 00:00:00 2001
From: Paul Kirth
Date: Wed, 30 Apr 2025 08:13:46 -0700
Subject: [PATCH] [clang-doc] Implement setupTemplateValue for
HTMLMustacheGenerator
https://github.com/ilovepi updated
https://github.com/llvm/llvm-project/pull/138066
>From e94b231dbca9073da99f616516e21350d1136168 Mon Sep 17 00:00:00 2001
From: Paul Kirth
Date: Tue, 29 Apr 2025 18:08:03 -0700
Subject: [PATCH] [clang-doc] Update clang-doc tool to enable mustache
templates
Th
https://github.com/ilovepi updated
https://github.com/llvm/llvm-project/pull/138063
>From 6880c2fcb571c53ad4e21804b805e82a93077bc1 Mon Sep 17 00:00:00 2001
From: Paul Kirth
Date: Wed, 30 Apr 2025 08:11:39 -0700
Subject: [PATCH] [clang-doc] Extract Info into JSON values
Split from #133161. This
https://github.com/ilovepi updated
https://github.com/llvm/llvm-project/pull/138064
>From 5e56a521547f6e5b309fcfd65f5ad459a03f9abc Mon Sep 17 00:00:00 2001
From: Paul Kirth
Date: Wed, 30 Apr 2025 08:13:46 -0700
Subject: [PATCH] [clang-doc] Implement setupTemplateValue for
HTMLMustacheGenerator
https://github.com/ilovepi updated
https://github.com/llvm/llvm-project/pull/138065
>From 2d48537e7a270c0a1c6f463ef1118a65c40a6f27 Mon Sep 17 00:00:00 2001
From: Paul Kirth
Date: Tue, 29 Apr 2025 18:31:54 -0700
Subject: [PATCH] [clang-doc] Update serializer for improved template handling
This
https://github.com/ilovepi updated
https://github.com/llvm/llvm-project/pull/138063
>From 6880c2fcb571c53ad4e21804b805e82a93077bc1 Mon Sep 17 00:00:00 2001
From: Paul Kirth
Date: Wed, 30 Apr 2025 08:11:39 -0700
Subject: [PATCH] [clang-doc] Extract Info into JSON values
Split from #133161. This
https://github.com/ilovepi updated
https://github.com/llvm/llvm-project/pull/138066
>From e94b231dbca9073da99f616516e21350d1136168 Mon Sep 17 00:00:00 2001
From: Paul Kirth
Date: Tue, 29 Apr 2025 18:08:03 -0700
Subject: [PATCH] [clang-doc] Update clang-doc tool to enable mustache
templates
Th
https://github.com/ilovepi updated
https://github.com/llvm/llvm-project/pull/138067
>From 46795349a75a0815041e7ac3038be9c00ce8ad2b Mon Sep 17 00:00:00 2001
From: Paul Kirth
Date: Wed, 30 Apr 2025 14:20:40 -0700
Subject: [PATCH] [clang-doc] Track if a type is a template or builtin
Originally pa
jschueller wrote:
some of it is fixed by #110932
https://github.com/llvm/llvm-project/pull/138550
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Author: Michele Scuttari
Date: 2025-05-22T09:12:32+02:00
New Revision: 06eb7d7fe399ab4a5fbd289afa35f12ba008685f
URL:
https://github.com/llvm/llvm-project/commit/06eb7d7fe399ab4a5fbd289afa35f12ba008685f
DIFF:
https://github.com/llvm/llvm-project/commit/06eb7d7fe399ab4a5fbd289afa35f12ba008685f.di
atrosinenko wrote:
@jacobbramley As far as I can see, one possible reason for some control flow
not to be detected is that BOLT does not detect jump tables correctly on
AArch64. When I tried to debug this some time ago, it looked to me like branch
instructions related to jump tables are analyz
https://github.com/mydeveloperday approved this pull request.
https://github.com/llvm/llvm-project/pull/141004
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mydeveloperday wrote:
I'm good with merging
https://github.com/llvm/llvm-project/pull/141002
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https://github.com/mydeveloperday approved this pull request.
https://github.com/llvm/llvm-project/pull/141002
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https://github.com/arsenm created
https://github.com/llvm/llvm-project/pull/141048
This makes little difference in the final output, as we manage to form this
after these are lowered to the _ieee operations. This does result in fewer steps
in the DAG, and helps prepare for changing the handling
https://github.com/arsenm ready_for_review
https://github.com/llvm/llvm-project/pull/141048
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arsenm wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/141048?utm_source=stack-comment-downstack-mergeability-warning";
llvmbot wrote:
@llvm/pr-subscribers-backend-amdgpu
Author: Matt Arsenault (arsenm)
Changes
This makes little difference in the final output, as we manage to form this
after these are lowered to the _ieee operations. This does result in fewer steps
in the DAG, and helps prepare for changing
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/132382
>From 5b98486a1016600094a409d22a136be94456c79d Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Thu, 8 May 2025 12:02:27 +0200
Subject: [PATCH] AMDGPU/GlobalISel: add RegBankLegalize rules for AND OR
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/132383
>From 649adb11ef0be72fe30d9752538f2ae1f3ff86e9 Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Thu, 8 May 2025 12:03:28 +0200
Subject: [PATCH] AMDGPU/GlobalISel: add RegBankLegalize rules for extend
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/132385
>From cb28f826ba50fd242b19272583488a049d7e2fc3 Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Mon, 14 Apr 2025 16:35:19 +0200
Subject: [PATCH] AMDGPU/GlobalISel: add RegBankLegalize rules for bit s
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/132385
>From cb28f826ba50fd242b19272583488a049d7e2fc3 Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Mon, 14 Apr 2025 16:35:19 +0200
Subject: [PATCH] AMDGPU/GlobalISel: add RegBankLegalize rules for bit s
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/132382
>From 5b98486a1016600094a409d22a136be94456c79d Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Thu, 8 May 2025 12:02:27 +0200
Subject: [PATCH] AMDGPU/GlobalISel: add RegBankLegalize rules for AND OR
petar-avramovic wrote:
ping
https://github.com/llvm/llvm-project/pull/132383
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https://github.com/hekota updated
https://github.com/llvm/llvm-project/pull/140937
>From 3f882eb22c0035e5f9dfe7b7324fb44a7a66dea8 Mon Sep 17 00:00:00 2001
From: Helena Kotas
Date: Wed, 21 May 2025 09:18:02 -0700
Subject: [PATCH 1/4] [DirectX] Update resource type names in DXIL metadata to
incl
https://github.com/jmorse edited
https://github.com/llvm/llvm-project/pull/134646
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