Rendering to a linear depth buffer on gen4 is causing a GPU hang in the
CI system. Until a better explanation is found, assume that errata is
applicable to all gen4 platforms.
Fixes fbe01625f6bf2cef6742e1ff0d3d44a2afec003e
("i965/miptree: Share tiling_flags in miptree_create").
Reported-by: Mark
On Fri, Jul 13, 2018 at 01:01:27PM +0300, Pohjolainen, Topi wrote:
> On Wed, Jul 11, 2018 at 09:27:23PM -0700, Nanley Chery wrote:
> > The current behavior masked two bugs where the flag was not set to true
> > after modifying the stencil texture. One case was a regression
On Thu, Jul 12, 2018 at 06:35:06PM +0100, Chris Wilson wrote:
> Quoting Nanley Chery (2018-07-12 18:28:16)
> > Retile miptrees to a linear tiling less often. Retiling can cause issues
> > with imported BOs.
> >
> > Bugzilla: https://bugs.freedesktop.org/show_bug.
We'd like to reuse this helper.
Cc:
---
src/mesa/drivers/dri/i965/intel_blit.c| 12 ++--
src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 10 ++
2 files changed, 12 insertions(+), 10 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_blit.c
Drop an if statement whose predicate never evaluates to true. row_pitch
belongs to a surface with non-linear tiling. According to
isl_calc_tiled_min_row_pitch, the pitch is a multiple of the tile width.
By looking at isl_tiling_get_info, we see that non-linear tilings have
widths greater than or
Retile miptrees to a linear tiling less often. Retiling can cause issues
with imported BOs.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106738
Suggested-by: Chris Wilson
Cc:
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 12 ++--
1 file changed, 6 insertions(+), 6
The current behavior masked two bugs where the flag was not set to true
after modifying the stencil texture. One case was a regression
introduced with commit bdbb527a65fc729e7a9319ae67de60d03d06c3fd and
another was a bug in the depthstencil mapping code. These have since
been fixed.
To prevent
On Thu, Jun 14, 2018 at 10:50:57PM +0300, Eleni Maria Stea wrote:
> On 06/14/2018 10:27 PM, Nanley Chery wrote:
>
> > +Jason, Ken
> >
> > Hello,
> >
> > I recently did some miptree work relating to the r8stencil_mt and I
> > think I now have a mor
These buffer objects are never accessed with the CPU.
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index
On Fri, Jul 06, 2018 at 01:29:29PM -0700, Nanley Chery wrote:
> On Fri, Jul 06, 2018 at 03:36:01PM +0300, Pohjolainen, Topi wrote:
> > On Tue, Jun 12, 2018 at 12:21:52PM -0700, Nanley Chery wrote:
> > > This series fixes a couple stencil texturing bugs on HSW and
> > >
On Fri, Jul 06, 2018 at 03:36:01PM +0300, Pohjolainen, Topi wrote:
> On Tue, Jun 12, 2018 at 12:21:52PM -0700, Nanley Chery wrote:
> > This series fixes a couple stencil texturing bugs on HSW and
> > cache-tracking for certain stencil BOs on all platforms.
> >
> > Na
On Fri, Jul 06, 2018 at 03:21:31PM +0300, Pohjolainen, Topi wrote:
> On Fri, Jul 06, 2018 at 03:17:14PM +0300, Pohjolainen, Topi wrote:
> > On Tue, Jun 12, 2018 at 12:22:02PM -0700, Nanley Chery wrote:
> > > ---
> > > src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 40 +
On Mon, Jun 18, 2018 at 03:42:13PM -0700, Nanley Chery wrote:
> On Thu, Jun 14, 2018 at 07:50:54PM +0100, Chris Wilson wrote:
> > Quoting Nanley Chery (2018-06-14 19:46:09)
> > > On Thu, Jun 14, 2018 at 10:01:18AM -0700, Nanley Chery wrote:
> > > > On Thu, Jun 14, 20
On Fri, Jun 15, 2018 at 08:11:57AM +0300, Tapani Pälli wrote:
> Patch sets additional formats renderable and enables the extension
> when OpenGL ES 3.1 is supported.
>
> v2: instead of dummy_true, have a separate toggle for extension
> (Eric Anholt)
>
> Signed-off-by: Tapani Pälli
> ---
>
to get any info on other apps? Either way, more testing is
good.
This patch is
Reviewed-by: Nanley Chery
> --Jason
>
> On Tue, Feb 20, 2018 at 1:52 PM, Jason Ekstrand
> wrote:
>
> > We have to do resolves whenever we go into the general layout for these
> > images. H
On Thu, Jun 14, 2018 at 07:50:54PM +0100, Chris Wilson wrote:
> Quoting Nanley Chery (2018-06-14 19:46:09)
> > On Thu, Jun 14, 2018 at 10:01:18AM -0700, Nanley Chery wrote:
> > > On Thu, Jun 14, 2018 at 04:18:30PM +0300, Martin Peres wrote:
> > > > This fixes scre
On Thu, Jun 07, 2018 at 09:34:41AM +0300, Eleni Maria Stea wrote:
> Gen 7 GPUs store the compressed EAC/ETC2 images in other non-compressed
> formats that can render. When GetCompressed* functions are called, the
> pixels are returned in the non-compressed format that is used for the
> rendering.
On Thu, Jun 14, 2018 at 10:01:18AM -0700, Nanley Chery wrote:
> On Thu, Jun 14, 2018 at 04:18:30PM +0300, Martin Peres wrote:
> > This fixes screenshots using 8k+ wide display setups in modesetting.
> >
> > Chris Wilson even recommended the changes in intel_mipmap_tree.c
&
On Thu, Jun 14, 2018 at 04:18:30PM +0300, Martin Peres wrote:
> This fixes screenshots using 8k+ wide display setups in modesetting.
>
> Chris Wilson even recommended the changes in intel_mipmap_tree.c
> should read 131072 instead of 65535, but I for sure got confused by
> his explanation.
>
>
On Wed, Jun 13, 2018 at 09:44:14AM +0300, Pohjolainen, Topi wrote:
> On Tue, Jun 12, 2018 at 12:22:03PM -0700, Nanley Chery wrote:
> > Enable a future patch to create the r8stencil_mt in this function.
> > ---
> > src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 48 +-
On Wed, Jun 13, 2018 at 09:39:08AM +0300, Pohjolainen, Topi wrote:
> On Tue, Jun 12, 2018 at 12:22:02PM -0700, Nanley Chery wrote:
> > ---
> > src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 40 ---
> > 1 file changed, 26 insertions(+), 14 deletions(-)
>
On Wed, Jun 13, 2018 at 09:33:41AM +0300, Pohjolainen, Topi wrote:
> On Tue, Jun 12, 2018 at 12:22:00PM -0700, Nanley Chery wrote:
> > ---
> > src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 30 +--
> > 1 file changed, 15 insertions(+), 15 deletions(-)
>
On Wed, Jun 13, 2018 at 09:25:02AM +0300, Pohjolainen, Topi wrote:
> On Tue, Jun 12, 2018 at 12:21:56PM -0700, Nanley Chery wrote:
> > Fix the case where only stencil writes are enabled on a depth stencil
>
> Isn't this an issue even when depth writes are enabled? Both would ad
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 40 ---
1 file changed, 26 insertions(+), 14 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index cfb83d15ecc..5e00da86d32 100644
---
This enum constant was introduced to enable blit maps with intel_miptree_create
da2880bea05bfc87109477ab026a7f5401fc8f0c. Now that such maps use the more
direct make_surface function which allows you to specify the tiling directly,
the constant is no longer being used.
---
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 11 ---
1 file changed, 4 insertions(+), 7 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 97de30076e0..cfb83d15ecc 100644
---
Enable a future patch to create the r8stencil_mt in this function.
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 48 +--
1 file changed, 12 insertions(+), 36 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 30 +--
1 file changed, 15 insertions(+), 15 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 03628e3fd9f..97de30076e0 100644
---
The current behavior masked two bugs where the flag was not set to true
after modifying the stencil texture. One case was a regression
introduced with commit bdbb527a65fc729e7a9319ae67de60d03d06c3fd and
another was a bug in the depthstencil mapping code. These have since
been fixed.
To prevent
Fixes the regresion introduced with commit
bdbb527a65fc729e7a9319ae67de60d03d06c3fd
"i965: Use ISL for emitting depth/stencil/hiz state on gen6+"
Found by inspection.
Prevents regressing the piglit test, fbo-depth-array stencil-draw, later
on in this series.
Cc: Jason Ekstrand
---
Found by initializing the r8stencil_needs_update to false in
make_separate_stencil_surface.
Prevents regressing the piglit test arb_stencil_texturing-draw, later on
in the series.
Cc: Jordan Justen
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 4 +++-
1 file changed, 3 insertions(+), 1
Do this so that we don't have to special case linearly-tiled depth
buffers in miptree_create.
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
Note that the separate stencil miptree now has the same alloc_flag as
the depth component.
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 29 ---
1 file changed, 6 insertions(+), 23 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
Fix the case where only stencil writes are enabled on a depth stencil
texture. Found by inspection.
---
I'm looking into writing a test for this.
src/mesa/drivers/dri/i965/brw_draw.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_draw.c
This series fixes a couple stencil texturing bugs on HSW and
cache-tracking for certain stencil BOs on all platforms.
Nanley Chery (13):
i965: Set the r8stencil flag in miptree_finish_write
i965/miptree: Set the r8stencil flag in map_depthstencil
i965/draw: Set the r8stencil flag after
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 15 +++
1 file changed, 7 insertions(+), 8 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index ca909c3fab7..03628e3fd9f 100644
---
This seems to be the most appropriate place.
---
src/mesa/drivers/dri/i965/brw_blorp.c | 6 +-
src/mesa/drivers/dri/i965/brw_clear.c | 8
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 4 +++-
src/mesa/drivers/dri/i965/intel_tex_image.c | 3 ---
4 files changed, 4
On Fri, May 11, 2018 at 04:55:27PM -0700, Nanley Chery wrote:
> On Mon, Mar 19, 2018 at 11:26:59AM -0700, Francisco Jerez wrote:
> > Instead of directly using intel_obj->buffer. Among other things
> > intel_bufferobj_buffer() will update intel_buffer_object::
> > gpu
On Wed, May 30, 2018 at 10:57:05PM +0100, Chris Wilson wrote:
> Quoting Nanley Chery (2018-05-30 21:44:35)
> > We previously retiled miptrees to work around limitations of the BLT
> > engine. BLORP fallbacks can overcome these, so we no longer have need
> > for retiling.
>
The BLORP fallback can handle large row pitches. A patch is on the
piglit mailing list to modify the test,
piglit.spec.!opengl 1_1.getteximage-simple, to hit this case.
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 15 +--
1 file changed, 1 insertion(+), 14 deletions(-)
diff
We previously retiled miptrees to work around limitations of the BLT
engine. BLORP fallbacks can overcome these, so we no longer have need
for retiling.
Removing retiling fixes a number of problems. If the row pitch was too
wide for the BLT engine, we retiled to linear and had the following
We're going to enable blit maps on row pitches greater than the BLT
engine's limit. Make blit maps fall back to BLORP which can handle such
pitches.
---
src/mesa/drivers/dri/i965/intel_blit.c| 6 +
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 24 +--
2 files
On Tue, May 22, 2018 at 10:45:55AM -0700, Ian Romanick wrote:
> On 05/22/2018 09:03 AM, Nanley Chery wrote:
> > On Wed, Jan 03, 2018 at 10:41:43AM -0800, Ian Romanick wrote:
> >> From: Ian Romanick <ian.d.roman...@intel.com>
> >>
> >> Every other caller of
_bytes(obj->_BufferObjectFormat);
> const unsigned buffer_size = (!obj->BufferObject ? 0 :
> obj->BufferObject->Size);
> + const unsigned buffer_offset = MIN2(buffer_size, obj->BufferOffset);
>
Clamping the offset is a
17.3" <mesa-sta...@lists.freedesktop.org>
I think this fixes tag should catch all relevant stable releases:
Fixes: 67b53ee4183 "i965: Represent depth surfaces with isl"
With at least the fixes tag, this patch is
Reviewed-by: Nanley Chery <nanley.g.ch...@intel.com>
> -
On Tue, May 22, 2018 at 01:09:18PM +0200, Juan A. Suarez Romero wrote:
> On Thu, 2018-05-03 at 14:22 -0700, Nanley Chery wrote:
> > On Thu, May 03, 2018 at 12:40:49PM -0700, Jason Ekstrand wrote:
> > > Good catch. Rb
> > >
> >
> > Thanks!
> >
> &g
ttps://www.mesa3d.org/submittingpatches.html).
> Bug: https://github.com/mesa3d/mesa/pull/5
> Bug: https://bugs.launchpad.net/ubuntu/+source/gnome-shell/+bug/1760415
I'd also add
Fixes: 67b53ee4183 "i965: Represent depth surfaces with isl"
With those changes, this patch is
Reviewed-by: N
On Thu, May 17, 2018 at 09:25:18AM -0700, Dylan Baker wrote:
> Quoting Nanley Chery (2018-05-03 12:03:48)
> > Before this patch, if we failed to initialize an MCS buffer, we'd
> > end up in a state in which the miptree thinks it has an MCS buffer,
> > but doesn't. We also leak
On Thu, May 17, 2018 at 07:44:34AM +0300, Pohjolainen, Topi wrote:
> On Wed, May 16, 2018 at 09:33:34AM -0700, Nanley Chery wrote:
> > On Wed, May 16, 2018 at 09:11:38AM +0300, Pohjolainen, Topi wrote:
> > > On Wed, May 09, 2018 at 10:47:24AM -0700, Nanley Chery wrote:
Synchronize the requirements listed in isl_surf_get_ccs_surf with
intel_miptree_supports_ccs by importing a restriction from ISL. Some
implications:
* We successfully create every aux_surf in alloc_aux
* We only return false from alloc_aux if we run out of memory
---
This is useful for every user of ISL. Drop the comment along the way to
match similar functions in ISL.
---
src/intel/isl/isl.c | 2 ++
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 2 --
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git
intel_miptree_supports_{ccs,mcs,hiz} ensures the format is valid for the
color or depth miptree before the miptree is assigned an aux_usage.
alloc_aux switches on the aux_usage so don't assert that the format is
valid.
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 5 -
1 file changed, 5
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 6 +-
1 file changed, 1 insertion(+), 5 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 0289f4f7e4c..1a797326a82 100644
---
uffer fast-clear"
which will be pushed soon.
Nanley Chery (4):
i965: Make get_ccs_surf succeed in alloc_aux
i965/miptree: Simplify the switch in supports_ccs
i965/miptree: Remove format assertion in alloc_aux
i965: isl: Move the MCS gen7+ assertion into ISL
src/intel
On Wed, May 16, 2018 at 09:11:38AM +0300, Pohjolainen, Topi wrote:
> On Wed, May 09, 2018 at 10:47:24AM -0700, Nanley Chery wrote:
> > v2: Inline the switch statement (Jason)
> >
> > Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net>
> > ---
> > src/mesa/dr
On Wed, May 16, 2018 at 09:02:51AM +0300, Pohjolainen, Topi wrote:
> On Tue, May 08, 2018 at 02:05:37PM -0700, Nanley Chery wrote:
> > On Tue, May 08, 2018 at 08:31:39AM +0300, Pohjolainen, Topi wrote:
> > > On Mon, May 07, 2018 at 10:11:39AM -0700, Nanley Chery wrote:
> >
On Fri, May 11, 2018 at 05:09:57PM -0700, Francisco Jerez wrote:
> Hey Nanley,
>
> Nanley Chery <nanleych...@gmail.com> writes:
>
> > On Mon, Mar 19, 2018 at 11:26:58AM -0700, Francisco Jerez wrote:
> >> Otherwise the specified surface state will allow
ou think about leaving the bug open until we create a piglit
test to reproduce it? We could create a new bug otherwise.
> Reported-by: Nanley Chery <nanleych...@gmail.com>
> Cc: mesa-sta...@lists.freedesktop.org
> ---
> src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 8 +---
On Mon, Mar 19, 2018 at 11:26:58AM -0700, Francisco Jerez wrote:
> Otherwise the specified surface state will allow the GPU to access
> memory up to BufferOffset bytes past the end of the buffer. Found by
> inspection.
>
> Cc: mesa-sta...@lists.freedesktop.org
> ---
>
g/show_bug.cgi?id=106481
> ---
> src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 54
> ++--
> 1 file changed, 32 insertions(+), 22 deletions(-)
This patch is
Reviewed-by: Nanley Chery <nanley.g.ch...@intel.com>
>
> diff --git a/src/mesa/drivers/dri/i
show_bug.cgi?id=106465
> ---
> src/mesa/main/shaderimage.c | 25 -
> 1 file changed, 12 insertions(+), 13 deletions(-)
>
This patch is
Reviewed-by: Nanley Chery <nanley.g.ch...@intel.com>
> diff --git a/src/mesa/main/shaderimage.c b/src/mesa/m
v2: Inline the switch statement (Jason)
Reviewed-by: Jason Ekstrand
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 90 ---
1 file changed, 38 insertions(+), 52 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
one I
> didn't expect to like but when I saw it, it completely changed my mind.
> That seems like exactly the right way to do this.
>
Awesome. Thanks!
-Nanley
> --Jason
>
> On Thu, May 3, 2018 at 12:03 PM, Nanley Chery <nanleych...@gmail.com> wrote:
>
> > M
On Tue, May 08, 2018 at 04:52:09PM -0700, Jason Ekstrand wrote:
> On Thu, May 3, 2018 at 12:03 PM, Nanley Chery <nanleych...@gmail.com> wrote:
>
> > There isn't much that changes between the aux allocation functions.
> > Remove the duplicated code.
> > ---
On Tue, May 08, 2018 at 03:33:22PM -0700, Jason Ekstrand wrote:
> On Thu, May 3, 2018 at 12:03 PM, Nanley Chery <nanleych...@gmail.com> wrote:
>
> > Before this patch, if we failed to initialize an MCS buffer, we'd
> > end up in a state in which the miptree thi
On Tue, May 08, 2018 at 09:24:19AM +0300, Pohjolainen, Topi wrote:
> On Thu, May 03, 2018 at 12:04:00PM -0700, Nanley Chery wrote:
> > Although BLORP currently does the update when performing a fast clear,
> > it's simpler to do it ourselves. Remove the dependency on BLORP.
>
On Tue, May 08, 2018 at 08:43:20AM +0300, Pohjolainen, Topi wrote:
> On Mon, May 07, 2018 at 11:04:20AM -0700, Nanley Chery wrote:
> > On Mon, May 07, 2018 at 03:06:29PM +0300, Pohjolainen, Topi wrote:
> > > On Thu, May 03, 2018 at 12:03:53PM -0700, Nanley Chery wrote:
>
On Tue, May 08, 2018 at 08:22:39AM +0300, Pohjolainen, Topi wrote:
> On Mon, May 07, 2018 at 11:35:39AM -0700, Nanley Chery wrote:
> > On Mon, May 07, 2018 at 10:10:16AM -0700, Nanley Chery wrote:
> > > On Mon, May 07, 2018 at 11:51:50AM +0300, Pohjolainen, Topi wrote:
> >
On Thu, May 03, 2018 at 12:03:52PM -0700, Nanley Chery wrote:
> A name of "aux-miptree" should be sufficient.
I should mention that I went over this some teamates on #intel-3d and
received no objections.
Another comment below.
> ---
> src/mesa/drivers/dri/i965/inte
On Tue, May 08, 2018 at 08:31:39AM +0300, Pohjolainen, Topi wrote:
> On Mon, May 07, 2018 at 10:11:39AM -0700, Nanley Chery wrote:
> > On Mon, May 07, 2018 at 11:30:15AM +0300, Pohjolainen, Topi wrote:
> > > On Thu, May 03, 2018 at 12:03:51PM -0700, Nanley Chery wrote:
> >
On Mon, May 07, 2018 at 11:12:26AM -0700, Nanley Chery wrote:
> On Mon, May 07, 2018 at 03:36:54PM +0300, Pohjolainen, Topi wrote:
> > On Thu, May 03, 2018 at 12:03:55PM -0700, Nanley Chery wrote:
> > > We're going to delete intel_miptree_alloc_ccs() in the next commit. With
On Mon, May 07, 2018 at 10:10:16AM -0700, Nanley Chery wrote:
> On Mon, May 07, 2018 at 11:51:50AM +0300, Pohjolainen, Topi wrote:
> > On Fri, May 04, 2018 at 11:04:40AM -0700, Nanley Chery wrote:
> > > On Fri, May 04, 2018 at 10:00:32AM -0700, Nanley Chery wrote:
> >
On Mon, May 07, 2018 at 04:12:24PM +0300, Pohjolainen, Topi wrote:
> On Thu, May 03, 2018 at 12:03:56PM -0700, Nanley Chery wrote:
> > There isn't much that changes between the aux allocation functions.
> > Remove the duplicated code.
> > ---
> > src/mesa/drivers/d
On Mon, May 07, 2018 at 03:36:54PM +0300, Pohjolainen, Topi wrote:
> On Thu, May 03, 2018 at 12:03:55PM -0700, Nanley Chery wrote:
> > We're going to delete intel_miptree_alloc_ccs() in the next commit. With
> > that in mind, replace the use of this function in
> >
On Mon, May 07, 2018 at 03:06:29PM +0300, Pohjolainen, Topi wrote:
> On Thu, May 03, 2018 at 12:03:53PM -0700, Nanley Chery wrote:
> > We have enough information to determine the optimal flags internally.
> > ---
> > src/mesa/drivers/dri/i965/int
On Mon, May 07, 2018 at 11:30:15AM +0300, Pohjolainen, Topi wrote:
> On Thu, May 03, 2018 at 12:03:51PM -0700, Nanley Chery wrote:
> > The indirect clear color isn't correctly tracked in
> > intel_miptree::fast_clear_color. The initial value of ::fast_clear_color
>
On Mon, May 07, 2018 at 11:51:50AM +0300, Pohjolainen, Topi wrote:
> On Fri, May 04, 2018 at 11:04:40AM -0700, Nanley Chery wrote:
> > On Fri, May 04, 2018 at 10:00:32AM -0700, Nanley Chery wrote:
> > > On Fri, May 04, 2018 at 09:42:34AM -0700, Nanley Chery wrote:
> >
On Mon, May 07, 2018 at 09:49:01AM +0300, Tapani Pälli wrote:
>
> On 05/04/2018 05:59 PM, Nanley Chery wrote:
> > On Fri, May 04, 2018 at 09:03:32AM +0300, Tapani Pälli wrote:
> > > Hi Nanley;
> > >
> >
> > Hey Tapani,
> >
> > > O
On Fri, May 04, 2018 at 10:00:32AM -0700, Nanley Chery wrote:
> On Fri, May 04, 2018 at 09:42:34AM -0700, Nanley Chery wrote:
> > On Thu, May 03, 2018 at 12:03:50PM -0700, Nanley Chery wrote:
> > > Add infrastructure for initializing the clear color BO.
> > > ---
>
On Fri, May 04, 2018 at 09:42:34AM -0700, Nanley Chery wrote:
> On Thu, May 03, 2018 at 12:03:50PM -0700, Nanley Chery wrote:
> > Add infrastructure for initializing the clear color BO.
> > ---
> > src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 68
> >
On Thu, May 03, 2018 at 12:03:50PM -0700, Nanley Chery wrote:
> Add infrastructure for initializing the clear color BO.
> ---
> src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 68
> ---
> 1 file changed, 31 insertions(+), 37 deletions(-)
>
> diff --g
On Fri, May 04, 2018 at 09:03:32AM +0300, Tapani Pälli wrote:
> Hi Nanley;
>
Hey Tapani,
> On 05/03/2018 10:03 PM, Nanley Chery wrote:
> > Before this patch, if we failed to initialize an MCS buffer, we'd
> > end up in a state in which the miptree thinks it has an MCS bu
On Thu, May 03, 2018 at 12:40:49PM -0700, Jason Ekstrand wrote:
> Good catch. Rb
>
Thanks!
> On May 3, 2018 12:04:59 Nanley Chery <nanleych...@gmail.com> wrote:
>
> > Before this patch, the aux_state was actually AUX_INVALID because the BO
> > was never defined.
If the aux state is CLEAR and clear color value has changed, only the
surface state must be updated. The bit-pattern in the aux buffer is
exactly the same.
---
src/mesa/drivers/dri/i965/brw_blorp.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git
With the previous patches, we now update the indirect clear color buffer
every time the clear color changes. Avoid redundant updates.
---
src/mesa/drivers/dri/i965/brw_blorp.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c
Allow callers to handle updating the indirect clear color buffer
themselves. This can reduce the number of clear color updates in the
case where a caller performs multiple fast clears with the same clear
color.
---
src/intel/blorp/blorp.h | 5 +
src/intel/blorp/blorp_genX_exec.h | 6
Reduce code duplication now and prevent it in the following commits.
---
src/mesa/drivers/dri/i965/brw_clear.c | 3 ++-
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 13 -
src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 5 -
3 files changed, 2 insertions(+), 19
This comment made more sense when it was above the calls to
intel_miptree_slice_set_needs_depth_resolve(). We stopped using these
functions at commit 554f7d6d02931ea45653c8872565d21c1678a6da
("i965: Move depth to the new resolve functions").
---
src/mesa/drivers/dri/i965/brw_clear.c | 4
1
We're going to delete intel_miptree_alloc_ccs() in the next commit. With
that in mind, replace the use of this function in
do_single_blorp_clear() with intel_miptree_alloc_aux() and move the
delayed allocation logic to it's callers.
---
src/mesa/drivers/dri/i965/brw_blorp.c | 2 +-
Reduce complexity and allow the next patch to delete some code. With
this change, clear operations will still be skipped and setting the
aux_state will cause no side-effects.
Remove the associated comment which implies an early return.
Reviewed-by: Rafael Antognolli
Although BLORP currently does the update when performing a fast clear,
it's simpler to do it ourselves. Remove the dependency on BLORP.
---
src/mesa/drivers/dri/i965/brw_clear.c | 37 ---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 13 ++
2 files
This reverts commit 1d94aa19877fb702ffacacde28ad7253cce72c97.
The next patch will make depth miptrees use the clear color setter that
was originally being used for color miptrees. Go back to using the
isl_color_value parameter because it's the same type as the
fast_clear_color field used by color
There isn't much that changes between the aux allocation functions.
Remove the duplicated code.
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 227 +++---
src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 9 -
2 files changed, 95 insertions(+), 141 deletions(-)
diff
We have enough information to determine the optimal flags internally.
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 29 +--
1 file changed, 14 insertions(+), 15 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
Drop an unused parameter.
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 9 -
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index e065c2f62e0..1de381141ea 100644
---
Before this patch, the aux_state was actually AUX_INVALID because the BO
was never defined. This was fine on single slice miptrees because we
would fast-clear the resource right after creation. For multi-slice
miptrees on SKL+ however, this results in undefined behavior when
accessing a non-base
A name of "aux-miptree" should be sufficient.
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 9 -
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index
The indirect clear color isn't correctly tracked in
intel_miptree::fast_clear_color. The initial value of ::fast_clear_color
is zero, while that of the indirect clear color is undefined or
non-zero.
Topi Pohjolainen discovered this issue with MCS buffers. This issue is
apparent when fast-clearing
Add infrastructure for initializing the clear color BO.
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 68 ---
1 file changed, 31 insertions(+), 37 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
Before this patch, if we failed to initialize an MCS buffer, we'd
end up in a state in which the miptree thinks it has an MCS buffer,
but doesn't. We also leaked the clear_color_bo if it existed.
With this patch, we now free the miptree aux buffer resources and let
intel_miptree_alloc_mcs() know
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