Re: [Mesa-dev] [PATCH 1/3] mesa/main/shaderapi: Use generate_sha1() unconditionally

On 05/17/2018 02:00 PM, Benedikt Schemmer wrote: Ok I found the commit. But it says: "Until we have a proper fix." So this would be a good time I guess ;) Agreed, using ENABLE_SHADER_CACHE to guard some OS specifics is dirty, it should be only guarding shader cache itself. --- author

Re: [Mesa-dev] [PATCH] vulkan: update vk_icd.h to current upstream

Acked-by: Jason Ekstrand On Thu, May 17, 2018 at 10:05 PM, Tapani Pälli wrote: > Import from commit eb0c1fd on branch 'master' > of https://github.com/KhronosGroup/Vulkan-Headers.git. > > Signed-off-by: Tapani Pälli > --- >

[Mesa-dev] [PATCH] vulkan: update vk_icd.h to current upstream

Import from commit eb0c1fd on branch 'master' of https://github.com/KhronosGroup/Vulkan-Headers.git. Signed-off-by: Tapani Pälli --- include/vulkan/vk_icd.h | 67 ++--- 1 file changed, 53 insertions(+), 14 deletions(-) diff

Re: [Mesa-dev] [PATCH] vbo: remove MaxVertexAttribStride assert check.

On 15 May 2018 at 16:31, Mathias Fröhlich wrote: > Hi Dave, > > On Tuesday, 15 May 2018 07:44:44 CEST Dave Airlie wrote: >> From: Dave Airlie >> >> Some drivers (virgl) don't support GL4.4 or GLES3.1 yet, >> so never fill in this const. > > May be I

Re: [Mesa-dev] [PATCH 1/2] dri_util: Add R10G10B10{A, X}2 translation between DRI and mesa_format.

Series Reviewed-by: Tapani Pälli On 05/07/2018 06:45 PM, Miguel Casas wrote: Add R10G10B10{A,X}2 translation between mesa_format and DRI format to driGLFormatToImageFormat() and driImageFormatToGLFormat(). Bug: https://crbug.com/776093 ---

[Mesa-dev] [RFC PATCH] gallium: add interface for advanced MSAA

From: Marek Olšák The interface only uses general MSAA terms, so it's "advanced MSAA" and not something vendor-specific. It's a proper subset of EQAA, and a proper superset of CSAA, so it's neither. Changes: - pipe_resource is changed - is_format_supported is changed - a

Re: [Mesa-dev] [PATCH] radeonsi: skip ES output stores for undefined output components

Tested-by: Dieter Nützel on RX580 with UH, UV, glmark2, Blender 2.79, FreeCAD 0.17, Gimp 2.10, digikam 5.9.0, Krita 4.0.3 and some Mesa-demos Dieter Am 18.05.2018 00:14, schrieb Marek Olšák: From: Marek Olšák ---

Re: [Mesa-dev] [PATCH] draw: get rid of special logic to not emit null tris

Tested-by: Dieter Nützel on RX580 with UH, UV, glmark2, Blender 2.79, FreeCAD 0.17, Gimp 2.10, digikam 5.9.0, Krita 4.0.3 and some Mesa-demos Dieter Am 17.05.2018 18:30, schrieb srol...@vmware.com: From: Roland Scheidegger I've confirmed after

Re: [Mesa-dev] [PATCH 6/6] radeonsi: set DB_EQAA.MAX_ANCHOR_SAMPLES correctly

For the series: Tested-by: Dieter Nützel on RX580 with UH, UV, glmark2, Blender 2.79, FreeCAD 0.17, Gimp 2.10, digikam 5.9.0, Krita 4.0.3 and some Mesa-demos Dieter 17.05.2018 03:47, schrieb Marek Olšák: From: Marek Olšák ---

[Mesa-dev] [PATCH 1/1] travis: Adapt to radeonsi dropping support for LLVM 4

meson Vulkan, Clover, and autotools Vulkan need to be switched to llvm 5 Fixes: f9eb1ef870eba9fdacf9a8cbd815ec3bff81db05 Signed-off-by: Jan Vesely --- .travis.yml | 14 +++--- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/.travis.yml b/.travis.yml

[Mesa-dev] [PATCH 1/2] r600/compute: Remove unused compute_memory_pool functions

Signed-off-by: Aaron Watry --- .../drivers/r600/compute_memory_pool.c| 92 --- .../drivers/r600/compute_memory_pool.h| 11 --- 2 files changed, 103 deletions(-) diff --git a/src/gallium/drivers/r600/compute_memory_pool.c

[Mesa-dev] [PATCH 2/2] r600/compute: Mark several functions as static

They're not used anywhere else, so keep them private Signed-off-by: Aaron Watry --- .../drivers/r600/compute_memory_pool.c| 35 +++ .../drivers/r600/compute_memory_pool.h| 24 - 2 files changed, 29 insertions(+), 30 deletions(-)

Re: [Mesa-dev] [PATCH] Revert "st/nir: use NIR for asm programs"

On 18/05/18 00:53, Eric Anholt wrote: This reverts commit 5c33e8c7729edd5e16020ebb8703be96523e04f2. It broke fixed function vertex programs on vc4 and v3d, and apparently caused trouble for radeonsi's NIR paths as well. Has someone reported trouble with radeonsi NIR? I'm not aware of any

[Mesa-dev] [Bug 106556] Upgrade to 18.0 completely breaks gnome-shell

https://bugs.freedesktop.org/show_bug.cgi?id=106556 Timothy Arceri changed: What|Removed |Added QA Contact|mesa-dev@lists.freedesktop.

[Mesa-dev] [Bug 61761] glPolygonOffsetEXT, OFFSET_BIAS incorrectly set to a huge number

https://bugs.freedesktop.org/show_bug.cgi?id=61761 Timothy Arceri changed: What|Removed |Added Status|NEW |RESOLVED

[Mesa-dev] [PATCH] v3d: Include v3d_drm.h path.

Fix build error. CC v3d_blit.lo In file included from v3d_blit.c:27:0: v3d_context.h:39:10: fatal error: v3d_drm.h: No such file or directory #include "v3d_drm.h" ^~~ Fixes: 8a793d42f1cc ("v3d: Switch the vc5 driver to using the finalized V3D UABI.") Signed-off-by:

[Mesa-dev] [Bug 106558] lower_x86.cpp:125:53: error: ‘x86_avx512_mask_permvar_sf_256’ is not a member of ‘llvm::Intrinsic’

https://bugs.freedesktop.org/show_bug.cgi?id=106558 Bug ID: 106558 Summary: lower_x86.cpp:125:53: error: ‘x86_avx512_mask_permvar_sf_256’ is not a member of ‘llvm::Intrinsic’ Product: Mesa Version: git

[Mesa-dev] [PATCH] radeonsi: skip ES output stores for undefined output components

From: Marek Olšák --- src/gallium/drivers/radeonsi/si_shader.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/gallium/drivers/radeonsi/si_shader.c b/src/gallium/drivers/radeonsi/si_shader.c index e8d08cd8e7f..0d24c3af10a 100644 ---

Re: [Mesa-dev] [PATCH mesa] i965: Check result of make_surface() for miptree_create

On Thu, May 17, 2018 at 01:05:13PM +0100, Eric Engestrom wrote: > From: Andrea Azzarone > > Since make_surface() can fail we need to check the result before > dereferencing it. > This line should be wrapped to 75 characters or less (see

Re: [Mesa-dev] [Mesa-stable] [PATCH 01/17] i965/miptree: Fix handling of uninitialized MCS buffers

On Thu, May 17, 2018 at 09:25:18AM -0700, Dylan Baker wrote: > Quoting Nanley Chery (2018-05-03 12:03:48) > > Before this patch, if we failed to initialize an MCS buffer, we'd > > end up in a state in which the miptree thinks it has an MCS buffer, > > but doesn't. We also leaked the clear_color_bo

Re: [Mesa-dev] [PATCH] tgsi: fix incorrect tgsi_shader_info::num_tokens computation

Oh yes, that looks quite wrong. Reviewed-by: Roland Scheidegger Am 17.05.2018 um 22:06 schrieb Brian Paul: > We were incrementing num_tokens in each loop iteration while parsing > the shader. But each call to tgsi_parse_token() can consume more than > one token (and often

Re: [Mesa-dev] [PATCH] draw: get rid of special logic to not emit null tris

On 05/17/2018 10:30 AM, srol...@vmware.com wrote: From: Roland Scheidegger I've confirmed after 77554d220d6d74b4d913dc37ea3a874e9dc550e4 we no longer need this to pass some tests from another api (as we no longer generate the bogus extra null tris in the first place). ---

Re: [Mesa-dev] [PATCH] tgsi: fix incorrect tgsi_shader_info::num_tokens computation

Reviewed-by: Neha Bhende Regards, Neha From: Brian Paul Sent: Thursday, May 17, 2018 1:06:26 PM To: mesa-dev@lists.freedesktop.org Cc: Charmaine Lee; Neha Bhende; Roland Scheidegger Subject: [PATCH] tgsi: fix incorrect

[Mesa-dev] [PATCH] tgsi: fix incorrect tgsi_shader_info::num_tokens computation

We were incrementing num_tokens in each loop iteration while parsing the shader. But each call to tgsi_parse_token() can consume more than one token (and often does). Instead, just call the tgsi_num_tokens() function. Luckily, this issue doesn't seem to effect any current users of this field

Re: [Mesa-dev] [PATCH] cmake: Bump minimum version to 3.2.

I think this is a reasonable thing to do, 3.2 is from early 2015, so it shouldn't be too much to ask for. Reviewed-by: Dylan Baker Quoting Vinson Lee (2018-05-17 11:37:12) > This build error occurs with cmake 2.8.12. > /bin/sh: BYPRODUCTS: command not found > > BYPRODUCTS

[Mesa-dev] [Bug 106556] Upgrade to 18.0 completely breaks gnome-shell

https://bugs.freedesktop.org/show_bug.cgi?id=106556 Bug ID: 106556 Summary: Upgrade to 18.0 completely breaks gnome-shell Product: Mesa Version: 18.0 Hardware: x86-64 (AMD64) OS: Linux (All) Status: NEW

Re: [Mesa-dev] [PATCH 2/2] radv: add radv_emit_shader_pointer() helper

On 05/17/2018 04:31 PM, Bas Nieuwenhuizen wrote: Do we want the new function inlined? Yeah, we can inline it. 32-bit GPU pointers won't be too intrusive in this function. Reviewed-by: Bas Nieuwenhuizen On Thu, May 17, 2018 at 2:16 PM, Samuel Pitoiset

[Mesa-dev] [Bug 106251] [PATCH] SWR driver doesn't compile with LLVM 7.0 snapshots

https://bugs.freedesktop.org/show_bug.cgi?id=106251 George Kyriazis changed: What|Removed |Added Resolution|--- |FIXED

[Mesa-dev] [Bug 101614] OSMesa 17.1.3 simd16intrin build FAIL on Win/MinGW - 'expected initializer before _simd16_setzero_ps ...'

https://bugs.freedesktop.org/show_bug.cgi?id=101614 George Kyriazis changed: What|Removed |Added Status|REOPENED|RESOLVED

[Mesa-dev] [ANNOUNCE] mesa 18.0.4

Mesa 18.0.4 is now available. In this release we have: r600 driver gets a fix for constant buffer boounds, which fixes rendering bugs in Trine and Witcher 1. Several fixes for RADV driver: fixes around alpha channel in Pre-Vega, fix in multisample image copies, and fixes around multilayer

[Mesa-dev] [PATCH] cmake: Bump minimum version to 3.2.

This build error occurs with cmake 2.8.12. /bin/sh: BYPRODUCTS: command not found BYPRODUCTS is not available until cmake 3.2. https://cmake.org/cmake/help/v3.2/release/3.2.html Fixes: 2f02cf0d4c2d ("Generate xml for builtin profiles") Bugzilla:

Re: [Mesa-dev] [PATCH 2/4] mesa: Remove flush_vertrices argument from VAO methods.

Hi, On Thursday, 17 May 2018 16:03:39 CEST Brian Paul wrote: > In the subject line "flush_vertices" > > For this series, Reviewed-by: Brian Paul > > More nice clean-ups! Thank you! I have changed the subject ... And that part is pushed - thanks for the review! best

[Mesa-dev] [PATCH] draw: get rid of special logic to not emit null tris

From: Roland Scheidegger I've confirmed after 77554d220d6d74b4d913dc37ea3a874e9dc550e4 we no longer need this to pass some tests from another api (as we no longer generate the bogus extra null tris in the first place). --- src/gallium/auxiliary/draw/draw_pipe_clip.c | 38

Re: [Mesa-dev] [Mesa-stable] [PATCH 01/17] i965/miptree: Fix handling of uninitialized MCS buffers

Quoting Nanley Chery (2018-05-03 12:03:48) > Before this patch, if we failed to initialize an MCS buffer, we'd > end up in a state in which the miptree thinks it has an MCS buffer, > but doesn't. We also leaked the clear_color_bo if it existed. > > With this patch, we now free the miptree aux

Re: [Mesa-dev] [PATCH] mesa: drop GL_EXT_polygon_offset support

Reviewed-by: Marek Olšák Marek On Fri, May 11, 2018 at 1:38 AM, Timothy Arceri wrote: > glPolygonOffset() has been part of the GL standard since 1.1. Also > niether AMD or Nvidia support this in their binary drivers. > > Bugzilla:

Re: [Mesa-dev] [PATCH 2/6] radeonsi: disable primitive binning for all blitter ops

On Thu, May 17, 2018 at 4:35 AM, Grazvydas Ignotas wrote: > On Thu, May 17, 2018 at 4:47 AM, Marek Olšák wrote: > > From: Marek Olšák > > > > same as Vulkan. > > Ambiguous. Did you mean amdvlk? > Of course. Marek

[Mesa-dev] [Bug 78097] glUniform1ui and friends not supported by display lists

https://bugs.freedesktop.org/show_bug.cgi?id=78097 --- Comment #4 from Lionel Landwerlin --- Arg apologies, I was running against the wrong version of Mesa. -- You are receiving this mail because: You are the assignee for the

Re: [Mesa-dev] [PATCH 1/5] swr/rast: Remove unneeded virtual from methods

Whole series Reviewed-By: George Kyriazis > Thanks! On May 16, 2018, at 11:14 AM, Alok Hota > wrote: --- src/gallium/drivers/swr/rasterizer/jitter/JitManager.h | 4 ++-- 1 file

[Mesa-dev] [Bug 78097] glUniform1ui and friends not supported by display lists

https://bugs.freedesktop.org/show_bug.cgi?id=78097 Lionel Landwerlin changed: What|Removed |Added Resolution|---

[Mesa-dev] [Bug 78097] glUniform1ui and friends not supported by display lists

https://bugs.freedesktop.org/show_bug.cgi?id=78097 --- Comment #3 from Lionel Landwerlin --- $ ./bin/gl-3.0-dlist-uint-uniforms -auto -fbo Testing glUniformui GL_COMPILE: scalar mode pre-initialize compiling post-compile verify

[Mesa-dev] [Bug 78097] glUniform1ui and friends not supported by display lists

https://bugs.freedesktop.org/show_bug.cgi?id=78097 Lionel Landwerlin changed: What|Removed |Added Status|RESOLVED

Re: [Mesa-dev] [PATCH v2 0/6] broadcom/vc4: Native fence fd support

Stefan Schake writes: > v2 drops the submit flags, directly moves in fence handling to the > job submit function and queries for the syncobj cap instead of using > a separate support parameter. > > This series adds support for the native fence fd extension to vc4. > The

[Mesa-dev] [PATCH] Revert "st/nir: use NIR for asm programs"

This reverts commit 5c33e8c7729edd5e16020ebb8703be96523e04f2. It broke fixed function vertex programs on vc4 and v3d, and apparently caused trouble for radeonsi's NIR paths as well. --- src/mesa/state_tracker/st_program.c | 65 - 1 file changed, 7 insertions(+), 58

Re: [Mesa-dev] [PATCH 2/2] radv: add radv_emit_shader_pointer() helper

Do we want the new function inlined? Reviewed-by: Bas Nieuwenhuizen On Thu, May 17, 2018 at 2:16 PM, Samuel Pitoiset wrote: > For future work (support for 32-bit GPU pointers). > > Signed-off-by: Samuel Pitoiset >

Re: [Mesa-dev] [PATCH v2] android: enable VK_ANDROID_native_buffer

Whatever. If there isn't too much of a rush, my preference would be to pull in the vk_icd.h fix as a pull from upstream and then do this afterwards. I guess this doesn't help anyone without the vk_icd.h fix. If we are in a rush, I'd be ok with making the fix in our tree so long as it's in

Re: [Mesa-dev] [PATCH 06/22] compiler/nir: support 16-bit float in nir_imm_floatN_t

After sending this, I realized that it's probably because you depend on nir_imm_intN_t(). Alternatively, we could make a nir_imm_float16() helper which may be nicer for cases where you know you need 16-bit floats. This is fine though. Rb. On May 17, 2018 07:01:53 Jason Ekstrand

Re: [Mesa-dev] [PATCH 9.5/17] squash! i965/miptree: Unify aux buffer allocation

On Thu, May 17, 2018 at 07:44:34AM +0300, Pohjolainen, Topi wrote: > On Wed, May 16, 2018 at 09:33:34AM -0700, Nanley Chery wrote: > > On Wed, May 16, 2018 at 09:11:38AM +0300, Pohjolainen, Topi wrote: > > > On Wed, May 09, 2018 at 10:47:24AM -0700, Nanley Chery wrote: > > > > v2: Inline the

Re: [Mesa-dev] [PATCH 21/22] intel/compiler: lower 16-bit flrp

Rb On May 17, 2018 01:48:43 Iago Toral Quiroga wrote: --- src/intel/compiler/brw_compiler.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/intel/compiler/brw_compiler.c b/src/intel/compiler/brw_compiler.c index 36a870ece0d..250e4695ded 100644 ---

Re: [Mesa-dev] [PATCH 19/22] intel/compiler: lower 16-bit fmod

Rb On May 17, 2018 01:48:33 Iago Toral Quiroga wrote: --- src/intel/compiler/brw_compiler.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/intel/compiler/brw_compiler.c b/src/intel/compiler/brw_compiler.c index 6480dbefbf6..36a870ece0d 100644 ---

Re: [Mesa-dev] [PATCH 20/22] compiler/nir: add lowering for 16-bit flrp

Rb On May 17, 2018 01:49:07 Iago Toral Quiroga wrote: --- src/compiler/nir/nir.h| 1 + src/compiler/nir/nir_opt_algebraic.py | 1 + 2 files changed, 2 insertions(+) diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h index 59c84bde268..7e4c78cc1b7

Re: [Mesa-dev] [PATCH 18/22] compiler/nir: add lowering option for 16-bit fmod

Rb On May 17, 2018 01:48:27 Iago Toral Quiroga wrote: --- src/compiler/nir/nir.h| 1 + src/compiler/nir/nir_opt_algebraic.py | 1 + 2 files changed, 2 insertions(+) diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h index a379928cdcd..59c84bde268

Re: [Mesa-dev] [PATCH 15/22] compiler/spirv: implement 16-bit exp and log

Rb On May 17, 2018 01:48:43 Iago Toral Quiroga wrote: --- src/compiler/spirv/vtn_glsl450.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/compiler/spirv/vtn_glsl450.c b/src/compiler/spirv/vtn_glsl450.c index 70e3eb80c4c..324e8b5874a 100644 ---

Re: [Mesa-dev] [PATCH 2/4] mesa: Remove flush_vertrices argument from VAO methods.

In the subject line "flush_vertices" For this series, Reviewed-by: Brian Paul More nice clean-ups! -Brian On 05/17/2018 12:37 AM, mathias.froehl...@gmx.net wrote: From: Mathias Fröhlich The flush_vertices argument is now unused, remove it.

Re: [Mesa-dev] [PATCH 07/22] compiler/spirv: handle 16-bit float in radians() and degrees()

Rb On May 17, 2018 01:48:03 Iago Toral Quiroga wrote: --- src/compiler/spirv/vtn_glsl450.c | 10 -- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/src/compiler/spirv/vtn_glsl450.c b/src/compiler/spirv/vtn_glsl450.c index 6fa759b1bba..ffe12a71818

Re: [Mesa-dev] [PATCH 06/22] compiler/nir: support 16-bit float in nir_imm_floatN_t

Why did the function move? On May 17, 2018 01:47:51 Iago Toral Quiroga wrote: --- src/compiler/nir/nir_builder.h | 29 - 1 file changed, 16 insertions(+), 13 deletions(-) diff --git a/src/compiler/nir/nir_builder.h

Re: [Mesa-dev] [PATCH 03/22] compiler/spirv: fix SpvOpIsInf for 16-bit float

On May 17, 2018 01:47:11 Iago Toral Quiroga wrote: --- src/compiler/spirv/vtn_alu.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/compiler/spirv/vtn_alu.c b/src/compiler/spirv/vtn_alu.c index 5f9cc97fdfb..62a5149797a 100644 ---

[Mesa-dev] [PATCH 2/2] radv: add radv_emit_shader_pointer() helper

For future work (support for 32-bit GPU pointers). Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_cmd_buffer.c | 13 ++--- src/amd/vulkan/radv_device.c | 17 +++-- src/amd/vulkan/radv_private.h| 3 +++ 3 files changed, 20

[Mesa-dev] [PATCH 1/2] radv: add some helpers for cleaning up radv_get_preamble_cs()

Because this function looks a bit ugly to me. Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_device.c | 214 +-- 1 file changed, 128 insertions(+), 86 deletions(-) diff --git a/src/amd/vulkan/radv_device.c

[Mesa-dev] [PATCH mesa] i965: Check result of make_surface() for miptree_create

From: Andrea Azzarone Since make_surface() can fail we need to check the result before dereferencing it. Bug: https://github.com/mesa3d/mesa/pull/5 Bug: https://bugs.launchpad.net/ubuntu/+source/gnome-shell/+bug/1760415 Reviewed-by: Eric Engestrom

Re: [Mesa-dev] [PATCH] autotools, meson: add tileset.h

On Monday, 2018-05-14 11:05:34 -0700, Dylan Baker wrote: > Quoting Eric Engestrom (2018-05-14 06:09:59) > > > > Dylan, what do you think? Do we want to remove all the unnecessary > > files() from meson, or keep them to mirror what was needed by autotools? > > I'd vote 'remove', but the "let's do

Re: [Mesa-dev] [PATCH 1/3] mesa/main/shaderapi: Use generate_sha1() unconditionally

I looked at the appveyor log for that specific build https://ci.appveyor.com/project/mesa3d/mesa/build/3186 It seems to only complain about disk_cache.c src\util\disk_cache.c(28) : fatal error C1083: Cannot open include file: 'sys/file.h': No such file or directory scons: ***

Re: [Mesa-dev] [PATCH 09/22] intel/compiler: implement 16-bit multiply-add

Hi, On 17.05.2018 11:46, Iago Toral Quiroga wrote: The PRM for MAD states that F, DF and HF are supported, however, then it requires that the instruction includes a 2-bit mask specifying the types of each operand like this: > 00: 32-bit float 01: 32-bit signed integer 10: 32-bit unsigned

Re: [Mesa-dev] [PATCH 1/3] mesa/main/shaderapi: Use generate_sha1() unconditionally

Ok I found the commit. But it says: "Until we have a proper fix." So this would be a good time I guess ;) --- author Emil Velikov 2017-01-18 19:40:31 + committer Emil Velikov 2017-01-18 20:09:01 + commit

[Mesa-dev] [PATCH 0/2] st/dri format handling cleanups

Hi all, those 2 patches clean up and align the format handling in the dri state tracker to how the intel driver implements some details of the interface. This is mostly in preparation for etnaviv to support native planar YUV import without needing any of the R8/RG88 sampler rewrites, as those

[Mesa-dev] [PATCH 2/2] st/dri: replace format conversion functions with single mapping table

Each time I have to touch the buffer import/export functions in the dri state tracker I get lost in the maze of functions converting between DRI_IMAGE_FOURCC, DRI_IMAGE_FORMAT, DRI_IMAGE_COMPONENTS and pipe format. Rip it out and replace by a single table, which defines the correspondence between

[Mesa-dev] [PATCH 1/2] st/dri: allow both render and sampler compatible dma-buf formats

Currently all the EGL APIs are missing a way to specify how an imported dma-buf is intended to be used. Demanding the format to be both usable for sampling and rendering artificially restricts the list of formats a driver is able to import. Looking at how the Intel driver implements those DRI2

[Mesa-dev] [RFC PATCH] virgl: Always assume that ORIGIN_UPPER_LEFT and PIXEL_CENTER* are supported

The driver must support at least one of PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT and one of PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER otherwise glsl_to_tgsi will fire an assert.

Re: [Mesa-dev] [PATCH 1/3] mesa/main/shaderapi: Use generate_sha1() unconditionally

On 05/17/2018 11:38 AM, Benedikt Schemmer wrote: Thanks for reviewing! Am 17.05.2018 um 08:42 schrieb Tapani Pälli: On 05/10/2018 12:05 PM, Benedikt Schemmer wrote: Move shader-cache code from back to front and make generate_sha1() usable unconditionally to avoid code duplication in the

Re: [Mesa-dev] [PATCH 2/2] radv: remove the radv_finishme() when compiling shaders

Reviewed-by: Bas Nieuwenhuizen for both. On Thu, May 17, 2018 at 9:56 AM, Samuel Pitoiset wrote: > Having an entrypoint different than "main" doesn't mean we > have multiple shaders per module. > > Signed-off-by: Samuel Pitoiset

Re: [Mesa-dev] [PATCH] radv: only pass the global BO list at submit time if enabled

Reviewed-by: Bas Nieuwenhuizen On Thu, May 17, 2018 at 11:36 AM, Samuel Pitoiset wrote: > That way the winsys might use a faster path when the global > BO list is NULL. > > Signed-off-by: Samuel Pitoiset > --- >

[Mesa-dev] [PATCH] radv: only pass the global BO list at submit time if enabled

That way the winsys might use a faster path when the global BO list is NULL. Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_device.c | 8 ++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/src/amd/vulkan/radv_device.c

[Mesa-dev] [PATCH] i965/disasm: Always print message descriptor and SFID for SEND instructions

Having the disassembly always show the message descriptor and SFID makes it easier to debug what data is actually fed to the external units. Descriptor format was changed to unsigned so that immediate values as 'src1' will get printed out in a readable format. --- src/intel/compiler/brw_disasm.c

Re: [Mesa-dev] [PATCH 2/3] mesa/main/shaderapi: Use sha as part of captured shaders name

On 05/17/2018 11:49 AM, Benedikt Schemmer wrote: Am 17.05.2018 um 09:11 schrieb Tapani Pälli: some nitpicking below .. I'll do some testing to see that things work as before but overall these changes look good to me. Would be nice to hear comments from active shader-db users. On

Re: [Mesa-dev] [PATCH 2/3] mesa/main/shaderapi: Use sha as part of captured shaders name

Am 17.05.2018 um 09:11 schrieb Tapani Pälli: > some nitpicking below .. I'll do some testing to see that things work as > before but overall these changes look good to me. Would be nice to hear > comments from active shader-db users. > > On 05/10/2018 12:05 PM, Benedikt Schemmer wrote: >> It

[Mesa-dev] [PATCH 19/22] intel/compiler: lower 16-bit fmod

--- src/intel/compiler/brw_compiler.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/intel/compiler/brw_compiler.c b/src/intel/compiler/brw_compiler.c index 6480dbefbf6..36a870ece0d 100644 --- a/src/intel/compiler/brw_compiler.c +++ b/src/intel/compiler/brw_compiler.c @@ -33,6 +33,7 @@

[Mesa-dev] [PATCH 21/22] intel/compiler: lower 16-bit flrp

--- src/intel/compiler/brw_compiler.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/intel/compiler/brw_compiler.c b/src/intel/compiler/brw_compiler.c index 36a870ece0d..250e4695ded 100644 --- a/src/intel/compiler/brw_compiler.c +++ b/src/intel/compiler/brw_compiler.c @@ -33,6 +33,7 @@

[Mesa-dev] [PATCH 20/22] compiler/nir: add lowering for 16-bit flrp

--- src/compiler/nir/nir.h| 1 + src/compiler/nir/nir_opt_algebraic.py | 1 + 2 files changed, 2 insertions(+) diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h index 59c84bde268..7e4c78cc1b7 100644 --- a/src/compiler/nir/nir.h +++ b/src/compiler/nir/nir.h @@ -1871,6

[Mesa-dev] [PATCH 22/22] intel/compiler: Extended Math is limited to SIMD8 on half-float

From the Skylake PRM, Extended Math Function: "The execution size must be no more than 8 when half-floats are used in source or destination operand." Earlier generations do not support Extended Math with half-float. --- src/intel/compiler/brw_fs.cpp | 30 +++--- 1

[Mesa-dev] [PATCH 17/22] compiler/spirv: implement 16-bit frexp

--- src/compiler/spirv/vtn_glsl450.c | 48 ++-- 1 file changed, 46 insertions(+), 2 deletions(-) diff --git a/src/compiler/spirv/vtn_glsl450.c b/src/compiler/spirv/vtn_glsl450.c index 738f1ea93f1..88d2dcfb0fd 100644 --- a/src/compiler/spirv/vtn_glsl450.c +++

[Mesa-dev] [PATCH 18/22] compiler/nir: add lowering option for 16-bit fmod

--- src/compiler/nir/nir.h| 1 + src/compiler/nir/nir_opt_algebraic.py | 1 + 2 files changed, 2 insertions(+) diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h index a379928cdcd..59c84bde268 100644 --- a/src/compiler/nir/nir.h +++ b/src/compiler/nir/nir.h @@ -1877,6

[Mesa-dev] [PATCH 16/22] compiler/spirv: implement 16-bit hyperbolic trigonometric functions

--- src/compiler/spirv/vtn_glsl450.c | 29 +++-- 1 file changed, 19 insertions(+), 10 deletions(-) diff --git a/src/compiler/spirv/vtn_glsl450.c b/src/compiler/spirv/vtn_glsl450.c index 324e8b5874a..738f1ea93f1 100644 --- a/src/compiler/spirv/vtn_glsl450.c +++

[Mesa-dev] [PATCH 14/22] compiler/spirv: implement 16-bit atan2

--- src/compiler/spirv/vtn_glsl450.c | 22 +++--- 1 file changed, 15 insertions(+), 7 deletions(-) diff --git a/src/compiler/spirv/vtn_glsl450.c b/src/compiler/spirv/vtn_glsl450.c index 9e565ef9e5a..70e3eb80c4c 100644 --- a/src/compiler/spirv/vtn_glsl450.c +++

[Mesa-dev] [PATCH 13/22] compiler/spirv: implement 16-bit atan

--- src/compiler/spirv/vtn_glsl450.c | 37 + 1 file changed, 25 insertions(+), 12 deletions(-) diff --git a/src/compiler/spirv/vtn_glsl450.c b/src/compiler/spirv/vtn_glsl450.c index 8cbdaad3998..9e565ef9e5a 100644 --- a/src/compiler/spirv/vtn_glsl450.c +++

[Mesa-dev] [PATCH 15/22] compiler/spirv: implement 16-bit exp and log

--- src/compiler/spirv/vtn_glsl450.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/compiler/spirv/vtn_glsl450.c b/src/compiler/spirv/vtn_glsl450.c index 70e3eb80c4c..324e8b5874a 100644 --- a/src/compiler/spirv/vtn_glsl450.c +++ b/src/compiler/spirv/vtn_glsl450.c @@

[Mesa-dev] [PATCH 12/22] compiler/spirv: implement 16-bit acos

--- src/compiler/spirv/vtn_glsl450.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/compiler/spirv/vtn_glsl450.c b/src/compiler/spirv/vtn_glsl450.c index 845e5a9e517..8cbdaad3998 100644 --- a/src/compiler/spirv/vtn_glsl450.c +++ b/src/compiler/spirv/vtn_glsl450.c @@

[Mesa-dev] [PATCH 10/22] intel/compiler: allow extended math functions with HF operands

The PRM states that half-float operands are supported since gen9. --- src/intel/compiler/brw_eu_emit.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c index ee5a048bcaa..20c3f9fa933 100644 ---

[Mesa-dev] [PATCH 11/22] compiler/spirv: implement 16-bit asin

--- src/compiler/spirv/vtn_glsl450.c | 20 +--- 1 file changed, 13 insertions(+), 7 deletions(-) diff --git a/src/compiler/spirv/vtn_glsl450.c b/src/compiler/spirv/vtn_glsl450.c index ffe12a71818..845e5a9e517 100644 --- a/src/compiler/spirv/vtn_glsl450.c +++

[Mesa-dev] [PATCH 09/22] intel/compiler: implement 16-bit multiply-add

The PRM for MAD states that F, DF and HF are supported, however, then it requires that the instruction includes a 2-bit mask specifying the types of each operand like this: 00: 32-bit float 01: 32-bit signed integer 10: 32-bit unsigned integer 11: 64-bit float So 16-bit float would not be

[Mesa-dev] [PATCH 08/22] intel/compiler: implement 16-bit fsign

--- src/intel/compiler/brw_fs_nir.cpp | 27 +-- 1 file changed, 21 insertions(+), 6 deletions(-) diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index fb5ad7a614a..91283ab4911 100644 --- a/src/intel/compiler/brw_fs_nir.cpp +++

[Mesa-dev] [PATCH 06/22] compiler/nir: support 16-bit float in nir_imm_floatN_t

--- src/compiler/nir/nir_builder.h | 29 - 1 file changed, 16 insertions(+), 13 deletions(-) diff --git a/src/compiler/nir/nir_builder.h b/src/compiler/nir/nir_builder.h index 02a9dbfb040..198c42dd823 100644 --- a/src/compiler/nir/nir_builder.h +++

[Mesa-dev] [PATCH 07/22] compiler/spirv: handle 16-bit float in radians() and degrees()

--- src/compiler/spirv/vtn_glsl450.c | 10 -- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/src/compiler/spirv/vtn_glsl450.c b/src/compiler/spirv/vtn_glsl450.c index 6fa759b1bba..ffe12a71818 100644 --- a/src/compiler/spirv/vtn_glsl450.c +++

[Mesa-dev] [PATCH 04/22] intel/compiler: lower some 16-bit float operations to 32-bit

The hardware doesn't support half-float for these. --- src/intel/compiler/brw_nir.c | 5 + 1 file changed, 5 insertions(+) diff --git a/src/intel/compiler/brw_nir.c b/src/intel/compiler/brw_nir.c index dfeea73b06a..ff245b59b81 100644 --- a/src/intel/compiler/brw_nir.c +++

[Mesa-dev] [PATCH 03/22] compiler/spirv: fix SpvOpIsInf for 16-bit float

--- src/compiler/spirv/vtn_alu.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/compiler/spirv/vtn_alu.c b/src/compiler/spirv/vtn_alu.c index 5f9cc97fdfb..62a5149797a 100644 --- a/src/compiler/spirv/vtn_alu.c +++ b/src/compiler/spirv/vtn_alu.c @@ -578,7 +578,9 @@

[Mesa-dev] [PATCH 05/22] intel/compiler: lower 16-bit extended math to 32-bit prior to gen9

Extended math desn't support half-float on these generations. --- src/intel/compiler/brw_nir.c | 13 - 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/src/intel/compiler/brw_nir.c b/src/intel/compiler/brw_nir.c index ff245b59b81..8337da57585 100644 ---

[Mesa-dev] [PATCH 02/22] i965/fs: Implement float64 to float16 conversion

From: Samuel Iglesias Gonsálvez It is not supported directly in the HW, we need to convert to float32 first as intermediate step. Signed-off-by: Samuel Iglesias Gonsálvez --- src/intel/compiler/brw_fs_nir.cpp | 17 + 1 file changed,

[Mesa-dev] [PATCH 01/22] i965/fs: implement conversions from float16 to 64 bits data types

From: Samuel Iglesias Gonsálvez Signed-off-by: Samuel Iglesias Gonsálvez --- src/intel/compiler/brw_fs_nir.cpp | 32 1 file changed, 32 insertions(+) diff --git a/src/intel/compiler/brw_fs_nir.cpp

Re: [Mesa-dev] [PATCH 6/9] intel/blorp: Make blorp_ccs_ambiguate just an internal helper

On Wed, 2018-05-16 at 08:44 -0700, Jason Ekstrand wrote: > On Wed, May 16, 2018 at 4:00 AM, Iago Toral > wrote: > > On Tue, 2018-05-15 at 15:28 -0700, Jason Ekstrand wrote: > > > > > Now that anv uses blorp_ccs_op for everything, we no longer need > > to > > > > > expose the

[Mesa-dev] [PATCH 00/22] spirv/intel: half-float compiler enablement

Most of our compiler was already 16-bit aware thanks to previous work on VK_KHR_16bit_storage and shaderInt16, but specifically for 16-bit floating point, we were missing a few things such as some lowerings that depend on the specific bit representation of the float or some hardware restrictions

Re: [Mesa-dev] [PATCH 3/3] mesa/main/shaderapi: purely non-functional cleanups, like whitespace errors and cleanups

Am 17.05.2018 um 08:59 schrieb Tapani Pälli: > > > On 05/10/2018 12:05 PM, Benedikt Schemmer wrote: >> remove a memset too and yes, this is all functionally identical >> >> --- >>   src/mesa/main/shaderapi.c | 40 >>   1 file changed, 20 insertions(+),

Re: [Mesa-dev] [PATCH 1/3] mesa/main/shaderapi: Use generate_sha1() unconditionally

Thanks for reviewing! Am 17.05.2018 um 08:42 schrieb Tapani Pälli: > > > On 05/10/2018 12:05 PM, Benedikt Schemmer wrote: >> Move shader-cache code from back to front and make generate_sha1() usable >> unconditionally to avoid code duplication in the following patch >> >> --- >>  

  1   2   >