Re: [Mesa-dev] [PATCH] nir: move ALU instruction before the jump instruction

On Wed, 2019-02-13 at 11:53 -0800, Ian Romanick wrote: > On 2/13/19 9:59 AM, Juan A. Suarez Romero wrote: > > On Wed, 2019-02-13 at 09:16 -0800, Ian Romanick wrote: > > > On 2/13/19 7:53 AM, Juan A. Suarez Romero wrote: > > > > On Tue, 2019-02-12 at 16:22 -0800, Ian Romanick wrote: > > > > > On

[Mesa-dev] [PATCH 0/4] RadeonSI: Follow-up for the primitive culling series

Hi, This fixes Sea Islands and makes it faster. Please review. Thanks, Marek ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH 3/4] radeonsi: fix cache coherency for primitive culling on CI

From: Marek Olšák --- .../radeonsi/si_compute_prim_discard.c| 20 ++- 1 file changed, 11 insertions(+), 9 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_compute_prim_discard.c b/src/gallium/drivers/radeonsi/si_compute_prim_discard.c index

[Mesa-dev] [PATCH 2/4] winsys/amdgpu: clean up and remove nonsensical assertion

From: Marek Olšák The assertion considers max_dw from the current IB in the chain, but big_ib_buffer is a buffer for the next IB, which can be smaller. --- src/gallium/winsys/amdgpu/drm/amdgpu_cs.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git

[Mesa-dev] [PATCH 1/4] winsys/amdgpu: enable chaining for compute IBs

From: Marek Olšák --- src/gallium/winsys/amdgpu/drm/amdgpu_cs.c | 12 ++-- 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c index 912307e7d11..eb2944766fc 100644 ---

[Mesa-dev] [PATCH 4/4] radeonsi: emulate REWIND using INDIRECT_BUFFER for primitive culling on CI

From: Marek Olšák This increases "Paraview - Many Spheres" performance from 37.91 to 43 fps on Hawaii. --- src/gallium/drivers/r300/r300_blit.c | 2 +- src/gallium/drivers/r300/r300_render.c| 2 +- src/gallium/drivers/r600/r600_hw_context.c| 2 +-

Re: [Mesa-dev] [PATCH 00/26] RadeonSI: Primitive culling with async compute

I have some fixes for Sea Islands that improve Radeon 290X performance to 43 fps, moving it just below Radeon VII in the picture. Marek On Wed, Feb 13, 2019 at 12:16 AM Marek Olšák wrote: > Hi, > > This patch series uses async compute to do primitive culling before > the vertex shader. It

[Mesa-dev] [PATCH] panfrost: Improve logging and patch memory leaks

Signed-off-by: Alyssa Rosenzweig --- src/gallium/drivers/panfrost/pan_context.c | 21 +- src/gallium/drivers/panfrost/pan_resource.c | 76 - 2 files changed, 48 insertions(+), 49 deletions(-) diff --git a/src/gallium/drivers/panfrost/pan_context.c

Re: [Mesa-dev] [PATCH] panfrost: Resolve alignment issue on 32-bit

> You've got a float *out that's unaligned? I would recommend a void > pointer if you're breaking the alignment rules. Fixed in the (much more comprehensive) "backport to T760" patchset, thank you :) -A ___ mesa-dev mailing list

Re: [Mesa-dev] [PATCH 2/2] nir/xfb: Properly align 64-bit values

Scratch the ML patches. It needed a bit more work yet. I've moved it to an MR. On Wed, Feb 13, 2019 at 11:32 AM Jason Ekstrand wrote: > Fixes: 19064b8c "nir: Add a pass for gathering transform feedback info" > Cc: Alejandro Piñeiro > --- > src/compiler/nir/nir_gather_xfb_info.c | 4 >

[Mesa-dev] [MR] NIR: Various XFB fixes

This little series fixes a few issues for XFB on NIR: 1. We weren't properly handling alignments on 64-bit things or things which contain 64-bit things. 2. We weren't properly handling clip/cull distances. This MR fixes both of these problems. With this MR, ANV now passes all of the proposed

[Mesa-dev] [MR] nir: Make nir_dead_cf faster

This MR adds a couple of patches which should substantially improve the speed of nir_dead_cf by stopping relying on liveness analysis. I've marked it WIP because I have yet to give it any real testing. https://gitlab.freedesktop.org/mesa/mesa/merge_requests/247

Re: [Mesa-dev] [PATCH 00/26] RadeonSI: Primitive culling with async compute

Got it (merged in), thanks. But now I need some sleep. Have to drive my wife to the hospital in a few hours. No, not hyperacute. Dieter Am 14.02.2019 03:07, schrieb Marek Olšák: I just updated the branch, fixing video players. Marek On Wed, Feb 13, 2019 at 8:28 PM Dieter Nützel wrote: Now

[Mesa-dev] [PATCH] swr: set PIPE_CAP_MAX_VARYINGS correctly

Unfortunately swr was missed in the original commit. The number of varyings should generally match up to what's reported as the shader caps for fragment inputs. Fixes: 6010d7b8e8be (gallium: add PIPE_CAP_MAX_VARYINGS) Signed-off-by: Ilia Mirkin Cc: 19.0 ---

Re: [Mesa-dev] [PATCH 1/2] panfrost: Identify MALI_OCCLUSION_PRECISE bit

On Wed, Feb 13, 2019 at 9:52 PM Alyssa Rosenzweig wrote: > > Setting this is required for desktop-style occlusion queries. > > Signed-off-by: Alyssa Rosenzweig > --- > src/gallium/drivers/panfrost/include/panfrost-job.h | 10 ++ > src/gallium/drivers/panfrost/pan_context.c | 2

Re: [Mesa-dev] [PATCH v2 2/2] radeonsi/nir: set colors_read properly

For the series Tested-by: Dieter Nützel on Polaris 20 Dieter Am 12.02.2019 01:15, schrieb Timothy Arceri: shader-db results for VEGA64: Totals from affected shaders: SGPRS: 1976 -> 1976 (0.00 %) VGPRS: 1240 -> 1144 (-7.74 %) Spilled SGPRs: 145 -> 145 (0.00 %) Spilled VGPRs: 0 -> 0 (0.00 %)

Re: [Mesa-dev] [PATCH] radeonsi/nir: set shader_buffers_declared properly

Tested-by: Dieter Nützel Am 12.02.2019 04:46, schrieb Timothy Arceri: --- src/gallium/drivers/radeonsi/si_shader_nir.c | 32 ++-- 1 file changed, 22 insertions(+), 10 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_shader_nir.c

[Mesa-dev] [PATCH 2/2] panfrost: Implement PIPE_QUERY_OCCLUSION_COUNTER

Signed-off-by: Alyssa Rosenzweig --- src/gallium/drivers/panfrost/pan_context.c | 9 - 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/src/gallium/drivers/panfrost/pan_context.c b/src/gallium/drivers/panfrost/pan_context.c index 73e7d4aaa8f..e51ca8f3982 100644 ---

[Mesa-dev] [PATCH 1/2] panfrost: Identify MALI_OCCLUSION_PRECISE bit

Setting this is required for desktop-style occlusion queries. Signed-off-by: Alyssa Rosenzweig --- src/gallium/drivers/panfrost/include/panfrost-job.h | 10 ++ src/gallium/drivers/panfrost/pan_context.c | 2 +- 2 files changed, 7 insertions(+), 5 deletions(-) diff --git

Re: [Mesa-dev] [PATCH 00/26] RadeonSI: Primitive culling with async compute

I just updated the branch, fixing video players. Marek On Wed, Feb 13, 2019 at 8:28 PM Dieter Nützel wrote: > Now with LLVM 9.0 git;-) > > Running, except mplayer/mpv (same as before). > > mplayer: ../src/gallium/drivers/radeon/radeon_winsys.h:866: > radeon_get_heap_index: Assertion `!"32BIT

[Mesa-dev] [PATCH] panfrost: Backport driver to Mali T600/T700

There are a few differenes between Mali T860 (Panfrost's primary reference target) and the older Midgard generations (T600/T700): - Miscellaneous different magic numbers. It's not clear what these numbers mean on either the old or new configurations yet. - Errata fixes. T800 is the final

Re: [Mesa-dev] [PATCH 00/26] RadeonSI: Primitive culling with async compute

Yes, you need amd-staging-drm-next. Marek On Wed, Feb 13, 2019 at 8:28 PM Dieter Nützel wrote: > Now with LLVM 9.0 git;-) > > Running, except mplayer/mpv (same as before). > > mplayer: ../src/gallium/drivers/radeon/radeon_winsys.h:866: > radeon_get_heap_index: Assertion `!"32BIT without WC is

[Mesa-dev] [PATCH] nir: remove simple dead if detection from nir_opt_dead_cf()

This was probably useful when it was first written, however it looks to be no longer necessary. As far as I can tell these days dce is smart enough to remove useless instructions from if branches. Once this is done nir_opt_peephole_select() will end up removing the empty if. Removing this

Re: [Mesa-dev] [PATCH 00/26] RadeonSI: Primitive culling with async compute

Now with LLVM 9.0 git;-) Running, except mplayer/mpv (same as before). mplayer: ../src/gallium/drivers/radeon/radeon_winsys.h:866: radeon_get_heap_index: Assertion `!"32BIT without WC is disallowed"' failed. Abbruch (core dumped) mpv: ../src/gallium/drivers/radeon/radeon_winsys.h:866:

Re: [Mesa-dev] [PATCH] spirv: Add missing break

rb On Wed, Feb 13, 2019 at 5:14 PM Caio Marcelo de Oliveira Filho < caio.olive...@intel.com> wrote: > Reviewed-by: Caio Marcelo de Oliveira Filho > > > On Wed, Feb 13, 2019 at 03:03:59PM -0800, Ian Romanick wrote: > > From: Ian Romanick > > > > Fixes: c6465fec0c5 ("spirv: add

Re: [Mesa-dev] [PATCH] spirv: Add missing break

Reviewed-by: Caio Marcelo de Oliveira Filho On Wed, Feb 13, 2019 at 03:03:59PM -0800, Ian Romanick wrote: > From: Ian Romanick > > Fixes: c6465fec0c5 ("spirv: add SpvCapabilityInt64Atomics") > CID: 1442555 > --- > src/compiler/spirv/spirv_to_nir.c | 1 + > 1 file changed, 1 insertion(+) > >

[Mesa-dev] [PATCH] spirv: Add missing break

From: Ian Romanick Fixes: c6465fec0c5 ("spirv: add SpvCapabilityInt64Atomics") CID: 1442555 --- src/compiler/spirv/spirv_to_nir.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/compiler/spirv/spirv_to_nir.c b/src/compiler/spirv/spirv_to_nir.c index 1cbc926c818..5e8eb222555 100644 ---

Re: [Mesa-dev] Thoughts on fp64 for GLES?

On Thu, 14 Feb 2019 at 06:04, Stéphane Marchesin wrote: > > On Wed, Feb 13, 2019 at 11:09 AM Elie Tournier > wrote: > > > > > > > > On Wednesday, 13 February 2019, Stéphane Marchesin > > wrote: > >> > >> On Wed, Feb 13, 2019 at 10:29 AM Elie Tournier > >> wrote: > >> > > >> > > >> > > >> >

Re: [Mesa-dev] [PATCH 2/4] nir: turn ssa check into an assert

On 2/13/19 12:00 AM, Timothy Arceri wrote: > Everthing should be in ssa form when this is called. Checking > for it here is expensive so turn this into an assert instead. > > Do the cheap thing first and check if we can even progress with > this instruction type. > --- >

Re: [Mesa-dev] [PATCH 4/4] nir: reorder some code

On 14/2/19 1:44 am, Jason Ekstrand wrote: I'm not sure that I think about this one. I kind of like the pattern where the first thing in the switch case on subtype is a cast to that subtype. It's also just a cast in debug builds so it should generate zero code. Callgrind did show a change but

[Mesa-dev] [ANNOUNCE] mesa 19.0.0-rc4

Hi List, I've gone ahead and made a -rc4 today as I tsaid I would yesterday. This includes all of the patches from rc3, plus a whole set of changes that should have been in both -rc2 and -rc3. Among the changes pulled in since rc3: - one fix for meson - a plethora of nouveau fixes - fixes for

Re: [Mesa-dev] [PATCH 4/4] radv: reduce the number of loaded channels for vertex input fetches

On 2/13/19 10:59 PM, Bas Nieuwenhuizen wrote: On Tue, Feb 12, 2019 at 3:07 PM Samuel Pitoiset wrote: It's unnecessary to load more channels than the vertex attribute format. The remaining channels are filled with 0 for y and z, and 1 for w. 29077 shaders in 15096 tests Totals: SGPRS: 1321605

[Mesa-dev] [Bug 109401] [DXVK] Project Cars rendering problems

https://bugs.freedesktop.org/show_bug.cgi?id=109401 --- Comment #4 from Samuel Pitoiset --- The trees issue should be fixed with https://cgit.freedesktop.org/mesa/mesa/commit/?id=334da034d8d91ca5a0a1bff8deaefd8ca762c42e -- You are receiving this mail because: You are the QA Contact for the

Re: [Mesa-dev] [PATCH 4/4] radv: reduce the number of loaded channels for vertex input fetches

On Tue, Feb 12, 2019 at 3:07 PM Samuel Pitoiset wrote: > > It's unnecessary to load more channels than the vertex attribute > format. The remaining channels are filled with 0 for y and z, > and 1 for w. > > 29077 shaders in 15096 tests > Totals: > SGPRS: 1321605 -> 1318869 (-0.21 %) > VGPRS:

Re: [Mesa-dev] RFC - libglvnd and GLXVND vendor enumeration to facilitate GLX multi-vendor PRIME GPU offload

On 2/13/19 2:32 PM, Andy Ritger wrote: On Wed, Feb 13, 2019 at 12:15:02PM -0700, Kyle Brenneman wrote: On 02/12/2019 01:58 AM, Michel Dänzer wrote: On 2019-02-11 5:18 p.m., Andy Ritger wrote: On Mon, Feb 11, 2019 at 12:09:26PM +0100, Michel Dänzer wrote: On 2019-02-08 11:43 p.m., Kyle

Re: [Mesa-dev] RFC - libglvnd and GLXVND vendor enumeration to facilitate GLX multi-vendor PRIME GPU offload

On Wed, Feb 13, 2019 at 12:15:02PM -0700, Kyle Brenneman wrote: > On 02/12/2019 01:58 AM, Michel Dänzer wrote: > > On 2019-02-11 5:18 p.m., Andy Ritger wrote: > > > On Mon, Feb 11, 2019 at 12:09:26PM +0100, Michel Dänzer wrote: > > > > On 2019-02-08 11:43 p.m., Kyle Brenneman wrote: > > > > >

[Mesa-dev] [PATCH 8/9] ir3: Extend lower_io_offsets pass to lower SSBO dword offset computation

The lowering will take an SSBO intrinsic and replace it with the new ir3-specific version that adds an extra source. That source will hold the SSA value resulting from inserting a division by 4 (an SHR op) of the original byte-offset source of the intrinsic. ---

[Mesa-dev] [PATCH 9/9] ir3/compiler: Handle the new ir3 intrinsics for SSBO

These intrinsics have the offset in dwords already computed in the last source, so the change here is basically using that instead of emitting the ir3_SHR to divide the byte-offset by 4. The improvement in shader stats is dramatic, of up to ~15% in instruction count in some cases. Tested on a5xx.

[Mesa-dev] [PATCH 2/9] ir3/compiler: Handle newly added intrinsic image_deref_load_param_ir3

Compiler will emit an uniform value corresponding to the requested parameter (bpp, y-stride or z-stride) for the dereferenced image. --- src/freedreno/ir3/ir3_compiler_nir.c | 18 ++ 1 file changed, 18 insertions(+) diff --git a/src/freedreno/ir3/ir3_compiler_nir.c

[Mesa-dev] [PATCH 1/9] nir: Add a new intrinsic 'image_deref_load_param_ir3'

This is a freedreno specific intrinsic intended to be injected by a 'ir3_nir_lower_sampler_io' pass that will be introduced later in this series, and consumed by ir3_compiler_nir. The intrinsic will load-in SSA values for various image constants (from image_dims), namely the format's

[Mesa-dev] [PATCH 0/9] freedreno: Add a NIR pass to lower backend IO offset computations

This series introduces a new ir3-specific NIR pass that moves offset computations for different IO ops that currently occur in the backend, to NIR. For now, it handles image store/atomics, and SSBO load/store/atomics. Lowering UBO offsets is WIP and will probably be sent as follow up patches.

[Mesa-dev] [PATCH 7/9] nir: Add ir3-specific version of most SSBO intrinsics

These are Freedreno specific versions of SSBO intrinsics that add an extra source to hold the dword-offset, which is needed by the backend apart from the byte-offset already provided by NIR in one of the sources. NIR lowering pass 'ir3_nir_lower_io_offset' will replace the original SSBO

[Mesa-dev] [PATCH 3/9] nir: Add a new ALU nir_op_imad24_ir3

ir3 compiler has an integer multiply-add instruction (MAD_S24) that is used for different offset calculations in the backend. Since we intend to move some of these calculations to NIR, we need a new ALU op that can directly represent it. --- src/compiler/nir/nir_opcodes.py | 16

[Mesa-dev] [PATCH 5/9] ir3/nir: Add a new pass 'ir3_nir_lower_io_offsets'

This pass moves to NIR some offset computations that are currently implemented on the IR3 backend compiler, to allow NIR to possibly optimize them. For now, it only supports lowering byte-offset computation for image store and atomics. --- src/freedreno/Makefile.sources | 1 +

[Mesa-dev] [PATCH 6/9] ir3/compiler: Use the new lower_io_offsets pass

This effectively removes all offset calculations in ir3_compiler_nir::get_image_offset(). No regressions observed on affected tests from Khronos CTS and piglit suites, compared to master. Unfortunately shader-db is not helpful for stats in this case. Few shaders there exercise image store or

[Mesa-dev] [PATCH 4/9] ir3_compiler/nir: Handle newly added opcode nir_op_imad24_ir3

It simply emits an ir3_MAD_S24. --- src/freedreno/ir3/ir3_compiler_nir.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/freedreno/ir3/ir3_compiler_nir.c b/src/freedreno/ir3/ir3_compiler_nir.c index df948995000..05dc5ef7cf6 100644 --- a/src/freedreno/ir3/ir3_compiler_nir.c +++

Re: [Mesa-dev] [PATCH 00/38] radv, ac: 16-bit and 8-bit arithmetic and 8-bit storage

On 2/13/19 9:20 PM, Rhys Perry wrote: Quite a bit of the patches aren't specific to a single extension as many make code size-generic and some of the extensions intersect in functionality. It might still be possible to roughly order the patches by functionality but I'm not sure if it would be

Re: [Mesa-dev] [PATCH] radv: always export gl_SampleMask when the fragment shader uses it

Reviewed-by: Bas Nieuwenhuizen I'm assuming the real fix is for the shader to not write the sample mask if we have 1 sample? On Tue, Feb 12, 2019 at 6:52 PM Samuel Pitoiset wrote: > > For some reasons, this breaks trees rendering in Project Cars. > > Fixes: 85010585cde ("radv: only enable

Re: [Mesa-dev] [PATCH 00/38] radv, ac: 16-bit and 8-bit arithmetic and 8-bit storage

Quite a bit of the patches aren't specific to a single extension as many make code size-generic and some of the extensions intersect in functionality. It might still be possible to roughly order the patches by functionality but I'm not sure if it would be very useful (possible order in

Re: [Mesa-dev] Thoughts on fp64 for GLES?

On Wed, Feb 13, 2019 at 11:09 AM Elie Tournier wrote: > > > > On Wednesday, 13 February 2019, Stéphane Marchesin > wrote: >> >> On Wed, Feb 13, 2019 at 10:29 AM Elie Tournier >> wrote: >> > >> > >> > >> > On Wednesday, 13 February 2019, Ilia Mirkin wrote: >> >> >> >> On Wed, Feb 13, 2019 at

Re: [Mesa-dev] [PATCH] nir: move ALU instruction before the jump instruction

On 2/13/19 9:59 AM, Juan A. Suarez Romero wrote: > On Wed, 2019-02-13 at 09:16 -0800, Ian Romanick wrote: >> On 2/13/19 7:53 AM, Juan A. Suarez Romero wrote: >>> On Tue, 2019-02-12 at 16:22 -0800, Ian Romanick wrote: On 2/12/19 12:58 AM, Juan A. Suarez Romero wrote: > opt_split_alu_of_phi

Re: [Mesa-dev] RFC - libglvnd and GLXVND vendor enumeration to facilitate GLX multi-vendor PRIME GPU offload

On 02/12/2019 01:58 AM, Michel Dänzer wrote: On 2019-02-11 5:18 p.m., Andy Ritger wrote: On Mon, Feb 11, 2019 at 12:09:26PM +0100, Michel Dänzer wrote: On 2019-02-08 11:43 p.m., Kyle Brenneman wrote: Also, is Mesa the only client-side vendor library that works with the Xorg GLX module? I

Re: [Mesa-dev] Thoughts on fp64 for GLES?

On Wednesday, 13 February 2019, Stéphane Marchesin < stephane.marche...@gmail.com> wrote: > On Wed, Feb 13, 2019 at 10:29 AM Elie Tournier > wrote: > > > > > > > > On Wednesday, 13 February 2019, Ilia Mirkin > wrote: > >> > >> On Wed, Feb 13, 2019 at 12:47 PM Elie Tournier > wrote: > >> > > >>

Re: [Mesa-dev] Thoughts on fp64 for GLES?

On Wed, Feb 13, 2019 at 10:29 AM Elie Tournier wrote: > > > > On Wednesday, 13 February 2019, Ilia Mirkin wrote: >> >> On Wed, Feb 13, 2019 at 12:47 PM Elie Tournier >> wrote: >> > >> > On Fri, Jan 25, 2019 at 11:52:56AM -0800, Stéphane Marchesin wrote: >> > > On Fri, Jan 25, 2019 at 2:25 AM

Re: [Mesa-dev] Thoughts on fp64 for GLES?

On Wednesday, 13 February 2019, Ilia Mirkin wrote: > On Wed, Feb 13, 2019 at 1:29 PM Elie Tournier > wrote: > > > > > > > > On Wednesday, 13 February 2019, Ilia Mirkin > wrote: > >> > >> On Wed, Feb 13, 2019 at 12:47 PM Elie Tournier > wrote: > >> > > >> > On Fri, Jan 25, 2019 at 11:52:56AM

[Mesa-dev] [Bug 109391] LTO Build fails

https://bugs.freedesktop.org/show_bug.cgi?id=109391 Hi-Angel changed: What|Removed |Added Resolution|--- |FIXED Status|NEW

Re: [Mesa-dev] Thoughts on fp64 for GLES?

On Wed, Feb 13, 2019 at 1:29 PM Elie Tournier wrote: > > > > On Wednesday, 13 February 2019, Ilia Mirkin wrote: >> >> On Wed, Feb 13, 2019 at 12:47 PM Elie Tournier >> wrote: >> > >> > On Fri, Jan 25, 2019 at 11:52:56AM -0800, Stéphane Marchesin wrote: >> > > On Fri, Jan 25, 2019 at 2:25 AM

Re: [Mesa-dev] Thoughts on fp64 for GLES?

On Wednesday, 13 February 2019, Ilia Mirkin wrote: > On Wed, Feb 13, 2019 at 12:47 PM Elie Tournier > wrote: > > > > On Fri, Jan 25, 2019 at 11:52:56AM -0800, Stéphane Marchesin wrote: > > > On Fri, Jan 25, 2019 at 2:25 AM Gert Wollny > wrote: > > > > > > > > Am Donnerstag, den 24.01.2019,

Re: [Mesa-dev] RFC - libglvnd and GLXVND vendor enumeration to facilitate GLX multi-vendor PRIME GPU offload

On 02/11/2019 02:51 PM, Andy Ritger wrote: On Fri, Feb 08, 2019 at 03:43:25PM -0700, Kyle Brenneman wrote: On 2/8/19 2:33 PM, Andy Ritger wrote: On Fri, Feb 08, 2019 at 03:01:33PM -0500, Adam Jackson wrote: On Fri, 2019-02-08 at 10:19 -0800, Andy Ritger wrote: (1) If configured for PRIME

Re: [Mesa-dev] RFC - libglvnd and GLXVND vendor enumeration to facilitate GLX multi-vendor PRIME GPU offload

On 02/08/2019 11:19 AM, Andy Ritger wrote: (I'll omit EGL and Vulkan for the moment, for the sake of focus, and those APIs have programmatic ways to enumerate and select GPUs. Though, some of what we decide here for GLX we may want to leverage for other APIs.) Today, GLX implementations

Re: [Mesa-dev] [PATCH] nir: move ALU instruction before the jump instruction

On Wed, 2019-02-13 at 09:16 -0800, Ian Romanick wrote: > On 2/13/19 7:53 AM, Juan A. Suarez Romero wrote: > > On Tue, 2019-02-12 at 16:22 -0800, Ian Romanick wrote: > > > On 2/12/19 12:58 AM, Juan A. Suarez Romero wrote: > > > > opt_split_alu_of_phi moves ALU instruction to the end of continue

Re: [Mesa-dev] Thoughts on fp64 for GLES?

On Wed, Feb 13, 2019 at 12:47 PM Elie Tournier wrote: > > On Fri, Jan 25, 2019 at 11:52:56AM -0800, Stéphane Marchesin wrote: > > On Fri, Jan 25, 2019 at 2:25 AM Gert Wollny wrote: > > > > > > Am Donnerstag, den 24.01.2019, 22:25 -0800 schrieb Stéphane Marchesin: > > > > > > > > Yes, it's for

[Mesa-dev] [PATCH] radv/winsys: fix BO list creation when RADV_DEBUG=allbos is set

Fixes: 50fd253bd6e ("radv/winsys: Add priority handling during submit.") Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c

Re: [Mesa-dev] Thoughts on fp64 for GLES?

On Fri, Jan 25, 2019 at 11:52:56AM -0800, Stéphane Marchesin wrote: > On Fri, Jan 25, 2019 at 2:25 AM Gert Wollny wrote: > > > > Am Donnerstag, den 24.01.2019, 22:25 -0800 schrieb Stéphane Marchesin: > > > > > > Yes, it's for running virgl on top of GLES. To emulate fp64 in GL on > > > the guest

[Mesa-dev] [PATCH 2/2] nir/xfb: Properly align 64-bit values

Fixes: 19064b8c "nir: Add a pass for gathering transform feedback info" Cc: Alejandro Piñeiro --- src/compiler/nir/nir_gather_xfb_info.c | 4 1 file changed, 4 insertions(+) diff --git a/src/compiler/nir/nir_gather_xfb_info.c b/src/compiler/nir/nir_gather_xfb_info.c index

[Mesa-dev] [PATCH 1/2] compiler/types: Add a contains_64bit helper

--- src/compiler/glsl_types.cpp | 16 src/compiler/glsl_types.h | 6 ++ src/compiler/nir_types.cpp | 6 ++ src/compiler/nir_types.h| 1 + 4 files changed, 29 insertions(+) diff --git a/src/compiler/glsl_types.cpp b/src/compiler/glsl_types.cpp index

Re: [Mesa-dev] [PATCH] nir: move ALU instruction before the jump instruction

On 2/13/19 7:53 AM, Juan A. Suarez Romero wrote: > On Tue, 2019-02-12 at 16:22 -0800, Ian Romanick wrote: >> On 2/12/19 12:58 AM, Juan A. Suarez Romero wrote: >>> opt_split_alu_of_phi moves ALU instruction to the end of continue block. >>> >>> But if the continue block ends with a jump instruction

Re: [Mesa-dev] [PATCH 00/26] RadeonSI: Primitive culling with async compute

On Wed, Feb 13, 2019 at 11:51 AM Axel Davy wrote: > On 13/02/2019 17:42, Marek Olšák wrote: > > On Wed, Feb 13, 2019 at 2:28 AM Axel Davy wrote: > >> On 13/02/2019 06:15, Marek Olšák wrote: >> > I decided to enable this optimization on all Pro graphics cards. >> > The reason is that I haven't

Re: [Mesa-dev] [PATCH 00/26] RadeonSI: Primitive culling with async compute

On 13/02/2019 17:42, Marek Olšák wrote: On Wed, Feb 13, 2019 at 2:28 AM Axel Davy > wrote: On 13/02/2019 06:15, Marek Olšák wrote: > I decided to enable this optimization on all Pro graphics cards. > The reason is that I haven't had time to benchmark

Re: [Mesa-dev] [PATCH 00/26] RadeonSI: Primitive culling with async compute

On Wed, Feb 13, 2019 at 2:28 AM Axel Davy wrote: > On 13/02/2019 06:15, Marek Olšák wrote: > > I decided to enable this optimization on all Pro graphics cards. > > The reason is that I haven't had time to benchmark games. > > This decision may be changed based on community feedback, etc. > > >

Re: [Mesa-dev] [PATCH 00/26] RadeonSI: Primitive culling with async compute

Dieter, you need final LLVM 8.0. Marek On Wed, Feb 13, 2019 at 11:02 AM Dieter Nützel wrote: > GREAT stuff, Marek! > > But sadly some crashes. > Is my LLVM git version to old? > 7. Jan 2019 (short before 8.0 cut) > > LLVM (http://llvm.org/): >LLVM version 8.0.0svn >Optimized build. >

Re: [Mesa-dev] [PATCH 00/26] RadeonSI: Primitive culling with async compute

GREAT stuff, Marek! But sadly some crashes. Is my LLVM git version to old? 7. Jan 2019 (short before 8.0 cut) LLVM (http://llvm.org/): LLVM version 8.0.0svn Optimized build. Default target: x86_64-unknown-linux-gnu Host CPU: nehalem Registered Targets: amdgcn - AMD GCN GPUs

Re: [Mesa-dev] [PATCH] nir: move ALU instruction before the jump instruction

On Tue, 2019-02-12 at 16:22 -0800, Ian Romanick wrote: > On 2/12/19 12:58 AM, Juan A. Suarez Romero wrote: > > opt_split_alu_of_phi moves ALU instruction to the end of continue block. > > > > But if the continue block ends with a jump instruction (an explicit > > "continue" instruction) then the

Re: [Mesa-dev] [PATCH 4/4] nir: reorder some code

I'm not sure that I think about this one. I kind of like the pattern where the first thing in the switch case on subtype is a cast to that subtype. It's also just a cast in debug builds so it should generate zero code. On February 13, 2019 02:00:49 Timothy Arceri wrote: The compile shoud do

Re: [Mesa-dev] [PATCH 1/4] nir: prehash instruction in nir_instr_set_add_or_rewrite()

Yeah, I've always felt like this helper should use the pre-hashed versions. Rb On February 13, 2019 02:00:44 Timothy Arceri wrote: There is no need to hash the instruction twice, especially as we end up adding it in the majority of cases. --- src/compiler/nir/nir_instr_set.c | 9 + 1

Re: [Mesa-dev] [PATCH] nir/xfb: Properly align 64-bit values

I vaguely remember glslang doing something similar when computing offsets. This, and other xfb corner cases, were the reason I thought/concluded it would made sense to let glslang (or any other frontend) to do the offset assignment also for structs, so SPIR-V consuming drivers didn't need to

Re: [Mesa-dev] [PATCH 2/3] st/mesa: enable GL_EXT_float_blend when possible

Reviewed-by: Erik Faye-Lund And just for the record, I think this is the right "compromise" between checking all possible formats and facilitating fallbacks. On Tue, 2019-02-12 at 22:40 -0500, Ilia Mirkin wrote: > If the driver supports PIPE_BIND_BLENABLE on RGBA32F, flip > EXT_float_blend on

Re: [Mesa-dev] A few NIR compile time optimisations

On 13/2/19 8:47 pm, Timothy Arceri wrote: On 13/2/19 8:38 pm, Timothy Arceri wrote: On 13/2/19 8:26 pm, Connor Abbott wrote: Reviewed-by: Connor Abbott > I'm a bit surprised it's that slow... do you have any idea what's going on? I've made flamegraphs in the past

Re: [Mesa-dev] A few NIR compile time optimisations

On 13/2/19 10:01 pm, Michel Dänzer wrote: On 2019-02-13 10:38 a.m., Timothy Arceri wrote: On 13/2/19 8:26 pm, Connor Abbott wrote: Reviewed-by: Connor Abbott mailto:cwabbo...@gmail.com>> I'm a bit surprised it's that slow... do you have any idea what's going on? I've made flamegraphs in the

[Mesa-dev] [Bug 109622] Risen 3 flickering rainbow artifacts

https://bugs.freedesktop.org/show_bug.cgi?id=109622 Bug ID: 109622 Summary: Risen 3 flickering rainbow artifacts Product: Mesa Version: 18.3 Hardware: Other OS: All Status: NEW Severity: normal

Re: [Mesa-dev] A few NIR compile time optimisations

On 2019-02-13 10:38 a.m., Timothy Arceri wrote: > On 13/2/19 8:26 pm, Connor Abbott wrote: >> Reviewed-by: Connor Abbott > > >> >> I'm a bit surprised it's that slow... do you have any idea what's >> going on? I've made flamegraphs in the past on i965 to see where most

[Mesa-dev] [PATCH v5 4/4] i965: Enabled the OES_copy_image extension on Gen 7 GPUs

OES_copy_image extension was disabled on Gen7 due to the lack of support for ETC2 images. Enabled it back. (Kenneth Graunke) v2: - Removed the blank lines in the comments above OES_copy_image and OES_texture_view extensions in intel_extensions.c (Nanley Chery) ---

[Mesa-dev] [PATCH v5 3/4] i965: Fixed the CopyImageSubData for ETC2 on Gen < 8

For CopyImageSubData to copy the data during the 1st draw call, we need to update the shadow tree right before the rendering. v2: - Added assertion that the miptree doesn't need update at the time we update the texture surface. (Nanley Chery) v3: - As we now update the tree before the

[Mesa-dev] [PATCH v5 2/4] i965: Faking the ETC2 compression on Gen < 8 GPUs using two miptrees.

GPUs Gen < 8 cannot sample ETC2 formats. So far, they converted the compressed EAC/ETC2 images to non-compressed RGBA images. When GetCompressed* functions were called, the pixels were returned in this RGBA format and not the compressed format that was expected. Trying to fix this problem, we use

[Mesa-dev] [PATCH v5 1/4] i965: Rename intel_mipmap_tree::r8stencil_* -> ::shadow_*

From: Nanley Chery Use more generic field names. We'll reuse these fields for a workaround with ASTC miptrees. Reviewed-by: Eleni Maria Stea --- src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 8 src/mesa/drivers/dri/i965/intel_mipmap_tree.c| 16

[Mesa-dev] [PATCH v5 0/4] improved the support for ETC2 formats on Gen 7

Intel Gen7 GPUs don't support the ETC2 formats natively and in order to show the pixels properly we convert them to RGBA and create RGBA miptrees. The problem with that is that the GetCompressed* functions that should return the compressed pixel values return the RGBA instead. These patches are

Re: [Mesa-dev] [PATCH v2] egl/dri2: try to bind old context if bindContext failed

Hello Emil, thanks for your feedback, I agree, dri2_make_current() looks complex. I'll comment inline. Emil Velikov writes: > Hi all, > > Haven't looked it this has landed or not. > > On Tue, 5 Feb 2019 at 16:41, Eric Engestrom wrote: >> >> On Friday, 2019-02-01 13:36:27 +, Luigi

Re: [Mesa-dev] A few NIR compile time optimisations

On 13/2/19 8:38 pm, Timothy Arceri wrote: On 13/2/19 8:26 pm, Connor Abbott wrote: Reviewed-by: Connor Abbott > I'm a bit surprised it's that slow... do you have any idea what's going on? I've made flamegraphs in the past on i965 to see where most of the time is

Re: [Mesa-dev] A few NIR compile time optimisations

On 13/2/19 8:26 pm, Connor Abbott wrote: Reviewed-by: Connor Abbott > I'm a bit surprised it's that slow... do you have any idea what's going on? I've made flamegraphs in the past on i965 to see where most of the time is spent. Some shaders are actually faster,

Re: [Mesa-dev] A few NIR compile time optimisations

Reviewed-by: Connor Abbott I'm a bit surprised it's that slow... do you have any idea what's going on? I've made flamegraphs in the past on i965 to see where most of the time is spent. On Wed, Feb 13, 2019 at 9:00 AM Timothy Arceri wrote: > Currently the radeonsi NIR backend takes around

Re: [Mesa-dev] [PATCH 2/4] nir: turn ssa check into an assert

On 13/2/19 7:00 pm, Timothy Arceri wrote: Everthing should be in ssa form when this is called. Checking for it here is expensive so turn this into an assert instead. Do the cheap thing first and check if we can even progress with this instruction type. Sorry this second line was meant to be

[Mesa-dev] [PATCH 2/4] nir: turn ssa check into an assert

Everthing should be in ssa form when this is called. Checking for it here is expensive so turn this into an assert instead. Do the cheap thing first and check if we can even progress with this instruction type. --- src/compiler/nir/nir_instr_set.c | 14 +++--- 1 file changed, 11

[Mesa-dev] [PATCH 1/4] nir: prehash instruction in nir_instr_set_add_or_rewrite()

There is no need to hash the instruction twice, especially as we end up adding it in the majority of cases. --- src/compiler/nir/nir_instr_set.c | 9 + 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/src/compiler/nir/nir_instr_set.c b/src/compiler/nir/nir_instr_set.c index

[Mesa-dev] [PATCH 3/4] nir: turn an ssa check in nir_search into an assert

Everything should be in ssa form when we call this. This is a hotpath so replace the check with an assert. --- src/compiler/nir/nir_search.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/compiler/nir/nir_search.c b/src/compiler/nir/nir_search.c index

[Mesa-dev] [PATCH 4/4] nir: reorder some code

The compile shoud do this for us so this is more for neatness rather than speed. --- src/compiler/nir/nir_search.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/compiler/nir/nir_search.c b/src/compiler/nir/nir_search.c index d257b639189..f0a79a54301 100644 ---

[Mesa-dev] A few NIR compile time optimisations

Currently the radeonsi NIR backend takes around twice the time of the tgsi backend to compile shader-db. These are some first steps at reducing the overhead of NIR. This series reduces the compile time of a Deus Ex program I was profiling by around 5%.