Re: [Mesa-dev] [PATCH 5/5] anv: disable repacking for compression for applicable gen

On Thu, Jun 27, 2019 at 9:55 AM Dongwon Kim wrote: > > set bit15 (Disable Rebacking for Compression) of CACHE_MODE_0 register Repacking With minor nits fixed. This series is: Reviewed-by: Anuj Phogat I'll push the series after testing with these changes. Thanks for the patches :) > i

Re: [Mesa-dev] [PATCH 4/5] iris: disable repacking for compression for applicable gen

On Thu, Jun 27, 2019 at 9:55 AM Dongwon Kim wrote: > > set bit15 (Disable Rebacking for Compression) of CACHE_MODE_0 register Repacking > if the gen attribute, 'disable_ccs_repack' is set. > > Signed-off-by: Dongwon Kim > --- > src/gallium/drivers/iris/iris_state.c | 10 ++ > 1 file

Re: [Mesa-dev] [PATCH 3/5] i965: disable repacking for compression for applicable gen

On Thu, Jun 27, 2019 at 9:55 AM Dongwon Kim wrote: > > set bit15 (Disable Rebacking for Compression) of CACHE_MODE_0 register Disable Repacking > if the gen attribute, 'disable_ccs_repack' is set. > > Signed-off-by: Dongwon Kim > --- > src/mesa/drivers/dri/i965/brw_defines.h | 1 + >

Re: [Mesa-dev] [PATCH 2/5] intel: add disable_ccs_repack to gen_device_info

On Thu, Jun 27, 2019 at 9:55 AM Dongwon Kim wrote: > > add a new attribute, 'disable_ccs_repack' to gen_device info, which > indicates whether repacking of components in certain pixel formats > before compression needs to be disabled to keep the compatibility > with decompression capability of

Re: [Mesa-dev] [PATCH v2] ehl: disable repacking for compression for compatibilty

+mesa-dev On Thu, Jun 20, 2019 at 12:20 PM Anuj Phogat wrote: > > I sent out comments on your older patch. They applies to this patch too. > Split i965 and anv changes in separate patches. > > On Thu, Jun 20, 2019 at 11:25 AM Dongwon Kim wrote: > > > > Repacking

Re: [Mesa-dev] [PATCH] iris/ehl: disable repacking for compression for compatibilty

On Tue, Jun 4, 2019 at 9:20 AM Dongwon Kim wrote: > > Repacking components in certain pixel formats before compression > shouldn't be done for EHL to keep the compatibility with decompression > capability in its display controller. > > Signed-off-by: Dongwon Kim > --- >

Re: [Mesa-dev] [PATCH] intel/compiler/icl: Use tcs barrier id bits 24:30 instead of 24:27

Topi, Are you also planning to send out a similar patch for Iris ? Thanks Anuj On Mon, Apr 8, 2019 at 4:20 PM Anuj Phogat wrote: > > On Wed, Mar 27, 2019 at 9:47 AM Topi Pohjolainen > wrote: > > > > Similarly to 1cc17fb731466c68586915acbb916586457b19bc > > &g

Re: [Mesa-dev] [PATCH] intel/compiler/icl: Use tcs barrier id bits 24:30 instead of 24:27

On Wed, Mar 27, 2019 at 9:47 AM Topi Pohjolainen wrote: > > Similarly to 1cc17fb731466c68586915acbb916586457b19bc > > Fixes gpu hangs with dEQP-VK.tessellation.shader_input_output.barrier > > CC: Anuj Phogat > CC: Clayton Craft > Signed-off-by: Topi Pohjolainen >

Re: [Mesa-dev] [PATCH] intel/disasm: Disassemble JIP offset for while

> > ___ > mesa-dev mailing list > mesa-dev@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/mesa-dev looks fine to me. Reviewed-by: Anuj Phogat ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH] intel/compiler: Set flag reg/subreg number properly

_set_default_flag_reg(p, 0, 0); >brw_MOV(p, offset(retype(payload, BRW_REGISTER_TYPE_UD), 1), >offset(retype(implied_header, BRW_REGISTER_TYPE_UD), 1)); >brw_pop_insn_state(p); > -- > 2.20.1 > > ___ > mesa-dev m

Re: [Mesa-dev] [PATCH 1/5] intel/fs: Exclude control sources from execution type and region alignment calculations.

Fixes all subgroup test failures in vulkancts on Icelake. Series is: Tested-by: Anuj Phogat On Fri, Jan 18, 2019 at 4:09 PM Francisco Jerez wrote: > > Currently the execution type calculation will return a bogus value in > cases like: > > mov_indirect(8) vgrf0:w, vgrf1:w

Re: [Mesa-dev] [PATCH] intel/eu: Stop overriding exec sizes in send_indirect_message

, BRW_REGISTER_TYPE_UD)); > brw_inst_set_sfid(devinfo, send, sfid); > -- Reviewed-by: Anuj Phogat > 2.20.1 > > ___ > mesa-dev mailing list > mesa-dev@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/mesa-dev ___

Re: [Mesa-dev] [PATCH] i965: Don't override subslice count to 4 on Gen11.

nfo->gen >= 9 && devinfo->gen < 11) > subslices = 4 * brw->screen->devinfo.num_slices; > >unsigned scratch_ids_per_subslice; > -- > 2.19.1 > Reviewed-by: Anuj Phogat ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH 2/5] i965/icl: Set use full ways in L3CNTLREG

On Mon, Nov 26, 2018 at 11:47 AM Francisco Jerez wrote: > > Anuj Phogat writes: > > > L3 allocation table in h/w specification recommends using 4 KB > > granularity for programming allocation fields in L3CNTLREG. > > > > Signed-off-by: Anuj Phogat > >

[Mesa-dev] [PATCH V2 1/4] i965/icl: Fix L3 configurations

Use L3 configuration specified in h/w specification. V2: Drop configs which do under allocation of l3 cache. Bump up the comment above table. Signed-off-by: Anuj Phogat Cc: Kenneth Graunke Cc: Francisco Jerez --- src/intel/common/gen_l3_config.c | 12 ++-- 1 file changed, 6

Re: [Mesa-dev] [PATCH 4/5] i965/icl: Set config#9 as default config

Dropping this patch. On Tue, Nov 13, 2018 at 2:34 PM Anuj Phogat wrote: > > Config#6 recommended by h/w specification causes multiple piglit > regressions. Use config#9 instead which works well. Setting a weight > here so that we get the desired config. > > Signed-off-by:

Re: [Mesa-dev] [PATCH 1/5] i965/icl: Fix L3 configurations

On Fri, Nov 16, 2018 at 2:52 PM Francisco Jerez wrote: > > Anuj Phogat writes: > > > On Fri, Nov 16, 2018 at 6:21 AM Eero Tamminen > > wrote: > >> > >> Hi, > >> > >> On 16.11.2018 10.33, Francisco Jerez wrote: > >> > Kenne

Re: [Mesa-dev] [PATCH 1/5] i965/icl: Fix L3 configurations

On Fri, Nov 16, 2018 at 6:21 AM Eero Tamminen wrote: > > Hi, > > On 16.11.2018 10.33, Francisco Jerez wrote: > > Kenneth Graunke writes: > [...] > >> Perhaps we'll get both configs working, and then will want to be able > >> to select between them. I question whether the additional URB is truly

Re: [Mesa-dev] [PATCH 1/5] i965/icl: Fix L3 configurations

No problem Ken. On Tue, Nov 13, 2018 at 9:48 PM Kenneth Graunke wrote: > On Tuesday, November 13, 2018 2:33:58 PM PST Anuj Phogat wrote: > > Use L3 configuration table specified in h/w specification. > > > > Signed-off-by: Anuj Phogat > > Cc: Kenneth Graunke >

[Mesa-dev] [PATCH 1/5] i965/icl: Fix L3 configurations

Use L3 configuration table specified in h/w specification. Signed-off-by: Anuj Phogat Cc: Kenneth Graunke Cc: Francisco Jerez Cc: Lionel Landwerlin --- src/intel/common/gen_l3_config.c | 16 ++-- 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/src/intel/common

[Mesa-dev] [PATCH 2/5] i965/icl: Set use full ways in L3CNTLREG

L3 allocation table in h/w specification recommends using 4 KB granularity for programming allocation fields in L3CNTLREG. Signed-off-by: Anuj Phogat Cc: Kenneth Graunke Cc: Francisco Jerez Cc: Lionel Landwerlin --- src/mesa/drivers/dri/i965/brw_defines.h | 1 + src/mesa/drivers/dri/i965

[Mesa-dev] [PATCH 3/5] intel/icl: Set way_size_per_bank to 4

Signed-off-by: Anuj Phogat Cc: Kenneth Graunke Cc: Francisco Jerez Cc: Lionel Landwerlin --- src/intel/common/gen_l3_config.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/intel/common/gen_l3_config.c b/src/intel/common/gen_l3_config.c index 079608198bc

[Mesa-dev] [PATCH 5/5] anv/icl: Set use full ways in L3CNTLREG

L3 allocation table in h/w specification recommends using 4 KB granularity for programming allocation fields in L3CNTLREG. Signed-off-by: Anuj Phogat Cc: Kenneth Graunke Cc: Francisco Jerez Cc: Lionel Landwerlin --- src/intel/genxml/gen11.xml | 1 + src/intel/vulkan/genX_cmd_buffer.c

[Mesa-dev] [PATCH 4/5] i965/icl: Set config#9 as default config

Config#6 recommended by h/w specification causes multiple piglit regressions. Use config#9 instead which works well. Setting a weight here so that we get the desired config. Signed-off-by: Anuj Phogat Cc: Kenneth Graunke Cc: Francisco Jerez Cc: Lionel Landwerlin --- src/intel/common

Re: [Mesa-dev] [PATCH] intel/l3: update ICL L3 configurations

Lionel, I have this patch along with few other patches in my 'icl-urb-configs' branch at https://github.com/aphogat/mesa. But, I'm getting many piglit regressions with these patches. That's the reason I haven't sent them out to the list. I also talked to Ken about my changes. Unfortunately we

[Mesa-dev] [PATCH] anv/icl: Set Error Detection Behavior Control Bit in L3CNTLREG

The default setting of this bit is not the desirable behavior. WA_1406697149 Signed-off-by: Anuj Phogat --- src/intel/genxml/gen11.xml | 1 + src/intel/vulkan/genX_cmd_buffer.c | 7 +++ 2 files changed, 8 insertions(+) diff --git a/src/intel/genxml/gen11.xml b/src/intel/genxml

[Mesa-dev] [PATCH] i965/icl: Set Error Detection Behavior Control Bit in L3CNTLREG

The default setting of this bit is not the desirable behavior. WA_1406697149 Signed-off-by: Anuj Phogat --- src/mesa/drivers/dri/i965/brw_defines.h | 1 + src/mesa/drivers/dri/i965/brw_state_upload.c | 7 +++ 2 files changed, 8 insertions(+) diff --git a/src/mesa/drivers/dri/i965

[Mesa-dev] [PATCH] i965/anv: Disable prefetching of sampler state entries

WA_1606682166: Incorrect TDL's SSP address shift in SARB for 16:6 & 18:8 modes. Disable the Sampler state prefetch functionality in the SARB by programming 0xB000[30] to '1'. This is to be done at boot time and the feature must remain disabled permanently. Signed-off-by: Anuj Phogat ---

[Mesa-dev] [PATCH] i965/icl: Disable prefetching of sampler state entries

en Signed-off-by: Anuj Phogat Cc: Mark Janes --- Latest kernel from drm-tip do have this workaround implemented but we're seeing few deqp regressions with that kernel. I'm adding this workaround to Mesa to make some progress in ICL testing on CI. We can always revert the patch when we don't n

Re: [Mesa-dev] [PATCH] intel/compiler/icl: Use invocation id bits 22:16 instead of 23:17

gt; > Fixes: > KHR-GL46.tessellation_shader.tessellation_shader_tc_barriers.barrier_guarded_read_write_calls > > CC: Anuj Phogat > CC: Mark Janes > Signed-off-by: Topi Pohjolainen > --- > src/intel/compiler/brw_fs.cpp | 8 ++-- > 1 file changed, 6 insertions(+), 2 deletions(-) > > diff -

Re: [Mesa-dev] [PATCH] intel/compiler/icl: Use barrier id bits 24:30 instead of 24:27, 31

On Thu, Sep 20, 2018 at 11:01 PM Topi Pohjolainen wrote: > > Fixes gpu hangs with Carchase and Manhattan. > > Cc: Anuj Phogat > Signed-off-by: Topi Pohjolainen > --- > src/intel/compiler/brw_fs_visitor.cpp | 16 +--- > 1 file changed, 13 insertions(+), 3 del

[Mesa-dev] [PATCH] intel/icl: Fix URB size for different SKUs

Different ICL SKUs have different URB sizes. Signed-off-by: Anuj Phogat --- src/intel/dev/gen_device_info.c | 43 ++--- 1 file changed, 29 insertions(+), 14 deletions(-) diff --git a/src/intel/dev/gen_device_info.c b/src/intel/dev/gen_device_info.c index 3cece52a041

[Mesa-dev] [PATCH] i965: Set minimum message length of 2 for SIMD8 URB write

It fixes simulator error about h/w spec violation with piglit test: glsl-1.50/execution/geometry/generate-zero-primitives.shader_test. Simulator throws an error if dataLength < 1 for URB SIMD 8 write message. Signed-off-by: Anuj Phogat Cc: Kenneth Graunke Cc: --- I doubt if sett

[Mesa-dev] [PATCH V2] i965/icl: Set Enabled Texel Offset Precision Fix bit

h/w specification requires this bit to be always set. V2: Fix bit mask (Chris Wilson) Suggested-by: Kenneth Graunke Signed-off-by: Anuj Phogat --- src/mesa/drivers/dri/i965/brw_defines.h | 4 src/mesa/drivers/dri/i965/brw_state_upload.c | 7 +++ 2 files changed, 11 insertions

Re: [Mesa-dev] [PATCH] i965/icl: Set Enabled Texel Offset Precision Fix bit

On Tue, Aug 28, 2018 at 10:57 AM Chris Wilson wrote: > > Quoting Anuj Phogat (2018-08-28 18:53:59) > > h/w specification requires this bit to be always set. > > > > Suggested-by: Kenneth Graunke > > Signed-off-by: Anuj Phogat > > --- > > src/me

[Mesa-dev] [PATCH] anv/icl: Set Enabled Texel Offset Precision Fix bit

h/w specification requires this bit to be always set. Suggested-by: Kenneth Graunke Signed-off-by: Anuj Phogat --- src/intel/genxml/gen11.xml| 5 + src/intel/vulkan/genX_state.c | 14 ++ 2 files changed, 19 insertions(+) diff --git a/src/intel/genxml/gen11.xml b/src/intel

[Mesa-dev] [PATCH] i965/icl: Set Enabled Texel Offset Precision Fix bit

h/w specification requires this bit to be always set. Suggested-by: Kenneth Graunke Signed-off-by: Anuj Phogat --- src/mesa/drivers/dri/i965/brw_defines.h | 4 src/mesa/drivers/dri/i965/brw_state_upload.c | 7 +++ 2 files changed, 11 insertions(+) diff --git a/src/mesa/drivers

Re: [Mesa-dev] [PATCH] i965/icl: Allow headerless sampler messages for pre-emptable contexts

On Mon, Aug 20, 2018 at 2:13 PM Kenneth Graunke wrote: > > On Monday, August 20, 2018 10:26:29 AM PDT Anuj Phogat wrote: > > On Mon, Aug 20, 2018 at 12:18 AM Kenneth Graunke wrote: > [snip] > > > I don't know if people are trying to enable pre-emption during GPGPU > &g

Re: [Mesa-dev] [PATCH] i965/icl: Allow headerless sampler messages for pre-emptable contexts

On Mon, Aug 20, 2018 at 12:18 AM Kenneth Graunke wrote: > > On Friday, August 17, 2018 5:13:25 PM PDT Anuj Phogat wrote: > > It fixes simulator warnings in piglit tests complaining about missing > > support for headerless sampler messages for pre-emptable contexts. > &g

[Mesa-dev] [PATCH] anv/icl: Allow headerless sampler messages for pre-emptable contexts

It fixes simulator warnings in vulkancts tests complaining about missing support for headerless sampler messages for pre-emptable contexts. Bit 5 in SAMPLER MODE register is newly introduced for ICLLP. Signed-off-by: Anuj Phogat --- src/intel/genxml/gen11.xml| 5 + src/intel/vulkan

[Mesa-dev] [PATCH] anv/icl: Disable binding table prefetching

Gen 11 workarounds table #2056 WABTPPrefetchDisable suggests to disable prefetching of binding tables for ICLLP A0 and B0 steppings. We have a similar patch for i965 driver in Mesa commit a5889d70. Signed-off-by: Anuj Phogat --- src/intel/vulkan/genX_pipeline.c | 21 +++-- 1

[Mesa-dev] [PATCH] i965/icl: Allow headerless sampler messages for pre-emptable contexts

It fixes simulator warnings in piglit tests complaining about missing support for headerless sampler messages for pre-emptable contexts. Bit 5 in SAMPLER MODE register is newly introduced for ICLLP. Signed-off-by: Anuj Phogat --- src/mesa/drivers/dri/i965/brw_defines.h | 4 src/mesa

Re: [Mesa-dev] [PATCH] intel: Switch the order of the 2x MSAA sample positions

> * > * 4X MSAA sample index / number layout > @@ -107,7 +107,7 @@ gen6_get_sample_position(struct gl_context *ctx, > void > gen6_set_sample_maps(struct gl_context *ctx) > { > - uint8_t map_2x[2] = {0, 1}; > + uint8_t map_2x[2] = {1, 0}; > uint8_t

Re: [Mesa-dev] [PATCH] i965: Expose ARB_base_instance extension

t; > ___ > mesa-dev mailing list > mesa-dev@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/mesa-dev It's EXT_base_instance for gles. With suggested changes to Subject: Reviewed-by: Anuj Phogat ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH] i965/icl: Disable binding table prefetching

checks in the code. Signed-off-by: Anuj Phogat --- src/intel/blorp/blorp_genX_exec.h | 7 +++ src/mesa/drivers/dri/i965/genX_state_upload.c | 14 +- 2 files changed, 20 insertions(+), 1 deletion(-) diff --git a/src/intel/blorp/blorp_genX_exec.h b/src/intel/blorp

Re: [Mesa-dev] [PATCH 01/11] spirv: initialize is_vertex_input

: > VARYING_SLOT_VAR0; >} else if (vtn_var->mode != vtn_variable_mode_uniform) { > vtn_warn("Location must be on input, output, uniform, sampler or " > -- > 2.18.0 > > ___ > mesa-dev mailing list > mesa-dev@lists.f

Re: [Mesa-dev] [PATCH] i965/icl: Don't set float blend optimization bit in CACHE_MODE_SS

Bump. On Fri, Jun 1, 2018 at 2:40 PM Anuj Phogat wrote: > > CACHE_MODE_SS is not listed in gfxspecs table for user mode > non-privileged registers. So, making any changes from Mesa > will do nothing. Kernel is already setting this bit in > CACHE_MODE_SS register which is saved/r

Re: [Mesa-dev] [PATCH] anv/icl: Don't set float blend optimization bit in CACHE_MODE_SS

Bump On Fri, Jun 1, 2018 at 2:40 PM Anuj Phogat wrote: > > CACHE_MODE_SS is not listed in gfxspecs table for user mode > non-privileged registers. So, making any changes from Mesa > will do nothing. Kernel is already setting this bit in > CACHE_MODE_SS register which is saved/r

[Mesa-dev] [PATCH] anv/icl: Don't set float blend optimization bit in CACHE_MODE_SS

CACHE_MODE_SS is not listed in gfxspecs table for user mode non-privileged registers. So, making any changes from Mesa will do nothing. Kernel is already setting this bit in CACHE_MODE_SS register which is saved/restored to/from the HW context image. Signed-off-by: Anuj Phogat Cc: Lionel

[Mesa-dev] [PATCH] i965/icl: Don't set float blend optimization bit in CACHE_MODE_SS

CACHE_MODE_SS is not listed in gfxspecs table for user mode non-privileged registers. So, making any changes from Mesa will do nothing. Kernel is already setting this bit in CACHE_MODE_SS register which is saved/restored to/from the HW context image. Signed-off-by: Anuj Phogat Cc: Lionel

[Mesa-dev] [PATCH] i965/glk: Add l3 banks count for 2x6 configuration

2x6 configuration with pci-id 0x3185 has same number of banks (2) as 3x6 configuration (pci-id 0x3184). Reported-by: Clayton Craft <clayton.a.cr...@intel.com> Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com> Cc: <mesa-sta...@lists.freedesktop.org> Cc: Lionel Landwerlin

Re: [Mesa-dev] [PATCH 2/2] intel/isl/storage: Don't lower most UNORM formats on gen11+

Yes, I did. No regressions. On Thu, May 10, 2018 at 12:09 PM, Jason Ekstrand <ja...@jlekstrand.net> wrote: > Did you get a chance to test them? > > > On May 10, 2018 11:58:54 Anuj Phogat <anuj.pho...@gmail.com> wrote: > >> On Mon, May 7, 2018 at 2:56 PM, Jas

Re: [Mesa-dev] [PATCH 2/2] intel/isl/storage: Don't lower most UNORM formats on gen11+

turn (devinfo->gen >= 11 ? format : ISL_FORMAT_R8_UINT); > > default: > assert(!"Unknown image format"); > -- > 2.5.0.400.gff86faf > > ___ > mesa-dev mailing list > mesa-dev@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/mesa-dev Both patches are: Reviewed-by and Tested-by: Anuj Phogat <anuj.pho...@gmail.com> ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH] spirv: Apply OriginUpperLeft to FragCoord

fallthrough */ >case SpvBuiltInFragCoord: > nir_var->data.pixel_center_integer = b->pixel_center_integer; > + /* fallthrough */ > + case SpvBuiltInSamplePosition: > + nir_var->data.origin_upper_left = b->origin_upper_left; > break; >

Re: [Mesa-dev] [PATCH] intel: fix aubinator include

drm > * So, reuse intel_aub.h from libdrm and #define the > -- > 2.17.0 > > _______ > mesa-dev mailing list > mesa-dev@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/mesa-dev Reviewed-by: Anuj Phogat <an

Re: [Mesa-dev] [PATCH] anv: Advertise variableMultisampleRate

ing list > mesa-dev@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/mesa-dev Reviewed-by: Anuj Phogat <anuj.pho...@gmail.com> ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH] anv: Don't advertise Float64 or Int64 on HW withou 64-bit types

urceMinLod = false, >.variableMultisampleRate = true, > -- > 2.5.0.400.gff86faf > > ___ > mesa-dev mailing list > mesa-dev@lists.freedesktop.org > https:

[Mesa-dev] [PATCH] anv/icl: Enable Vulkan on Ice Lake

This patch enables the Vulkan driver on Ice Lake h/w with added warning about preliminary support. Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com> --- src/intel/vulkan/anv_device.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/intel/vulkan/anv_device.c b/src/intel/

Re: [Mesa-dev] [PATCH] i965/urb/cnl: Apply gen7 CS stall

On Thu, Apr 19, 2018 at 7:44 AM, Topi Pohjolainen < topi.pohjolai...@gmail.com> wrote: > This didn't actually help the failing tests I'm looking at > but hopefully has teeth elsewhere. > > CC: Jason Ekstrand <ja...@jlekstrand.net> > CC: Jordan Justen <jordan.l.jus..

Re: [Mesa-dev] [PATCH 2/2] i965/blorp: Do the gen11 BTI flush

For the series: Reviewed-by: Anuj Phogat <anuj.pho...@gmail.com> This might explain piglit GPU hangs or failures. I'll do a piglit run with these patches. Thanks Anuj On Tue, Apr 17, 2018 at 3:10 PM, Jason Ekstrand <ja...@jlekstrand.net> wrote: > --- > src/mes

[Mesa-dev] [PATCH] Add more Coffee Lake brand strings

Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com> --- include/pci_ids/i965_pci_ids.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/pci_ids/i965_pci_ids.h b/include/pci_ids/i965_pci_ids.h index 8716d758f0..c740a50bca 100644 --- a/include/pci_ids/i965_pci

Re: [Mesa-dev] [PATCH 01/17] intel: Add a preliminary device for Ice Lake

On Wed, Feb 21, 2018 at 11:04 AM, Matt Turner <matts...@gmail.com> wrote: > On Wed, Feb 21, 2018 at 10:37 AM, Anuj Phogat <anuj.pho...@gmail.com> wrote: >> On Wed, Feb 21, 2018 at 9:22 AM, Rafael Antognolli >> <rafael.antogno...@intel.com> wrote: >>> My u

Re: [Mesa-dev] [PATCH 01/17] intel: Add a preliminary device for Ice Lake

is patch should be the last patch in this series. Otherwise we'll have a commit with ICL PCI IDs but missing compiler changes. Almost nothing will work without the compiler patches. > > Rafael > > On Tue, Feb 20, 2018 at 09:15:08PM -0800, Matt Turner wrote: >> From: Anuj Phogat <a

Re: [Mesa-dev] [PATCH 01/17] intel: Add a preliminary device for Ice Lake

On Wed, Feb 21, 2018 at 11:09 AM, Scott D Phillips <scott.d.phill...@intel.com> wrote: > Anuj Phogat <anuj.pho...@gmail.com> writes: > >> On Wed, Feb 21, 2018 at 10:00 AM, Scott D Phillips >> <scott.d.phill...@intel.com> wrote: >>> Matt Turner <

Re: [Mesa-dev] [PATCH 01/17] intel: Add a preliminary device for Ice Lake

On Wed, Feb 21, 2018 at 10:00 AM, Scott D Phillips <scott.d.phill...@intel.com> wrote: > Matt Turner <matts...@gmail.com> writes: > >> From: Anuj Phogat <anuj.pho...@intel.com> >> >> Signed-off-by: Anuj Phogat <anuj.pho...@intel.com> &g

Re: [Mesa-dev] [PATCH 05/10] anv/icl: Don't use DISPATCH_MODE_SIMD4X2

On Thu, Feb 15, 2018 at 6:07 PM, Jason Ekstrand <ja...@jlekstrand.net> wrote: > On Thu, Feb 15, 2018 at 5:44 PM, Anuj Phogat <anuj.pho...@gmail.com> wrote: >> >> Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com> >> --- >> src/intel/vulkan/genX

Re: [Mesa-dev] [PATCH 00/10] intel/anv: Prepare to add Ice Lake (ICL) support

On Thu, Feb 15, 2018 at 6:14 PM, Jason Ekstrand <ja...@jlekstrand.net> wrote: > I made a few fairly trivial comments but it all looks pretty good. > > Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net> Thanks for the quick review Jason. > > On Thu, Feb 15, 2018 at 5:4

Re: [Mesa-dev] [PATCH 10/10] anv/icl: Add render target flush after uploading binding table

On Thu, Feb 15, 2018 at 6:12 PM, Jason Ekstrand <ja...@jlekstrand.net> wrote: > > > On Thu, Feb 15, 2018 at 5:44 PM, Anuj Phogat <anuj.pho...@gmail.com> wrote: >> >> The PIPE_CONTROL command description says: >> >> "Whenever a Binding Table In

Re: [Mesa-dev] [PATCH 09/10] anv/icl: Enable float blend optimization

On Thu, Feb 15, 2018 at 6:13 PM, Jason Ekstrand <ja...@jlekstrand.net> wrote: > On Thu, Feb 15, 2018 at 5:44 PM, Anuj Phogat <anuj.pho...@gmail.com> wrote: >> >> Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com> >> --- >> src/intel/vulkan/genX_state.c

[Mesa-dev] [PATCH 04/10] anv/icl: Don't use SingleVertexDispatch

Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com> --- src/intel/vulkan/genX_pipeline.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/intel/vulkan/genX_pipeline.c b/src/intel/vulkan/genX_pipeline.c index 784559380d..85391c93ca 100644 --- a/src/intel/vulkan/genX_pipeline.c +++

[Mesa-dev] [PATCH 05/10] anv/icl: Don't use DISPATCH_MODE_SIMD4X2

Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com> --- src/intel/vulkan/genX_pipeline.c | 7 +++ 1 file changed, 7 insertions(+) diff --git a/src/intel/vulkan/genX_pipeline.c b/src/intel/vulkan/genX_pipeline.c index 85391c93ca..290d78e608 100644 --- a/src/intel/vulkan/genX_pipeline.c

[Mesa-dev] [PATCH 06/10] anv/icl: Generate gen11 entry point functions

Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com> --- src/intel/vulkan/anv_entrypoints_gen.py | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/src/intel/vulkan/anv_entrypoints_gen.py b/src/intel/vulkan/anv_entrypoints_gen.py index 1bab885180..c5a654f19b 100644 ---

[Mesa-dev] [PATCH 09/10] anv/icl: Enable float blend optimization

Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com> --- src/intel/vulkan/genX_state.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/intel/vulkan/genX_state.c b/src/intel/vulkan/genX_state.c index 54fb8634fd..f39508034f 100644 --- a/src/intel/vulkan/genX_state.c +++

[Mesa-dev] [PATCH 10/10] anv/icl: Add render target flush after uploading binding table

board Stall bit must be set in this packet." Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com> --- src/intel/vulkan/genX_cmd_buffer.c | 21 + 1 file changed, 21 insertions(+) diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c

[Mesa-dev] [PATCH 01/10] anv/icl: Add gen11 mocs defines

Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com> --- src/intel/vulkan/anv_private.h | 11 +++ 1 file changed, 11 insertions(+) diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h index d38dd9e422..009f5304f2 100644 --- a/src/intel/vulkan/anv_private.h +++

[Mesa-dev] [PATCH 07/10] anv/icl: Build anv libs for gen11

Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com> --- src/intel/Android.vulkan.mk | 21 + src/intel/Makefile.sources | 4 src/intel/Makefile.vulkan.am | 7 ++- src/intel/vulkan/meson.build | 2 +- 4 files changed, 32 insertions(+), 2 deletions(-) diff

[Mesa-dev] [PATCH 02/10] anv/icl: Add #define genX

Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com> --- src/intel/vulkan/anv_private.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h index 009f5304f2..9822afb81d 100644 --- a/src/intel/vulkan/anv_private.h +++ b/src

[Mesa-dev] [PATCH 03/10] anv/icl: Don't set ResetGatewayTimer

Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com> --- src/intel/vulkan/genX_pipeline.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/intel/vulkan/genX_pipeline.c b/src/intel/vulkan/genX_pipeline.c index 45ebe31de6..784559380d 100644 --- a/src/intel/vulkan/genX_pipeline.c +++

[Mesa-dev] [PATCH 08/10] anv/icl: Use gen11 functions

Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com> --- src/intel/vulkan/anv_blorp.c | 3 +++ src/intel/vulkan/anv_device.c | 3 +++ 2 files changed, 6 insertions(+) diff --git a/src/intel/vulkan/anv_blorp.c b/src/intel/vulkan/anv_blorp.c index d38b343671..d98bf8364d 100644 --- a/src

[Mesa-dev] [PATCH 00/10] intel/anv: Prepare to add Ice Lake (ICL) support

. https://github.com/aphogat/mesa.git Anuj Phogat (10): anv/icl: Add gen11 mocs defines anv/icl: Add #define genX anv/icl: Don't set ResetGatewayTimer anv/icl: Don't use SingleVertexDispatch anv/icl: Don't use DISPATCH_MODE_SIMD4X2 anv/icl: Generate gen11 entry point functions anv/icl

Re: [Mesa-dev] [PATCH V2 16/16] i965/icl: Add render target flush after uploading binding table

+Ken On Thu, Feb 15, 2018 at 11:11 AM, Anuj Phogat <anuj.pho...@gmail.com> wrote: > From PIPE_CONTROL command description in gfxspecs: > > "Whenever a Binding Table Index (BTI) used by a Render Taget Message > points to a different RENDER_SURFACE_STATE, SW must issue a

[Mesa-dev] [PATCH V2 16/16] i965/icl: Add render target flush after uploading binding table

I, PS Scoreboard Stall bit must be set in this packet." V2: Move the PIPE_CONTROL to update_renderbuffer_surfaces() in brw_wm_surface_state.c (Ken). Fixes a fulsim error and a GPU hang described in below JIRA. JIRA: MD5-322 Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com> ---

[Mesa-dev] [PATCH 14/16] intel/common/icl: Add has_sample_with_hiz flag in gen_device_info

org> Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com> Cc: Kenneth Graunke <kenn...@whitecape.org> --- src/intel/common/gen_device_info.c| 7 +++ src/intel/common/gen_device_info.h| 2 +- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 5 + 3 files cha

Re: [Mesa-dev] [PATCH 02/16] intel/genxml/icl: Generate packing headers

On Thu, Feb 15, 2018 at 9:49 AM, Emil Velikov <emil.l.veli...@gmail.com> wrote: > On 13 February 2018 at 19:15, Anuj Phogat <anuj.pho...@gmail.com> wrote: >> Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com> >> --- >> src/intel/Android.genxml.mk | 5

Re: [Mesa-dev] [PATCH 16/16] i965/icl: Add render target flush after uploading binding table

On Tue, Feb 13, 2018 at 4:17 PM, Kenneth Graunke <kenn...@whitecape.org> wrote: > On Tuesday, February 13, 2018 11:15:16 AM PST Anuj Phogat wrote: >> From PIPE_CONTROL command description in gfxspecs: >> >> "Whenever a Binding Table Index (BTI) used by a

Re: [Mesa-dev] [PATCH 14/16] i965/icl: Disable HiZ surface sampling

On Tue, Feb 13, 2018 at 4:25 PM, Kenneth Graunke <kenn...@whitecape.org> wrote: > On Tuesday, February 13, 2018 11:15:14 AM PST Anuj Phogat wrote: >> On gen11+ AUX_HIZ is not a supported value for surfaces being >> sampled by the 3D sampler. >> >> Signed-off-by: A

Re: [Mesa-dev] [PATCH] i965: Add ICL to test_eu_validate.cpp

Sent this patch to ML by mistake :(. Reviewers can ignore this one for now. Matt can send it out later with rest of his compiler changes. On Tue, Feb 13, 2018 at 2:41 PM, Anuj Phogat <anuj.pho...@gmail.com> wrote: > From: Matt Turner <matts...@gmail.com> > > ---

[Mesa-dev] [PATCH] i965: Add ICL to test_eu_validate.cpp

From: Matt Turner --- src/intel/compiler/test_eu_validate.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/src/intel/compiler/test_eu_validate.cpp b/src/intel/compiler/test_eu_validate.cpp index f6c2b35625..d987311ef8 100644 ---

[Mesa-dev] [PATCH 01/16] intel/genxml/icl: Add gen11.xml

Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com> --- This patch adds a big xml file. So I couldn't send the patch to the list. Clamping down the patch so that reviewers can actually see what i'm doing in [PATCH 01/16 ]. The whole patch can be found in my 'review' branch on github. src

[Mesa-dev] [PATCH 1.5/16] intel/genxml/icl: Add Cache Mode SubSlice Register to gen11.xml

Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com> --- This patch will be squashed with [PATCH 01/16] src/intel/genxml/gen11.xml | 12 1 file changed, 12 insertions(+) diff --git a/src/intel/genxml/gen11.xml b/src/intel/genxml/gen11.xml index 2490b0e25b..84020f7015 100644 ---

Re: [Mesa-dev] [PATCH 3/3] docs: Add Cannonlake support to 18.0 release notes.

14.3 > > ___ > mesa-dev mailing list > mesa-dev@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/mesa-dev Series-is: Reviewed-by: Anuj Phogat <anuj.pho...@gmail.com> ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH 00/16] Prepare to add Ice Lake (ICL) support

This series is also available at: https://github.com/aphogat/mesa.git Branch: review On Tue, Feb 13, 2018 at 11:15 AM, Anuj Phogat <anuj.pho...@gmail.com> wrote: > > This series prepares the driver to enable Ice Lake support > in i965 driver. It adds gen11.xml, wires up the build &

[Mesa-dev] [PATCH 14/16] i965/icl: Disable HiZ surface sampling

On gen11+ AUX_HIZ is not a supported value for surfaces being sampled by the 3D sampler. Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com> --- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/mesa/drivers/dr

[Mesa-dev] [PATCH 06/16] intel/icl: Do StateCacheInvalidation for indirect clear color

StateCacheInvalidation is required on all gen7+ platforms. We don't need to update this check for every new gen h/w unless this requirement is changed. So, dropping the check for latest gen h/w. Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com> --- src/intel/blorp/blorp_genX_exec.h | 2

[Mesa-dev] [PATCH 16/16] i965/icl: Add render target flush after uploading binding table

I, PS Scoreboard Stall bit must be set in this packet." Fixes a fulsim error and a GPU hang described in below JIRA. JIRA: MD5-322 Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com> --- src/mesa/drivers/dri/i965/brw_binding_tables.c | 14 ++ 1 file changed, 14 insertion

[Mesa-dev] [PATCH 13/16] i965/icl: Add assertions to check dispatch mode is SIMD8

SIMD4x2 dispatch mode has been removed in GEN11. We're not using it anyways in Mesa. Adding few asserts to make it explicit. Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com> --- src/intel/blorp/blorp_genX_exec.h | 4 src/mesa/drivers/dri/i965/genX_state_upload.c | 5 ++

[Mesa-dev] [PATCH 15/16] i965/icl: Enable float blend optimization and Wa3DStateMode

Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com> --- src/mesa/drivers/dri/i965/brw_state_upload.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c index 2c8c0f4b27..86c12e4d35

[Mesa-dev] [PATCH 11/16] i965/icl: Update the assert in brw_memory_barrier()

Nothing is changed here from gen10 to gen11. So, just update the assert. Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com> --- src/mesa/drivers/dri/i965/brw_program.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/brw_program.c b/src/mesa/d

[Mesa-dev] [PATCH 02/16] intel/genxml/icl: Generate packing headers

Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com> --- src/intel/Android.genxml.mk | 5 + src/intel/Makefile.sources| 3 ++- src/intel/genxml/genX_pack.h | 2 ++ src/intel/genxml/gen_macros.h | 3 +++ 4 files changed, 12 insertions(+), 1 deletion(-) diff --git a/src

[Mesa-dev] [PATCH 05/16] intel/isl/icl: Build and use gen11 surface state emit functions

Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com> --- src/intel/Android.isl.mk | 20 src/intel/Makefile.isl.am | 4 src/intel/Makefile.sources | 4 src/intel/isl/isl.c| 3 +++ src/intel/isl/isl_priv.h | 3 +++ src/intel/isl/meson.build | 2

  1   2   3   4   5   6   7   8   9   10   >