On Tue, Nov 27, 2018 at 7:45 PM Jordan Justen wrote:
>
> On 2018-11-27 19:20:09, Matt Turner wrote:
> > On Tue, Nov 27, 2018 at 5:13 PM Jordan Justen
> > wrote:
> > >
> > > This documents a mechanism for using GitLab Merge Requests as an
> > >
On Tue, Nov 27, 2018 at 7:26 PM Jordan Justen wrote:
>
> On 2018-11-27 18:04:17, Matt Turner wrote:
> > On Tue, Nov 27, 2018 at 6:00 PM Jordan Justen
> > wrote:
> > >
> > > On 2018-11-27 17:17:15, Matt Turner wrote:
> > > > On Tue, Nov 2
Wouldn't it be better to just include the stdlib.h/stddef.h header
that defines NULL?
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On Tue, Nov 27, 2018 at 5:13 PM Jordan Justen wrote:
>
> This documents a mechanism for using GitLab Merge Requests as an
> optional, secondary way to get code reviews for patchsets.
>
> We still require all patches to be emailed.
>
> Aside from the potential usage for code review comments, it
On Tue, Nov 27, 2018 at 6:00 PM Jordan Justen wrote:
>
> On 2018-11-27 17:17:15, Matt Turner wrote:
> > On Tue, Nov 27, 2018 at 5:13 PM Jordan Justen
> > wrote:
> > >
> > > This adds the "Developer's Certificate of Origin 1.1" from the Linux
>
On Tue, Nov 27, 2018 at 5:13 PM Jordan Justen wrote:
>
> This adds the "Developer's Certificate of Origin 1.1" from the Linux
> kernel. It indicates that by using Signed-off-by you are certifying
> that your patch meets the DCO 1.1 guidelines.
Do we gain anything if it's optional?
On Tue, Nov 27, 2018 at 1:13 AM Timo Aaltonen wrote:
>
> On 17.11.2018 6.04, Dylan Baker wrote:
> > Quoting Dylan Baker (2018-09-17 09:44:07)
> >> I feel like for !windows meson is in good enough shape at this point that
> >> we
> >> can start having the discussion about deleting the autotools
---
src/compiler/glsl/glsl_to_nir.cpp | 4
1 file changed, 4 deletions(-)
diff --git a/src/compiler/glsl/glsl_to_nir.cpp
b/src/compiler/glsl/glsl_to_nir.cpp
index dc6ffa3599d..61b544fd6d3 100644
--- a/src/compiler/glsl/glsl_to_nir.cpp
+++ b/src/compiler/glsl/glsl_to_nir.cpp
@@ -96,8 +96,6
---
src/intel/compiler/brw_fs.cpp | 5 +
1 file changed, 5 insertions(+)
diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp
index e030f7215ce..c3a09d31938 100644
--- a/src/intel/compiler/brw_fs.cpp
+++ b/src/intel/compiler/brw_fs.cpp
@@ -6036,6 +6036,11 @@
We normally call with stderr which is unbuffered, so this won't affect
that, but it does let me call nir_print_shader(nir, fopen("log", "w+"))
from gdb and actually get the whole shader in my file.
---
src/compiler/nir/nir_print.c | 1 +
1 file changed, 1 insertion(+)
diff --git
On Wed, Nov 21, 2018 at 10:48 AM Matt Turner wrote:
>
> Thanks Arfrever and Dylan.
>
> Acked-by: Matt Turner
Hmm, actually this doesn't seem to work for me. With it applied I get:
src/mesa/drivers/dri/meson.build:59:8: ERROR: Python object does not
have method path.
whic
On Thu, Nov 15, 2018 at 2:16 PM Sagar Ghuge wrote:
>
> While disassembling the predicate always print flag subregister number
> to keep grammar same across the generation for assembler tool.
That's reasonable.
> Signed-off-by: Sagar Ghuge
> ---
> src/intel/compiler/brw_disasm.c | 3 +--
> 1
Thanks Arfrever and Dylan.
Acked-by: Matt Turner
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On Tue, Nov 13, 2018 at 6:41 PM Roland Scheidegger wrote:
>
> Am 14.11.18 um 03:21 schrieb Matt Turner:
> > On Tue, Nov 13, 2018 at 6:03 PM Roland Scheidegger
> > wrote:
> >>
> >> Am 13.11.18 um 23:49 schrieb Dylan Baker:
> >>> Quoting Roland Sche
On Fri, Nov 16, 2018 at 10:34 AM Dylan Baker wrote:
>
> Quoting Roland Scheidegger (2018-11-13 18:41:00)
> > Am 14.11.18 um 03:21 schrieb Matt Turner:
> > > On Tue, Nov 13, 2018 at 6:03 PM Roland Scheidegger
> > > wrote:
> > >>
> > >> Am
Reviewed-by: Matt Turner
and pushed.
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ses where direct
> conversion to 32bit int wouldn't).
> So ideally you'd pick a variant where the compiler is smart enough to
> recognize it can be done with a single instruction. I would guess
> nearbyintf + int cast should do just about everywhere, at least as long
> as x64 or x86 + sse2
On Mon, Nov 12, 2018 at 8:35 AM Juan A. Suarez Romero
wrote:
>
> Hello list,
>
> The candidate for the Mesa 18.2.5 is now available. Currently we have:
> - 25 queued
> - 0 nominated (outstanding)
> - and 2 rejected patch
If it's not a big deal if would be convenient for me (for Gentoo) to
On Tue, Nov 13, 2018 at 9:43 AM Emil Velikov wrote:
>
> Hi Matt,
>
> On Mon, 12 Nov 2018 at 21:26, Matt Turner wrote:
> >
> > Prior to this patch sizeof(linear_header) was 20 bytes in a
> > non-debug build on 32-bit platforms. We do some pointer arithmetic to
&g
On Mon, Nov 12, 2018 at 3:07 PM Eric Anholt wrote:
>
> Matt Turner writes:
>
> > Prior to this patch sizeof(linear_header) was 20 bytes in a
> > non-debug build on 32-bit platforms. We do some pointer arithmetic to
> > calculate the next available l
The debug code is all asserts, so protect it with the same thing that
controls assert.
---
src/util/ralloc.c | 18 --
1 file changed, 4 insertions(+), 14 deletions(-)
diff --git a/src/util/ralloc.c b/src/util/ralloc.c
index 5d77f75ee85..745b4cf1226 100644
--- a/src/util/ralloc.c
Prior to this patch sizeof(linear_header) was 20 bytes in a
non-debug build on 32-bit platforms. We do some pointer arithmetic to
calculate the next available location with
ptr = (linear_size_chunk *)((char *)[1] + latest->offset);
in linear_alloc_child(). The [1] adds 20 bytes, so an
Thank you. I noticed this as well.
Reviewed-by: Matt Turner
I'll commit it tomorrow if there are no additional comments.
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The underscore change alone is enough to fix the build on 32-bit ppc
and sparc. It's unclear to me if the dep_atomic even changes anything.
Without it I still see -latomic in the command to build
src/util/u_atomic_test. I would just drop that part.
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Thanks
Reviewed-by: Matt Turner
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On Wed, Nov 7, 2018 at 12:53 PM Jan Vesely wrote:
>
> On Wed, 2018-11-07 at 18:51 +, Emil Velikov wrote:
> > On Wed, 7 Nov 2018 at 18:39, Jan Vesely wrote:
> > > On Tue, 2018-11-06 at 12:09 +, Emil Velikov wrote:
> > > > On Thu, 1 Nov 2018 at 16:13, Michel Dänzer wrote:
> > > > > On
m0);
Maybe here too?
Otherwise, looks great to me.
Reviewed-by: Matt Turner
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On Thu, Nov 1, 2018 at 3:37 PM Ian Romanick wrote:
>
> From: Ian Romanick
>
> Signed-off-by: Ian Romanick
> Cc: Matt Turner
> ---
> .../tests/warnings/031-__-in-function-name.vert| 22
> ++
> .../warnings/031-__-in-function-name.vert.e
Reviewed-by: Matt Turner
Probably fine to add a Tested-by from the reporter as well.
Thanks Dylan!
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On Fri, Oct 26, 2018 at 3:06 AM Sergii Romantsov
wrote:
>
> While building of 32bit Mesa gcc doesn't specifies __SSE__ by default.
> So it has to be done manually by flag '-msee'.
> Added support of such specification to build-system.
>
> CC: Dylan Baker
> Bugzilla:
On Mon, Oct 22, 2018 at 2:14 PM Sagar Ghuge wrote:
>
>
>
> On 10/22/18 10:34 AM, Matt Turner wrote:
> > On Fri, Oct 5, 2018 at 11:15 AM Sagar Ghuge wrote:
> >>
> >> avoid misinterpretation of encoded immediate values in instruction and
> >> disass
=
> +#if defined(USE_SSE41)
> + cpu_has_sse4_1 ? tiled_to_linear_sse41 :
> +#endif
> + tiled_to_linear;
> +
> + const mem_copy_fn_type copy_type =
> +#if defined(USE_SSE41)
> + cpu_has_sse4_1 ? INTEL_COPY_STREAMING_LOAD :
> +#endif
> +
Thanks Dylan!
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On Fri, Oct 5, 2018 at 11:15 AM Sagar Ghuge wrote:
>
> avoid misinterpretation of encoded immediate values in instruction and
> disassembled output.
>
> Signed-off-by: Sagar Ghuge
> ---
> While encoding the immediate floating point values in instruction we use
> values upto precision 8, but
On Tue, Oct 16, 2018 at 4:57 PM Sagar Ghuge wrote:
>
Let's describe a little of why we're doing this and how we found it.
If I recall correctly, we set a NOP (XYZW) swizzle on 3-src
instructions, except we set an swizzle on LRP. Is that correct?
> Signed-off-by: Sagar Ghuge
> ---
>
d(c) instruction use
> >> register type of unsigned doubleword for src1 when message descriptor is
> >> immediate value. Bspec does not specifiy anything for src1 immediate
> >
> > s/specifiy/specify
> >
> oops, I will fix it and resend the patch. I don't have push
Subject: s/Losten/Loosen/
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Sounds like a good idea to me.
Acked-by: Matt Turner
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On Thu, Oct 18, 2018 at 6:06 PM Kenneth Graunke wrote:
>
> This warning detects non-void functions with a missing return statement,
> return statements with a value in void functions, and functions with an
> bogus return type that ends up defaulting to int. It's already enabled
> by default with
On Thu, Oct 18, 2018 at 1:28 PM Roland Scheidegger wrote:
>
> Am 18.10.18 um 19:25 schrieb Matt Turner:
> > On Thu, Oct 18, 2018 at 8:46 AM Eric Engestrom
> > wrote:
> >>
> >> Fixes: a4c4efad89eceb26cf82 "radv: Rework guard band calculation"
> &
On Thu, Oct 18, 2018 at 8:46 AM Eric Engestrom wrote:
>
> Fixes: a4c4efad89eceb26cf82 "radv: Rework guard band calculation"
> Cc: Bas Nieuwenhuizen
> Signed-off-by: Eric Engestrom
> ---
> src/amd/vulkan/si_cmd_buffer.c | 8
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff
On Sun, Oct 14, 2018 at 3:58 PM Jason Ekstrand wrote:
>
> On October 14, 2018 17:12:34 Matt Turner wrote:
>
> > From: Jason Ekstrand
> >
> > [mattst88]: Found in an old branch of Jason's.
> >
> > Jason implemented: inot, iand, ior, iadd, isub, ineg, ia
Reviewed-by: Matt Turner
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FINISHME: Figure out what to do about lowering mov operations. Currently
if we attempt to lower them in NIR we get stuck in an infinite loop. The
last patch of this series lowers them in the backend instead, but I'm
certainly open to ideas.
---
src/compiler/nir/nir.h | 9 +++-
Unfortunately some int64 lowerings generate more int64 operations, so we
need to call this function a few times. Also call
nir_lower_alu_to_scalar() beforehand to make more int64 operations
available for lowering.
---
src/intel/compiler/brw_nir.c | 10 +++---
1 file changed, 7 insertions(+),
---
src/intel/compiler/brw_nir.c | 14 +++---
1 file changed, 11 insertions(+), 3 deletions(-)
diff --git a/src/intel/compiler/brw_nir.c b/src/intel/compiler/brw_nir.c
index 066724c58a6..7eb9c385694 100644
--- a/src/intel/compiler/brw_nir.c
+++ b/src/intel/compiler/brw_nir.c
@@ -677,9
---
src/compiler/nir/nir.h | 1 +
src/compiler/nir/nir_lower_int64.c | 142 +
2 files changed, 143 insertions(+)
diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h
index 12cbd030e21..2c477126acc 100644
--- a/src/compiler/nir/nir.h
+++
FINISHME: Lower them in NIR instead?
---
src/intel/compiler/brw_fs.cpp | 21 -
1 file changed, 20 insertions(+), 1 deletion(-)
diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp
index 69726ed70e8..9e50df59356 100644
--- a/src/intel/compiler/brw_fs.cpp
From: Jason Ekstrand
[mattst88]: Found in an old branch of Jason's.
Jason implemented: inot, iand, ior, iadd, isub, ineg, iabs, compare,
imin, imax, umin, umax
Matt implemented: ixor, imov, bcsel
---
src/compiler/nir/nir_lower_int64.c | 186
---
src/intel/compiler/brw_fs.cpp | 6 ++
src/intel/compiler/brw_shader.h | 2 ++
2 files changed, 8 insertions(+)
diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp
index 23a25fedca5..69726ed70e8 100644
--- a/src/intel/compiler/brw_fs.cpp
+++
Nice.
Reviewed-by: Matt Turner
A piglit test would be a great addition as well.
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On Tue, Sep 25, 2018 at 8:50 AM Samuel Pitoiset
wrote:
> On 9/25/18 6:46 AM, Timothy Arceri wrote:
> > On 25/9/18 10:35 am, Marek Olšák wrote:
> >> Do you know what's broken in LLVM? Or is it a problem with the ISA?
> >
> > I haven't actually dug any further. Adding Samuel to see if he remembers
On Fri, Sep 21, 2018 at 11:38 AM Emil Velikov wrote:
>
> On 20 September 2018 at 19:19, Dylan Baker wrote:
> > Quoting Eric Engestrom (2018-09-20 07:56:45)
> >> On Thursday, 2018-09-20 15:28:09 +0100, Emil Velikov wrote:
> >> > Hi Chuck,
> >> >
> >> > On 18 September 2018 at 16:00, Chuck Atkins
On Mon, Sep 17, 2018 at 5:50 PM Marek Olšák wrote:
>
> One missing feature is --with-sha1=. libcrypto has an unstable ABI and
> Steam uses it. For Mesa to work with Steam, libnettle has/had to be
> used instead.
We imported OpenBSD's sha1 implementation a year and a half ago to
avoid all of
On Mon, Sep 17, 2018 at 9:46 AM Dylan Baker wrote:
>
> I feel like for !windows meson is in good enough shape at this point that we
> can start having the discussion about deleting the autotools build. So, is
> there
> anything left that autotools can do that meson cannot (that we actually want
On Sun, Sep 9, 2018 at 5:00 PM Timothy Arceri wrote:
> On 10/09/18 09:52, Matt Turner wrote:
> > On Sun, Sep 9, 2018 at 4:41 PM Timothy Arceri wrote:
> >>
> >> On 10/09/18 09:22, Ian Romanick wrote:
> >>> On 09/08/2018 06:37 AM, Jason Ekstrand wrote:
>
On Sun, Sep 9, 2018 at 4:41 PM Timothy Arceri wrote:
>
> On 10/09/18 09:22, Ian Romanick wrote:
> > On 09/08/2018 06:37 AM, Jason Ekstrand wrote:
> >> Is there going to be an accompanying series on the piglit list? I don't
> >> see anything there immediately.
> >
> > Which is one of the major
Looks great!
Reviewed-by: Matt Turner
and pushed. Thanks a bunch!
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On Mon, Aug 20, 2018 at 3:13 PM Sagar Ghuge wrote:
>
> Adds a new i965 instruction disassemble tool
>
> v2: 1) fix a few nits (Matt Turner)
> 2) Remove i965_disasm header (Matt Turner)
>
> Signed-off-by: Sagar Ghuge
> ---
> src/intel/Makefile.tools.am |
Looks great!
Reviewed-by: Matt Turner
I'll push it shortly.
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On Thu, Aug 16, 2018 at 1:51 PM Sagar Ghuge wrote:
>
> Adds a new i965 instruction disassemble tool
This looks very good. A few comments about the structure inline.
> Signed-off-by: Sagar Ghuge
> ---
> src/intel/Makefile.tools.am | 15 +++
> src/intel/tools/i965_disasm.c | 202
Cool. This looks pretty good to me. A few comments inline.
On Wed, Aug 15, 2018 at 2:00 PM Sagar Ghuge wrote:
>
> INTEL_DEBUG=hex prints 32 bit hex value
> and due to endianness of CPU byte order is
> reversed. In order to disassemble binary
> files, print each byte instead of 32 bit hex
>
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On Thu, Aug 16, 2018 at 5:50 PM Jason Ekstrand wrote:
> If that's true then the extension makes no sense other than maybe "we're a
> UMA, we can make things cheap." I think it's more likely that the intention
> is to use a fenced map through the GTT to do the detiling. That said, given
> how
3 is enough to cause it.
Reviewed-by: Matt Turner
I will add the Bugzilla tag and an appropriate commit message, tag it
for stable, and commit it.
Thanks for the patch!
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On Thu, May 24, 2018 at 4:16 AM, vadym.shovkoplias
wrote:
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104388
> Signed-off-by: Andriy Khulap
> ---
> src/mesa/drivers/dri/i965/genX_state_upload.c | 11 +++
> 1 file changed, 11 insertions(+)
>
> diff --git
Reviewed-by: Matt Turner
and pushed.
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Reviewed-by: Matt Turner
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On Sun, Jul 15, 2018 at 7:26 PM, Timothy Arceri wrote:
> Noticed in a unigine shader.
> ---
> src/compiler/nir/nir_opt_algebraic.py | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/src/compiler/nir/nir_opt_algebraic.py
> b/src/compiler/nir/nir_opt_algebraic.py
> index
On Fri, Jul 13, 2018 at 11:10 AM, Matt Turner wrote:
> On Sun, Jul 8, 2018 at 5:27 PM, Jose Maria Casanova Crespo
> wrote:
>> Implement at brw_eu_validate the restriction from Intel Broadwell PRM,
>> vol 07, section "Instruction Set Reference", subsection "EUI
must not be used for return address when there is a src and
> dest overlap in send instruction."
>
> v2: Style fixes (Matt Turner)
>
> Reviewed-by: Matt Turner
> ---
> src/intel/compiler/brw_eu_validate.c | 11 +++
> 1 file changed, 11 insertions(+)
>
>
On Thu, Jul 5, 2018 at 7:42 AM Lionel Landwerlin
wrote:
>
> Older system might not have support for memfd_create at the kernel
> level. There we won't be able to use aubinator.
>
> We also initially tried to workaround some libc having the
> memfd_create syscall number defined, but not the
On Wed, Jul 4, 2018 at 9:59 AM Jason Ekstrand wrote:
>
> Many fragment shaders do a discard using relatively little information
> but still put the discard fairly far down in the shader for no good
> reason. If the discard is moved higher up, we can possibly avoid doing
> some or almost all of
On Thu, May 31, 2018 at 10:39 AM Matt Turner wrote:
>
> On Fri, May 25, 2018 at 3:28 PM, Matt Turner wrote:
> >> 1-6, 8-20 are
> >>
> >> Reviewed-by: Matt Turner
> >
> > 7, 22-31 are too.
>
> 34-49 are too.
21 landed separately. 32, 33, 51
On Thu, May 31, 2018 at 10:54 AM Francisco Jerez wrote:
>
> Matt Turner writes:
>
> > On Fri, May 25, 2018 at 8:08 PM, Jason Ekstrand
> > wrote:
> >> On May 25, 2018 15:28:22 Matt Turner wrote:
> >>
> >>> On Thu, May 24, 2018 at 2:56
[DevSNB]: must be even register aligned.
> + *
> + * This restriction is lifted on Ivy Bridge.
> + *
> + * This means that we need to split PLN into LINE+MAC on-the-fly.
> + * Unfortunately, the inputs are laid out for PLN and not LIN+MAC so
s/LIN/LINE/
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On Wed, May 23, 2018 at 3:12 PM Dongwon Kim wrote:
>
> Thanks, Matt!!
> I am glad to see it is finally merged. By the way, not sure if you
> saw this patch.
>
> [PATCH shaderdb] run: handling binding of attribute variable name (v2)
>
unnecessary argument from callers.
>
> Cc: Timothy Arceri
> Cc: Matt Turner
> Cc: Ian Romanick
> Signed-off-by: Eric Engestrom
> ---
> src/gallium/auxiliary/util/u_format.c | 12
> src/gallium/auxiliary/util/u_format.h | 7 +--
>
On Sun, Jun 17, 2018 at 4:09 PM Jason Ekstrand wrote:
>
> On Sun, Jun 17, 2018 at 11:40 AM, Matt Turner wrote:
>>
>> On Sun, Jun 17, 2018 at 10:03 AM Jason Ekstrand wrote:
>> >
>> > On June 17, 2018 08:25:07 Rob Clark wrote:
>> >
>>
On Sun, Jun 17, 2018 at 10:03 AM Jason Ekstrand wrote:
>
> On June 17, 2018 08:25:07 Rob Clark wrote:
>
> > On Sun, Jun 17, 2018 at 2:55 AM, Jordan Justen
> > wrote:
> >> On 2018-06-15 15:16:50, Laura Ekstrand wrote:
> >>>
> >>> We are now running on our own Docker image:
> >>>
Yay! This option has had no effect on i965 for years, but I'm very
glad to see it gone all together.
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Is LLVM-5 now your oldest supported version? I know Igalia build tests
with versions going all the way back to 3.3 before stable releases, so
they might be able to cut down the required testing.
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Reviewed-by: Matt Turner
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:
> | declaration{ $$ = $1; }
> | pragma_statement { $$ = NULL; }
> | layout_defaults{ $$ = $1; }
> + | ';' { $$ = NULL; }
Indentation.
Also, piglit test?
With those,
Reviewed-by: Matt Turner
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On Wed, Jun 13, 2018 at 8:37 AM, Dylan Baker wrote:
> Quoting Matt Turner (2018-06-12 17:50:20)
>> Commit 54ba73ef102f (configure.ac/meson.build: Fix -latomic test) fixed
>> some checks for -latomic, and then commit 54bbe600ec26 (configure.ac:
>> rework -latomic check) furth
From: Andrew Galante
Some platforms have 64-bit __atomic_load_n but not 64-bit
__atomic_add_fetch, so test for both of them.
Bug: https://bugs.gentoo.org/655616
Reviewed-by: Matt Turner
---
configure.ac | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/configure.ac b
From: Andrew Galante
Some platforms have 64-bit __atomic_load_n but not 64-bit
__atomic_add_fetch, so test for both of them.
Bug: https://bugs.gentoo.org/655616
Reviewed-by: Matt Turner
---
meson.build | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/meson.build b
Commit 54ba73ef102f (configure.ac/meson.build: Fix -latomic test) fixed
some checks for -latomic, and then commit 54bbe600ec26 (configure.ac:
rework -latomic check) further extended the fixes in configure.ac but
not in Meson. This commit extends those fixes to the Meson tests.
Fixes: 54bbe600ec26
Series looks good to me. Compile tested on ppc64 and ppc64le and
confirmed that the POWER8 intrinsics are enabled only on ppc64le.
Reviewed-by: Matt Turner
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On Thu, Jun 7, 2018 at 11:53 AM, Dylan Baker wrote:
> ---
> meson.build | 30 ++
> meson_options.txt | 7 +++
> 2 files changed, 33 insertions(+), 4 deletions(-)
>
> diff --git a/meson.build b/meson.build
> index 0171328bcd7..f6fe141056a 100644
> ---
On Thu, Jun 7, 2018 at 2:01 AM, Erik Faye-Lund wrote:
> Just as a fun toy, I decided to give an animated SVG "variation" of
> this a go myself:
>
> https://codepen.io/kusma/pen/vrXppL
>
> The actual SVG can be found here:
>
> https://gitlab.freedesktop.org/snippets/492
>
> The gears were
bled.
>
> Fixes: 2d62fc06465281d3d45b8a7c7fd2b17ef718448c
>("meson: disable x86 asm in fewer cases.")
> CC: Matt Turner
> Signed-off-by: Dylan Baker
> ---
> meson.build | 5 -
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/meson.buil
On Thu, Jun 7, 2018 at 11:29 AM, Dylan Baker wrote:
> Quoting Matt Turner (2018-06-07 11:20:37)
>> Port of 6dfc5e28f7d0 (configure.ac: Add support to enable read-only text
>> segment on x86.) to Meson.
>> ---
>> meson.build | 5 +
>> meson_options.txt |
Port of 6dfc5e28f7d0 (configure.ac: Add support to enable read-only text
segment on x86.) to Meson.
---
meson.build | 5 +
meson_options.txt | 6 ++
2 files changed, 11 insertions(+)
diff --git a/meson.build b/meson.build
index 32ab30faa4b..161aae83e31 100644
--- a/meson.build
+++
On Wed, Jun 6, 2018 at 2:33 PM, Ian Romanick wrote:
> From: Ian Romanick
>
> Shader-db results:
>
> Skylake and Broadwell had similar results. (Skylake shown)
> total instructions in shared programs: 14371513 -> 14346174 (-0.18%)
> instructions in affected programs: 890389 -> 865050 (-2.85%)
>
On Tue, May 29, 2018 at 7:41 AM, Eric Engestrom
wrote:
> Cc: Emil Velikov
> Cc: Daniel Stone
> Signed-off-by: Eric Engestrom
> ---
I just pushed this series. Thanks!
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On Tue, Jun 5, 2018 at 8:24 AM, Emil Velikov wrote:
> On 5 June 2018 at 16:07, Eric Engestrom wrote:
>> On Tuesday, 2018-06-05 15:14:30 +0100, Emil Velikov wrote:
>>> From: Emil Velikov
>>>
>>> Recently the wayland-egl library and pkg-config file were moved to the
>>> Wayland repository. With
On Tue, Jun 5, 2018 at 7:14 AM, Emil Velikov wrote:
> From: Emil Velikov
>
> Recently the wayland-egl library and pkg-config file were moved to the
> Wayland repository. With that a strange conflict came to be - which one
> should be used and when.
>
> The long term goal is to remove the Mesa
On Mon, Jun 4, 2018 at 9:47 AM, Eric Engestrom wrote:
> On Monday, 2018-06-04 09:15:06 -0700, Matt Turner wrote:
>> On Thu, May 31, 2018 at 10:22 AM, Emil Velikov
>> wrote:
>> > On 29 May 2018 at 15:41, Eric Engestrom wrote:
>> >> Cc: Emil Velikov
>
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