Re: [Mesa-dev] [PATCH mesa] build systems: uniformize git_sha1.h generation

On Tue, Jun 27, 2017 at 5:47 AM, Eric Engestrom wrote: > Signed-off-by: Eric Engestrom > --- > Note: Autotools and SCons are tested, but Android isn't. > --- > git_sha1_gen.sh | 13 + > src/Makefile.am

Re: [Mesa-dev] Updating Khronos-supplied headers (and gl.xml)

just the way it is. > > I've had the patch in my local tree without issues for a while. Please > review! in glxext.h: -#ifdef BUILDING_MESA -/* Avoid uint <-> void* warnings */ -typedef unsigned long GLhandleARB; -#else typedef void *GLhandleARB; -#endif Other than that, I didn't

Re: [Mesa-dev] [PATCH] mesa/marshal: add custom marshalling for glNamedBuffer(Sub)Data

On Sat, Jun 24, 2017 at 9:59 AM, Grigori Goronzy wrote: > These entry points are used by Alien Isolation and caused > synchronization with glthread. The async marshalling implementation > is similar to glBuffer(Sub)Data. > > Results in an approximately 6x drop in glthread

Re: [Mesa-dev] [PATCH] i965/miptree: Move isl_surf_get_(hiz|mcs)_surf out of the assert

On Wed, Jun 21, 2017 at 3:50 PM, Mike Lothian wrote: > Do intel run mesa through any of their test boxes like they do with kernel > patches? Don't top quote. Yes, we have a CI system that we use extensively and has massively reduced the number of regressions we have.

Re: [Mesa-dev] [RFC 01/22] RFC: egl/x11: Support DRI3 v1.1

On Tue, Jun 20, 2017 at 8:18 AM, Daniel Stone wrote: > Hey Emil, > A few bits from me, since this is actually lfrb's code ... > > On 20 June 2017 at 15:19, Emil Velikov wrote: >> Top-level comments >> >> Build POV: >> - Having the

Re: [Mesa-dev] [PATCH v1 2/7] etnaviv: Add return statement to etna_amode so compiler is happy

On Mon, Jun 19, 2017 at 12:52 PM, Chad Versace wrote: > On Fri 16 Jun 2017, Christian Gmeiner wrote: >> 2017-06-16 14:54 GMT+02:00 Emil Velikov : >> > On 15 June 2017 at 21:47, Robert Foss wrote: >> >> From: Tomeu

Re: [Mesa-dev] [PATCH v1 5/7] android: enable texture-float

On Fri, Jun 16, 2017 at 6:18 AM, Emil Velikov wrote: > On 15 June 2017 at 21:47, Robert Foss wrote: >> From: Rob Herring >> >> This is required by freedreno at least for GLES3 support. >> >> See docs/patents.txt for

Re: [Mesa-dev] [PATCH 3/3] i965/gen4: Add support for single layer in alignment workaround

On Fri, Jun 9, 2017 at 7:04 AM, Topi Pohjolainen wrote: > On gen < 6 one doesn't have level or layer specifiers available > for render and depth targets. In order to support rendering to > specific level/layer, driver needs to manually offset the surface > to the

Re: [Mesa-dev] [PATCH] mesa/main/debug: Check if we successfully reopened the ppm file.

Reviewed-by: Matt Turner <matts...@gmail.com> Could also make the code use freopen() instead of back-to-back fclose+fopen, but it doesn't matter. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/li

Re: [Mesa-dev] [PATCH] i965: Replace 0 with ISL_FORMAT_UNSUPPORTED in format table (v2)

be 0. > */ > - static const uint32_t table[MESA_FORMAT_COUNT] = > - { > - [MESA_FORMAT_A8B8G8R8_UNORM] = 0, > + static const enum isl_format table[MESA_FORMAT_COUNT] = { > + [0 ... MESA_FORMAT_COUNT-1] = ISL_FORMAT_UNSUPPORTED, > + Awesome. Reviewed-by: Mat

Re: [Mesa-dev] [PATCH 4/6] i965: Replace 0 with ISL_FORMAT_UNSUPPORTED in format table

On Wed, May 31, 2017 at 10:42 PM, Jason Ekstrand wrote: > On May 31, 2017 9:32:23 PM Ian Romanick wrote: > >> Having the unsupported format value not be zero isn't very safe. The >> C99 rules say that any field missing an initializer is implicitly >>

Re: [Mesa-dev] [PATCH 00/16] i965: Write-combine mappings and other performance improvements for non-LLC

On Wed, May 24, 2017 at 1:04 PM, Matt Turner <matts...@gmail.com> wrote: > The series aims to improve performance on non-LLC platforms like Braswell and > Broxton. > > Unsynchronized mappings were not actually unsynchronized on non-LLC platforms, > hurting Unigine Valley pe

[Mesa-dev] [PATCH 11.3/16] i965: Make unsynchronized maps unsynchronized on non-LLC

--- src/mesa/drivers/dri/i965/brw_bufmgr.c | 14 +- 1 file changed, 1 insertion(+), 13 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_bufmgr.c b/src/mesa/drivers/dri/i965/brw_bufmgr.c index 4ab72cd..15610db 100644 --- a/src/mesa/drivers/dri/i965/brw_bufmgr.c +++

[Mesa-dev] [PATCH 11.2/16] i965: Implement brw_bo_map_unsynchronized() with MAP_ASYNC

This way we can let brw_bo_map() choose the best mapping type. Part of the patch inlines map_gtt() into brw_bo_map_gtt() (and removes map_gtt()). brw_bo_map_gtt() just wrapped map_gtt() with locking and a call to set_domain(). map_gtt() is called by brw_bo_map_unsynchronized() to avoid the call

[Mesa-dev] [PATCH 11.4/16] i965: Remove brw_bo_map_unsynchronized()

Call brw_bo_map() directly. --- src/mesa/drivers/dri/i965/brw_bufmgr.c | 20 -- src/mesa/drivers/dri/i965/brw_bufmgr.h | 1 - src/mesa/drivers/dri/i965/brw_program_cache.c| 4 ++-- src/mesa/drivers/dri/i965/intel_buffer_objects.c | 27

[Mesa-dev] [PATCH 11.1/16] i965: Elide call to set_domain() if MAP_ASYNC

No functional change (no callers currently pass MAP_ASYNC) --- These four patches split 11/16 like Ken suggested src/mesa/drivers/dri/i965/brw_bufmgr.c | 12 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_bufmgr.c

Re: [Mesa-dev] [PATCH 08/16] i965: Pass flags to brw_bo_map_*

On Fri, May 26, 2017 at 1:50 AM, Kenneth Graunke <kenn...@whitecape.org> wrote: > On Wednesday, May 24, 2017 1:04:50 PM PDT Matt Turner wrote: >> brw_bo_map_cpu() took a write_enable arg, but it wasn't always clear >> whether we were also planning to read from the buff

Re: [Mesa-dev] [PATCH 10/16] i965: Add and use brw_bo_map()

On Fri, May 26, 2017 at 1:55 AM, Kenneth Graunke <kenn...@whitecape.org> wrote: > On Wednesday, May 24, 2017 1:04:52 PM PDT Matt Turner wrote: >> We can encapsulate the logic for choosing the mapping type. This will >> also help when we add WC mappings. > > I

Re: [Mesa-dev] [PATCH v2 0/6] Various fixes to integer GetUniform*()

On Mon, May 22, 2017 at 2:40 AM, Iago Toral <ito...@igalia.com> wrote: > On Sat, 2017-05-20 at 14:09 -0700, Matt Turner wrote: >> On Thu, May 18, 2017 at 2:43 AM, Iago Toral Quiroga <ito...@igalia.co >> m> wrote: >> > The main change is that we now use round*()

Re: [Mesa-dev] [PATCH] i965/copy_image: Use the blitter on gen5

Reviewed-by: Matt Turner <matts...@gmail.com> ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH 11/16] i965: Replace brw_bo_map_unsynchronized with MAP_ASYNC

This way we can let brw_bo_map() choose the best mapping type. Part of the patch inlines map_gtt() into brw_bo_map_gtt() (and removes map_gtt()). brw_bo_map_gtt() just wrapped map_gtt() with locking and a call to set_domain(). map_gtt() is called by brw_bo_map_unsynchronized() to avoid the call

[Mesa-dev] [PATCH 15/16] i965: Enable tiled memcpy get tex image path on non-LLC

--- src/mesa/drivers/dri/i965/intel_tex_image.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/i965/intel_tex_image.c b/src/mesa/drivers/dri/i965/intel_tex_image.c index 59d5fa4..75b5d6e 100644 --- a/src/mesa/drivers/dri/i965/intel_tex_image.c +++

[Mesa-dev] [PATCH 14/16] i965: Enable tiled memcpy pixel read path on non-LLC

--- src/mesa/drivers/dri/i965/intel_pixel_read.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/i965/intel_pixel_read.c b/src/mesa/drivers/dri/i965/intel_pixel_read.c index eb3f66f..5085683 100644 --- a/src/mesa/drivers/dri/i965/intel_pixel_read.c +++

[Mesa-dev] [PATCH 10/16] i965: Add and use brw_bo_map()

We can encapsulate the logic for choosing the mapping type. This will also help when we add WC mappings. --- src/mesa/drivers/dri/i965/brw_bufmgr.c| 30 +-- src/mesa/drivers/dri/i965/brw_bufmgr.h| 5 ++--

[Mesa-dev] [PATCH 12/16] i965: Use write-combine mappings where available

Write-combine mappings give much better performance on writes than uncached access through the GTT. --- src/mesa/drivers/dri/i965/brw_bufmgr.c | 69 ++ 1 file changed, 69 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_bufmgr.c

[Mesa-dev] [PATCH 16/16] i965: Enable tiled memcpy tex image path on non-LLC

--- src/mesa/drivers/dri/i965/intel_tex_subimage.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/i965/intel_tex_subimage.c b/src/mesa/drivers/dri/i965/intel_tex_subimage.c index 7acb3d3..2aead41 100644 ---

[Mesa-dev] [PATCH 05/16] i965: Pass the map-mode along to intel_mipmap_tree_map_raw()

From: Chris Wilson <ch...@chris-wilson.co.uk> Since we can distinguish when mapping between READ and WRITE, we can pass along the map mode to avoid stalls and flushes where possible. Reviewed-by: Kenneth Graunke <kenn...@whitecape.org> Reviewed-by: Matt Turner <matts...@gmail.com

[Mesa-dev] [PATCH 09/16] i965: Drop MAP_READ from some write-only mappings

--- src/mesa/drivers/dri/i965/brw_performance_query.c | 2 +- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 2 +- src/mesa/drivers/dri/i965/intel_screen.c | 2 +- src/mesa/drivers/dri/i965/intel_tex_subimage.c| 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git

[Mesa-dev] [PATCH 02/16] i965: Remove brw_bo's virtual member

Just return the map from brw_map_bo_* --- src/mesa/drivers/dri/i965/brw_bufmgr.c| 49 +-- src/mesa/drivers/dri/i965/brw_bufmgr.h| 19 ++--- src/mesa/drivers/dri/i965/brw_context.h | 2 + src/mesa/drivers/dri/i965/brw_performance_query.c |

[Mesa-dev] [PATCH 13/16] i965: Explicitly disallow tiled memcpy path on Gen4 with swizzling.

From: Chris Wilson <ch...@chris-wilson.co.uk> The manual detiling paths are not prepared to handle Gen4-G45 with swizzling enabled, so explicitly disable them. (They're already disabled because these platforms don't have LLC but the next patch will enable this path). Reviewed-by: Matt

[Mesa-dev] [PATCH 01/16] i965: Remove unused brw_bo_map__* functions

--- src/mesa/drivers/dri/i965/brw_bufmgr.c | 105 - src/mesa/drivers/dri/i965/brw_bufmgr.h | 4 -- 2 files changed, 109 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_bufmgr.c b/src/mesa/drivers/dri/i965/brw_bufmgr.c index 2f17934..6ea6978 100644 ---

[Mesa-dev] [PATCH 08/16] i965: Pass flags to brw_bo_map_*

brw_bo_map_cpu() took a write_enable arg, but it wasn't always clear whether we were also planning to read from the buffer. I kept everything semantically identical by passing only MAP_READ or MAP_READ | MAP_WRITE depending on the write_enable argument. The other flags are not used yet, but

[Mesa-dev] [PATCH 03/16] i965: Remove unused 'use_resource_streamer' field

Missing in the resource streamer removal of commit 951f56cd43bc. --- src/mesa/drivers/dri/i965/brw_context.h | 1 - 1 file changed, 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h index b99d2a9..f902265 100644 ---

[Mesa-dev] [PATCH 07/16] i965: Rename brw_bo_map() -> brw_bo_map_cpu()

I'm going to make a new function named brw_bo_map() in a later patch that is responsible for choosing the mapping type, so this patch clears the way. --- src/mesa/drivers/dri/i965/brw_bufmgr.c| 9 + src/mesa/drivers/dri/i965/brw_bufmgr.h| 4 ++--

[Mesa-dev] [PATCH 04/16] i965: Add a cache_coherent field to brw_bo

--- src/mesa/drivers/dri/i965/brw_bufmgr.c| 1 + src/mesa/drivers/dri/i965/brw_bufmgr.h| 5 + src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 3 +++ 3 files changed, 9 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_bufmgr.c b/src/mesa/drivers/dri/i965/brw_bufmgr.c

[Mesa-dev] [PATCH 06/16] i965: Rename *_virtual -> map_*

I think these are better names, and it reduces the delta between upstream and Chris Wilson's brw-batch branch. --- src/mesa/drivers/dri/i965/brw_bufmgr.c | 56 +- src/mesa/drivers/dri/i965/brw_bufmgr.h | 6 ++-- 2 files changed, 31 insertions(+), 31 deletions(-)

[Mesa-dev] [PATCH 00/16] i965: Write-combine mappings and other performance improvements for non-LLC

The series aims to improve performance on non-LLC platforms like Braswell and Broxton. Unsynchronized mappings were not actually unsynchronized on non-LLC platforms, hurting Unigine Valley performance quite a lot. That's fixed. We also start using write-combining, a feature available since Linux

Re: [Mesa-dev] [PATCH V2] intel/compiler: Make use of IS_INTEGER_DWORD macro

On Wed, May 24, 2017 at 9:21 AM, Anuj Phogat wrote: > This patch makes non-functional changes. > > V2: Rename IS_DWORD to IS_INTEGER_DWORD To be honest, I don't like IS_DWORD/IS_INTEGER_DWORD -- for the same reason Alejandro noted. It's not clear what it means exactly,

Re: [Mesa-dev] [PATCH] glsl: Fix g++ initializer order warning

Reviewed-by: Matt Turner <matts...@gmail.com> ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH v2 0/6] Various fixes to integer GetUniform*()

and adds another patch at the end to remove the remaining uses > of IROUND macros in this function (still used for signed integer cases) for > the sake of consistency. Thank you for doing this. Assuming my suggestions to use lround/llround/etc don't cause problems, the series is Revie

Re: [Mesa-dev] [PATCH v2 6/6] mesa/main: replace remaining uses of IROUND() in GetUniform*() by round()

On Thu, May 18, 2017 at 2:43 AM, Iago Toral Quiroga wrote: > These were correct since they were used only in conversions to signed > integers, > however this makes the implementation a bit more is more consistent and > reduces > chances of propagating use of these macros to

Re: [Mesa-dev] [PATCH v2 5/6] mesa/main: conversion from float in GetUniformi64v requires rounding to nearest

On Thu, May 18, 2017 at 2:43 AM, Iago Toral Quiroga wrote: > As we do for all other cases of float/double conversions to integers. > > v2: use round() instead of IROUND() macros > --- > src/mesa/main/uniform_query.cpp | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > >

Re: [Mesa-dev] [PATCH v2 4/6] mesa/main: Add conversion from double to uint64/int64 in GetUniform*i64v()

On Thu, May 18, 2017 at 2:43 AM, Iago Toral Quiroga wrote: > v2: > - need unsigned rounding for double->uint64 conversion (Nicolai) > - use round() instead of IROUND() macros > --- > src/mesa/main/uniform_query.cpp | 14 ++ > 1 file changed, 14 insertions(+) >

Re: [Mesa-dev] [PATCH v2 3/6] mesa/main: Clamp GetUniformui64v values to be >= 0

On Thu, May 18, 2017 at 2:43 AM, Iago Toral Quiroga wrote: > Like we do for the 32-bit case. > > v2: > - need unsigned rounding for float->uint64 conversion (Nicolai) > - use roundf() instead of IROUND() macros > --- > src/mesa/main/uniform_query.cpp | 46 >

Re: [Mesa-dev] [PATCH v2 2/6] mesa/main: Clamp GetUniformuiv values to be >= 0

On Thu, May 18, 2017 at 2:43 AM, Iago Toral Quiroga wrote: > From: Kenneth Graunke > > Section 2.2.2 (Data Conversions For State Query Commands) of the > OpenGL 4.5 October 24th 2016 specification says: > > "If a command returning unsigned integer data

Re: [Mesa-dev] [PATCH 11/11] intel/aubinator_error_decode: Disassemble shader programs

On Wed, May 17, 2017 at 9:29 AM, Anuj Phogat <anuj.pho...@gmail.com> wrote: > On Mon, May 1, 2017 at 1:54 PM, Matt Turner <matts...@gmail.com> wrote: >> --- >> src/intel/Makefile.tools.am | 6 +- >> src/intel/too

Re: [Mesa-dev] [PATCH 11/43] intel/gensml: Suffix KSP0 fields on Iron Lake

xml > +++ b/src/intel/genxml/gen5.xml > @@ -864,8 +864,8 @@ > > > > - > - > + I removed the brackets from the Kernel Start Pointer names in commit 3443bd45a3. Please just add 0 and not [0] With that, Reviewed-by: Matt Turner <matts...@gmail.com>

Re: [Mesa-dev] [PATCH 02/11] i965: Pass pointer and end of assembly to brw_validate_instructions

On Tue, May 16, 2017 at 8:44 AM, Aaron Watry wrote: > Hi Matt, > > This commit seems to have broken make check for me. > > In src/intel/compiler/test_eu_validate.cpp, line 121, I'm getting: > > ~/src/mesa/src/intel/compiler/test_eu_validate.cpp:121:41: error: use of >

Re: [Mesa-dev] [PATCH 3/4] glsl: Merge if-simplification and conditional discard optimization

On Mon, Apr 24, 2017 at 4:50 PM, Matt Turner <matts...@gmail.com> wrote: > On Thu, Apr 6, 2017 at 12:49 PM, Thomas Helland > <thomashellan...@gmail.com> wrote: >> The conditional discard pass follows the same pattern, so merge the >> two, and avoid running the vis

Re: [Mesa-dev] [PATCH 11/11] intel/aubinator_error_decode: Disassemble shader programs

On Fri, May 5, 2017 at 12:44 AM, Pohjolainen, Topi <topi.pohjolai...@gmail.com> wrote: > On Mon, May 01, 2017 at 01:54:55PM -0700, Matt Turner wrote: >> --- >> src/intel/Makefile.tools.am | 6 +- >> src/intel/tools/aub

Re: [Mesa-dev] [PATCH 1/3] intel: gen decoder: don't check for size_t negative values

Reviewed-by: Matt Turner <matts...@gmail.com> ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH 2/3] intel: compiler: remove duplicated code

On Mon, May 8, 2017 at 3:02 PM, Lionel Landwerlin <lionel.g.landwer...@intel.com> wrote: > CID: 1399470: (Control flow issues) > > Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com> > Cc: Matt Turner <matts...@gmail.com> > --- > src/i

Re: [Mesa-dev] [PATCH 3/3] intel: compiler: prevent integer overflow

On Mon, May 8, 2017 at 3:02 PM, Lionel Landwerlin <lionel.g.landwer...@intel.com> wrote: > CID: 1399477, 1399478 (Integer handling issues) > > Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com> > Cc: Matt Turner <matts...@gmail.com> > --- > src/

Re: [Mesa-dev] [PATCH 09/11] intel/tools: Refactor gen_disasm_disassemble() to use annotations

On Tue, May 2, 2017 at 6:03 AM, Iago Toral <ito...@igalia.com> wrote: > On Mon, 2017-05-01 at 13:54 -0700, Matt Turner wrote: >> Which will allow us to print validation errors found in shader >> assembly >> in GPU hang error states. >> ---

Re: [Mesa-dev] [PATCH 02/11] i965: Pass pointer and end of assembly to brw_validate_instructions

On Tue, May 2, 2017 at 5:30 AM, Iago Toral <ito...@igalia.com> wrote: > On Mon, 2017-05-01 at 13:54 -0700, Matt Turner wrote: >> This will allow us to more easily run brw_validate_instructions() on >> shader programs we find in GPU hang error states. >> --- >

Re: [Mesa-dev] [PATCH] i965: Make the field computed_depth_mode an enum.

On Wed, May 3, 2017 at 6:03 PM, Kenneth Graunke wrote: > On Tuesday, May 2, 2017 11:02:58 AM PDT Rafael Antognolli wrote: >> Since the enum is in the same header now, we can use it as the type of >> the field. >> >> Signed-off-by: Rafael Antognolli

Re: [Mesa-dev] [PATCH 3/5 v2] glsl: Restrict func redeclarations (not just redefinitions) on GLSL 1.00.

Thanks. This patch has no regressions. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH 3/5] glsl: Restrict func redeclarations (not just redefinitions) on GLSL 1.00.

On Tue, May 2, 2017 at 10:36 AM, Eric Anholt wrote: > Fixes DEQP's scoping.invalid.redeclare_function_fragment/vertex. > --- > src/compiler/glsl/ast_to_hir.cpp | 10 ++ > 1 file changed, 10 insertions(+) > > diff --git a/src/compiler/glsl/ast_to_hir.cpp >

Re: [Mesa-dev] [PATCH 0/5] misc dEQP fixes for vc4

On Tue, May 2, 2017 at 10:36 AM, Eric Anholt wrote: > Here's a little set of changes for dEQP fixes for GLES2 contexts. I > haven't done a full run to confirm no regressions, as full runs on > hardware take a day or so. I'm hoping the Intel CI system might be > able to test

Re: [Mesa-dev] [PATCH] fix minor error in YUV2RGB matrix used in shader

On Tue, May 2, 2017 at 7:24 AM, Johnson Lin wrote: > The matrix used for YCbCr to RGB is listed in Wiki https://en.wikipedia.org/ > wiki/YCbCr; There is minor error in the matrix constant: 0.0625=16/256 should > be 16.0/255,and 0.5=128.0/256 should be 128.0/255. > Note

[Mesa-dev] [PATCH 10/11] intel/aubinator_error_decode: Stop decoding after MI_BATCH_BUFFER_END

--- src/intel/tools/aubinator_error_decode.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/intel/tools/aubinator_error_decode.c b/src/intel/tools/aubinator_error_decode.c index 2e62369..244bef8 100644 --- a/src/intel/tools/aubinator_error_decode.c +++

[Mesa-dev] [PATCH 11/11] intel/aubinator_error_decode: Disassemble shader programs

--- src/intel/Makefile.tools.am | 6 +- src/intel/tools/aubinator_error_decode.c | 178 ++- 2 files changed, 180 insertions(+), 4 deletions(-) diff --git a/src/intel/Makefile.tools.am b/src/intel/Makefile.tools.am index 576beea..1175118 100644 ---

[Mesa-dev] [PATCH 08/11] intel/decoder: Fix indentation

--- src/intel/common/gen_decoder.c | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/intel/common/gen_decoder.c b/src/intel/common/gen_decoder.c index 15bba32..049d1be 100644 --- a/src/intel/common/gen_decoder.c +++ b/src/intel/common/gen_decoder.c @@ -433,8 +433,8

[Mesa-dev] [PATCH 09/11] intel/tools: Refactor gen_disasm_disassemble() to use annotations

Which will allow us to print validation errors found in shader assembly in GPU hang error states. --- src/intel/tools/disasm.c | 71 +--- 1 file changed, 43 insertions(+), 28 deletions(-) diff --git a/src/intel/tools/disasm.c b/src/intel/tools/disasm.c

[Mesa-dev] [PATCH 03/11] i965: Allow brw_eu_validate to handle compact instructions

This will allow the validator to run on shader programs we find in the GPU hang error state. --- src/intel/compiler/brw_eu_validate.c | 14 ++ 1 file changed, 14 insertions(+) diff --git a/src/intel/compiler/brw_eu_validate.c b/src/intel/compiler/brw_eu_validate.c index

[Mesa-dev] [PATCH 04/11] i965: Add a weak no-op nir_print_instr() symbol

intel_asm_annotation.c is part of libintel_compiler.la, which contains code for disassembling and validating shaders that we want to call in aubinator_error_decode. dump_assembly() calls nir_print_instr() to print annotations, and although dump_assembly() is not called by aubinator_error_decode

[Mesa-dev] [PATCH 07/11] genxml: Rename "VS Function Enable" to just "Function Enable"

Other commands have a field with an identical function and call it "Function Enable". --- src/intel/genxml/gen45.xml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/intel/genxml/gen45.xml b/src/intel/genxml/gen45.xml index 1a5a521..b7f0c8b 100644 ---

[Mesa-dev] [PATCH 05/11] genxml: Remove brackets from kernel start pointer names

Newer Gens' names don't have the brackets. Having common names will make some later patches simpler. --- src/intel/genxml/gen4.xml | 2 +- src/intel/genxml/gen45.xml | 2 +- src/intel/genxml/gen6.xml | 6 +++--- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git

[Mesa-dev] [PATCH 06/11] genxml: Remove hyphens from pixel dispatch enable names

Newer Gens' names don't have the hyphens. Having common names will make some later patches simpler. --- src/intel/genxml/gen4.xml | 6 +++--- src/intel/genxml/gen45.xml | 10 +- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/src/intel/genxml/gen4.xml

[Mesa-dev] [PATCH 02/11] i965: Pass pointer and end of assembly to brw_validate_instructions

This will allow us to more easily run brw_validate_instructions() on shader programs we find in GPU hang error states. --- src/intel/compiler/brw_eu.h | 3 ++- src/intel/compiler/brw_eu_validate.c | 10 -- src/intel/compiler/brw_fs_generator.cpp | 10 --

[Mesa-dev] [PATCH 01/11] i965: Mark shader programs for capture in the error state.

When the GPU hangs, the kernel saves some state for us. Until now it has not included the shader programs, which are very often the reason the GPU hang occurred. With the programs saved in the error state, we should be more capable of debugging hangs. Thanks to Chris Wilson and Ben Widawsky who

[Mesa-dev] [PATCH 00/11] i965: Shader programs in the error state

This series adds the userspace portion required to save the shader programs that were running when a GPU hang occurred in the error state. From there we can feed the error state to aubinator_error_decode, which will parse the batch and find the shader programs, validate them (using

Re: [Mesa-dev] [RFC 1/2] glx|egl: allow to test if glthread is safe enough on X11 platform

On Fri, Apr 28, 2017 at 2:11 PM, Gregory Hainaut wrote: > I extended the struct __DRIbackgroundCallableExtensionRec because > the other function pointer is already related for glthread. > > DRI2/DRI3 glx code path check that display can be locked (basically >

Re: [Mesa-dev] [PATCH] egl: polish dri2_to_egl_attribute_map[]

Nice change. Reviewed-by: Matt Turner <matts...@gmail.com> ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH 3/4] glsl: Merge if-simplification and conditional discard optimization

On Thu, Apr 6, 2017 at 12:49 PM, Thomas Helland wrote: > The conditional discard pass follows the same pattern, so merge the > two, and avoid running the visitor two times. > --- > src/compiler/Makefile.sources | 1 - >

Re: [Mesa-dev] [PATCH] docs: Update MESA_shader_integer_functions spec to version 3.

Acked-by: Matt Turner <matts...@gmail.com> ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH] i965/fs: Take into account lower frequency of conditional blocks in spilling cost heuristic.

Nice idea. I'm happy with 0.5. It's a nice improvement already. Reviewed-by: Matt Turner <matts...@gmail.com> ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH] intel/aubinator_error_decode: Stop decoding after MI_BATCH_BUFFER_END

--- src/intel/tools/aubinator_error_decode.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/intel/tools/aubinator_error_decode.c b/src/intel/tools/aubinator_error_decode.c index 2e62369..244bef8 100644 --- a/src/intel/tools/aubinator_error_decode.c +++

Re: [Mesa-dev] [PATCH 0/4] GLSL passes begone

On Thu, Apr 6, 2017 at 12:49 PM, Thomas Helland wrote: > This series has been reciding on my computer for way to long, > so it's about time I get it out there for some feedback. > The rationale is that in the glsl compiler a lot of the overhead > is in cache misses due

Re: [Mesa-dev] [PATCH v2 1/4] intel/aubinator_error_decode: Fix structure decode data

%s\n", > color, offset, p[0], gen_group_get_name(inst), reset_color); > > - gen_print_group(stdout, inst, offset, data, > + gen_print_group(stdout, inst, offset, p, > option_color == COLOR_ALWAYS); Nice. This fixes a bug I was seeing as well. Reviewed-

Re: [Mesa-dev] [PATCH] mesa: stop abstracting buffer object hashtable locking

Reviewed-by: Matt Turner <matts...@gmail.com> ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH] intel/vec4: Add some fall through comments

Thank you. These coverity warnings have been coming back repeatedly it seems. Reviewed-by: Matt Turner <matts...@gmail.com> ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH v2] util/u_atomic: provide 64bit atomics where they're missing

On Mon, Apr 3, 2017 at 1:37 PM, Mark Janes wrote: > > This commit appears to intermittently provoke gpu hangs on 32-bit Intel > systems when running > > piglit.shaders.glsl-max-varyings >max_varying_components > > Since the behavior is intermittent, I may have identified

Re: [Mesa-dev] [PATCH 1/2] intel: gen_decoder: store pointer to current decoded field in iterator

Both are Reviewed-by: Matt Turner <matts...@gmail.com> ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH v2] util/u_atomic: provide 64bit atomics where they're missing

On Thu, Mar 30, 2017 at 3:47 PM, Matt Turner <matts...@gmail.com> wrote: > On Thu, Mar 30, 2017 at 3:26 PM, Grazvydas Ignotas <nota...@gmail.com> wrote: >> There are still some distributions trying to support unfortunate people >> with old or exotic CPUs that don't h

Re: [Mesa-dev] [PATCH v2] util/u_atomic: provide 64bit atomics where they're missing

gzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93089 > Signed-off-by: Grazvydas Ignotas <nota...@gmail.com> > Reviewed-by: Matt Turner <matts...@gmail.com> Thanks, I'll commit this. > --- > no commit access, but request sent: > https://bugs.freedesktop.org/show_bug.c

Re: [Mesa-dev] [PATCH] intel: genxml: add gen7 ERR_INT register

Reviewed-by: Matt Turner <matts...@gmail.com> ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH 7/7] intel: tools: add aubinator_error_decode tool

> +} > + > +int > +main(int argc, char *argv[]) > +{ > + FILE *file; > + const char *path; > + struct stat st; > + int c, i, error; > + bool help = false, pager = true; > + const struct option aubinator_opts[] = { > + { "help", no_ar

Re: [Mesa-dev] [PATCH 0/7] Aubinator error decode

1-3 are Reviewed-by: Matt Turner <matts...@gmail.com> I think 4 should touch gen75.xml, and I sent a comment. I cannot find the registers in 5 or 6 in the internal documentation. I'll review patch 7 separately. ___ mesa-dev mailing list me

Re: [Mesa-dev] [PATCH 4/7] intel: genxml: add gen7 ERR_INT register

On Wed, Mar 29, 2017 at 1:07 PM, Lionel Landwerlin wrote: > Signed-off-by: Lionel Landwerlin > --- > src/intel/genxml/gen7.xml | 11 +++ > 1 file changed, 11 insertions(+) > > diff --git a/src/intel/genxml/gen7.xml

Re: [Mesa-dev] [PATCH] drirc: Set glsl_zero_init for Kerbal Space Program.

SL shaders used by the > application use variables before initializing them, incorrectly > assuming that they will be implicitly set to zero by the > implementation. Sigh. Acked-by: Matt Turner <matts...@gmail.com> ___ mesa-dev mailing list mesa-d

Re: [Mesa-dev] [PATCH] util/u_atomic: provide 64bit atomics where they're missing

a library call to > a helper, but it's implementation is missing and we get a linker error. > This allows us to provide our implementation, which is marked weak to > prefer a better implementation, should one exist. > > Cc: Matt Turner <matts...@gmail.com> > Bugzilla: https

Re: [Mesa-dev] [PATCH] [RFC v2] mesa/glthread: Call unmarshal_batch directly in glthread_finish when batch queue is empty.

On Wed, Mar 29, 2017 at 9:11 AM, Bartosz Tomczyk wrote: > This avoids costly thread synchronisation. With this fix games that > previously regressed with mesa_glthread=true like xonotic or grid autosport. > Could someone test if games that benefit from glthread

Re: [Mesa-dev] [PATCH v3] i965: expose BRW_OPCODE_[F32TO16/F16TO32] name on gen8+

Thanks. That looks good. Reviewed-by: Matt Turner <matts...@gmail.com> ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH] i965: expose BRW_OPCODE_[F32TO16/F16TO32] opcode_descs on gen8+

On Wed, Mar 29, 2017 at 4:47 AM, Alejandro Piñeiro wrote: > Technically those hw operations are only available on gen7, as gen8+ > support the conversion on the MOV. But, when using the builder to > implement nir operations (example: nir_op_fquantize2f16), it is not > needed

Re: [Mesa-dev] [Mesa-stable] [PATCH] i965/fs: Don't emit SEL instructions for type-converting MOVs.

Thanks. I've pushed this patch as commit 7dccd38b400d3a65da20ddefe282a7bb0b7ccb58 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH 1/3] glsl: delay optimisations on individual shaders when cache is available

On Sun, Mar 26, 2017 at 8:14 PM, Timothy Arceri wrote: > Due to a max limit of 65,536 entries on the index table that we use to > decide if we can skip compiling individual shaders, it is very likely > we will have collisions. > > To avoid doing too much work when the

Re: [Mesa-dev] [PATCH 3/3] glsl: don't run the GLSL pre-processor when we are skipping compilation

On Sun, Mar 26, 2017 at 8:14 PM, Timothy Arceri wrote: > Improves Deus Ex start-up times from ~30 seconds to ~22 seconds. > > Also fixes the leaking of state. > --- > src/compiler/glsl/glsl_parser_extras.cpp | 19 ++- > 1 file changed, 10 insertions(+), 9

Re: [Mesa-dev] [Mesa-stable] [PATCH] i965/fs: Don't emit SEL instructions for type-converting MOVs.

On Fri, Mar 24, 2017 at 12:06 AM, Francisco Jerez <curroje...@riseup.net> wrote: > Samuel Iglesias Gonsálvez <sigles...@igalia.com> writes: > >> On Thu, 2017-03-23 at 13:50 -0700, Matt Turner wrote: >>> SEL can only convert between a few integer types

Re: [Mesa-dev] [PATCH] i965: Require Kernel 3.6 for Gen4-5 platforms.

ent from 2.6.39. > > This is necessary for glClientWaitSync with a timeout to work, which > is a feature we expose on Gen4-5. Without it, we would fall back to an > infinite wait, which is pretty bad. > > See kernel commit 172cf15d18889313bf2c3bfb81fcea08369274ef in 3.6+.

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