Re: [Mesa-dev] [PATCH 5/5] anv: disable repacking for compression for applicable gen

[Anuj Phogat]

On Thu, Jun 27, 2019 at 9:55 AM Dongwon Kim  wrote:
>
> set bit15 (Disable Rebacking for Compression) of CACHE_MODE_0 register
Repacking

With minor nits fixed. This series is:
Reviewed-by: Anuj Phogat 

I'll push the series after testing with these changes. Thanks for the patches :)

> if the gen attribute, 'disable_ccs_repack' is set.
>
> Signed-off-by: Dongwon Kim 
> ---
>  src/intel/vulkan/genX_state.c | 18 ++
>  1 file changed, 18 insertions(+)
>
> diff --git a/src/intel/vulkan/genX_state.c b/src/intel/vulkan/genX_state.c
> index 21b8cd648d4..c1163628cc0 100644
> --- a/src/intel/vulkan/genX_state.c
> +++ b/src/intel/vulkan/genX_state.c
> @@ -225,6 +225,24 @@ genX(init_device_state)(struct anv_device *device)
> }
>  #endif
>
> +#if GEN_GEN >= 11
> +   /* hardware specification recommends disabling repacking for
> +* the compatibility with decompression mechanism in display controller.
> +*/
> +   if (device->info.disable_ccs_repack) {
> +  uint32_t cache_mode_0;
> +  anv_pack_struct(_mode_0,
> +  GENX(CACHE_MODE_0),
> +  .DisableRepackingforCompression = true,
> +  .DisableRepackingforCompressionMask = true);
> +
> +  anv_batch_emit(, GENX(MI_LOAD_REGISTER_IMM), lri) {
> + lri.RegisterOffset = GENX(CACHE_MODE_0_num);
> + lri.DataDWord  = cache_mode_0;
> +  }
> +   }
> +#endif
> +
> /* Set the "CONSTANT_BUFFER Address Offset Disable" bit, so
>  * 3DSTATE_CONSTANT_XS buffer 0 is an absolute address.
>  *
> --
> 2.17.1
>
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Re: [Mesa-dev] [PATCH 4/5] iris: disable repacking for compression for applicable gen

[Anuj Phogat]

On Thu, Jun 27, 2019 at 9:55 AM Dongwon Kim  wrote:
>
> set bit15 (Disable Rebacking for Compression) of CACHE_MODE_0 register
Repacking
> if the gen attribute, 'disable_ccs_repack' is set.
>
> Signed-off-by: Dongwon Kim 
> ---
>  src/gallium/drivers/iris/iris_state.c | 10 ++
>  1 file changed, 10 insertions(+)
>
> diff --git a/src/gallium/drivers/iris/iris_state.c 
> b/src/gallium/drivers/iris/iris_state.c
> index bf31f31f3e4..ce25f1ffcb3 100644
> --- a/src/gallium/drivers/iris/iris_state.c
> +++ b/src/gallium/drivers/iris/iris_state.c
> @@ -755,6 +755,16 @@ iris_init_render_context(struct iris_screen *screen,
>}
>iris_emit_lri(batch, SLICE_COMMON_ECO_CHICKEN1, reg_val);
>
> +  /* hardware specification recommends disabling repacking for
> +   * the compatibility with decompression mechanism in display 
> controller.
> +   */
> +  if (devinfo->disable_ccs_repack) {
> + iris_pack_state(GENX(CACHE_MODE_0), _val, reg) {
> +reg.DisableRepackingforCompression = true;
> +reg.DisableRepackingforCompressionMask = true;
> + }
> + iris_emit_lri(batch, CACHE_MODE_0, reg_val);
> +  }
>
>// XXX: 3D_MODE?
>  #endif
> --
> 2.17.1
>
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Re: [Mesa-dev] [PATCH 3/5] i965: disable repacking for compression for applicable gen

[Anuj Phogat]

On Thu, Jun 27, 2019 at 9:55 AM Dongwon Kim  wrote:
>
> set bit15 (Disable Rebacking for Compression) of CACHE_MODE_0 register
Disable Repacking
> if the gen attribute, 'disable_ccs_repack' is set.
>
> Signed-off-by: Dongwon Kim 
> ---
>  src/mesa/drivers/dri/i965/brw_defines.h  | 1 +
>  src/mesa/drivers/dri/i965/brw_state_upload.c | 9 +
>  2 files changed, 10 insertions(+)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_defines.h 
> b/src/mesa/drivers/dri/i965/brw_defines.h
> index 17bca1991f1..e8507b7e5ff 100644
> --- a/src/mesa/drivers/dri/i965/brw_defines.h
> +++ b/src/mesa/drivers/dri/i965/brw_defines.h
> @@ -1576,6 +1576,7 @@ enum brw_pixel_shader_coverage_mask_mode {
>  # define GEN9_PARTIAL_RESOLVE_DISABLE_IN_VC (1 << 1)
>  # define GEN8_HIZ_PMA_MASK_BITS \
> REG_MASK(GEN8_HIZ_NP_PMA_FIX_ENABLE | GEN8_HIZ_NP_EARLY_Z_FAILS_DISABLE)
> +# define GEN11_DISABLE_REPACKING_FOR_COMPRESSION (1 << 15)
>
>  #define GEN7_GT_MODE0x7008
>  # define GEN9_SUBSLICE_HASHING_8x8  (0 << 8)
> diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c 
> b/src/mesa/drivers/dri/i965/brw_state_upload.c
> index 938b9defeda..09303600308 100644
> --- a/src/mesa/drivers/dri/i965/brw_state_upload.c
> +++ b/src/mesa/drivers/dri/i965/brw_state_upload.c
> @@ -121,6 +121,15 @@ brw_upload_initial_gpu_state(struct brw_context *brw)
> 
> REG_MASK(GEN11_STATE_CACHE_REDIRECT_TO_CS_SECTION_ENABLE));
> }
>
> +   /* hardware specification recommends disabling repacking for
> +* the compatibility with decompression mechanism in display controller.
> +*/
> +   if (devinfo->disable_ccs_repack) {
> +  brw_load_register_imm32(brw, GEN7_CACHE_MODE_0,
> +  GEN11_DISABLE_REPACKING_FOR_COMPRESSION |
> +  
> REG_MASK(GEN11_DISABLE_REPACKING_FOR_COMPRESSION));
> +   }
> +
> if (devinfo->gen == 10 || devinfo->gen == 11) {
>/* From gen10 workaround table in h/w specs:
> *
> --
> 2.17.1
>
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Re: [Mesa-dev] [PATCH 2/5] intel: add disable_ccs_repack to gen_device_info

[Anuj Phogat]

On Thu, Jun 27, 2019 at 9:55 AM Dongwon Kim  wrote:
>
> add a new attribute, 'disable_ccs_repack' to gen_device info, which
> indicates whether repacking of components in certain pixel formats
> before compression needs to be disabled to keep the compatibility
> with decompression capability of display controller (gen11+)
>
> Signed-off-by: Dongwon Kim 
> ---
>  src/intel/dev/gen_device_info.c | 3 +++
>  src/intel/dev/gen_device_info.h | 1 +
>  2 files changed, 4 insertions(+)
>
> diff --git a/src/intel/dev/gen_device_info.c b/src/intel/dev/gen_device_info.c
> index fec6159fd37..2b5be842a4e 100644
> --- a/src/intel/dev/gen_device_info.c
> +++ b/src/intel/dev/gen_device_info.c
> @@ -958,6 +958,7 @@ static const struct gen_device_info 
> gen_device_info_ehl_4x8 = {
>   [MESA_SHADER_GEOMETRY]  = 1032,
>},
> },
> +   .disable_ccs_repack = 1,
disable_ccs_repack = true

Similar change at few other places in this patch.
> .simulator_id = 28,
>  };
>
> @@ -978,6 +979,7 @@ static const struct gen_device_info 
> gen_device_info_ehl_4x4 = {
>   [MESA_SHADER_GEOMETRY]  = 1032,
>},
> },
> +   .disable_ccs_repack = 1,
> .num_eu_per_subslice = 4,
> .simulator_id = 28,
>  };
> @@ -999,6 +1001,7 @@ static const struct gen_device_info 
> gen_device_info_ehl_2x4 = {
>   [MESA_SHADER_GEOMETRY]  = 1032,
>},
> },
> +   .disable_ccs_repack = 1,
> .num_eu_per_subslice =4,
> .simulator_id = 28,
>  };
> diff --git a/src/intel/dev/gen_device_info.h b/src/intel/dev/gen_device_info.h
> index af13615be2b..4fe937355a7 100644
> --- a/src/intel/dev/gen_device_info.h
> +++ b/src/intel/dev/gen_device_info.h
> @@ -74,6 +74,7 @@ struct gen_device_info
> bool has_surface_tile_offset;
> bool supports_simd16_3src;
> bool has_resource_streamer;
> +   bool disable_ccs_repack;
>
> /**
>  * \name Intel hardware quirks
> --
> 2.17.1
>
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Re: [Mesa-dev] [PATCH v2] ehl: disable repacking for compression for compatibilty

[Anuj Phogat]

+mesa-dev

On Thu, Jun 20, 2019 at 12:20 PM Anuj Phogat  wrote:
>
> I sent out comments on your older patch. They applies to this patch too.
> Split i965 and anv changes in separate patches.
>
> On Thu, Jun 20, 2019 at 11:25 AM Dongwon Kim  wrote:
> >
> > Repacking components in certain pixel formats before compression
> > shouldn't be done for EHL to keep the compatibility with decompression
> > capability in its display controller.
> >
> > v2: applied to iris, i965 and anvil.
> >
> > Signed-off-by: Dongwon Kim 
> > ---
> >  src/gallium/drivers/iris/iris_state.c| 10 +++
> >  src/intel/dev/gen_device_info.c  |  4 +++
> >  src/intel/dev/gen_device_info.h  |  1 +
> >  src/intel/genxml/gen11.xml   | 30 +---
> >  src/intel/vulkan/genX_state.c| 18 
> >  src/mesa/drivers/dri/i965/brw_defines.h  |  1 +
> >  src/mesa/drivers/dri/i965/brw_state_upload.c |  9 ++
> >  7 files changed, 57 insertions(+), 16 deletions(-)
> >
> > diff --git a/src/gallium/drivers/iris/iris_state.c 
> > b/src/gallium/drivers/iris/iris_state.c
> > index 23f8d290368..8744178e94d 100644
> > --- a/src/gallium/drivers/iris/iris_state.c
> > +++ b/src/gallium/drivers/iris/iris_state.c
> > @@ -749,6 +749,16 @@ iris_init_render_context(struct iris_screen *screen,
> >}
> >iris_emit_lri(batch, SLICE_COMMON_ECO_CHICKEN1, reg_val);
> >
> > +  /* needed to disable replacking to keep the compatibility with
> > +   * decompressing mechanism in display controller.
> > +   */
> > +  if (devinfo->need_disable_ccs_repack) {
> > + iris_pack_state(GENX(CACHE_MODE_0), _val, reg) {
> > +reg.DisableRepackingforCompression = true;
> > +reg.DisableRepackingforCompressionMask = true;
> > + }
> > + iris_emit_lri(batch, CACHE_MODE_0, reg_val);
> > +  }
> >
> >// XXX: 3D_MODE?
> >  #endif
> > diff --git a/src/intel/dev/gen_device_info.c 
> > b/src/intel/dev/gen_device_info.c
> > index fec6159fd37..ee3ad7ba085 100644
> > --- a/src/intel/dev/gen_device_info.c
> > +++ b/src/intel/dev/gen_device_info.c
> > @@ -64,6 +64,7 @@ gen_device_name_to_pci_device_id(const char *name)
> >{ "cml", 0x9b41 },
> >{ "cnl", 0x5a52 },
> >{ "icl", 0x8a52 },
> > +  { "ehl", 0x4500 },
> > };
> >
> > for (unsigned i = 0; i < ARRAY_SIZE(name_map); i++) {
> > @@ -958,6 +959,7 @@ static const struct gen_device_info 
> > gen_device_info_ehl_4x8 = {
> >   [MESA_SHADER_GEOMETRY]  = 1032,
> >},
> > },
> > +   .need_disable_ccs_repack = 1,
> > .simulator_id = 28,
> >  };
> >
> > @@ -978,6 +980,7 @@ static const struct gen_device_info 
> > gen_device_info_ehl_4x4 = {
> >   [MESA_SHADER_GEOMETRY]  = 1032,
> >},
> > },
> > +   .need_disable_ccs_repack = 1,
> > .num_eu_per_subslice = 4,
> > .simulator_id = 28,
> >  };
> > @@ -999,6 +1002,7 @@ static const struct gen_device_info 
> > gen_device_info_ehl_2x4 = {
> >   [MESA_SHADER_GEOMETRY]  = 1032,
> >},
> > },
> > +   .need_disable_ccs_repack = 1,
> > .num_eu_per_subslice =4,
> > .simulator_id = 28,
> >  };
> > diff --git a/src/intel/dev/gen_device_info.h 
> > b/src/intel/dev/gen_device_info.h
> > index af13615be2b..e90d31935f1 100644
> > --- a/src/intel/dev/gen_device_info.h
> > +++ b/src/intel/dev/gen_device_info.h
> > @@ -74,6 +74,7 @@ struct gen_device_info
> > bool has_surface_tile_offset;
> > bool supports_simd16_3src;
> > bool has_resource_streamer;
> > +   bool need_disable_ccs_repack;
> >
> > /**
> >  * \name Intel hardware quirks
> > diff --git a/src/intel/genxml/gen11.xml b/src/intel/genxml/gen11.xml
> > index 1579345f69f..c1774501f4c 100644
> > --- a/src/intel/genxml/gen11.xml
> > +++ b/src/intel/genxml/gen11.xml
> > @@ -6818,30 +6818,28 @@
> >
> >
> >
> > -
> > +
> >   > end="1" type="bool"/>
> > - > end="2" type="bool"/>
> > +
> >  
> > - > type="bool"/>
> > - > type="uint">
> > -  
> > -  
> > -  
> > -
> > + > type="bool&quo

Re: [Mesa-dev] [PATCH] iris/ehl: disable repacking for compression for compatibilty

[Anuj Phogat]

On Tue, Jun 4, 2019 at 9:20 AM Dongwon Kim  wrote:
>
> Repacking components in certain pixel formats before compression
> shouldn't be done for EHL to keep the compatibility with decompression
> capability in its display controller.
>
> Signed-off-by: Dongwon Kim 
> ---
>  src/gallium/drivers/iris/iris_state.c | 10 +
>  src/intel/dev/gen_device_info.c   |  4 
>  src/intel/dev/gen_device_info.h   |  1 +
>  src/intel/genxml/gen11.xml| 30 +--
>  4 files changed, 29 insertions(+), 16 deletions(-)
>
> diff --git a/src/gallium/drivers/iris/iris_state.c 
> b/src/gallium/drivers/iris/iris_state.c
> index fb72c4b5b7d..cc9e1148418 100644
> --- a/src/gallium/drivers/iris/iris_state.c
> +++ b/src/gallium/drivers/iris/iris_state.c
> @@ -749,6 +749,16 @@ iris_init_render_context(struct iris_screen *screen,
>}
>iris_emit_lri(batch, SLICE_COMMON_ECO_CHICKEN1, reg_val);
>
> +  /* needed to disable replacking to keep the compatibility with
Hardware specification recommends disabling repacking 
> +   * decompressing mechanism in display controller.
decompression ...
> +   */
> +  if (devinfo->need_disable_ccs_repack) {
> + iris_pack_state(GENX(CACHE_MODE_0), _val, reg) {
> +reg.DisableRepackingforCompression = true;
> +reg.DisableRepackingforCompressionMask = true;
> + }
> + iris_emit_lri(batch, CACHE_MODE_0, reg_val);
> +  }
>
>// XXX: 3D_MODE?
>  #endif
> diff --git a/src/intel/dev/gen_device_info.c b/src/intel/dev/gen_device_info.c
> index fec6159fd37..ee3ad7ba085 100644
> --- a/src/intel/dev/gen_device_info.c
> +++ b/src/intel/dev/gen_device_info.c
> @@ -64,6 +64,7 @@ gen_device_name_to_pci_device_id(const char *name)
>{ "cml", 0x9b41 },
>{ "cnl", 0x5a52 },
>{ "icl", 0x8a52 },
> +  { "ehl", 0x4500 },
> };
>
> for (unsigned i = 0; i < ARRAY_SIZE(name_map); i++) {
> @@ -958,6 +959,7 @@ static const struct gen_device_info 
> gen_device_info_ehl_4x8 = {
>   [MESA_SHADER_GEOMETRY]  = 1032,
>},
> },
> +   .need_disable_ccs_repack = 1,
> .simulator_id = 28,
>  };
>
> @@ -978,6 +980,7 @@ static const struct gen_device_info 
> gen_device_info_ehl_4x4 = {
>   [MESA_SHADER_GEOMETRY]  = 1032,
>},
> },
> +   .need_disable_ccs_repack = 1,
> .num_eu_per_subslice = 4,
> .simulator_id = 28,
>  };
> @@ -999,6 +1002,7 @@ static const struct gen_device_info 
> gen_device_info_ehl_2x4 = {
>   [MESA_SHADER_GEOMETRY]  = 1032,
>},
> },
> +   .need_disable_ccs_repack = 1,
> .num_eu_per_subslice =4,
> .simulator_id = 28,
>  };
> diff --git a/src/intel/dev/gen_device_info.h b/src/intel/dev/gen_device_info.h
> index af13615be2b..e90d31935f1 100644
> --- a/src/intel/dev/gen_device_info.h
> +++ b/src/intel/dev/gen_device_info.h
> @@ -74,6 +74,7 @@ struct gen_device_info
> bool has_surface_tile_offset;
> bool supports_simd16_3src;
> bool has_resource_streamer;
> +   bool need_disable_ccs_repack;
How about disable_ccs_repack ?
>
> /**
>  * \name Intel hardware quirks
> diff --git a/src/intel/genxml/gen11.xml b/src/intel/genxml/gen11.xml
> index 1579345f69f..c1774501f4c 100644
> --- a/src/intel/genxml/gen11.xml
> +++ b/src/intel/genxml/gen11.xml
> @@ -6818,30 +6818,28 @@
>
>
>
> -
> +
>   end="1" type="bool"/>
> - end="2" type="bool"/>
> +
>  
> -
> - type="uint">
> -  
> -  
> -  
> -
> + type="bool"/>
> + type="bool"/>
> + end="8" type="bool"/>
>   type="bool"/>
> - type="bool"/>
> +
>   start="12" end="14" type="uint"/>
> -
> - type="bool"/>
> + type="bool"/>
> +
>   end="17" type="bool"/>
> - start="18" end="18" type="bool"/>
> + type="bool"/>
>  
> - type="bool"/>
> - type="uint"/>
> + type="bool"/>
> + end="22" type="bool"/>
> + start="24" end="24" type="bool"/>
>   type="bool"/>
> - end="27" type="bool"/>
> +
>   start="28" end="30" type="uint"/>
> -
> + type="bool"/>
>
I would recommend to pull out all above changes where you're
fixing  fields of CACHE_MODE_0 in a separate patch.
>
>
> --
> 2.17.1
>
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Re: [Mesa-dev] [PATCH] intel/compiler/icl: Use tcs barrier id bits 24:30 instead of 24:27

[Anuj Phogat]

Topi, Are you also planning to send out a similar patch for Iris ?

Thanks
Anuj

On Mon, Apr 8, 2019 at 4:20 PM Anuj Phogat  wrote:
>
> On Wed, Mar 27, 2019 at 9:47 AM Topi Pohjolainen
>  wrote:
> >
> > Similarly to 1cc17fb731466c68586915acbb916586457b19bc
> >
> > Fixes gpu hangs with dEQP-VK.tessellation.shader_input_output.barrier
> >
> > CC: Anuj Phogat 
> > CC: Clayton Craft 
> > Signed-off-by: Topi Pohjolainen 
> > ---
> >  src/intel/compiler/brw_fs_nir.cpp | 21 +++--
> >  1 file changed, 15 insertions(+), 6 deletions(-)
> >
> > diff --git a/src/intel/compiler/brw_fs_nir.cpp 
> > b/src/intel/compiler/brw_fs_nir.cpp
> > index 747529e72d8..ee8274de65a 100644
> > --- a/src/intel/compiler/brw_fs_nir.cpp
> > +++ b/src/intel/compiler/brw_fs_nir.cpp
> > @@ -2458,15 +2458,24 @@ fs_visitor::nir_emit_tcs_intrinsic(const fs_builder 
> > ,
> >bld.exec_all().MOV(m0, brw_imm_ud(0u));
> >
> >/* Copy "Barrier ID" from r0.2, bits 16:13 */
> > -  chanbld.AND(m0_2, retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD),
> > -  brw_imm_ud(INTEL_MASK(16, 13)));
> > +  if (devinfo->gen < 11) {
> > + chanbld.AND(m0_2, retype(brw_vec1_grf(0, 2), 
> > BRW_REGISTER_TYPE_UD),
> > + brw_imm_ud(INTEL_MASK(16, 13)));
> >
> > -  /* Shift it up to bits 27:24. */
> > -  chanbld.SHL(m0_2, m0_2, brw_imm_ud(11));
> > + /* Shift it up to bits 27:24. */
> > + chanbld.SHL(m0_2, m0_2, brw_imm_ud(11));
> > +  } else {
> > + chanbld.AND(m0_2, retype(brw_vec1_grf(0, 2), 
> > BRW_REGISTER_TYPE_UD),
> > + brw_imm_ud(INTEL_MASK(30, 24)));
> > +  }
> >
> >/* Set the Barrier Count and the enable bit */
> > -  chanbld.OR(m0_2, m0_2,
> > - brw_imm_ud(tcs_prog_data->instances << 9 | (1 << 15)));
> > +  if (devinfo->gen < 11)
> > + chanbld.OR(m0_2, m0_2,
> > +brw_imm_ud(tcs_prog_data->instances << 9 | (1 << 15)));
> > +  else
> > + chanbld.OR(m0_2, m0_2,
> > +brw_imm_ud(tcs_prog_data->instances << 8 | (1 << 15)));
> >
> >bld.emit(SHADER_OPCODE_BARRIER, bld.null_reg_ud(), m0);
> >break;
> > --
> > 2.13.6
> >
>
> Fixes the gpu hang.
> Reviewed-by: Anuj Phogat 
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Re: [Mesa-dev] [PATCH] intel/compiler/icl: Use tcs barrier id bits 24:30 instead of 24:27

[Anuj Phogat]

On Wed, Mar 27, 2019 at 9:47 AM Topi Pohjolainen
 wrote:
>
> Similarly to 1cc17fb731466c68586915acbb916586457b19bc
>
> Fixes gpu hangs with dEQP-VK.tessellation.shader_input_output.barrier
>
> CC: Anuj Phogat 
> CC: Clayton Craft 
> Signed-off-by: Topi Pohjolainen 
> ---
>  src/intel/compiler/brw_fs_nir.cpp | 21 +++--
>  1 file changed, 15 insertions(+), 6 deletions(-)
>
> diff --git a/src/intel/compiler/brw_fs_nir.cpp 
> b/src/intel/compiler/brw_fs_nir.cpp
> index 747529e72d8..ee8274de65a 100644
> --- a/src/intel/compiler/brw_fs_nir.cpp
> +++ b/src/intel/compiler/brw_fs_nir.cpp
> @@ -2458,15 +2458,24 @@ fs_visitor::nir_emit_tcs_intrinsic(const fs_builder 
> ,
>bld.exec_all().MOV(m0, brw_imm_ud(0u));
>
>/* Copy "Barrier ID" from r0.2, bits 16:13 */
> -  chanbld.AND(m0_2, retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD),
> -  brw_imm_ud(INTEL_MASK(16, 13)));
> +  if (devinfo->gen < 11) {
> + chanbld.AND(m0_2, retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD),
> + brw_imm_ud(INTEL_MASK(16, 13)));
>
> -  /* Shift it up to bits 27:24. */
> -  chanbld.SHL(m0_2, m0_2, brw_imm_ud(11));
> + /* Shift it up to bits 27:24. */
> + chanbld.SHL(m0_2, m0_2, brw_imm_ud(11));
> +  } else {
> + chanbld.AND(m0_2, retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD),
> + brw_imm_ud(INTEL_MASK(30, 24)));
> +  }
>
>/* Set the Barrier Count and the enable bit */
> -  chanbld.OR(m0_2, m0_2,
> - brw_imm_ud(tcs_prog_data->instances << 9 | (1 << 15)));
> +  if (devinfo->gen < 11)
> + chanbld.OR(m0_2, m0_2,
> +brw_imm_ud(tcs_prog_data->instances << 9 | (1 << 15)));
> +  else
> + chanbld.OR(m0_2, m0_2,
> +    brw_imm_ud(tcs_prog_data->instances << 8 | (1 << 15)));
>
>bld.emit(SHADER_OPCODE_BARRIER, bld.null_reg_ud(), m0);
>break;
> --
> 2.13.6
>

Fixes the gpu hang.
Reviewed-by: Anuj Phogat 
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Re: [Mesa-dev] [PATCH] intel/disasm: Disassemble JIP offset for while

[Anuj Phogat]

On Wed, Mar 27, 2019 at 5:12 PM Sagar Ghuge  wrote:
>
> Signed-off-by: Sagar Ghuge 
> ---
>  src/intel/compiler/brw_disasm.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/src/intel/compiler/brw_disasm.c b/src/intel/compiler/brw_disasm.c
> index efca3e2ce7d..440e51faa61 100644
> --- a/src/intel/compiler/brw_disasm.c
> +++ b/src/intel/compiler/brw_disasm.c
> @@ -1661,7 +1661,8 @@ brw_disassemble_inst(FILE *file, const struct 
> gen_device_info *devinfo,
>format(file, "Pop: %"PRIu64, brw_inst_gen4_pop_count(devinfo, inst));
> } else if (devinfo->gen < 6 && (opcode == BRW_OPCODE_IF ||
> opcode == BRW_OPCODE_IFF ||
> -   opcode == BRW_OPCODE_HALT)) {
> +   opcode == BRW_OPCODE_HALT ||
> +   opcode == BRW_OPCODE_WHILE)) {
>pad(file, 16);
>format(file, "Jump: %d", brw_inst_gen4_jump_count(devinfo, inst));
> } else if (devinfo->gen < 6 && opcode == BRW_OPCODE_ENDIF) {
> --
> 2.20.1
>
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looks fine to me.
Reviewed-by: Anuj Phogat 
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Re: [Mesa-dev] [PATCH] intel/compiler: Set flag reg/subreg number properly

[Anuj Phogat]

On Wed, Mar 27, 2019 at 4:05 PM Sagar Ghuge  wrote:
>
> If predicate control is set to None, then in that case we can simply set
> flag reg/subreg number to zero. This allows round-tripping through the
> assembler/disassembler
>
> Signed-off-by: Sagar Ghuge 
> ---
>  src/intel/compiler/brw_eu_emit.c| 7 +++
>  src/intel/compiler/brw_fs_generator.cpp | 1 +
>  2 files changed, 8 insertions(+)
>
> diff --git a/src/intel/compiler/brw_eu_emit.c 
> b/src/intel/compiler/brw_eu_emit.c
> index 94e247e1a39..f59543db8df 100644
> --- a/src/intel/compiler/brw_eu_emit.c
> +++ b/src/intel/compiler/brw_eu_emit.c
> @@ -2267,6 +2267,13 @@ brw_fb_WRITE(struct brw_codegen *p,
> brw_inst_set_sfid(devinfo, insn, target_cache);
> brw_inst_set_compression(devinfo, insn, false);
>
> +   if (brw_inst_pred_control(devinfo, insn) == BRW_PREDICATE_NONE) {
> +  brw_inst_set_flag_subreg_nr(devinfo, insn, 0);
> +  if (devinfo->gen >= 7) {
> + brw_inst_set_flag_reg_nr(devinfo, insn, 0);
> +  }
> +   }
> +
> if (devinfo->gen >= 6) {
>/* headerless version, just submit color payload */
>src0 = payload;
> diff --git a/src/intel/compiler/brw_fs_generator.cpp 
> b/src/intel/compiler/brw_fs_generator.cpp
> index c24d4eb7cab..242450c605e 100644
> --- a/src/intel/compiler/brw_fs_generator.cpp
> +++ b/src/intel/compiler/brw_fs_generator.cpp
> @@ -307,6 +307,7 @@ fs_generator::fire_fb_write(fs_inst *inst,
>brw_set_default_mask_control(p, BRW_MASK_DISABLE);
>brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
>brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
> +  brw_set_default_flag_reg(p, 0, 0);
>brw_MOV(p, offset(retype(payload, BRW_REGISTER_TYPE_UD), 1),
>offset(retype(implied_header, BRW_REGISTER_TYPE_UD), 1));
>brw_pop_insn_state(p);
> --
> 2.20.1
>
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Change looks correct and harmless.
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Re: [Mesa-dev] [PATCH 1/5] intel/fs: Exclude control sources from execution type and region alignment calculations.

[Anuj Phogat]

Fixes all subgroup test failures in vulkancts on Icelake.
Series is:
Tested-by: Anuj Phogat 
On Fri, Jan 18, 2019 at 4:09 PM Francisco Jerez  wrote:
>
> Currently the execution type calculation will return a bogus value in
> cases like:
>
>   mov_indirect(8) vgrf0:w, vgrf1:w, vgrf2:ud, 32u
>
> Which will be considered to have a 32-bit integer execution type even
> though the actual indirect move operation will be carried out with
> 16-bit precision.
>
> Similarly there's no need to apply the CHV/BXT double-precision region
> alignment restrictions to such control sources, since they aren't
> directly involved in the double-precision arithmetic operations
> emitted by these virtual instructions.  Applying the CHV/BXT
> restrictions to control sources was expected to be harmless if mildly
> inefficient, but unfortunately it exposed problems at codegen level
> for virtual instructions (namely the SHUFFLE instruction used for the
> Vulkan 1.1 subgroup feature) that weren't prepared to accept control
> sources with an arbitrary strided region.
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109328
> Reported-by: Mark Janes 
> Fixes: efa4e4bc5fc "intel/fs: Introduce regioning lowering pass."
> ---
>  src/intel/compiler/brw_fs.cpp | 54 +++
>  src/intel/compiler/brw_fs_lower_regioning.cpp |  6 +--
>  src/intel/compiler/brw_ir_fs.h| 10 +++-
>  3 files changed, 66 insertions(+), 4 deletions(-)
>
> diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp
> index 0359eb079f7..f475b617df2 100644
> --- a/src/intel/compiler/brw_fs.cpp
> +++ b/src/intel/compiler/brw_fs.cpp
> @@ -271,6 +271,60 @@ fs_inst::is_send_from_grf() const
> }
>  }
>
> +bool
> +fs_inst::is_control_source(unsigned arg) const
> +{
> +   switch (opcode) {
> +   case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
> +   case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
> +   case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4:
> +   case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7:
FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7 is now removed from
master. This series need a rebase.
> +  return arg == 0;
> +
> +   case SHADER_OPCODE_BROADCAST:
> +   case SHADER_OPCODE_SHUFFLE:
> +   case SHADER_OPCODE_QUAD_SWIZZLE:
> +   case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
> +   case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
> +   case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
> +   case SHADER_OPCODE_IMAGE_SIZE:
> +   case SHADER_OPCODE_GET_BUFFER_SIZE:
> +  return arg == 1;
> +
> +   case SHADER_OPCODE_MOV_INDIRECT:
> +   case SHADER_OPCODE_CLUSTER_BROADCAST:
> +   case SHADER_OPCODE_TEX:
> +   case FS_OPCODE_TXB:
> +   case SHADER_OPCODE_TXD:
> +   case SHADER_OPCODE_TXF:
> +   case SHADER_OPCODE_TXF_LZ:
> +   case SHADER_OPCODE_TXF_CMS:
> +   case SHADER_OPCODE_TXF_CMS_W:
> +   case SHADER_OPCODE_TXF_UMS:
> +   case SHADER_OPCODE_TXF_MCS:
> +   case SHADER_OPCODE_TXL:
> +   case SHADER_OPCODE_TXL_LZ:
> +   case SHADER_OPCODE_TXS:
> +   case SHADER_OPCODE_LOD:
> +   case SHADER_OPCODE_TG4:
> +   case SHADER_OPCODE_TG4_OFFSET:
> +   case SHADER_OPCODE_SAMPLEINFO:
> +   case SHADER_OPCODE_UNTYPED_ATOMIC:
> +   case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT:
> +   case SHADER_OPCODE_UNTYPED_SURFACE_READ:
> +   case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
> +   case SHADER_OPCODE_BYTE_SCATTERED_READ:
> +   case SHADER_OPCODE_BYTE_SCATTERED_WRITE:
> +   case SHADER_OPCODE_TYPED_ATOMIC:
> +   case SHADER_OPCODE_TYPED_SURFACE_READ:
> +   case SHADER_OPCODE_TYPED_SURFACE_WRITE:
> +  return arg == 1 || arg == 2;
> +
> +   default:
> +  return false;
> +   }
> +}
> +
>  /**
>   * Returns true if this instruction's sources and destinations cannot
>   * safely be the same register.
> diff --git a/src/intel/compiler/brw_fs_lower_regioning.cpp 
> b/src/intel/compiler/brw_fs_lower_regioning.cpp
> index df50993dee6..6a3c23892b4 100644
> --- a/src/intel/compiler/brw_fs_lower_regioning.cpp
> +++ b/src/intel/compiler/brw_fs_lower_regioning.cpp
> @@ -74,7 +74,7 @@ namespace {
>   unsigned stride = inst->dst.stride * type_sz(inst->dst.type);
>
>   for (unsigned i = 0; i < inst->sources; i++) {
> -if (!is_uniform(inst->src[i]))
> +if (!is_uniform(inst->src[i]) && !inst->is_control_source(i))
> stride = MAX2(stride, inst->src[i].stride *
>   type_sz(inst->src[i].type));
>   }
> @@ -92,7 +92,7 @@ namespace {
> required_dst_byte_offset(const fs_inst *inst)
> {
>for (unsigned i = 0; i < inst->sources; i++) {
> - if (!is_unif

Re: [Mesa-dev] [PATCH] intel/eu: Stop overriding exec sizes in send_indirect_message

[Anuj Phogat]

On Sat, Jan 12, 2019 at 7:56 PM Jason Ekstrand  wrote:
>
> For a long time, we based exec sizes on destination register widths.
> We've not been doing that since 1ca3a9442760b6f7 but a few remnants
> accidentally remained.
> ---
>  src/intel/compiler/brw_eu_emit.c | 3 ---
>  1 file changed, 3 deletions(-)
>
> diff --git a/src/intel/compiler/brw_eu_emit.c 
> b/src/intel/compiler/brw_eu_emit.c
> index 45e2552783b..0b4cd4dc213 100644
> --- a/src/intel/compiler/brw_eu_emit.c
> +++ b/src/intel/compiler/brw_eu_emit.c
> @@ -2473,9 +2473,6 @@ brw_send_indirect_message(struct brw_codegen *p,
>brw_set_src1(p, send, addr);
> }
>
> -   if (dst.width < BRW_EXECUTE_8)
> -  brw_inst_set_exec_size(devinfo, send, dst.width);
> -
> brw_set_dest(p, send, dst);
> brw_set_src0(p, send, retype(payload, BRW_REGISTER_TYPE_UD));
>     brw_inst_set_sfid(devinfo, send, sfid);
> --
Reviewed-by: Anuj Phogat 

> 2.20.1
>
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Re: [Mesa-dev] [PATCH] i965: Don't override subslice count to 4 on Gen11.

[Anuj Phogat]

On Fri, Dec 14, 2018 at 3:59 PM Kenneth Graunke  wrote:
>
> Gen9-10 have fewer than 4 subslices per slice, so they need this to be
> rounded up.  Gen11 isn't documented as needing this hack, and it can
> also have more than 4 subslices, so the hack actually can break things.
> ---
>  src/mesa/drivers/dri/i965/brw_program.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> I have not tested this patch.  I made the equivalent change to iris and
> it fixed some geometry shader tests that were spilling (but don't spill
> on i965 - that's a compiler quality regression I have yet to fix)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_program.c 
> b/src/mesa/drivers/dri/i965/brw_program.c
> index 96247f32f0f..730d6dc0d5a 100644
> --- a/src/mesa/drivers/dri/i965/brw_program.c
> +++ b/src/mesa/drivers/dri/i965/brw_program.c
> @@ -407,7 +407,7 @@ brw_alloc_stage_scratch(struct brw_context *brw,
> * and we wish to view that there are 4 subslices per slice
> * instead of the actual number of subslices per slice.
> */
> -  if (devinfo->gen >= 9)
> +  if (devinfo->gen >= 9 && devinfo->gen < 11)
>   subslices = 4 * brw->screen->devinfo.num_slices;
>
>unsigned scratch_ids_per_subslice;
> --
> 2.19.1
>

Reviewed-by: Anuj Phogat 
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Re: [Mesa-dev] [PATCH 2/5] i965/icl: Set use full ways in L3CNTLREG

[Anuj Phogat]

On Mon, Nov 26, 2018 at 11:47 AM Francisco Jerez  wrote:
>
> Anuj Phogat  writes:
>
> > L3 allocation table in h/w specification recommends using 4 KB
> > granularity for programming allocation fields in L3CNTLREG.
> >
> > Signed-off-by: Anuj Phogat 
> > Cc: Kenneth Graunke 
> > Cc: Francisco Jerez 
> > Cc: Lionel Landwerlin 
> > ---
> >  src/mesa/drivers/dri/i965/brw_defines.h   | 1 +
> >  src/mesa/drivers/dri/i965/gen7_l3_state.c | 1 +
> >  2 files changed, 2 insertions(+)
> >
> > diff --git a/src/mesa/drivers/dri/i965/brw_defines.h 
> > b/src/mesa/drivers/dri/i965/brw_defines.h
> > index 897c91aa31e..b8ada02d6eb 100644
> > --- a/src/mesa/drivers/dri/i965/brw_defines.h
> > +++ b/src/mesa/drivers/dri/i965/brw_defines.h
> > @@ -1647,6 +1647,7 @@ enum brw_pixel_shader_coverage_mask_mode {
> >  # define GEN8_L3CNTLREG_ALL_ALLOC_SHIFT25
> >  # define GEN8_L3CNTLREG_ALL_ALLOC_MASK INTEL_MASK(31, 25)
> >  # define GEN8_L3CNTLREG_EDBC_NO_HANG   (1 << 9)
> > +# define GEN8_L3CNTLREG_USE_FULL_WAYS  (1 << 10)
> >
>
> This bit only exists in Gen11, you should probably prefix the define
> with GEN11 instead.  With that fixed:
Fixed locally. Thanks.
>
> Reviewed-by: Francisco Jerez 
>
> >  #define GEN10_CACHE_MODE_SS0x0e420
> >  #define GEN10_FLOAT_BLEND_OPTIMIZATION_ENABLE (1 << 4)
> > diff --git a/src/mesa/drivers/dri/i965/gen7_l3_state.c 
> > b/src/mesa/drivers/dri/i965/gen7_l3_state.c
> > index 8c6c4c47481..fb9b2703a50 100644
> > --- a/src/mesa/drivers/dri/i965/gen7_l3_state.c
> > +++ b/src/mesa/drivers/dri/i965/gen7_l3_state.c
> > @@ -119,6 +119,7 @@ setup_l3_config(struct brw_context *brw, const struct 
> > gen_l3_config *cfg)
> >assert(!cfg->n[GEN_L3P_IS] && !cfg->n[GEN_L3P_C] && 
> > !cfg->n[GEN_L3P_T]);
> >
> >const unsigned imm_data = ((has_slm ? GEN8_L3CNTLREG_SLM_ENABLE : 0) 
> > |
> > + (devinfo->gen == 11 ? GEN8_L3CNTLREG_USE_FULL_WAYS : 0) |
> >   SET_FIELD(cfg->n[GEN_L3P_URB], GEN8_L3CNTLREG_URB_ALLOC) |
> >   SET_FIELD(cfg->n[GEN_L3P_RO], GEN8_L3CNTLREG_RO_ALLOC) |
> >   SET_FIELD(cfg->n[GEN_L3P_DC], GEN8_L3CNTLREG_DC_ALLOC) |
> > --
> > 2.17.1
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[Mesa-dev] [PATCH V2 1/4] i965/icl: Fix L3 configurations

[Anuj Phogat]

Use L3 configuration specified in h/w specification.

V2: Drop configs which do under allocation of l3 cache.
Bump up the comment above table.

Signed-off-by: Anuj Phogat 
Cc: Kenneth Graunke 
Cc: Francisco Jerez 
---
 src/intel/common/gen_l3_config.c | 12 ++--
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/src/intel/common/gen_l3_config.c b/src/intel/common/gen_l3_config.c
index b977c6ab136..32264394fb6 100644
--- a/src/intel/common/gen_l3_config.c
+++ b/src/intel/common/gen_l3_config.c
@@ -134,15 +134,15 @@ static const struct gen_l3_config cnl_l3_configs[] = {
 
 /**
  * ICL validated L3 configurations.  \sa icl_l3_configs.
+ * Zeroth entry in below table has been commented out intentionally
+ * due to known issues with this configuration. Many other entries
+ * suggested by h/w specification aren't added here because they
+ * do under allocation of L3 cache with below partitioning.
  */
 static const struct gen_l3_config icl_l3_configs[] = {
/* SLM URB ALL DC  RO  IS   C   T */
-   {{  0, 64, 64,  0,  0,  0,  0,  0 }},
-   {{  0, 64,  0, 16, 48,  0,  0,  0 }},
-   {{  0, 48,  0, 16, 64,  0,  0,  0 }},
-   {{  0, 32,  0,  0, 96,  0,  0,  0 }},
-   {{  0, 32, 96,  0,  0,  0,  0,  0 }},
-   {{  0, 32,  0, 16, 80,  0,  0,  0 }},
+   /*{{  0, 16, 80,  0,  0,  0,  0,  0 }},*/
+   {{  0, 32, 64,  0,  0,  0,  0,  0 }},
{{  0 }}
 };
 
-- 
2.17.1

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Re: [Mesa-dev] [PATCH 4/5] i965/icl: Set config#9 as default config

[Anuj Phogat]

Dropping this patch.
On Tue, Nov 13, 2018 at 2:34 PM Anuj Phogat  wrote:
>
> Config#6 recommended by h/w specification causes multiple piglit
> regressions. Use config#9 instead which works well. Setting a weight
> here so that we get the desired config.
>
> Signed-off-by: Anuj Phogat 
> Cc: Kenneth Graunke 
> Cc: Francisco Jerez 
> Cc: Lionel Landwerlin 
> ---
>  src/intel/common/gen_l3_config.c | 13 ++---
>  1 file changed, 10 insertions(+), 3 deletions(-)
>
> diff --git a/src/intel/common/gen_l3_config.c 
> b/src/intel/common/gen_l3_config.c
> index de16ad23017..52c1cdd32f4 100644
> --- a/src/intel/common/gen_l3_config.c
> +++ b/src/intel/common/gen_l3_config.c
> @@ -257,7 +257,13 @@ gen_get_default_l3_weights(const struct gen_device_info 
> *devinfo,
> w.w[GEN_L3P_SLM] = devinfo->gen < 11 && needs_slm;
> w.w[GEN_L3P_URB] = 1.0;
>
> -   if (devinfo->gen >= 8) {
> +   if (devinfo->gen == 11) {
> +  /* Config#6 recommended by h/w specification causes multiple piglit
> +   * regressions. Use config#9 instead which works well. Setting a weight
> +   * here so that we get the desired config.
> +  */
> +  w.w[GEN_L3P_ALL] = 2.0;
> +   } else if (devinfo->gen >= 8) {
>w.w[GEN_L3P_ALL] = 1.0;
> } else {
>w.w[GEN_L3P_DC] = needs_dc ? 0.1 : 0;
> @@ -277,8 +283,9 @@ gen_get_default_l3_config(const struct gen_device_info 
> *devinfo)
>  * default configuration.
>  */
> const struct gen_l3_config *const cfg = get_l3_configs(devinfo);
> -   assert(cfg == gen_get_l3_config(devinfo,
> -gen_get_default_l3_weights(devinfo, false, false)));
> +   assert(devinfo->gen == 11 ||
> +  cfg == gen_get_l3_config(devinfo,
> +  gen_get_default_l3_weights(devinfo, false, false)));
> return cfg;
>  }
>
> --
> 2.17.1
>
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Re: [Mesa-dev] [PATCH 1/5] i965/icl: Fix L3 configurations

[Anuj Phogat]

On Fri, Nov 16, 2018 at 2:52 PM Francisco Jerez  wrote:
>
> Anuj Phogat  writes:
>
> > On Fri, Nov 16, 2018 at 6:21 AM Eero Tamminen  
> > wrote:
> >>
> >> Hi,
> >>
> >> On 16.11.2018 10.33, Francisco Jerez wrote:
> >> > Kenneth Graunke  writes:
> >> [...]
> >> >> Perhaps we'll get both configs working, and then will want to be able
> >> >> to select between them.  I question whether the additional URB is truly
> >> >> that valuable - how large are the actual gains? - considering that we
> >> >> have to stall in order to reconfigure everything anyway...
> >>
> >> It's more about value of additional space for caching textures.
> >>
> >> One can calculate required max URB space when GS/TS isn't used, whereas
> >> textures can fill all available cache.  For example, if draw does just a
> >> single quad, L3 is better utilized with minimal URB space and leaving
> >> rest for texture caching.
> >>
> > Right. URB (16) and ALL (80) config is the one with minimum URB allocation.
> > But, it's not working probably because of a hardware bug. Inferring from 
> > above
> > comments by ken and Eero, If we ever get it working, we should always be 
> > using
> > just that one config and that's the config which h/w documentation 
> > recommends
> > as well. Correct me if that's not what you meant.
>
> I don't think anybody said that.  There is a use-case for the 32/64
> configuration even after we get thee other configuration working, that's
> why the hardware even gives you the choice.
>
> > In that case, I would prefer to bypass all this code and do it in
> > brw_upload_initial_gpu_state().
> >
>
> There is no real benefit from that.  It would be more complexity than
> using the exact same codepath for all platforms.  It won't improve
> runtime performance measurably.  And it will close the door to several
> performance optimizations which are still valuable on ICL.
>
ok. I don't see an agreement on the changes proposed by Ken. So, I propose
to go ahead with current way of uploading l3 config on ICL and make further
changes on top of it when we have more information. I think programming the
right config is more important atm.

> >>
> >> > That just means that the update frequency needs to be low enough for the
> >> > stall overhead to be negligible -- E.g. at batch buffer boundaries or
> >> > wherever we're getting stalled anyway.
> >>
> >>
> >> - Eero
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Re: [Mesa-dev] [PATCH 1/5] i965/icl: Fix L3 configurations

[Anuj Phogat]

On Fri, Nov 16, 2018 at 6:21 AM Eero Tamminen  wrote:
>
> Hi,
>
> On 16.11.2018 10.33, Francisco Jerez wrote:
> > Kenneth Graunke  writes:
> [...]
> >> Perhaps we'll get both configs working, and then will want to be able
> >> to select between them.  I question whether the additional URB is truly
> >> that valuable - how large are the actual gains? - considering that we
> >> have to stall in order to reconfigure everything anyway...
>
> It's more about value of additional space for caching textures.
>
> One can calculate required max URB space when GS/TS isn't used, whereas
> textures can fill all available cache.  For example, if draw does just a
> single quad, L3 is better utilized with minimal URB space and leaving
> rest for texture caching.
>
Right. URB (16) and ALL (80) config is the one with minimum URB allocation.
But, it's not working probably because of a hardware bug. Inferring from above
comments by ken and Eero, If we ever get it working, we should always be using
just that one config and that's the config which h/w documentation recommends
as well. Correct me if that's not what you meant. In that case, I
would prefer to
bypass all this code and do it in brw_upload_initial_gpu_state().

>
> > That just means that the update frequency needs to be low enough for the
> > stall overhead to be negligible -- E.g. at batch buffer boundaries or
> > wherever we're getting stalled anyway.
>
>
> - Eero
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Re: [Mesa-dev] [PATCH 1/5] i965/icl: Fix L3 configurations

[Anuj Phogat]

No problem Ken.

On Tue, Nov 13, 2018 at 9:48 PM Kenneth Graunke 
wrote:

> On Tuesday, November 13, 2018 2:33:58 PM PST Anuj Phogat wrote:
> > Use L3 configuration table specified in h/w specification.
> >
> > Signed-off-by: Anuj Phogat 
> > Cc: Kenneth Graunke 
> > Cc: Francisco Jerez 
> > Cc: Lionel Landwerlin 
> > ---
> >  src/intel/common/gen_l3_config.c | 16 ++--
> >  1 file changed, 10 insertions(+), 6 deletions(-)
> >
> > diff --git a/src/intel/common/gen_l3_config.c
> b/src/intel/common/gen_l3_config.c
> > index b977c6ab136..079608198bc 100644
> > --- a/src/intel/common/gen_l3_config.c
> > +++ b/src/intel/common/gen_l3_config.c
> > @@ -137,12 +137,16 @@ static const struct gen_l3_config cnl_l3_configs[]
> = {
> >   */
> >  static const struct gen_l3_config icl_l3_configs[] = {
> > /* SLM URB ALL DC  RO  IS   C   T */
> > -   {{  0, 64, 64,  0,  0,  0,  0,  0 }},
> > -   {{  0, 64,  0, 16, 48,  0,  0,  0 }},
> > -   {{  0, 48,  0, 16, 64,  0,  0,  0 }},
> > -   {{  0, 32,  0,  0, 96,  0,  0,  0 }},
> > -   {{  0, 32, 96,  0,  0,  0,  0,  0 }},
> > -   {{  0, 32,  0, 16, 80,  0,  0,  0 }},
> > +   {{  0, 32, 32,  0,  0,  0,  0,  0 }},
> > +   {{  0, 32, 28,  0,  0,  0,  0,  0 }},
> > +   {{  0, 24,  0,  8, 28,  0,  0,  0 }},
> > +   {{  0, 16,  0,  0, 44,  0,  0,  0 }},
> > +   {{  0, 16, 12,  0,  0,  0,  0,  0 }},
> > +   {{  0, 16,  0,  0, 12,  0,  0,  0 }},
> > +   {{  0, 16, 80,  0,  0,  0,  0,  0 }},
> > +   {{  0, 16, 48,  0,  0,  0,  0,  0 }},
> > +   {{  0, 16, 44,  0,  0,  0,  0,  0 }},
> > +   {{  0, 32, 64,  0,  0,  0,  0,  0 }},
> > {{  0 }}
> >  };
> >
> >
>
> I'd like to review these, but I may not be able to until late this week
> or early next week.  Thanks!
>
> --Ken
>
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[Mesa-dev] [PATCH 1/5] i965/icl: Fix L3 configurations

[Anuj Phogat]

Use L3 configuration table specified in h/w specification.

Signed-off-by: Anuj Phogat 
Cc: Kenneth Graunke 
Cc: Francisco Jerez 
Cc: Lionel Landwerlin 
---
 src/intel/common/gen_l3_config.c | 16 ++--
 1 file changed, 10 insertions(+), 6 deletions(-)

diff --git a/src/intel/common/gen_l3_config.c b/src/intel/common/gen_l3_config.c
index b977c6ab136..079608198bc 100644
--- a/src/intel/common/gen_l3_config.c
+++ b/src/intel/common/gen_l3_config.c
@@ -137,12 +137,16 @@ static const struct gen_l3_config cnl_l3_configs[] = {
  */
 static const struct gen_l3_config icl_l3_configs[] = {
/* SLM URB ALL DC  RO  IS   C   T */
-   {{  0, 64, 64,  0,  0,  0,  0,  0 }},
-   {{  0, 64,  0, 16, 48,  0,  0,  0 }},
-   {{  0, 48,  0, 16, 64,  0,  0,  0 }},
-   {{  0, 32,  0,  0, 96,  0,  0,  0 }},
-   {{  0, 32, 96,  0,  0,  0,  0,  0 }},
-   {{  0, 32,  0, 16, 80,  0,  0,  0 }},
+   {{  0, 32, 32,  0,  0,  0,  0,  0 }},
+   {{  0, 32, 28,  0,  0,  0,  0,  0 }},
+   {{  0, 24,  0,  8, 28,  0,  0,  0 }},
+   {{  0, 16,  0,  0, 44,  0,  0,  0 }},
+   {{  0, 16, 12,  0,  0,  0,  0,  0 }},
+   {{  0, 16,  0,  0, 12,  0,  0,  0 }},
+   {{  0, 16, 80,  0,  0,  0,  0,  0 }},
+   {{  0, 16, 48,  0,  0,  0,  0,  0 }},
+   {{  0, 16, 44,  0,  0,  0,  0,  0 }},
+   {{  0, 32, 64,  0,  0,  0,  0,  0 }},
{{  0 }}
 };
 
-- 
2.17.1

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[Mesa-dev] [PATCH 2/5] i965/icl: Set use full ways in L3CNTLREG

[Anuj Phogat]

L3 allocation table in h/w specification recommends using 4 KB
granularity for programming allocation fields in L3CNTLREG.

Signed-off-by: Anuj Phogat 
Cc: Kenneth Graunke 
Cc: Francisco Jerez 
Cc: Lionel Landwerlin 
---
 src/mesa/drivers/dri/i965/brw_defines.h   | 1 +
 src/mesa/drivers/dri/i965/gen7_l3_state.c | 1 +
 2 files changed, 2 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/brw_defines.h 
b/src/mesa/drivers/dri/i965/brw_defines.h
index 897c91aa31e..b8ada02d6eb 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -1647,6 +1647,7 @@ enum brw_pixel_shader_coverage_mask_mode {
 # define GEN8_L3CNTLREG_ALL_ALLOC_SHIFT25
 # define GEN8_L3CNTLREG_ALL_ALLOC_MASK INTEL_MASK(31, 25)
 # define GEN8_L3CNTLREG_EDBC_NO_HANG   (1 << 9)
+# define GEN8_L3CNTLREG_USE_FULL_WAYS  (1 << 10)
 
 #define GEN10_CACHE_MODE_SS0x0e420
 #define GEN10_FLOAT_BLEND_OPTIMIZATION_ENABLE (1 << 4)
diff --git a/src/mesa/drivers/dri/i965/gen7_l3_state.c 
b/src/mesa/drivers/dri/i965/gen7_l3_state.c
index 8c6c4c47481..fb9b2703a50 100644
--- a/src/mesa/drivers/dri/i965/gen7_l3_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_l3_state.c
@@ -119,6 +119,7 @@ setup_l3_config(struct brw_context *brw, const struct 
gen_l3_config *cfg)
   assert(!cfg->n[GEN_L3P_IS] && !cfg->n[GEN_L3P_C] && !cfg->n[GEN_L3P_T]);
 
   const unsigned imm_data = ((has_slm ? GEN8_L3CNTLREG_SLM_ENABLE : 0) |
+ (devinfo->gen == 11 ? GEN8_L3CNTLREG_USE_FULL_WAYS : 0) |
  SET_FIELD(cfg->n[GEN_L3P_URB], GEN8_L3CNTLREG_URB_ALLOC) |
  SET_FIELD(cfg->n[GEN_L3P_RO], GEN8_L3CNTLREG_RO_ALLOC) |
  SET_FIELD(cfg->n[GEN_L3P_DC], GEN8_L3CNTLREG_DC_ALLOC) |
-- 
2.17.1

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[Mesa-dev] [PATCH 3/5] intel/icl: Set way_size_per_bank to 4

[Anuj Phogat]

Signed-off-by: Anuj Phogat 
Cc: Kenneth Graunke 
Cc: Francisco Jerez 
Cc: Lionel Landwerlin 
---
 src/intel/common/gen_l3_config.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/intel/common/gen_l3_config.c b/src/intel/common/gen_l3_config.c
index 079608198bc..de16ad23017 100644
--- a/src/intel/common/gen_l3_config.c
+++ b/src/intel/common/gen_l3_config.c
@@ -313,7 +313,8 @@ static unsigned
 get_l3_way_size(const struct gen_device_info *devinfo)
 {
const unsigned way_size_per_bank =
-  devinfo->gen >= 9 && devinfo->l3_banks == 1 ? 4 : 2;
+  (devinfo->gen >= 9 && devinfo->l3_banks == 1) || devinfo->gen == 11 ?
+  4 : 2;
 
assert(devinfo->l3_banks);
return way_size_per_bank * devinfo->l3_banks;
-- 
2.17.1

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[Mesa-dev] [PATCH 5/5] anv/icl: Set use full ways in L3CNTLREG

[Anuj Phogat]

L3 allocation table in h/w specification recommends using 4 KB
granularity for programming allocation fields in L3CNTLREG.

Signed-off-by: Anuj Phogat 
Cc: Kenneth Graunke 
Cc: Francisco Jerez 
Cc: Lionel Landwerlin 
---
 src/intel/genxml/gen11.xml | 1 +
 src/intel/vulkan/genX_cmd_buffer.c | 1 +
 2 files changed, 2 insertions(+)

diff --git a/src/intel/genxml/gen11.xml b/src/intel/genxml/gen11.xml
index b975fe94776..1239ed011ed 100644
--- a/src/intel/genxml/gen11.xml
+++ b/src/intel/genxml/gen11.xml
@@ -3547,6 +3547,7 @@
 
 
 
+
 
 
 
diff --git a/src/intel/vulkan/genX_cmd_buffer.c 
b/src/intel/vulkan/genX_cmd_buffer.c
index ed88157170d..c7e5ef9596e 100644
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@ -1623,6 +1623,7 @@ genX(cmd_buffer_config_l3)(struct anv_cmd_buffer 
*cmd_buffer,
 * desirable behavior.
*/
.ErrorDetectionBehaviorControl = true,
+   .UseFullWays = true,
 #endif
.URBAllocation = cfg->n[GEN_L3P_URB],
.ROAllocation = cfg->n[GEN_L3P_RO],
-- 
2.17.1

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[Mesa-dev] [PATCH 4/5] i965/icl: Set config#9 as default config

[Anuj Phogat]

Config#6 recommended by h/w specification causes multiple piglit
regressions. Use config#9 instead which works well. Setting a weight
here so that we get the desired config.

Signed-off-by: Anuj Phogat 
Cc: Kenneth Graunke 
Cc: Francisco Jerez 
Cc: Lionel Landwerlin 
---
 src/intel/common/gen_l3_config.c | 13 ++---
 1 file changed, 10 insertions(+), 3 deletions(-)

diff --git a/src/intel/common/gen_l3_config.c b/src/intel/common/gen_l3_config.c
index de16ad23017..52c1cdd32f4 100644
--- a/src/intel/common/gen_l3_config.c
+++ b/src/intel/common/gen_l3_config.c
@@ -257,7 +257,13 @@ gen_get_default_l3_weights(const struct gen_device_info 
*devinfo,
w.w[GEN_L3P_SLM] = devinfo->gen < 11 && needs_slm;
w.w[GEN_L3P_URB] = 1.0;
 
-   if (devinfo->gen >= 8) {
+   if (devinfo->gen == 11) {
+  /* Config#6 recommended by h/w specification causes multiple piglit
+   * regressions. Use config#9 instead which works well. Setting a weight
+   * here so that we get the desired config.
+  */
+  w.w[GEN_L3P_ALL] = 2.0;
+   } else if (devinfo->gen >= 8) {
   w.w[GEN_L3P_ALL] = 1.0;
} else {
   w.w[GEN_L3P_DC] = needs_dc ? 0.1 : 0;
@@ -277,8 +283,9 @@ gen_get_default_l3_config(const struct gen_device_info 
*devinfo)
 * default configuration.
 */
const struct gen_l3_config *const cfg = get_l3_configs(devinfo);
-   assert(cfg == gen_get_l3_config(devinfo,
-gen_get_default_l3_weights(devinfo, false, false)));
+   assert(devinfo->gen == 11 ||
+  cfg == gen_get_l3_config(devinfo,
+  gen_get_default_l3_weights(devinfo, false, false)));
return cfg;
 }
 
-- 
2.17.1

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Re: [Mesa-dev] [PATCH] intel/l3: update ICL L3 configurations

[Anuj Phogat]

Lionel,

I have this patch along with few other patches in my 'icl-urb-configs'
branch
at https://github.com/aphogat/mesa. But, I'm getting many piglit regressions
with these patches. That's the reason I haven't sent them out to the list.
I also
talked to Ken about my changes. Unfortunately we have no lead on what's
causing these regressions atm.

Thanks
Anuj

On Thu, Nov 8, 2018 at 4:26 AM Lionel Landwerlin <
lionel.g.landwer...@intel.com> wrote:

> I forgot to Cc some people :)
>
> On 07/11/2018 13:31, Lionel Landwerlin wrote:
> > CNL configurations where given in increments of 2Kb, while ICL are
> > given in increments of 4Kb. We seem to have missed some updates in the
> > internal documentation.
> >
> > Signed-off-by: Lionel Landwerlin 
> > BSpec: 21166
> > ---
> >   src/intel/common/gen_l3_config.c | 16 ++--
> >   1 file changed, 10 insertions(+), 6 deletions(-)
> >
> > diff --git a/src/intel/common/gen_l3_config.c
> b/src/intel/common/gen_l3_config.c
> > index b977c6ab136..079608198bc 100644
> > --- a/src/intel/common/gen_l3_config.c
> > +++ b/src/intel/common/gen_l3_config.c
> > @@ -137,12 +137,16 @@ static const struct gen_l3_config cnl_l3_configs[]
> = {
> >*/
> >   static const struct gen_l3_config icl_l3_configs[] = {
> >  /* SLM URB ALL DC  RO  IS   C   T */
> > -   {{  0, 64, 64,  0,  0,  0,  0,  0 }},
> > -   {{  0, 64,  0, 16, 48,  0,  0,  0 }},
> > -   {{  0, 48,  0, 16, 64,  0,  0,  0 }},
> > -   {{  0, 32,  0,  0, 96,  0,  0,  0 }},
> > -   {{  0, 32, 96,  0,  0,  0,  0,  0 }},
> > -   {{  0, 32,  0, 16, 80,  0,  0,  0 }},
> > +   {{  0, 32, 32,  0,  0,  0,  0,  0 }},
> > +   {{  0, 32, 28,  0,  0,  0,  0,  0 }},
> > +   {{  0, 24,  0,  8, 28,  0,  0,  0 }},
> > +   {{  0, 16,  0,  0, 44,  0,  0,  0 }},
> > +   {{  0, 16, 12,  0,  0,  0,  0,  0 }},
> > +   {{  0, 16,  0,  0, 12,  0,  0,  0 }},
> > +   {{  0, 16, 80,  0,  0,  0,  0,  0 }},
> > +   {{  0, 16, 48,  0,  0,  0,  0,  0 }},
> > +   {{  0, 16, 44,  0,  0,  0,  0,  0 }},
> > +   {{  0, 32, 64,  0,  0,  0,  0,  0 }},
> >  {{  0 }}
> >   };
> >
>
>
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[Mesa-dev] [PATCH] anv/icl: Set Error Detection Behavior Control Bit in L3CNTLREG

[Anuj Phogat]

The default setting of this bit is not the desirable behavior.
WA_1406697149

Signed-off-by: Anuj Phogat 
---
 src/intel/genxml/gen11.xml | 1 +
 src/intel/vulkan/genX_cmd_buffer.c | 7 +++
 2 files changed, 8 insertions(+)

diff --git a/src/intel/genxml/gen11.xml b/src/intel/genxml/gen11.xml
index c69d7dc89c2..454ef8f4103 100644
--- a/src/intel/genxml/gen11.xml
+++ b/src/intel/genxml/gen11.xml
@@ -3546,6 +3546,7 @@
   
 
 
+
 
 
 
diff --git a/src/intel/vulkan/genX_cmd_buffer.c 
b/src/intel/vulkan/genX_cmd_buffer.c
index 43a02f22567..ed88157170d 100644
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@ -1617,6 +1617,13 @@ genX(cmd_buffer_config_l3)(struct anv_cmd_buffer 
*cmd_buffer,
uint32_t l3cr;
anv_pack_struct(, GENX(L3CNTLREG),
.SLMEnable = has_slm,
+#if GEN_GEN == 11
+   /* WA_1406697149: Bit 9 "Error Detection Behavior Control" must be set
+* in L3CNTLREG register. The default setting of the bit is not the
+* desirable behavior.
+   */
+   .ErrorDetectionBehaviorControl = true,
+#endif
.URBAllocation = cfg->n[GEN_L3P_URB],
.ROAllocation = cfg->n[GEN_L3P_RO],
.DCAllocation = cfg->n[GEN_L3P_DC],
-- 
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[Mesa-dev] [PATCH] i965/icl: Set Error Detection Behavior Control Bit in L3CNTLREG

[Anuj Phogat]

The default setting of this bit is not the desirable behavior.
WA_1406697149

Signed-off-by: Anuj Phogat 
---
 src/mesa/drivers/dri/i965/brw_defines.h  | 1 +
 src/mesa/drivers/dri/i965/brw_state_upload.c | 7 +++
 2 files changed, 8 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/brw_defines.h 
b/src/mesa/drivers/dri/i965/brw_defines.h
index 97a787a2ab3..897c91aa31e 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -1646,6 +1646,7 @@ enum brw_pixel_shader_coverage_mask_mode {
 # define GEN8_L3CNTLREG_DC_ALLOC_MASK  INTEL_MASK(24, 18)
 # define GEN8_L3CNTLREG_ALL_ALLOC_SHIFT25
 # define GEN8_L3CNTLREG_ALL_ALLOC_MASK INTEL_MASK(31, 25)
+# define GEN8_L3CNTLREG_EDBC_NO_HANG   (1 << 9)
 
 #define GEN10_CACHE_MODE_SS0x0e420
 #define GEN10_FLOAT_BLEND_OPTIMIZATION_ENABLE (1 << 4)
diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c 
b/src/mesa/drivers/dri/i965/brw_state_upload.c
index 7f20579fb87..60b72bf4ab3 100644
--- a/src/mesa/drivers/dri/i965/brw_state_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_state_upload.c
@@ -79,6 +79,13 @@ brw_upload_initial_gpu_state(struct brw_context *brw)
   brw_load_register_imm32(brw, HALF_SLICE_CHICKEN7,
   TEXEL_OFFSET_FIX_MASK |
   TEXEL_OFFSET_FIX_ENABLE);
+
+  /* WA_1406697149: Bit 9 "Error Detection Behavior Control" must be set
+   * in L3CNTLREG register. The default setting of the bit is not the
+   * desirable behavior.
+   */
+  brw_load_register_imm32(brw, GEN8_L3CNTLREG,
+  GEN8_L3CNTLREG_EDBC_NO_HANG);
}
 
if (devinfo->gen == 10 || devinfo->gen == 11) {
-- 
2.17.1

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[Mesa-dev] [PATCH] i965/anv: Disable prefetching of sampler state entries

[Anuj Phogat]

WA_1606682166:
Incorrect TDL's SSP address shift in SARB for 16:6 & 18:8 modes.
Disable the Sampler state prefetch functionality in the SARB by
programming 0xB000[30] to '1'. This is to be done at boot time and
the feature must remain disabled permanently.

Signed-off-by: Anuj Phogat 
---
 src/intel/vulkan/genX_pipeline.c | 25 -
 1 file changed, 16 insertions(+), 9 deletions(-)

diff --git a/src/intel/vulkan/genX_pipeline.c b/src/intel/vulkan/genX_pipeline.c
index 9595a7133ae..a7c5048eb37 100644
--- a/src/intel/vulkan/genX_pipeline.c
+++ b/src/intel/vulkan/genX_pipeline.c
@@ -1163,7 +1163,12 @@ emit_3dstate_vs(struct anv_pipeline *pipeline)
   vs.SingleVertexDispatch   = false;
 #endif
   vs.VectorMaskEnable   = false;
-  vs.SamplerCount   = get_sampler_count(vs_bin);
+  /* WA_1606682166:
+   * Incorrect TDL's SSP address shift in SARB for 16:6 & 18:8 modes.
+   * Disable the Sampler state prefetch functionality in the SARB by
+   * programming 0xB000[30] to '1'.
+   */
+  vs.SamplerCount   = GEN_GEN == 11 ? 0 : 
get_sampler_count(vs_bin);
  /* Gen 11 workarounds table #2056 WABTPPrefetchDisable suggests to
   * disable prefetching of binding tables on A0 and B0 steppings.
   * TODO: Revisit this WA on newer steppings.
@@ -1238,8 +1243,8 @@ emit_3dstate_hs_te_ds(struct anv_pipeline *pipeline,
   hs.Enable = true;
   hs.StatisticsEnable = true;
   hs.KernelStartPointer = tcs_bin->kernel.offset;
-
-  hs.SamplerCount = get_sampler_count(tcs_bin);
+  /* WA_1606682166 */
+  hs.SamplerCount = GEN_GEN == 11 ? 0 : get_sampler_count(tcs_bin);
   /* Gen 11 workarounds table #2056 WABTPPrefetchDisable */
   hs.BindingTableEntryCount = GEN_GEN == 11 ? 0 : 
get_binding_table_entry_count(tcs_bin);
   hs.MaximumNumberofThreads = devinfo->max_tcs_threads - 1;
@@ -1289,8 +1294,8 @@ emit_3dstate_hs_te_ds(struct anv_pipeline *pipeline,
   ds.Enable = true;
   ds.StatisticsEnable = true;
   ds.KernelStartPointer = tes_bin->kernel.offset;
-
-  ds.SamplerCount = get_sampler_count(tes_bin);
+  /* WA_1606682166 */
+  ds.SamplerCount = GEN_GEN == 11 ? 0 : get_sampler_count(tes_bin);
   /* Gen 11 workarounds table #2056 WABTPPrefetchDisable */
   ds.BindingTableEntryCount = GEN_GEN == 11 ? 0 : 
get_binding_table_entry_count(tes_bin);
   ds.MaximumNumberofThreads = devinfo->max_tes_threads - 1;
@@ -1348,7 +1353,8 @@ emit_3dstate_gs(struct anv_pipeline *pipeline)
 
   gs.SingleProgramFlow   = false;
   gs.VectorMaskEnable= false;
-  gs.SamplerCount= get_sampler_count(gs_bin);
+  /* WA_1606682166 */
+  gs.SamplerCount= GEN_GEN == 11 ? 0 : 
get_sampler_count(gs_bin);
   /* Gen 11 workarounds table #2056 WABTPPrefetchDisable */
   gs.BindingTableEntryCount  = GEN_GEN == 11 ? 0 : 
get_binding_table_entry_count(gs_bin);
   gs.IncludeVertexHandles= gs_prog_data->base.include_vue_handles;
@@ -1590,7 +1596,8 @@ emit_3dstate_ps(struct anv_pipeline *pipeline,
 
   ps.SingleProgramFlow  = false;
   ps.VectorMaskEnable   = true;
-  ps.SamplerCount   = get_sampler_count(fs_bin);
+  /* WA_1606682166 */
+  ps.SamplerCount   = GEN_GEN == 11 ? 0 : 
get_sampler_count(fs_bin);
   /* Gen 11 workarounds table #2056 WABTPPrefetchDisable */
   ps.BindingTableEntryCount = GEN_GEN == 11 ? 0 : 
get_binding_table_entry_count(fs_bin);
   ps.PushConstantEnable = wm_prog_data->base.nr_params > 0 ||
@@ -1921,8 +1928,8 @@ compute_pipeline_create(
 
struct GENX(INTERFACE_DESCRIPTOR_DATA) desc = {
   .KernelStartPointer = cs_bin->kernel.offset,
-
-  .SamplerCount   = get_sampler_count(cs_bin),
+  /* WA_1606682166 */
+  .SamplerCount   = GEN_GEN == 11 ? 0 : get_sampler_count(cs_bin),
   /* Gen 11 workarounds table #2056 WABTPPrefetchDisable */
   .BindingTableEntryCount = GEN_GEN == 11 ? 0 : 
get_binding_table_entry_count(cs_bin),
   .BarrierEnable  = cs_prog_data->uses_barrier,
-- 
2.17.1

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[Mesa-dev] [PATCH] i965/icl: Disable prefetching of sampler state entries

[Anuj Phogat]

From: Topi Pohjolainen 

In the same spirit as commit a5889d70f2074201ceaeac4f96a9a0c0b1f68a31
"i965/icl: Disable binding table prefetching". Fixes some 110+
intermittent piglit failures with tex-miplevel-selection variants.

WA_1606682166:
Incorrect TDL's SSP address shift in SARB for 16:6 & 18:8 modes.
Disable the Sampler state prefetch functionality in the SARB by
programming 0xB000[30] to '1'. This is to be done at boot time and
the feature must remain disabled permanently.

Anuj: Set SamplerCount = 0 for vs, gs, hs, ds and wm units as well.

Signed-off-by: Topi Pohjolainen 
Signed-off-by: Anuj Phogat 
Cc: Mark Janes 
---
Latest kernel from drm-tip  do have this workaround implemented
but we're seeing few deqp regressions with that kernel. I'm
adding this workaround to Mesa to make some progress in ICL
testing on CI. We can always revert the patch when we don't
need it anymore.
---
 src/mesa/drivers/dri/i965/genX_state_upload.c | 15 ---
 1 file changed, 12 insertions(+), 3 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/genX_state_upload.c 
b/src/mesa/drivers/dri/i965/genX_state_upload.c
index 740cb0c4d2e..319800934d5 100644
--- a/src/mesa/drivers/dri/i965/genX_state_upload.c
+++ b/src/mesa/drivers/dri/i965/genX_state_upload.c
@@ -2004,7 +2004,8 @@ genX(upload_wm)(struct brw_context *brw)
   if (wm_prog_data->base.use_alt_mode)
  wm.FloatingPointMode = FLOATING_POINT_MODE_Alternate;
 
-  wm.SamplerCount = GEN_GEN == 5 ?
+  /* WA_1606682166 */
+  wm.SamplerCount = (GEN_GEN == 5 || GEN_GEN == 11) ?
  0 : DIV_ROUND_UP(stage_state->sampler_count, 4);
 
   wm.BindingTableEntryCount =
@@ -2166,7 +2167,10 @@ static const struct brw_tracked_state genX(wm_state) = {
 
 #define INIT_THREAD_DISPATCH_FIELDS(pkt, prefix) \
pkt.KernelStartPointer = KSP(brw, stage_state->prog_offset);   \
+   /* WA_1606682166 */\
pkt.SamplerCount   =   \
+  GEN_GEN == 11 ? \
+  0 : \
   DIV_ROUND_UP(CLAMP(stage_state->sampler_count, 0, 16), 4);  \
/* Gen 11 workarounds table #2056 WABTPPrefetchDisable suggests to \
 * disable prefetching of binding tables in A0 and B0 steppings.   \
@@ -3977,8 +3981,13 @@ genX(upload_ps)(struct brw_context *brw)
*/
   ps.VectorMaskEnable = GEN_GEN >= 8;
 
-  ps.SamplerCount =
- DIV_ROUND_UP(CLAMP(stage_state->sampler_count, 0, 16), 4);
+   /* WA_1606682166:
+* "Incorrect TDL's SSP address shift in SARB for 16:6 & 18:8 modes.
+* Disable the Sampler state prefetch functionality in the SARB by
+* programming 0xB000[30] to '1'."
+*/
+  ps.SamplerCount = GEN_GEN == 11 ?
+ 0 : DIV_ROUND_UP(CLAMP(stage_state->sampler_count, 0, 16), 4);
 
   /* BRW_NEW_FS_PROG_DATA */
   /* Gen 11 workarounds table #2056 WABTPPrefetchDisable suggests to 
disable
-- 
2.17.1

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Re: [Mesa-dev] [PATCH] intel/compiler/icl: Use invocation id bits 22:16 instead of 23:17

[Anuj Phogat]

On Tue, Oct 16, 2018 at 4:21 AM Topi Pohjolainen
 wrote:
>
> Identifier bits in the dispatch header have changed. See Bspec:
>
> SINGLE_PATCH Payload:
>
> 3D Pipeline Stages - 3D Pipeline Geometry -
> Hull Shader (HS) Stage IVB+ - Payloads IVB+
>
> Fixes: 
> KHR-GL46.tessellation_shader.tessellation_shader_tc_barriers.barrier_guarded_read_write_calls
>
> CC: Anuj Phogat 
> CC: Mark Janes 
> Signed-off-by: Topi Pohjolainen 
> ---
>  src/intel/compiler/brw_fs.cpp | 8 ++--
>  1 file changed, 6 insertions(+), 2 deletions(-)
>
> diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp
> index 23a25fedca5..757147b01ec 100644
> --- a/src/intel/compiler/brw_fs.cpp
> +++ b/src/intel/compiler/brw_fs.cpp
> @@ -6593,14 +6593,18 @@ fs_visitor::run_tcs_single_patch()
> if (tcs_prog_data->instances == 1) {
>invocation_id = channels_ud;
> } else {
> +  const unsigned invocation_id_mask = devinfo->gen >= 11 ?
> + INTEL_MASK(22, 16) : INTEL_MASK(23, 17);
> +  const unsigned invocation_id_shift = devinfo->gen >= 11 ? 16 : 17;
> +
>invocation_id = bld.vgrf(BRW_REGISTER_TYPE_UD);
>
>/* Get instance number from g0.2 bits 23:17, and multiply it by 8. */
>fs_reg t = bld.vgrf(BRW_REGISTER_TYPE_UD);
>fs_reg instance_times_8 = bld.vgrf(BRW_REGISTER_TYPE_UD);
>bld.AND(t, fs_reg(retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD)),
> -  brw_imm_ud(INTEL_MASK(23, 17)));
> -  bld.SHR(instance_times_8, t, brw_imm_ud(17 - 3));
> +  brw_imm_ud(invocation_id_mask));
> +  bld.SHR(instance_times_8, t, brw_imm_ud(invocation_id_shift - 3));
>
>bld.ADD(invocation_id, instance_times_8, channels_ud);
> }
> --
> 2.17.1
>

Reviewed-by: Anuj Phogat 
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Re: [Mesa-dev] [PATCH] intel/compiler/icl: Use barrier id bits 24:30 instead of 24:27, 31

[Anuj Phogat]

On Thu, Sep 20, 2018 at 11:01 PM Topi Pohjolainen
 wrote:
>
> Fixes gpu hangs with Carchase and Manhattan.
>
> Cc: Anuj Phogat 
> Signed-off-by: Topi Pohjolainen 
> ---
>  src/intel/compiler/brw_fs_visitor.cpp | 16 +---
>  1 file changed, 13 insertions(+), 3 deletions(-)
>
> diff --git a/src/intel/compiler/brw_fs_visitor.cpp 
> b/src/intel/compiler/brw_fs_visitor.cpp
> index cd2abbb5960..51a0ca2374a 100644
> --- a/src/intel/compiler/brw_fs_visitor.cpp
> +++ b/src/intel/compiler/brw_fs_visitor.cpp
> @@ -791,9 +791,19 @@ fs_visitor::emit_cs_terminate()
>  void
>  fs_visitor::emit_barrier()
>  {
> -   assert(devinfo->gen >= 7);
> -   const uint32_t barrier_id_mask =
> -  devinfo->gen >= 9 ? 0x8f00u : 0x0f00u;
> +   uint32_t barrier_id_mask;
> +   switch (devinfo->gen) {
> +   case 7:
> +   case 8:
> +  barrier_id_mask = 0x0f00u; break;
> +   case 9:
> +   case 10:
> +  barrier_id_mask = 0x8f00u; break;
> +   case 11:
> +  barrier_id_mask = 0x7f00u; break;
> +   default:
> +  unreachable("barrier is only available on gen >= 7");
> +   }
>
> /* We are getting the barrier ID from the compute shader header */
> assert(stage == MESA_SHADER_COMPUTE);
> --
> 2.17.1
>
Barrier ID now setting the right bits specified h/w documentation. Fixes the
GPU hangs. Good find Topi.
Reviewed-by: Anuj Phogat 
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[Mesa-dev] [PATCH] intel/icl: Fix URB size for different SKUs

[Anuj Phogat]

Different ICL SKUs have different URB sizes.

Signed-off-by: Anuj Phogat 
---
 src/intel/dev/gen_device_info.c | 43 ++---
 1 file changed, 29 insertions(+), 14 deletions(-)

diff --git a/src/intel/dev/gen_device_info.c b/src/intel/dev/gen_device_info.c
index 3cece52a041..e2c6cbc7101 100644
--- a/src/intel/dev/gen_device_info.c
+++ b/src/intel/dev/gen_device_info.c
@@ -872,20 +872,7 @@ static const struct gen_device_info 
gen_device_info_cnl_5x8 = {
.max_gs_threads = 224,   \
.max_tcs_threads = 224,  \
.max_tes_threads = 364,  \
-   .max_cs_threads = 56,\
-   .urb = { \
-  .size = 1024, \
-  .min_entries = {  \
- [MESA_SHADER_VERTEX]= 64,  \
- [MESA_SHADER_TESS_EVAL] = 34,  \
-  },\
-  .max_entries = {  \
- [MESA_SHADER_VERTEX]= 2384,\
- [MESA_SHADER_TESS_CTRL] = 1032,\
- [MESA_SHADER_TESS_EVAL] = 2384,\
- [MESA_SHADER_GEOMETRY]  = 1032,\
-  },\
-   }
+   .max_cs_threads = 56
 
 #define GEN11_FEATURES(_gt, _slices, _subslices, _l3) \
GEN8_FEATURES, \
@@ -897,23 +884,51 @@ static const struct gen_device_info 
gen_device_info_cnl_5x8 = {
.num_subslices = _subslices,   \
.num_eu_per_subslice = 8
 
+#define GEN11_URB_MIN_MAX_ENTRIES \
+   .min_entries = {   \
+  [MESA_SHADER_VERTEX]= 64,   \
+  [MESA_SHADER_TESS_EVAL] = 34,   \
+   }, \
+   .max_entries = {   \
+  [MESA_SHADER_VERTEX]= 2384, \
+  [MESA_SHADER_TESS_CTRL] = 1032, \
+  [MESA_SHADER_TESS_EVAL] = 2384, \
+  [MESA_SHADER_GEOMETRY]  = 1032, \
+   }
+
 static const struct gen_device_info gen_device_info_icl_8x8 = {
GEN11_FEATURES(2, 1, subslices(8), 8),
+   .urb = {
+  .size = 1024,
+  GEN11_URB_MIN_MAX_ENTRIES,
+   },
.simulator_id = 19,
 };
 
 static const struct gen_device_info gen_device_info_icl_6x8 = {
GEN11_FEATURES(1, 1, subslices(6), 6),
+   .urb = {
+  .size = 768,
+  GEN11_URB_MIN_MAX_ENTRIES,
+   },
.simulator_id = 19,
 };
 
 static const struct gen_device_info gen_device_info_icl_4x8 = {
GEN11_FEATURES(1, 1, subslices(4), 6),
+   .urb = {
+  .size = 768,
+  GEN11_URB_MIN_MAX_ENTRIES,
+   },
.simulator_id = 19,
 };
 
 static const struct gen_device_info gen_device_info_icl_1x8 = {
GEN11_FEATURES(1, 1, subslices(1), 6),
+   .urb = {
+  .size = 768,
+  GEN11_URB_MIN_MAX_ENTRIES,
+   },
.simulator_id = 19,
 };
 
-- 
2.17.1

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[Mesa-dev] [PATCH] i965: Set minimum message length of 2 for SIMD8 URB write

[Anuj Phogat]

It fixes simulator error about h/w spec violation with piglit test:
glsl-1.50/execution/geometry/generate-zero-primitives.shader_test.
Simulator throws an error if dataLength < 1 for URB SIMD 8 write
message.

Signed-off-by: Anuj Phogat 
Cc: Kenneth Graunke 
Cc: 
---
I doubt if setting final_gs_vertex_count to sources[1] is always
safe here. It is initialized to zero in case of  above mentioned
piglit test. I'm not seeing any regressions in CI with this patch
and it fixes the simulation error.
---
 src/intel/compiler/brw_fs.cpp | 21 +
 1 file changed, 9 insertions(+), 12 deletions(-)

diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp
index 5b87991652d..4df332efe9b 100644
--- a/src/intel/compiler/brw_fs.cpp
+++ b/src/intel/compiler/brw_fs.cpp
@@ -1437,19 +1437,16 @@ fs_visitor::emit_gs_thread_end()
 break;
  }
   }
-  fs_reg hdr = abld.vgrf(BRW_REGISTER_TYPE_UD, 1);
-  abld.MOV(hdr, fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD)));
-  inst = abld.emit(SHADER_OPCODE_URB_WRITE_SIMD8, reg_undef, hdr);
-  inst->mlen = 1;
-   } else {
-  fs_reg payload = abld.vgrf(BRW_REGISTER_TYPE_UD, 2);
-  fs_reg *sources = ralloc_array(mem_ctx, fs_reg, 2);
-  sources[0] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD));
-  sources[1] = this->final_gs_vertex_count;
-  abld.LOAD_PAYLOAD(payload, sources, 2, 2);
-  inst = abld.emit(SHADER_OPCODE_URB_WRITE_SIMD8, reg_undef, payload);
-  inst->mlen = 2;
}
+
+   fs_reg payload = abld.vgrf(BRW_REGISTER_TYPE_UD, 2);
+   fs_reg *sources = ralloc_array(mem_ctx, fs_reg, 2);
+   sources[0] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD));
+   sources[1] = this->final_gs_vertex_count;
+   abld.LOAD_PAYLOAD(payload, sources, 2, 2);
+   inst = abld.emit(SHADER_OPCODE_URB_WRITE_SIMD8, reg_undef, payload);
+   inst->mlen = 2;
+
inst->eot = true;
inst->offset = 0;
 }
-- 
2.17.1

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[Mesa-dev] [PATCH V2] i965/icl: Set Enabled Texel Offset Precision Fix bit

[Anuj Phogat]

h/w specification requires this bit to be always set.

V2: Fix bit mask (Chris Wilson)

Suggested-by: Kenneth Graunke 
Signed-off-by: Anuj Phogat 
---
 src/mesa/drivers/dri/i965/brw_defines.h  | 4 
 src/mesa/drivers/dri/i965/brw_state_upload.c | 7 +++
 2 files changed, 11 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/brw_defines.h 
b/src/mesa/drivers/dri/i965/brw_defines.h
index 433314115b1..97a787a2ab3 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -1673,6 +1673,10 @@ enum brw_pixel_shader_coverage_mask_mode {
 # define GLK_SCEC_BARRIER_MODE_3D_HULL (1 << 7)
 # define GLK_SCEC_BARRIER_MODE_MASKREG_MASK(1 << 7)
 
+#define HALF_SLICE_CHICKEN70xE194
+# define TEXEL_OFFSET_FIX_ENABLE   (1 << 1)
+# define TEXEL_OFFSET_FIX_MASK REG_MASK(1 << 1)
+
 #define GEN11_SAMPLER_MODE  0xE18C
 # define HEADERLESS_MESSAGE_FOR_PREEMPTABLE_CONTEXTS(1 << 5)
 # define HEADERLESS_MESSAGE_FOR_PREEMPTABLE_CONTEXTS_MASK   REG_MASK(1 << 5)
diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c 
b/src/mesa/drivers/dri/i965/brw_state_upload.c
index 2af4c45bc44..7f20579fb87 100644
--- a/src/mesa/drivers/dri/i965/brw_state_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_state_upload.c
@@ -72,6 +72,13 @@ brw_upload_initial_gpu_state(struct brw_context *brw)
   brw_load_register_imm32(brw, GEN11_SAMPLER_MODE,
   HEADERLESS_MESSAGE_FOR_PREEMPTABLE_CONTEXTS_MASK 
|
   HEADERLESS_MESSAGE_FOR_PREEMPTABLE_CONTEXTS);
+
+  /* Bit 1 "Enabled Texel Offset Precision Fix" must be set in
+   * HALF_SLICE_CHICKEN7 register.
+   */
+  brw_load_register_imm32(brw, HALF_SLICE_CHICKEN7,
+  TEXEL_OFFSET_FIX_MASK |
+  TEXEL_OFFSET_FIX_ENABLE);
}
 
if (devinfo->gen == 10 || devinfo->gen == 11) {
-- 
2.17.1

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Re: [Mesa-dev] [PATCH] i965/icl: Set Enabled Texel Offset Precision Fix bit

[Anuj Phogat]

On Tue, Aug 28, 2018 at 10:57 AM Chris Wilson  wrote:
>
> Quoting Anuj Phogat (2018-08-28 18:53:59)
> > h/w specification requires this bit to be always set.
> >
> > Suggested-by: Kenneth Graunke 
> > Signed-off-by: Anuj Phogat 
> > ---
> >  src/mesa/drivers/dri/i965/brw_defines.h  | 4 
> >  src/mesa/drivers/dri/i965/brw_state_upload.c | 7 +++
> >  2 files changed, 11 insertions(+)
> >
> > diff --git a/src/mesa/drivers/dri/i965/brw_defines.h 
> > b/src/mesa/drivers/dri/i965/brw_defines.h
> > index 433314115b1..1c73ddeb190 100644
> > --- a/src/mesa/drivers/dri/i965/brw_defines.h
> > +++ b/src/mesa/drivers/dri/i965/brw_defines.h
> > @@ -1673,6 +1673,10 @@ enum brw_pixel_shader_coverage_mask_mode {
> >  # define GLK_SCEC_BARRIER_MODE_3D_HULL (1 << 7)
> >  # define GLK_SCEC_BARRIER_MODE_MASKREG_MASK(1 << 7)
> >
> > +#define HALF_SLICE_CHICKEN70xE194
> > +# define TEXEL_OFFSET_FIX_ENABLE   (1 << 1)
> > +# define TEXEL_OFFSET_FIX_MASK REG_MASK(1 << 7)
>
> That mask doesn't match the enable-bit.
>
Right. copy-paste error :(
v2 coming.

> It'll probably be quite useful to record all the registers you are
> setting as part of the global setup and read them back later to make
> sure they stuck.
That's a good idea Chris. I'll do it later in a separate series.
> -Chris
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[Mesa-dev] [PATCH] anv/icl: Set Enabled Texel Offset Precision Fix bit

[Anuj Phogat]

h/w specification requires this bit to be always set.

Suggested-by: Kenneth Graunke 
Signed-off-by: Anuj Phogat 
---
 src/intel/genxml/gen11.xml|  5 +
 src/intel/vulkan/genX_state.c | 14 ++
 2 files changed, 19 insertions(+)

diff --git a/src/intel/genxml/gen11.xml b/src/intel/genxml/gen11.xml
index 1b3befbbfc9..c69d7dc89c2 100644
--- a/src/intel/genxml/gen11.xml
+++ b/src/intel/genxml/gen11.xml
@@ -3640,4 +3640,9 @@
 
   
 
+  
+
+
+  
+
 
diff --git a/src/intel/vulkan/genX_state.c b/src/intel/vulkan/genX_state.c
index d6ccd21524c..2f48a7e1995 100644
--- a/src/intel/vulkan/genX_state.c
+++ b/src/intel/vulkan/genX_state.c
@@ -172,6 +172,20 @@ genX(init_device_state)(struct anv_device *device)
   lri.RegisterOffset = GENX(SAMPLER_MODE_num);
   lri.DataDWord  = sampler_mode;
}
+
+   /* Bit 1 "Enabled Texel Offset Precision Fix" must be set in
+* HALF_SLICE_CHICKEN7 register.
+*/
+   uint32_t half_slice_chicken7;
+   anv_pack_struct(_slice_chicken7, GENX(HALF_SLICE_CHICKEN7),
+   .EnabledTexelOffsetPrecisionFix = true,
+   .EnabledTexelOffsetPrecisionFixMask = true);
+
+anv_batch_emit(, GENX(MI_LOAD_REGISTER_IMM), lri) {
+  lri.RegisterOffset = GENX(HALF_SLICE_CHICKEN7_num);
+  lri.DataDWord  = half_slice_chicken7;
+   }
+
 #endif
 
/* Set the "CONSTANT_BUFFER Address Offset Disable" bit, so
-- 
2.17.1

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[Mesa-dev] [PATCH] i965/icl: Set Enabled Texel Offset Precision Fix bit

[Anuj Phogat]

h/w specification requires this bit to be always set.

Suggested-by: Kenneth Graunke 
Signed-off-by: Anuj Phogat 
---
 src/mesa/drivers/dri/i965/brw_defines.h  | 4 
 src/mesa/drivers/dri/i965/brw_state_upload.c | 7 +++
 2 files changed, 11 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/brw_defines.h 
b/src/mesa/drivers/dri/i965/brw_defines.h
index 433314115b1..1c73ddeb190 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -1673,6 +1673,10 @@ enum brw_pixel_shader_coverage_mask_mode {
 # define GLK_SCEC_BARRIER_MODE_3D_HULL (1 << 7)
 # define GLK_SCEC_BARRIER_MODE_MASKREG_MASK(1 << 7)
 
+#define HALF_SLICE_CHICKEN70xE194
+# define TEXEL_OFFSET_FIX_ENABLE   (1 << 1)
+# define TEXEL_OFFSET_FIX_MASK REG_MASK(1 << 7)
+
 #define GEN11_SAMPLER_MODE  0xE18C
 # define HEADERLESS_MESSAGE_FOR_PREEMPTABLE_CONTEXTS(1 << 5)
 # define HEADERLESS_MESSAGE_FOR_PREEMPTABLE_CONTEXTS_MASK   REG_MASK(1 << 5)
diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c 
b/src/mesa/drivers/dri/i965/brw_state_upload.c
index 2af4c45bc44..7f20579fb87 100644
--- a/src/mesa/drivers/dri/i965/brw_state_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_state_upload.c
@@ -72,6 +72,13 @@ brw_upload_initial_gpu_state(struct brw_context *brw)
   brw_load_register_imm32(brw, GEN11_SAMPLER_MODE,
   HEADERLESS_MESSAGE_FOR_PREEMPTABLE_CONTEXTS_MASK 
|
   HEADERLESS_MESSAGE_FOR_PREEMPTABLE_CONTEXTS);
+
+  /* Bit 1 "Enabled Texel Offset Precision Fix" must be set in
+   * HALF_SLICE_CHICKEN7 register.
+   */
+  brw_load_register_imm32(brw, HALF_SLICE_CHICKEN7,
+  TEXEL_OFFSET_FIX_MASK |
+  TEXEL_OFFSET_FIX_ENABLE);
}
 
if (devinfo->gen == 10 || devinfo->gen == 11) {
-- 
2.17.1

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Re: [Mesa-dev] [PATCH] i965/icl: Allow headerless sampler messages for pre-emptable contexts

[Anuj Phogat]

On Mon, Aug 20, 2018 at 2:13 PM Kenneth Graunke  wrote:
>
> On Monday, August 20, 2018 10:26:29 AM PDT Anuj Phogat wrote:
> > On Mon, Aug 20, 2018 at 12:18 AM Kenneth Graunke wrote:
> [snip]
> > > I don't know if people are trying to enable pre-emption during GPGPU
> > > work on pre-Gen11.  If so, that probably will not work, and we'd either
> > > need to avoid headerless messages (gross) or disable preemption (maybe
> > > also bad...)
> > >
> > Why do you think it'll be problem for Pre-Gen11? I don't see a bit 
> > disallowing
> > preemption+headerless message for pre-Gen11.
>
> What's the more likely scenario?
>
> Timeline A:
>
> 1. Preemption support was newly added; it didn't work with headerless
> 2. Somebody realized it was important and added a fix to make them work,
>but added it as a chicken bit that requires manual intervention.
> 3. They enabled the chicken bit by default, so things work right away.
> 4. They remove the chicken bit; the hardware just works.
>
> Timeline B:
>
> 1. Preemption support was added and headerless works perfectly
> 2. Someone breaks headerless but adds a chicken bit to work around it
> 3. Someone enables the fix by default
> 4. They remove the chicken bit; the hardware just works.
>
> IMHO, the first scenario is the most likely sequence of events.
Makes sense. Thanks for explaining.
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Re: [Mesa-dev] [PATCH] i965/icl: Allow headerless sampler messages for pre-emptable contexts

[Anuj Phogat]

On Mon, Aug 20, 2018 at 12:18 AM Kenneth Graunke  wrote:
>
> On Friday, August 17, 2018 5:13:25 PM PDT Anuj Phogat wrote:
> > It fixes simulator warnings in piglit tests complaining about missing
> > support for headerless sampler messages for pre-emptable contexts.
> > Bit 5 in SAMPLER MODE register is newly introduced for ICLLP.
> >
> > Signed-off-by: Anuj Phogat 
> > ---
> >  src/mesa/drivers/dri/i965/brw_defines.h  |  4 
> >  src/mesa/drivers/dri/i965/brw_state_upload.c | 11 +++
> >  2 files changed, 15 insertions(+)
> >
> > diff --git a/src/mesa/drivers/dri/i965/brw_defines.h 
> > b/src/mesa/drivers/dri/i965/brw_defines.h
> > index 855f1c7d744..433314115b1 100644
> > --- a/src/mesa/drivers/dri/i965/brw_defines.h
> > +++ b/src/mesa/drivers/dri/i965/brw_defines.h
> > @@ -1673,4 +1673,8 @@ enum brw_pixel_shader_coverage_mask_mode {
> >  # define GLK_SCEC_BARRIER_MODE_3D_HULL (1 << 7)
> >  # define GLK_SCEC_BARRIER_MODE_MASKREG_MASK(1 << 7)
> >
> > +#define GEN11_SAMPLER_MODE  0xE18C
> > +# define HEADERLESS_MESSAGE_FOR_PREEMPTABLE_CONTEXTS(1 << 5)
> > +# define HEADERLESS_MESSAGE_FOR_PREEMPTABLE_CONTEXTS_MASK   REG_MASK(1 << 
> > 5)
> > +
> >  #endif
> > diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c 
> > b/src/mesa/drivers/dri/i965/brw_state_upload.c
> > index 757426407c3..5a334b48892 100644
> > --- a/src/mesa/drivers/dri/i965/brw_state_upload.c
> > +++ b/src/mesa/drivers/dri/i965/brw_state_upload.c
> > @@ -63,6 +63,17 @@ brw_upload_initial_gpu_state(struct brw_context *brw)
> >
> > brw_upload_invariant_state(brw);
> >
> > +   if (devinfo->gen == 11) {
> > +  /*  The default behavior of bit 5 "Headerless Message for 
> > Pre-emptable
> > +   *  Contexts" in SAMPLER MODE register is set to 0, which means
> > +   *  headerless sampler messages are not allowed for pre-emptable
> > +   *  contexts. Set the bit 5 to 1 to allow them.
>
> Bonus space after the stars.  Can we also change this to:
>
>* contexts.  Set bit 5 to allow them.
>
> Same for the anv patch.  Either way, both are:
> Reviewed-by: Kenneth Graunke 
>
Fixed locally. Thanks.
> I don't know if people are trying to enable pre-emption during GPGPU
> work on pre-Gen11.  If so, that probably will not work, and we'd either
> need to avoid headerless messages (gross) or disable preemption (maybe
> also bad...)
>
Why do you think it'll be problem for Pre-Gen11? I don't see a bit disallowing
preemption+headerless message for pre-Gen11.

> > +   */
> > +  brw_load_register_imm32(brw, GEN11_SAMPLER_MODE,
> > +  
> > HEADERLESS_MESSAGE_FOR_PREEMPTABLE_CONTEXTS_MASK |
> > +  HEADERLESS_MESSAGE_FOR_PREEMPTABLE_CONTEXTS);
> > +   }
> > +
> > if (devinfo->gen == 10 || devinfo->gen == 11) {
> >/* From gen10 workaround table in h/w specs:
> > *
> >
>
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[Mesa-dev] [PATCH] anv/icl: Allow headerless sampler messages for pre-emptable contexts

[Anuj Phogat]

It fixes simulator warnings in vulkancts tests complaining about missing
support for headerless sampler messages for pre-emptable contexts.
Bit 5 in SAMPLER MODE register is newly introduced for ICLLP.

Signed-off-by: Anuj Phogat 
---
 src/intel/genxml/gen11.xml|  5 +
 src/intel/vulkan/genX_state.c | 17 +
 2 files changed, 22 insertions(+)

diff --git a/src/intel/genxml/gen11.xml b/src/intel/genxml/gen11.xml
index bd3800e4b79..1b3befbbfc9 100644
--- a/src/intel/genxml/gen11.xml
+++ b/src/intel/genxml/gen11.xml
@@ -3635,4 +3635,9 @@
 
   
 
+  
+
+
+  
+
 
diff --git a/src/intel/vulkan/genX_state.c b/src/intel/vulkan/genX_state.c
index b1014d9e797..5b1b084a580 100644
--- a/src/intel/vulkan/genX_state.c
+++ b/src/intel/vulkan/genX_state.c
@@ -157,6 +157,23 @@ genX(init_device_state)(struct anv_device *device)
gen10_emit_wa_lri_to_cache_mode_zero();
 #endif
 
+#if GEN_GEN == 11
+   /*  The default behavior of bit 5 "Headerless Message for Pre-emptable
+*  Contexts" in SAMPLER MODE register is set to 0, which means
+*  headerless sampler messages are not allowed for pre-emptable
+*  contexts. Set the bit 5 to 1 to allow them.
+*/
+   uint32_t sampler_mode;
+   anv_pack_struct(_mode, GENX(SAMPLER_MODE),
+   .HeaderlessMessageforPreemptableContexts = true,
+   .HeaderlessMessageforPreemptableContextsMask = true);
+
+anv_batch_emit(, GENX(MI_LOAD_REGISTER_IMM), lri) {
+  lri.RegisterOffset = GENX(SAMPLER_MODE_num);
+  lri.DataDWord  = sampler_mode;
+   }
+#endif
+
/* Set the "CONSTANT_BUFFER Address Offset Disable" bit, so
 * 3DSTATE_CONSTANT_XS buffer 0 is an absolute address.
 *
-- 
2.17.0

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[Mesa-dev] [PATCH] anv/icl: Disable binding table prefetching

[Anuj Phogat]

Gen 11 workarounds table #2056 WABTPPrefetchDisable suggests to
disable prefetching of binding tables for ICLLP A0 and B0
steppings. We have a similar patch for i965 driver in  Mesa
commit a5889d70.

Signed-off-by: Anuj Phogat 
---
 src/intel/vulkan/genX_pipeline.c | 21 +++--
 1 file changed, 15 insertions(+), 6 deletions(-)

diff --git a/src/intel/vulkan/genX_pipeline.c b/src/intel/vulkan/genX_pipeline.c
index ec47360764c..078fb14e954 100644
--- a/src/intel/vulkan/genX_pipeline.c
+++ b/src/intel/vulkan/genX_pipeline.c
@@ -1136,7 +1136,11 @@ emit_3dstate_vs(struct anv_pipeline *pipeline)
 #endif
   vs.VectorMaskEnable   = false;
   vs.SamplerCount   = get_sampler_count(vs_bin);
-  vs.BindingTableEntryCount = get_binding_table_entry_count(vs_bin);
+ /* Gen 11 workarounds table #2056 WABTPPrefetchDisable suggests to
+  * disable prefetching of binding tables on A0 and B0 steppings.
+  * TODO: Revisit this WA on newer steppings.
+  */
+  vs.BindingTableEntryCount = GEN_GEN == 11 ? 0 : 
get_binding_table_entry_count(vs_bin);
   vs.FloatingPointMode  = IEEE754;
   vs.IllegalOpcodeExceptionEnable = false;
   vs.SoftwareExceptionEnable= false;
@@ -1187,7 +1191,8 @@ emit_3dstate_hs_te_ds(struct anv_pipeline *pipeline,
   hs.KernelStartPointer = tcs_bin->kernel.offset;
 
   hs.SamplerCount = get_sampler_count(tcs_bin);
-  hs.BindingTableEntryCount = get_binding_table_entry_count(tcs_bin);
+  /* Gen 11 workarounds table #2056 WABTPPrefetchDisable */
+  hs.BindingTableEntryCount = GEN_GEN == 11 ? 0 : 
get_binding_table_entry_count(tcs_bin);
   hs.MaximumNumberofThreads = devinfo->max_tcs_threads - 1;
   hs.IncludeVertexHandles = true;
   hs.InstanceCount = tcs_prog_data->instances - 1;
@@ -1237,7 +1242,8 @@ emit_3dstate_hs_te_ds(struct anv_pipeline *pipeline,
   ds.KernelStartPointer = tes_bin->kernel.offset;
 
   ds.SamplerCount = get_sampler_count(tes_bin);
-  ds.BindingTableEntryCount = get_binding_table_entry_count(tes_bin);
+  /* Gen 11 workarounds table #2056 WABTPPrefetchDisable */
+  ds.BindingTableEntryCount = GEN_GEN == 11 ? 0 : 
get_binding_table_entry_count(tes_bin);
   ds.MaximumNumberofThreads = devinfo->max_tes_threads - 1;
 
   ds.ComputeWCoordinateEnable =
@@ -1294,7 +1300,8 @@ emit_3dstate_gs(struct anv_pipeline *pipeline)
   gs.SingleProgramFlow   = false;
   gs.VectorMaskEnable= false;
   gs.SamplerCount= get_sampler_count(gs_bin);
-  gs.BindingTableEntryCount  = get_binding_table_entry_count(gs_bin);
+  /* Gen 11 workarounds table #2056 WABTPPrefetchDisable */
+  gs.BindingTableEntryCount  = GEN_GEN == 11 ? 0 : 
get_binding_table_entry_count(gs_bin);
   gs.IncludeVertexHandles= gs_prog_data->base.include_vue_handles;
   gs.IncludePrimitiveID  = gs_prog_data->include_primitive_id;
 
@@ -1535,7 +1542,8 @@ emit_3dstate_ps(struct anv_pipeline *pipeline,
   ps.SingleProgramFlow  = false;
   ps.VectorMaskEnable   = true;
   ps.SamplerCount   = get_sampler_count(fs_bin);
-  ps.BindingTableEntryCount = get_binding_table_entry_count(fs_bin);
+  /* Gen 11 workarounds table #2056 WABTPPrefetchDisable */
+  ps.BindingTableEntryCount = GEN_GEN == 11 ? 0 : 
get_binding_table_entry_count(fs_bin);
   ps.PushConstantEnable = wm_prog_data->base.nr_params > 0 ||
   wm_prog_data->base.ubo_ranges[0].length;
   ps.PositionXYOffsetSelect = wm_prog_data->uses_pos_offset ?
@@ -1868,7 +1876,8 @@ compute_pipeline_create(
   .KernelStartPointer = cs_bin->kernel.offset,
 
   .SamplerCount   = get_sampler_count(cs_bin),
-  .BindingTableEntryCount = get_binding_table_entry_count(cs_bin),
+  /* Gen 11 workarounds table #2056 WABTPPrefetchDisable */
+  .BindingTableEntryCount = GEN_GEN == 11 ? 0 : 
get_binding_table_entry_count(cs_bin),
   .BarrierEnable  = cs_prog_data->uses_barrier,
   .SharedLocalMemorySize  =
  encode_slm_size(GEN_GEN, cs_prog_data->base.total_shared),
-- 
2.17.0

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[Mesa-dev] [PATCH] i965/icl: Allow headerless sampler messages for pre-emptable contexts

[Anuj Phogat]

It fixes simulator warnings in piglit tests complaining about missing
support for headerless sampler messages for pre-emptable contexts.
Bit 5 in SAMPLER MODE register is newly introduced for ICLLP.

Signed-off-by: Anuj Phogat 
---
 src/mesa/drivers/dri/i965/brw_defines.h  |  4 
 src/mesa/drivers/dri/i965/brw_state_upload.c | 11 +++
 2 files changed, 15 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/brw_defines.h 
b/src/mesa/drivers/dri/i965/brw_defines.h
index 855f1c7d744..433314115b1 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -1673,4 +1673,8 @@ enum brw_pixel_shader_coverage_mask_mode {
 # define GLK_SCEC_BARRIER_MODE_3D_HULL (1 << 7)
 # define GLK_SCEC_BARRIER_MODE_MASKREG_MASK(1 << 7)
 
+#define GEN11_SAMPLER_MODE  0xE18C
+# define HEADERLESS_MESSAGE_FOR_PREEMPTABLE_CONTEXTS(1 << 5)
+# define HEADERLESS_MESSAGE_FOR_PREEMPTABLE_CONTEXTS_MASK   REG_MASK(1 << 5)
+
 #endif
diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c 
b/src/mesa/drivers/dri/i965/brw_state_upload.c
index 757426407c3..5a334b48892 100644
--- a/src/mesa/drivers/dri/i965/brw_state_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_state_upload.c
@@ -63,6 +63,17 @@ brw_upload_initial_gpu_state(struct brw_context *brw)
 
brw_upload_invariant_state(brw);
 
+   if (devinfo->gen == 11) {
+  /*  The default behavior of bit 5 "Headerless Message for Pre-emptable
+   *  Contexts" in SAMPLER MODE register is set to 0, which means
+   *  headerless sampler messages are not allowed for pre-emptable
+   *  contexts. Set the bit 5 to 1 to allow them.
+   */
+  brw_load_register_imm32(brw, GEN11_SAMPLER_MODE,
+  HEADERLESS_MESSAGE_FOR_PREEMPTABLE_CONTEXTS_MASK 
|
+  HEADERLESS_MESSAGE_FOR_PREEMPTABLE_CONTEXTS);
+   }
+
if (devinfo->gen == 10 || devinfo->gen == 11) {
   /* From gen10 workaround table in h/w specs:
*
-- 
2.17.0

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Re: [Mesa-dev] [PATCH] intel: Switch the order of the 2x MSAA sample positions

[Anuj Phogat]

On Wed, Aug 8, 2018 at 11:31 AM Jason Ekstrand  wrote:
>
> The Vulkan 1.1.82 spec flipped the order to better match D3D.
>
> Cc: mesa-sta...@lists.freedesktop.org
> ---
>  src/intel/blorp/blorp_blit.c   | 11 ++-
>  src/intel/common/gen_sample_positions.h|  8 
>  src/mesa/drivers/dri/i965/brw_multisample_state.h  |  8 
>  src/mesa/drivers/dri/i965/gen6_multisample_state.c |  4 ++--
>  4 files changed, 20 insertions(+), 11 deletions(-)
>
> diff --git a/src/intel/blorp/blorp_blit.c b/src/intel/blorp/blorp_blit.c
> index 561897894c3..013f7a14fa2 100644
> --- a/src/intel/blorp/blorp_blit.c
> +++ b/src/intel/blorp/blorp_blit.c
> @@ -776,6 +776,13 @@ blorp_nir_manual_blend_bilinear(nir_builder *b, 
> nir_ssa_def *pos,
> * grid of samples with in a pixel. Sample number layout shows the
> * rectangular grid of samples roughly corresponding to the real sample
> * locations with in a pixel.
> +   *
> +   * In the case of 2x MSAA, the layout of sample indices is reversed 
> from
> +   * the layout of sample numbers:
It is not clear from this comment if below layout is for sample index or sample
number. Adding "sample number layout:" on top of it will help.
> +   *   -
> +   *   | 1 | 0 |
> +   *   -
> +   *
> * In case of 4x MSAA, layout of sample indices matches the layout of
> * sample numbers:
> *   -
> @@ -819,7 +826,9 @@ blorp_nir_manual_blend_bilinear(nir_builder *b, 
> nir_ssa_def *pos,
>  key->x_scale * key->y_scale));
>sample = nir_f2i32(b, sample);
>
> -  if (tex_samples == 8) {
> +  if (tex_samples == 2) {
> + sample = nir_isub(b, nir_imm_int(b, 1), sample);
> +  } else if (tex_samples == 8) {
>   sample = nir_iand(b, nir_ishr(b, nir_imm_int(b, 0x64210573),
> nir_ishl(b, sample, nir_imm_int(b, 
> 2))),
> nir_imm_int(b, 0xf));
> diff --git a/src/intel/common/gen_sample_positions.h 
> b/src/intel/common/gen_sample_positions.h
> index f0ce95dd1fb..da48dcb5ed0 100644
> --- a/src/intel/common/gen_sample_positions.h
> +++ b/src/intel/common/gen_sample_positions.h
> @@ -42,10 +42,10 @@ prefix##0YOffset   = 0.5;
>   * c   1
>   */
>  #define GEN_SAMPLE_POS_2X(prefix) \
> -prefix##0XOffset   = 0.25; \
> -prefix##0YOffset   = 0.25; \
> -prefix##1XOffset   = 0.75; \
> -prefix##1YOffset   = 0.75;
> +prefix##0XOffset   = 0.75; \
> +prefix##0YOffset   = 0.75; \
> +prefix##1XOffset   = 0.25; \
> +prefix##1YOffset   = 0.25;
>
>  /**
>   * Sample positions:
> diff --git a/src/mesa/drivers/dri/i965/brw_multisample_state.h 
> b/src/mesa/drivers/dri/i965/brw_multisample_state.h
> index 6cf324e561c..2142a17a484 100644
> --- a/src/mesa/drivers/dri/i965/brw_multisample_state.h
> +++ b/src/mesa/drivers/dri/i965/brw_multisample_state.h
> @@ -38,13 +38,13 @@
>  /**
>   * 1x MSAA has a single sample at the center: (0.5, 0.5) -> (0x8, 0x8).
>   *
> - * 2x MSAA sample positions are (0.25, 0.25) and (0.75, 0.75):
> + * 2x MSAA sample positions are (0.75, 0.75) and (0.25, 0.25):
>   *   4 c
> - * 4 0
> - * c   1
> + * 4 1
> + * c   0
>   */
>  static const uint32_t
> -brw_multisample_positions_1x_2x = 0x0088cc44;
> +brw_multisample_positions_1x_2x = 0x008844cc;
>
>  /**
>   * Sample positions:
> diff --git a/src/mesa/drivers/dri/i965/gen6_multisample_state.c 
> b/src/mesa/drivers/dri/i965/gen6_multisample_state.c
> index bfa84fb9b77..78ff3942075 100644
> --- a/src/mesa/drivers/dri/i965/gen6_multisample_state.c
> +++ b/src/mesa/drivers/dri/i965/gen6_multisample_state.c
> @@ -70,7 +70,7 @@ gen6_get_sample_position(struct gl_context *ctx,
>   *
>   * 2X MSAA sample index / number layout
You should update this comment matching it up with comment in blorp and
add  "sample number layout:" on top of below layout. I would leave it up to
you if you also want to draw sample index layout here just for uniformity.
>   *   -
> - *   | 0 | 1 |
> + *   | 1 | 0 |
>   *   -
>   *
>   * 4X MSAA sample index / number layout
> @@ -107,7 +107,7 @@ gen6_get_sample_position(struct gl_context *ctx,
>  void
>  gen6_set_sample_maps(struct gl_context *ctx)
>  {
> -   uint8_t map_2x[2] = {0, 1};
> +   uint8_t map_2x[2] = {1, 0};
> uint8_t map_4x[4] = {0, 1, 2, 3};
> uint8_t map_8x[8] = {3, 7, 5, 0, 1, 2, 4, 6};
> uint8_t map_16x[16] = { 15, 10, 9, 7, 4, 1, 3, 13,
> --
> 2.17.1
>
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With above changes
Reviewed-by: Anuj Phogat 
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Re: [Mesa-dev] [PATCH] i965: Expose ARB_base_instance extension

[Anuj Phogat]

On Wed, Jul 25, 2018 at 10:49 AM Sagar Ghuge  wrote:
>
> The extension requires at least OpenGL 3.0 and
> OpenGL ES 3.0.
>
> Fixes two ext_base_instance tests:
>
> arb_base_instance-baseinstance-doesnt-affect-gl-instance-id_gles3
> arb_base_instance-drawarrays_gles3
>
> Signed-off-by: Sagar Ghuge 
> ---
>  src/mesa/drivers/dri/i965/intel_extensions.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c 
> b/src/mesa/drivers/dri/i965/intel_extensions.c
> index f837356478..9d119d0b4c 100644
> --- a/src/mesa/drivers/dri/i965/intel_extensions.c
> +++ b/src/mesa/drivers/dri/i965/intel_extensions.c
> @@ -315,7 +315,7 @@ intelInitExtensions(struct gl_context *ctx)
> if (devinfo->gen >= 6)
>ctx->Extensions.INTEL_performance_query = true;
>
> -   if (ctx->API == API_OPENGL_CORE)
> +   if (ctx->API != API_OPENGL_COMPAT)
>ctx->Extensions.ARB_base_instance = true;
> if (ctx->API != API_OPENGL_CORE)
>ctx->Extensions.ARB_color_buffer_float = true;
> --
> 2.17.1
>
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It's EXT_base_instance for gles.
With suggested changes to Subject:
Reviewed-by: Anuj Phogat 
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[Mesa-dev] [PATCH] i965/icl: Disable binding table prefetching

[Anuj Phogat]

From: Topi Pohjolainen 

Gen 11 workarounds table #2056 WABTPPrefetchDisable suggests to
disable prefetching of binding tables for ICLLP A0 and B0
steppings. It fixes multiple gpu hangs in
ext_framebuffer_multisample* tests on ICLLP B0 h/w.

Anuj: Add comments and commit message.
  Add gen 11 checks in the code.

Signed-off-by: Anuj Phogat 
---
 src/intel/blorp/blorp_genX_exec.h |  7 +++
 src/mesa/drivers/dri/i965/genX_state_upload.c | 14 +-
 2 files changed, 20 insertions(+), 1 deletion(-)

diff --git a/src/intel/blorp/blorp_genX_exec.h 
b/src/intel/blorp/blorp_genX_exec.h
index 8bd9174b677..50341ab0ecf 100644
--- a/src/intel/blorp/blorp_genX_exec.h
+++ b/src/intel/blorp/blorp_genX_exec.h
@@ -762,6 +762,13 @@ blorp_emit_ps_config(struct blorp_batch *batch,
  ps.BindingTableEntryCount = 1;
   }
 
+ /* Gen 11 workarounds table #2056 WABTPPrefetchDisable suggests to
+  * disable prefetching of binding tables on A0 and B0 steppings.
+  * TODO: Revisit this WA on C0 stepping.
+  */
+  if (GEN_GEN == 11)
+ ps.BindingTableEntryCount = 0;
+
   if (prog_data) {
  ps._8PixelDispatchEnable = prog_data->dispatch_8;
  ps._16PixelDispatchEnable = prog_data->dispatch_16;
diff --git a/src/mesa/drivers/dri/i965/genX_state_upload.c 
b/src/mesa/drivers/dri/i965/genX_state_upload.c
index 9e0a17b9d93..b02acaf40e5 100644
--- a/src/mesa/drivers/dri/i965/genX_state_upload.c
+++ b/src/mesa/drivers/dri/i965/genX_state_upload.c
@@ -2165,7 +2165,13 @@ static const struct brw_tracked_state genX(wm_state) = {
pkt.KernelStartPointer = KSP(brw, stage_state->prog_offset);   \
pkt.SamplerCount   =   \
   DIV_ROUND_UP(CLAMP(stage_state->sampler_count, 0, 16), 4);  \
+   /* Gen 11 workarounds table #2056 WABTPPrefetchDisable suggests to \
+* disable prefetching of binding tables in A0 and B0 steppings.   \
+* TODO: Revisit this WA on C0 stepping.   \
+*/\
pkt.BindingTableEntryCount =   \
+  GEN_GEN == 11 ? \
+  0 : \
   stage_prog_data->binding_table.size_bytes / 4;  \
pkt.FloatingPointMode  = stage_prog_data->use_alt_mode;\
   \
@@ -3954,7 +3960,13 @@ genX(upload_ps)(struct brw_context *brw)
  DIV_ROUND_UP(CLAMP(stage_state->sampler_count, 0, 16), 4);
 
   /* BRW_NEW_FS_PROG_DATA */
-  ps.BindingTableEntryCount = prog_data->base.binding_table.size_bytes / 4;
+  /* Gen 11 workarounds table #2056 WABTPPrefetchDisable suggests to 
disable
+   * prefetching of binding tables in A0 and B0 steppings.
+   * TODO: Revisit this workaround on C0 stepping.
+   */
+  ps.BindingTableEntryCount = GEN_GEN == 11 ?
+  0 :
+  prog_data->base.binding_table.size_bytes / 4;
 
   if (prog_data->base.use_alt_mode)
  ps.FloatingPointMode = Alternate;
-- 
2.17.0

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Re: [Mesa-dev] [PATCH 01/11] spirv: initialize is_vertex_input

[Anuj Phogat]

On Mon, Jul 16, 2018 at 3:38 PM Caio Marcelo de Oliveira Filho
 wrote:
>
> Fixes warning:
>
> ../../src/compiler/spirv/vtn_variables.c: In function ‘var_decoration_cb’:
> ../../src/compiler/spirv/vtn_variables.c:1400:12: warning: ‘is_vertex_input’ 
> may be used uninitialized in this function [-Wmaybe-uninitialized]
>bool is_vertex_input;
> ^~~
>
> The code used to set is_vertex_input in all possible codepaths, but
> after 23edc5b1ef3 "spirv: translate default-block uniforms" the
> compiler isn't sure all codepaths will initialize the variable.
> ---
>  src/compiler/spirv/vtn_variables.c | 4 +---
>  1 file changed, 1 insertion(+), 3 deletions(-)
>
> diff --git a/src/compiler/spirv/vtn_variables.c 
> b/src/compiler/spirv/vtn_variables.c
> index 6bd7aa1b0d5..fbfea6f8cef 100644
> --- a/src/compiler/spirv/vtn_variables.c
> +++ b/src/compiler/spirv/vtn_variables.c
> @@ -1397,10 +1397,9 @@ var_decoration_cb(struct vtn_builder *b, struct 
> vtn_value *val, int member,
>  */
> if (dec->decoration == SpvDecorationLocation) {
>unsigned location = dec->literals[0];
> -  bool is_vertex_input;
> +  bool is_vertex_input = false;
>if (b->shader->info.stage == MESA_SHADER_FRAGMENT &&
>vtn_var->mode == vtn_variable_mode_output) {
> - is_vertex_input = false;
>   location += FRAG_RESULT_DATA0;
>} else if (b->shader->info.stage == MESA_SHADER_VERTEX &&
>   vtn_var->mode == vtn_variable_mode_input) {
> @@ -1408,7 +1407,6 @@ var_decoration_cb(struct vtn_builder *b, struct 
> vtn_value *val, int member,
>   location += VERT_ATTRIB_GENERIC0;
>} else if (vtn_var->mode == vtn_variable_mode_input ||
>   vtn_var->mode == vtn_variable_mode_output) {
> - is_vertex_input = false;
>   location += vtn_var->patch ? VARYING_SLOT_PATCH0 : 
> VARYING_SLOT_VAR0;
>} else if (vtn_var->mode != vtn_variable_mode_uniform) {
>   vtn_warn("Location must be on input, output, uniform, sampler or "
> --
> 2.18.0
>
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For the series:
Reviewed-by: Anuj Phogat 
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Re: [Mesa-dev] [PATCH] i965/icl: Don't set float blend optimization bit in CACHE_MODE_SS

[Anuj Phogat]

Bump.
On Fri, Jun 1, 2018 at 2:40 PM Anuj Phogat  wrote:
>
> CACHE_MODE_SS is not listed in gfxspecs table for user mode
> non-privileged registers. So, making any changes from Mesa
> will do nothing. Kernel is already setting this bit in
> CACHE_MODE_SS register which is saved/restored to/from
> the HW context image.
>
> Signed-off-by: Anuj Phogat 
> Cc: Lionel Landwerlin 
> ---
>  src/mesa/drivers/dri/i965/brw_state_upload.c | 4 
>  1 file changed, 4 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c 
> b/src/mesa/drivers/dri/i965/brw_state_upload.c
> index d8273aa5734..757426407c3 100644
> --- a/src/mesa/drivers/dri/i965/brw_state_upload.c
> +++ b/src/mesa/drivers/dri/i965/brw_state_upload.c
> @@ -64,10 +64,6 @@ brw_upload_initial_gpu_state(struct brw_context *brw)
> brw_upload_invariant_state(brw);
>
> if (devinfo->gen == 10 || devinfo->gen == 11) {
> -  brw_load_register_imm32(brw, GEN10_CACHE_MODE_SS,
> -  
> REG_MASK(GEN10_FLOAT_BLEND_OPTIMIZATION_ENABLE) |
> -  GEN10_FLOAT_BLEND_OPTIMIZATION_ENABLE);
> -
>/* From gen10 workaround table in h/w specs:
> *
> *"On 3DSTATE_3D_MODE, driver must always program bits 31:16 of DW1
> --
> 2.17.0
>
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Re: [Mesa-dev] [PATCH] anv/icl: Don't set float blend optimization bit in CACHE_MODE_SS

[Anuj Phogat]

Bump
On Fri, Jun 1, 2018 at 2:40 PM Anuj Phogat  wrote:
>
> CACHE_MODE_SS is not listed in gfxspecs table for user mode
> non-privileged registers. So, making any changes from Mesa
> will do nothing. Kernel is already setting this bit in
> CACHE_MODE_SS register which is saved/restored to/from
> the HW context image.
>
> Signed-off-by: Anuj Phogat 
> Cc: Lionel Landwerlin 
> ---
>  src/intel/vulkan/genX_state.c | 12 
>  1 file changed, 12 deletions(-)
>
> diff --git a/src/intel/vulkan/genX_state.c b/src/intel/vulkan/genX_state.c
> index c6e54046910..06dc2d345e2 100644
> --- a/src/intel/vulkan/genX_state.c
> +++ b/src/intel/vulkan/genX_state.c
> @@ -121,18 +121,6 @@ genX(init_device_state)(struct anv_device *device)
> }
>  #endif
>
> -#if GEN_GEN == 10 || GEN_GEN == 11
> -   uint32_t cache_mode_ss;
> -   anv_pack_struct(_mode_ss, GENX(CACHE_MODE_SS),
> -   .FloatBlendOptimizationEnable = true,
> -   .FloatBlendOptimizationEnableMask = true);
> -
> -   anv_batch_emit(, GENX(MI_LOAD_REGISTER_IMM), lri) {
> -  lri.RegisterOffset = GENX(CACHE_MODE_SS_num);
> -  lri.DataDWord  = cache_mode_ss;
> -   }
> -#endif
> -
> anv_batch_emit(, GENX(3DSTATE_AA_LINE_PARAMETERS), aa);
>
> anv_batch_emit(, GENX(3DSTATE_DRAWING_RECTANGLE), rect) {
> --
> 2.17.0
>
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[Mesa-dev] [PATCH] anv/icl: Don't set float blend optimization bit in CACHE_MODE_SS

[Anuj Phogat]

CACHE_MODE_SS is not listed in gfxspecs table for user mode
non-privileged registers. So, making any changes from Mesa
will do nothing. Kernel is already setting this bit in
CACHE_MODE_SS register which is saved/restored to/from
the HW context image.

Signed-off-by: Anuj Phogat 
Cc: Lionel Landwerlin 
---
 src/intel/vulkan/genX_state.c | 12 
 1 file changed, 12 deletions(-)

diff --git a/src/intel/vulkan/genX_state.c b/src/intel/vulkan/genX_state.c
index c6e54046910..06dc2d345e2 100644
--- a/src/intel/vulkan/genX_state.c
+++ b/src/intel/vulkan/genX_state.c
@@ -121,18 +121,6 @@ genX(init_device_state)(struct anv_device *device)
}
 #endif
 
-#if GEN_GEN == 10 || GEN_GEN == 11
-   uint32_t cache_mode_ss;
-   anv_pack_struct(_mode_ss, GENX(CACHE_MODE_SS),
-   .FloatBlendOptimizationEnable = true,
-   .FloatBlendOptimizationEnableMask = true);
-
-   anv_batch_emit(, GENX(MI_LOAD_REGISTER_IMM), lri) {
-  lri.RegisterOffset = GENX(CACHE_MODE_SS_num);
-  lri.DataDWord  = cache_mode_ss;
-   }
-#endif
-
anv_batch_emit(, GENX(3DSTATE_AA_LINE_PARAMETERS), aa);
 
anv_batch_emit(, GENX(3DSTATE_DRAWING_RECTANGLE), rect) {
-- 
2.17.0

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[Mesa-dev] [PATCH] i965/icl: Don't set float blend optimization bit in CACHE_MODE_SS

[Anuj Phogat]

CACHE_MODE_SS is not listed in gfxspecs table for user mode
non-privileged registers. So, making any changes from Mesa
will do nothing. Kernel is already setting this bit in
CACHE_MODE_SS register which is saved/restored to/from
the HW context image.

Signed-off-by: Anuj Phogat 
Cc: Lionel Landwerlin 
---
 src/mesa/drivers/dri/i965/brw_state_upload.c | 4 
 1 file changed, 4 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c 
b/src/mesa/drivers/dri/i965/brw_state_upload.c
index d8273aa5734..757426407c3 100644
--- a/src/mesa/drivers/dri/i965/brw_state_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_state_upload.c
@@ -64,10 +64,6 @@ brw_upload_initial_gpu_state(struct brw_context *brw)
brw_upload_invariant_state(brw);
 
if (devinfo->gen == 10 || devinfo->gen == 11) {
-  brw_load_register_imm32(brw, GEN10_CACHE_MODE_SS,
-  REG_MASK(GEN10_FLOAT_BLEND_OPTIMIZATION_ENABLE) |
-  GEN10_FLOAT_BLEND_OPTIMIZATION_ENABLE);
-
   /* From gen10 workaround table in h/w specs:
*
*"On 3DSTATE_3D_MODE, driver must always program bits 31:16 of DW1
-- 
2.17.0

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[Mesa-dev] [PATCH] i965/glk: Add l3 banks count for 2x6 configuration

[Anuj Phogat]

2x6 configuration with pci-id 0x3185 has same number of
banks (2) as 3x6 configuration (pci-id 0x3184).

Reported-by: Clayton Craft <clayton.a.cr...@intel.com>
Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com>
Cc: <mesa-sta...@lists.freedesktop.org>
Cc: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Cc: Francisco Jerez <curroje...@riseup.net>
---
 src/intel/dev/gen_device_info.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/intel/dev/gen_device_info.c b/src/intel/dev/gen_device_info.c
index 653cece6d70..8e971329892 100644
--- a/src/intel/dev/gen_device_info.c
+++ b/src/intel/dev/gen_device_info.c
@@ -732,10 +732,10 @@ static const struct gen_device_info gen_device_info_glk = 
{
.l3_banks = 2,
 };
 
-/*TODO: Initialize l3_banks when we know the number. */
 static const struct gen_device_info gen_device_info_glk_2x6 = {
GEN9_LP_FEATURES_2X6,
.is_geminilake = true,
+   .l3_banks = 2,
 };
 
 static const struct gen_device_info gen_device_info_cfl_gt1 = {
-- 
2.17.0

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Re: [Mesa-dev] [PATCH 2/2] intel/isl/storage: Don't lower most UNORM formats on gen11+

[Anuj Phogat]

Yes, I did. No regressions.

On Thu, May 10, 2018 at 12:09 PM, Jason Ekstrand <ja...@jlekstrand.net> wrote:
> Did you get a chance to test them?
>
>
> On May 10, 2018 11:58:54 Anuj Phogat <anuj.pho...@gmail.com> wrote:
>
>> On Mon, May 7, 2018 at 2:56 PM, Jason Ekstrand <ja...@jlekstrand.net>
>> wrote:
>>>
>>> ---
>>>  src/intel/isl/isl_storage_image.c | 16 ++--
>>>  1 file changed, 10 insertions(+), 6 deletions(-)
>>>
>>> diff --git a/src/intel/isl/isl_storage_image.c
>>> b/src/intel/isl/isl_storage_image.c
>>> index 20f6fd5..ed1c600 100644
>>> --- a/src/intel/isl/isl_storage_image.c
>>> +++ b/src/intel/isl/isl_storage_image.c
>>> @@ -161,32 +161,36 @@ isl_lower_storage_image_format(const struct
>>> gen_device_info *devinfo,
>>> /* No normalized fixed-point formats are supported by the hardware.
>>> */
>>> case ISL_FORMAT_R16G16B16A16_UNORM:
>>> case ISL_FORMAT_R16G16B16A16_SNORM:
>>> -  return (devinfo->gen >= 8 || devinfo->is_haswell ?
>>> +  return (devinfo->gen >= 11 ? format :
>>> +  devinfo->gen >= 8 || devinfo->is_haswell ?
>>>ISL_FORMAT_R16G16B16A16_UINT :
>>>ISL_FORMAT_R32G32_UINT);
>>>
>>> case ISL_FORMAT_R8G8B8A8_UNORM:
>>> case ISL_FORMAT_R8G8B8A8_SNORM:
>>> -  return (devinfo->gen >= 8 || devinfo->is_haswell ?
>>> +  return (devinfo->gen >= 11 ? format :
>>> +  devinfo->gen >= 8 || devinfo->is_haswell ?
>>>ISL_FORMAT_R8G8B8A8_UINT : ISL_FORMAT_R32_UINT);
>>>
>>> case ISL_FORMAT_R16G16_UNORM:
>>> case ISL_FORMAT_R16G16_SNORM:
>>> -  return (devinfo->gen >= 8 || devinfo->is_haswell ?
>>> +  return (devinfo->gen >= 11 ? format :
>>> +  devinfo->gen >= 8 || devinfo->is_haswell ?
>>>ISL_FORMAT_R16G16_UINT : ISL_FORMAT_R32_UINT);
>>>
>>> case ISL_FORMAT_R8G8_UNORM:
>>> case ISL_FORMAT_R8G8_SNORM:
>>> -  return (devinfo->gen >= 8 || devinfo->is_haswell ?
>>> +  return (devinfo->gen >= 11 ? format :
>>> +  devinfo->gen >= 8 || devinfo->is_haswell ?
>>>ISL_FORMAT_R8G8_UINT : ISL_FORMAT_R16_UINT);
>>>
>>> case ISL_FORMAT_R16_UNORM:
>>> case ISL_FORMAT_R16_SNORM:
>>> -  return ISL_FORMAT_R16_UINT;
>>> +  return (devinfo->gen >= 11 ? format : ISL_FORMAT_R16_UINT);
>>>
>>> case ISL_FORMAT_R8_UNORM:
>>> case ISL_FORMAT_R8_SNORM:
>>> -  return ISL_FORMAT_R8_UINT;
>>> +  return (devinfo->gen >= 11 ? format : ISL_FORMAT_R8_UINT);
>>>
>>> default:
>>>assert(!"Unknown image format");
>>> --
>>> 2.5.0.400.gff86faf
>>>
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>>
>>
>> Both patches are:
>> Reviewed-by and Tested-by: Anuj Phogat <anuj.pho...@gmail.com>
>
>
>
>
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Re: [Mesa-dev] [PATCH 2/2] intel/isl/storage: Don't lower most UNORM formats on gen11+

[Anuj Phogat]

On Mon, May 7, 2018 at 2:56 PM, Jason Ekstrand <ja...@jlekstrand.net> wrote:
> ---
>  src/intel/isl/isl_storage_image.c | 16 ++--
>  1 file changed, 10 insertions(+), 6 deletions(-)
>
> diff --git a/src/intel/isl/isl_storage_image.c 
> b/src/intel/isl/isl_storage_image.c
> index 20f6fd5..ed1c600 100644
> --- a/src/intel/isl/isl_storage_image.c
> +++ b/src/intel/isl/isl_storage_image.c
> @@ -161,32 +161,36 @@ isl_lower_storage_image_format(const struct 
> gen_device_info *devinfo,
> /* No normalized fixed-point formats are supported by the hardware. */
> case ISL_FORMAT_R16G16B16A16_UNORM:
> case ISL_FORMAT_R16G16B16A16_SNORM:
> -  return (devinfo->gen >= 8 || devinfo->is_haswell ?
> +  return (devinfo->gen >= 11 ? format :
> +  devinfo->gen >= 8 || devinfo->is_haswell ?
>ISL_FORMAT_R16G16B16A16_UINT :
>ISL_FORMAT_R32G32_UINT);
>
> case ISL_FORMAT_R8G8B8A8_UNORM:
> case ISL_FORMAT_R8G8B8A8_SNORM:
> -  return (devinfo->gen >= 8 || devinfo->is_haswell ?
> +  return (devinfo->gen >= 11 ? format :
> +  devinfo->gen >= 8 || devinfo->is_haswell ?
>ISL_FORMAT_R8G8B8A8_UINT : ISL_FORMAT_R32_UINT);
>
> case ISL_FORMAT_R16G16_UNORM:
> case ISL_FORMAT_R16G16_SNORM:
> -  return (devinfo->gen >= 8 || devinfo->is_haswell ?
> +  return (devinfo->gen >= 11 ? format :
> +  devinfo->gen >= 8 || devinfo->is_haswell ?
>ISL_FORMAT_R16G16_UINT : ISL_FORMAT_R32_UINT);
>
> case ISL_FORMAT_R8G8_UNORM:
> case ISL_FORMAT_R8G8_SNORM:
> -  return (devinfo->gen >= 8 || devinfo->is_haswell ?
> +  return (devinfo->gen >= 11 ? format :
> +  devinfo->gen >= 8 || devinfo->is_haswell ?
>ISL_FORMAT_R8G8_UINT : ISL_FORMAT_R16_UINT);
>
> case ISL_FORMAT_R16_UNORM:
> case ISL_FORMAT_R16_SNORM:
> -  return ISL_FORMAT_R16_UINT;
> +  return (devinfo->gen >= 11 ? format : ISL_FORMAT_R16_UINT);
>
> case ISL_FORMAT_R8_UNORM:
> case ISL_FORMAT_R8_SNORM:
> -  return ISL_FORMAT_R8_UINT;
> +  return (devinfo->gen >= 11 ? format : ISL_FORMAT_R8_UINT);
>
> default:
>    assert(!"Unknown image format");
> --
> 2.5.0.400.gff86faf
>
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Both patches are:
Reviewed-by and Tested-by: Anuj Phogat <anuj.pho...@gmail.com>
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Re: [Mesa-dev] [PATCH] spirv: Apply OriginUpperLeft to FragCoord

[Anuj Phogat]

On Wed, May 2, 2018 at 10:49 AM, Neil Roberts <nrobe...@igalia.com> wrote:
> This behaviour was changed in 1e5b09f42f694687ac. The commit message
> for that says it is just a “tidy up” so my assumption is that the
> behaviour change was a mistake. It’s a little hard to decipher looking
> at the diff, but the previous code before that patch was:
>
>   if (builtin == SpvBuiltInFragCoord || builtin == SpvBuiltInSamplePosition)
>  nir_var->data.origin_upper_left = b->origin_upper_left;
>
>   if (builtin == SpvBuiltInFragCoord)
>  nir_var->data.pixel_center_integer = b->pixel_center_integer;
>
> After the patch the code was:
>
>   case SpvBuiltInSamplePosition:
>  nir_var->data.origin_upper_left = b->origin_upper_left;
>  /* fallthrough */
>   case SpvBuiltInFragCoord:
>  nir_var->data.pixel_center_integer = b->pixel_center_integer;
>  break;
>
> Before the patch origin_upper_left affected both builtins and
> pixel_center_integer only affected FragCoord. After the patch
> origin_upper_left only affects SamplePosition and pixel_center_integer
> affects both variables.
>
> This patch tries to restore the previous behaviour by changing the
> code to:
>
>   case SpvBuiltInFragCoord:
>  nir_var->data.pixel_center_integer = b->pixel_center_integer;
>  /* fallthrough */
>   case SpvBuiltInSamplePosition:
>  nir_var->data.origin_upper_left = b->origin_upper_left;
>  break;
>
> This change will be important for ARB_gl_spirv which is meant to
> support OriginLowerLeft.
> ---
>  src/compiler/spirv/vtn_variables.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/src/compiler/spirv/vtn_variables.c 
> b/src/compiler/spirv/vtn_variables.c
> index 9679ff6526c..fd8ab7f247a 100644
> --- a/src/compiler/spirv/vtn_variables.c
> +++ b/src/compiler/spirv/vtn_variables.c
> @@ -1419,11 +1419,11 @@ apply_var_decoration(struct vtn_builder *b, 
> nir_variable *nir_var,
>case SpvBuiltInTessLevelInner:
>   nir_var->data.compact = true;
>   break;
> -  case SpvBuiltInSamplePosition:
> - nir_var->data.origin_upper_left = b->origin_upper_left;
> - /* fallthrough */
>case SpvBuiltInFragCoord:
>   nir_var->data.pixel_center_integer = b->pixel_center_integer;
> + /* fallthrough */
> +  case SpvBuiltInSamplePosition:
> + nir_var->data.origin_upper_left = b->origin_upper_left;
>   break;
>default:
>   break;
> --
> 2.14.3
>
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Re: [Mesa-dev] [PATCH] intel: fix aubinator include

[Anuj Phogat]

On Wed, May 2, 2018 at 9:52 AM, Lionel Landwerlin
<lionel.g.landwer...@intel.com> wrote:
> Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>
> Fixes: 7c22c150c40b3 ("intel: Move batch decoder/disassembler from tools/ to 
> common/")
> ---
>  src/intel/tools/aubinator.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/src/intel/tools/aubinator.c b/src/intel/tools/aubinator.c
> index ab053c66b36..bc263dbf846 100644
> --- a/src/intel/tools/aubinator.c
> +++ b/src/intel/tools/aubinator.c
> @@ -40,8 +40,8 @@
>  #include "util/macros.h"
>
>  #include "common/gen_decoder.h"
> +#include "common/gen_disasm.h"
>  #include "intel_aub.h"
> -#include "gen_disasm.h"
>
>  /* Below is the only command missing from intel_aub.h in libdrm
>   * So, reuse intel_aub.h from libdrm and #define the
> --
> 2.17.0
>
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Reviewed-by: Anuj Phogat <anuj.pho...@gmail.com>
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Re: [Mesa-dev] [PATCH] anv: Advertise variableMultisampleRate

[Anuj Phogat]

On Mon, Apr 30, 2018 at 3:10 PM, Jason Ekstrand <ja...@jlekstrand.net> wrote:
>
> Initially, I didn't understand this feature.  Turns out that all it
> means is that you can switch multisample rates in the middle of a
> zero-attachment subpass.  We've been able to do this since forever.
> ---
>  src/intel/vulkan/anv_device.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
> index 202fe73..adcd506 100644
> --- a/src/intel/vulkan/anv_device.c
> +++ b/src/intel/vulkan/anv_device.c
> @@ -761,7 +761,7 @@ void anv_GetPhysicalDeviceFeatures(
>.shaderInt64  = pdevice->info.gen >= 8,
>.shaderInt16  = false,
>.shaderResourceMinLod = false,
> -  .variableMultisampleRate  = false,
> +  .variableMultisampleRate  = true,
>.inheritedQueries = true,
> };
>
> --
> 2.5.0.400.gff86faf
>
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Reviewed-by: Anuj Phogat <anuj.pho...@gmail.com>
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Re: [Mesa-dev] [PATCH] anv: Don't advertise Float64 or Int64 on HW withou 64-bit types

[Anuj Phogat]

On Mon, Apr 30, 2018 at 3:15 PM, Jason Ekstrand <ja...@jlekstrand.net>
wrote:

> ---
>  src/intel/vulkan/anv_device.c | 6 --
>  1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
> index adcd506..e82f294 100644
> --- a/src/intel/vulkan/anv_device.c
> +++ b/src/intel/vulkan/anv_device.c
> @@ -757,8 +757,10 @@ void anv_GetPhysicalDeviceFeatures(
>.shaderStorageImageArrayDynamicIndexing   = true,
>.shaderClipDistance   = true,
>.shaderCullDistance   = true,
> -  .shaderFloat64= pdevice->info.gen >= 8,
> -  .shaderInt64  = pdevice->info.gen >= 8,
> +  .shaderFloat64= pdevice->info.gen >= 8
> &&
> +
> pdevice->info.has_64bit_types,
> +  .shaderInt64  = pdevice->info.gen >= 8
> &&
> +
> pdevice->info.has_64bit_types,
>.shaderInt16  = false,
>.shaderResourceMinLod = false,
>.variableMultisampleRate  = true,
> --
> 2.5.0.400.gff86faf
>
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​s/withou/without in subject. With typo fixed:​
​Reviewed-by: Anuj Phogat <anuj.pho...@gmail.com>​
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[Mesa-dev] [PATCH] anv/icl: Enable Vulkan on Ice Lake

[Anuj Phogat]

This patch enables the Vulkan driver on Ice Lake h/w
with added warning about preliminary support.

Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com>
---
 src/intel/vulkan/anv_device.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index 7522b7865c..b456d3d4c5 100644
--- a/src/intel/vulkan/anv_device.c
+++ b/src/intel/vulkan/anv_device.c
@@ -323,6 +323,8 @@ anv_physical_device_init(struct anv_physical_device *device,
   intel_logw("Bay Trail Vulkan support is incomplete");
} else if (device->info.gen >= 8 && device->info.gen <= 10) {
   /* Gen8-10 fully supported */
+   } else if (device->info.gen == 11) {
+  intel_logw("Vulkan is not yet fully supported on gen11.");
} else {
   result = vk_errorf(device->instance, device,
  VK_ERROR_INCOMPATIBLE_DRIVER,
-- 
2.13.6

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Re: [Mesa-dev] [PATCH] i965/urb/cnl: Apply gen7 CS stall

[Anuj Phogat]

On Thu, Apr 19, 2018 at 7:44 AM, Topi Pohjolainen <
topi.pohjolai...@gmail.com> wrote:

> This didn't actually help the failing tests I'm looking at
> but hopefully has teeth elsewhere.
>
> CC: Jason Ekstrand <ja...@jlekstrand.net>
> CC: Jordan Justen <jordan.l.jus...@intel.com>
> CC: Anuj Phogat <anuj.pho...@gmail.com>
> Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com>
> ---
>  src/mesa/drivers/dri/i965/gen7_urb.c | 9 -
>  1 file changed, 8 insertions(+), 1 deletion(-)
>
> diff --git a/src/mesa/drivers/dri/i965/gen7_urb.c
> b/src/mesa/drivers/dri/i965/gen7_urb.c
> index 2e5f8e6..9e12657 100644
> --- a/src/mesa/drivers/dri/i965/gen7_urb.c
> +++ b/src/mesa/drivers/dri/i965/gen7_urb.c
> @@ -145,8 +145,15 @@ gen7_emit_push_constant_state(struct brw_context
> *brw, unsigned vs_size,
>  * in the ring after this instruction.
>  *
>  * No such restriction exists for Haswell or Baytrail.
> +*
> +* From the CNL Bspec, Windower -
> +* 3DSTATE_PUSH_CONSTANT_ALLOC_PS/VS/GS/DS/HS:
> +*
> +* This command must be followed by a PIPE_CONTROL with CS Stall
> bit
> +* set.
>  */
> -   if (devinfo->gen < 8 && !devinfo->is_haswell && !devinfo->is_baytrail)
> +   if ((devinfo->gen < 8 && !devinfo->is_haswell &&
> !devinfo->is_baytrail) ||
> +   devinfo->gen >= 10)
>gen7_emit_cs_stall_flush(brw);
>  }
>
> --
> 2.7.4
>
>
​Verified in BSpec.
​Reviewed-by: Anuj Phogat <anuj.pho...@gmail.com>
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Re: [Mesa-dev] [PATCH 2/2] i965/blorp: Do the gen11 BTI flush

[Anuj Phogat]

For the series:
Reviewed-by: Anuj Phogat <anuj.pho...@gmail.com>

This might explain piglit GPU hangs or failures. I'll do a piglit run with
these patches.
Thanks
Anuj

On Tue, Apr 17, 2018 at 3:10 PM, Jason Ekstrand <ja...@jlekstrand.net>
wrote:

> ---
>  src/mesa/drivers/dri/i965/genX_blorp_exec.c | 14 ++
>  1 file changed, 14 insertions(+)
>
> diff --git a/src/mesa/drivers/dri/i965/genX_blorp_exec.c
> b/src/mesa/drivers/dri/i965/genX_blorp_exec.c
> index 3406a6f..a6cb0e3 100644
> --- a/src/mesa/drivers/dri/i965/genX_blorp_exec.c
> +++ b/src/mesa/drivers/dri/i965/genX_blorp_exec.c
> @@ -241,6 +241,20 @@ genX(blorp_exec)(struct blorp_batch *batch,
> struct gl_context *ctx = >ctx;
> bool check_aperture_failed_once = false;
>
> +#if GEN_GEN >= 11
> +   /* The PIPE_CONTROL command description says:
> +*
> +* "Whenever a Binding Table Index (BTI) used by a Render Taget Message
> +*  points to a different RENDER_SURFACE_STATE, SW must issue a Render
> +*  Target Cache Flush by enabling this bit. When render target flush
> +*  is set due to new association of BTI, PS Scoreboard Stall bit must
> +*  be set in this packet."
> +   */
> +   brw_emit_pipe_control_flush(brw,
> +   PIPE_CONTROL_RENDER_TARGET_FLUSH |
> +   PIPE_CONTROL_STALL_AT_SCOREBOARD);
> +#endif
> +
> /* Flush the sampler and render caches.  We definitely need to flush
> the
>  * sampler cache so that we get updated contents from the render cache
> for
>  * the glBlitFramebuffer() source.  Also, we are sometimes warned in
> the
> --
> 2.5.0.400.gff86faf
>
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[Mesa-dev] [PATCH] Add more Coffee Lake brand strings

[Anuj Phogat]

Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com>
---
 include/pci_ids/i965_pci_ids.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/include/pci_ids/i965_pci_ids.h b/include/pci_ids/i965_pci_ids.h
index 8716d758f0..c740a50bca 100644
--- a/include/pci_ids/i965_pci_ids.h
+++ b/include/pci_ids/i965_pci_ids.h
@@ -165,8 +165,8 @@ CHIPSET(0x5927, kbl_gt3, "Intel(R) Iris Plus Graphics 650 
(Kaby Lake GT3e)")
 CHIPSET(0x593B, kbl_gt4, "Intel(R) Kabylake GT4")
 CHIPSET(0x3184, glk, "Intel(R) UHD Graphics 605 (Geminilake)")
 CHIPSET(0x3185, glk_2x6, "Intel(R) UHD Graphics 600 (Geminilake 2x6)")
-CHIPSET(0x3E90, cfl_gt1, "Intel(R) HD Graphics (Coffeelake 2x6 GT1)")
-CHIPSET(0x3E93, cfl_gt1, "Intel(R) HD Graphics (Coffeelake 2x6 GT1)")
+CHIPSET(0x3E90, cfl_gt1, "Intel(R) UHD Graphics 610 (Coffeelake 2x6 GT1)")
+CHIPSET(0x3E93, cfl_gt1, "Intel(R) UHD Graphics 610 (Coffeelake 2x6 GT1)")
 CHIPSET(0x3E99, cfl_gt1, "Intel(R) HD Graphics (Coffeelake 2x6 GT1)")
 CHIPSET(0x3EA1, cfl_gt1, "Intel(R) HD Graphics (Coffeelake 2x6 GT1)")
 CHIPSET(0x3EA4, cfl_gt1, "Intel(R) HD Graphics (Coffeelake 2x6 GT1)")
-- 
2.13.6

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Re: [Mesa-dev] [PATCH 01/17] intel: Add a preliminary device for Ice Lake

[Anuj Phogat]

On Wed, Feb 21, 2018 at 11:04 AM, Matt Turner <matts...@gmail.com> wrote:
> On Wed, Feb 21, 2018 at 10:37 AM, Anuj Phogat <anuj.pho...@gmail.com> wrote:
>> On Wed, Feb 21, 2018 at 9:22 AM, Rafael Antognolli
>> <rafael.antogno...@intel.com> wrote:
>>> My understanding is that this commit is enough to make the driver try to
>>> initialize, at least for i965. If that's the case, how about we add
>>> something like what was removed by commit
>>> bf1577fe0972ae910c071743dc89d261a46c2926 for CNL?
>>>
>>> It could be either in this commit, or in a commit that precedes this
>>> one. Anv has an extra check for gen <= 10, so we don't need to worry
>>> there yet.
>> Yes, It'll be great to add a similar patch before this one. Also, I
>> think this patch should be the last patch in this series. Otherwise we'll
>> have a commit with ICL PCI IDs but missing compiler changes. Almost
>> nothing will work without the compiler patches.
>
> Good point. The reason I moved it here was because a few of my patches
> add new fields to GEN11_FEATURES. How about I split the patch in two:
> one that modifies gen_device_info.c and another for later that
> actually adds the PCI IDs?
Sounds good to me.
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Re: [Mesa-dev] [PATCH 01/17] intel: Add a preliminary device for Ice Lake

[Anuj Phogat]

On Wed, Feb 21, 2018 at 9:22 AM, Rafael Antognolli
<rafael.antogno...@intel.com> wrote:
> My understanding is that this commit is enough to make the driver try to
> initialize, at least for i965. If that's the case, how about we add
> something like what was removed by commit
> bf1577fe0972ae910c071743dc89d261a46c2926 for CNL?
>
> It could be either in this commit, or in a commit that precedes this
> one. Anv has an extra check for gen <= 10, so we don't need to worry
> there yet.
Yes, It'll be great to add a similar patch before this one. Also, I
think this patch should be the last patch in this series. Otherwise we'll
have a commit with ICL PCI IDs but missing compiler changes. Almost
nothing will work without the compiler patches.

>
> Rafael
>
> On Tue, Feb 20, 2018 at 09:15:08PM -0800, Matt Turner wrote:
>> From: Anuj Phogat <anuj.pho...@intel.com>
>>
>> Signed-off-by: Anuj Phogat <anuj.pho...@intel.com>
>> ---
>>  include/pci_ids/i965_pci_ids.h |  9 ++
>>  src/intel/common/gen_device_info.c | 56 
>> +-
>>  2 files changed, 64 insertions(+), 1 deletion(-)
>>
>> diff --git a/include/pci_ids/i965_pci_ids.h b/include/pci_ids/i965_pci_ids.h
>> index feb9c582b19..81c9a5f13fb 100644
>> --- a/include/pci_ids/i965_pci_ids.h
>> +++ b/include/pci_ids/i965_pci_ids.h
>> @@ -196,3 +196,12 @@ CHIPSET(0x5A50, cnl_5x8, "Intel(R) HD Graphics 
>> (Cannonlake 5x8 GT2)")
>>  CHIPSET(0x5A51, cnl_5x8, "Intel(R) HD Graphics (Cannonlake 5x8 GT2)")
>>  CHIPSET(0x5A52, cnl_5x8, "Intel(R) HD Graphics (Cannonlake 5x8 GT2)")
>>  CHIPSET(0x5A54, cnl_5x8, "Intel(R) HD Graphics (Cannonlake 5x8 GT2)")
>> +CHIPSET(0x8A50, icl_8x8, "Intel(R) HD Graphics (Ice Lake 8x8 GT2)")
>> +CHIPSET(0x8A51, icl_8x8, "Intel(R) HD Graphics (Ice Lake 8x8 GT2)")
>> +CHIPSET(0x8A52, icl_8x8, "Intel(R) HD Graphics (Ice Lake 8x8 GT2)")
>> +CHIPSET(0x8A5A, icl_6x8, "Intel(R) HD Graphics (Ice Lake 6x8 GT1.5)")
>> +CHIPSET(0x8A5B, icl_4x8, "Intel(R) HD Graphics (Ice Lake 4x8 GT1)")
>> +CHIPSET(0x8A5C, icl_6x8, "Intel(R) HD Graphics (Ice Lake 6x8 GT1.5)")
>> +CHIPSET(0x8A5D, icl_4x8, "Intel(R) HD Graphics (Ice Lake 4x8 GT1)")
>> +CHIPSET(0x8A71, icl_1x8, "Intel(R) HD Graphics (Ice Lake 1x8 GT0.5)")
>> +CHIPSET(0xFF05, icl_8x8, "Intel(R) HD Graphics (Ice Lake Simulation)")
>> diff --git a/src/intel/common/gen_device_info.c 
>> b/src/intel/common/gen_device_info.c
>> index a08a13a32a4..8bf4b6b9bb0 100644
>> --- a/src/intel/common/gen_device_info.c
>> +++ b/src/intel/common/gen_device_info.c
>> @@ -731,6 +731,49 @@ static const struct gen_device_info 
>> gen_device_info_cnl_5x8 = {
>> .is_cannonlake = true,
>>  };
>>
>> +#define GEN11_HW_INFO   \
>> +   .gen = 11,   \
>> +   .has_pln = false,\
>> +   .max_vs_threads = 364,   \
>> +   .max_gs_threads = 224,   \
>> +   .max_tcs_threads = 224,  \
>> +   .max_tes_threads = 364,  \
>> +   .max_cs_threads = 56,\
>> +   .urb = { \
>> +  .size = 1024, \
>> +  .min_entries = {  \
>> + [MESA_SHADER_VERTEX]= 64,  \
>> + [MESA_SHADER_TESS_EVAL] = 34,  \
>> +  },\
>> +  .max_entries = {  \
>> + [MESA_SHADER_VERTEX]= 2384,\
>> + [MESA_SHADER_TESS_CTRL] = 1032,\
>> + [MESA_SHADER_TESS_EVAL] = 2384,\
>> + [MESA_SHADER_GEOMETRY]  = 1032,\
>> +  },\
>> +   }
>> +
>> +#define GEN11_FEATURES(_gt, _slices, _l3)   \
>> +   GEN8_FEATURES,   \
>> +   GEN11_HW_INFO,   \
>> +   .gt = _gt, .num_slices = _slices, .l3_banks = _l3
>> +
>> +static const struct gen_device_info gen_device_info_icl_8x8 = {
>> +   GEN11_FEATURES(2, 1, 8),
>> +};
>> +
>> +static const struct gen_device_info gen_device_info_icl_6x8 = {
>> +   GEN11_FEATURES(1, 1, 6),
>> +};
>> +
>> +static const struct gen_device_info gen_device_info_icl_4x8 = {

Re: [Mesa-dev] [PATCH 01/17] intel: Add a preliminary device for Ice Lake

[Anuj Phogat]

On Wed, Feb 21, 2018 at 11:09 AM, Scott D Phillips
<scott.d.phill...@intel.com> wrote:
> Anuj Phogat <anuj.pho...@gmail.com> writes:
>
>> On Wed, Feb 21, 2018 at 10:00 AM, Scott D Phillips
>> <scott.d.phill...@intel.com> wrote:
>>> Matt Turner <matts...@gmail.com> writes:
>>>
>>>> From: Anuj Phogat <anuj.pho...@intel.com>
>>>>
>>>> Signed-off-by: Anuj Phogat <anuj.pho...@intel.com>
>>>> ---
>>>>  include/pci_ids/i965_pci_ids.h |  9 ++
>>>>  src/intel/common/gen_device_info.c | 56 
>>>> +-
>>>>  2 files changed, 64 insertions(+), 1 deletion(-)
>>>>
>>>> diff --git a/include/pci_ids/i965_pci_ids.h 
>>>> b/include/pci_ids/i965_pci_ids.h
>>>> index feb9c582b19..81c9a5f13fb 100644
>>>> --- a/include/pci_ids/i965_pci_ids.h
>>>> +++ b/include/pci_ids/i965_pci_ids.h
>>>> @@ -196,3 +196,12 @@ CHIPSET(0x5A50, cnl_5x8, "Intel(R) HD Graphics 
>>>> (Cannonlake 5x8 GT2)")
>>>>  CHIPSET(0x5A51, cnl_5x8, "Intel(R) HD Graphics (Cannonlake 5x8 GT2)")
>>>>  CHIPSET(0x5A52, cnl_5x8, "Intel(R) HD Graphics (Cannonlake 5x8 GT2)")
>>>>  CHIPSET(0x5A54, cnl_5x8, "Intel(R) HD Graphics (Cannonlake 5x8 GT2)")
>>>> +CHIPSET(0x8A50, icl_8x8, "Intel(R) HD Graphics (Ice Lake 8x8 GT2)")
>>>> +CHIPSET(0x8A51, icl_8x8, "Intel(R) HD Graphics (Ice Lake 8x8 GT2)")
>>>> +CHIPSET(0x8A52, icl_8x8, "Intel(R) HD Graphics (Ice Lake 8x8 GT2)")
>>>> +CHIPSET(0x8A5A, icl_6x8, "Intel(R) HD Graphics (Ice Lake 6x8 GT1.5)")
>>>> +CHIPSET(0x8A5B, icl_4x8, "Intel(R) HD Graphics (Ice Lake 4x8 GT1)")
>>>> +CHIPSET(0x8A5C, icl_6x8, "Intel(R) HD Graphics (Ice Lake 6x8 GT1.5)")
>>>> +CHIPSET(0x8A5D, icl_4x8, "Intel(R) HD Graphics (Ice Lake 4x8 GT1)")
>>>> +CHIPSET(0x8A71, icl_1x8, "Intel(R) HD Graphics (Ice Lake 1x8 GT0.5)")
>>>> +CHIPSET(0xFF05, icl_8x8, "Intel(R) HD Graphics (Ice Lake Simulation)")
>>>
>>> Simulation should be removed.
>>>
>>>> diff --git a/src/intel/common/gen_device_info.c 
>>>> b/src/intel/common/gen_device_info.c
>>>> index a08a13a32a4..8bf4b6b9bb0 100644
>>>> --- a/src/intel/common/gen_device_info.c
>>>> +++ b/src/intel/common/gen_device_info.c
>>>> @@ -731,6 +731,49 @@ static const struct gen_device_info 
>>>> gen_device_info_cnl_5x8 = {
>>>> .is_cannonlake = true,
>>>>  };
>>>>
>>>> +#define GEN11_HW_INFO   \
>>>> +   .gen = 11,   \
>>>> +   .has_pln = false,\
>>>> +   .max_vs_threads = 364,   \
>>>> +   .max_gs_threads = 224,   \
>>>> +   .max_tcs_threads = 224,  \
>>>> +   .max_tes_threads = 364,  \
>>>> +   .max_cs_threads = 56,\
>>>> +   .urb = { \
>>>> +  .size = 1024, \
>>>> +  .min_entries = {  \
>>>> + [MESA_SHADER_VERTEX]= 64,  \
>>>> + [MESA_SHADER_TESS_EVAL] = 34,  \
>>>> +  },\
>>>> +  .max_entries = {  \
>>>> + [MESA_SHADER_VERTEX]= 2384,\
>>>> + [MESA_SHADER_TESS_CTRL] = 1032,\
>>>> + [MESA_SHADER_TESS_EVAL] = 2384,\
>>>> + [MESA_SHADER_GEOMETRY]  = 1032,\
>>>> +  },\
>>>> +   }
>>>> +
>>>> +#define GEN11_FEATURES(_gt, _slices, _l3)   \
>>>> +   GEN8_FEATURES,   \
>>>> +   GEN11_HW_INFO,   \
>>>> +   .gt = _gt, .num_slices = _slices, .l3_banks = _l3
>>>> +
>>>> +static const struct gen_device_info gen_device_info_icl_8x8 = {
>>>> +   GEN11_FEATURES(2, 1, 8),
>>>> +};
>>>> +
>>>> +static const struct gen_device_info gen_device_info_icl_6x8 = {
>>>> +   GEN11_FE

Re: [Mesa-dev] [PATCH 01/17] intel: Add a preliminary device for Ice Lake

[Anuj Phogat]

On Wed, Feb 21, 2018 at 10:00 AM, Scott D Phillips
<scott.d.phill...@intel.com> wrote:
> Matt Turner <matts...@gmail.com> writes:
>
>> From: Anuj Phogat <anuj.pho...@intel.com>
>>
>> Signed-off-by: Anuj Phogat <anuj.pho...@intel.com>
>> ---
>>  include/pci_ids/i965_pci_ids.h |  9 ++
>>  src/intel/common/gen_device_info.c | 56 
>> +-
>>  2 files changed, 64 insertions(+), 1 deletion(-)
>>
>> diff --git a/include/pci_ids/i965_pci_ids.h b/include/pci_ids/i965_pci_ids.h
>> index feb9c582b19..81c9a5f13fb 100644
>> --- a/include/pci_ids/i965_pci_ids.h
>> +++ b/include/pci_ids/i965_pci_ids.h
>> @@ -196,3 +196,12 @@ CHIPSET(0x5A50, cnl_5x8, "Intel(R) HD Graphics 
>> (Cannonlake 5x8 GT2)")
>>  CHIPSET(0x5A51, cnl_5x8, "Intel(R) HD Graphics (Cannonlake 5x8 GT2)")
>>  CHIPSET(0x5A52, cnl_5x8, "Intel(R) HD Graphics (Cannonlake 5x8 GT2)")
>>  CHIPSET(0x5A54, cnl_5x8, "Intel(R) HD Graphics (Cannonlake 5x8 GT2)")
>> +CHIPSET(0x8A50, icl_8x8, "Intel(R) HD Graphics (Ice Lake 8x8 GT2)")
>> +CHIPSET(0x8A51, icl_8x8, "Intel(R) HD Graphics (Ice Lake 8x8 GT2)")
>> +CHIPSET(0x8A52, icl_8x8, "Intel(R) HD Graphics (Ice Lake 8x8 GT2)")
>> +CHIPSET(0x8A5A, icl_6x8, "Intel(R) HD Graphics (Ice Lake 6x8 GT1.5)")
>> +CHIPSET(0x8A5B, icl_4x8, "Intel(R) HD Graphics (Ice Lake 4x8 GT1)")
>> +CHIPSET(0x8A5C, icl_6x8, "Intel(R) HD Graphics (Ice Lake 6x8 GT1.5)")
>> +CHIPSET(0x8A5D, icl_4x8, "Intel(R) HD Graphics (Ice Lake 4x8 GT1)")
>> +CHIPSET(0x8A71, icl_1x8, "Intel(R) HD Graphics (Ice Lake 1x8 GT0.5)")
>> +CHIPSET(0xFF05, icl_8x8, "Intel(R) HD Graphics (Ice Lake Simulation)")
>
> Simulation should be removed.
>
>> diff --git a/src/intel/common/gen_device_info.c 
>> b/src/intel/common/gen_device_info.c
>> index a08a13a32a4..8bf4b6b9bb0 100644
>> --- a/src/intel/common/gen_device_info.c
>> +++ b/src/intel/common/gen_device_info.c
>> @@ -731,6 +731,49 @@ static const struct gen_device_info 
>> gen_device_info_cnl_5x8 = {
>> .is_cannonlake = true,
>>  };
>>
>> +#define GEN11_HW_INFO   \
>> +   .gen = 11,   \
>> +   .has_pln = false,\
>> +   .max_vs_threads = 364,   \
>> +   .max_gs_threads = 224,   \
>> +   .max_tcs_threads = 224,  \
>> +   .max_tes_threads = 364,  \
>> +   .max_cs_threads = 56,\
>> +   .urb = { \
>> +  .size = 1024, \
>> +  .min_entries = {  \
>> + [MESA_SHADER_VERTEX]= 64,  \
>> + [MESA_SHADER_TESS_EVAL] = 34,  \
>> +  },\
>> +  .max_entries = {  \
>> + [MESA_SHADER_VERTEX]= 2384,\
>> + [MESA_SHADER_TESS_CTRL] = 1032,\
>> + [MESA_SHADER_TESS_EVAL] = 2384,\
>> + [MESA_SHADER_GEOMETRY]  = 1032,\
>> +  },\
>> +   }
>> +
>> +#define GEN11_FEATURES(_gt, _slices, _l3)   \
>> +   GEN8_FEATURES,   \
>> +   GEN11_HW_INFO,   \
>> +   .gt = _gt, .num_slices = _slices, .l3_banks = _l3
>> +
>> +static const struct gen_device_info gen_device_info_icl_8x8 = {
>> +   GEN11_FEATURES(2, 1, 8),
>> +};
>> +
>> +static const struct gen_device_info gen_device_info_icl_6x8 = {
>> +   GEN11_FEATURES(1, 1, 6),
>> +};
>> +
>> +static const struct gen_device_info gen_device_info_icl_4x8 = {
>> +   GEN11_FEATURES(1, 1, 6),
>
> Should be 1, 1, 4 right?
>
We don't have device attributes listed in the docs for this SKU :(. But,
as I have understood number of subslices don't affect the number
of banks. L3 banks are part of Slice common. e.g. 1x4x8 and
1x6x8 have the same number of L3 banks.
>> +};
>> +
>> +static const struct gen_device_info gen_device_info_icl_1x8 = {
>> +   GEN11_FEATURES(1, 1, 6),
>
> 1, 1, 1 ?
>
>> +};
>> +
>>  bool
>>  gen_get_device_info(int devid, struct gen_device_info *devinfo)
>>  {
>> @@ -757,10 +800,21 @@ gen_get_device_info(int devid, struct gen_device_in

Re: [Mesa-dev] [PATCH 05/10] anv/icl: Don't use DISPATCH_MODE_SIMD4X2

[Anuj Phogat]

On Thu, Feb 15, 2018 at 6:07 PM, Jason Ekstrand <ja...@jlekstrand.net> wrote:
> On Thu, Feb 15, 2018 at 5:44 PM, Anuj Phogat <anuj.pho...@gmail.com> wrote:
>>
>> Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com>
>> ---
>>  src/intel/vulkan/genX_pipeline.c | 7 +++
>>  1 file changed, 7 insertions(+)
>>
>> diff --git a/src/intel/vulkan/genX_pipeline.c
>> b/src/intel/vulkan/genX_pipeline.c
>> index 85391c93ca..290d78e608 100644
>> --- a/src/intel/vulkan/genX_pipeline.c
>> +++ b/src/intel/vulkan/genX_pipeline.c
>> @@ -1124,6 +1124,9 @@ emit_3dstate_vs(struct anv_pipeline *pipeline)
>>pipeline->shaders[MESA_SHADER_VERTEX];
>>
>> assert(anv_pipeline_has_stage(pipeline, MESA_SHADER_VERTEX));
>> +#if GEN_GEN >= 11
>> +   assert(vs_prog_data->base.dispatch_mode == DISPATCH_MODE_SIMD8);
>> +#endif
>>
>> anv_batch_emit(>batch, GENX(3DSTATE_VS), vs) {
>>vs.Enable   = true;
>> @@ -1253,10 +1256,14 @@ emit_3dstate_hs_te_ds(struct anv_pipeline
>> *pipeline,
>>   tes_prog_data->base.base.dispatch_grf_start_reg;
>>
>>  #if GEN_GEN >= 8
>> +#if GEN_GEN < 11
>>ds.DispatchMode =
>>   tes_prog_data->base.dispatch_mode == DISPATCH_MODE_SIMD8 ?
>>  DISPATCH_MODE_SIMD8_SINGLE_PATCH :
>>  DISPATCH_MODE_SIMD4X2;
>> +#else
>
>
> You can just put the assert here.
>
Fixed locally. Thanks.
>>
>> +  ds.DispatchMode = DISPATCH_MODE_SIMD8_SINGLE_PATCH;
>> +#endif
>>
>>ds.UserClipDistanceClipTestEnableBitmask =
>>   tes_prog_data->base.clip_distance_mask;
>> --
>> 2.13.6
>>
>> ___
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>
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Re: [Mesa-dev] [PATCH 00/10] intel/anv: Prepare to add Ice Lake (ICL) support

[Anuj Phogat]

On Thu, Feb 15, 2018 at 6:14 PM, Jason Ekstrand <ja...@jlekstrand.net> wrote:
> I made a few fairly trivial comments but it all looks pretty good.
>
> Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net>
Thanks for the quick review Jason.

>
> On Thu, Feb 15, 2018 at 5:44 PM, Anuj Phogat <anuj.pho...@gmail.com> wrote:
>>
>> This series prepares the driver to enable Ice Lake support
>> in Vulkan driver. It wires up the build infrastructure and
>> make few ICL specific changes suggested by h/w documentation.
>> This is not everything we need to enable Vulkan on Ice Lake.
>
>
> How much is left?
>
Remaining bits are:
Compiler changes to remove line, pln and lrp
Add ICL L3 config
Separate SLM from L3
Add fp64 support
Add ICL device info
Add ICL workarounds

>>
>> Series is also available in my review branch at github.
>> https://github.com/aphogat/mesa.git
>>
>> Anuj Phogat (10):
>>   anv/icl: Add gen11 mocs defines
>>   anv/icl: Add #define genX
>>   anv/icl: Don't set ResetGatewayTimer
>>   anv/icl: Don't use SingleVertexDispatch
>>   anv/icl: Don't use DISPATCH_MODE_SIMD4X2
>>   anv/icl: Generate gen11 entry point functions
>>   anv/icl: Build anv libs for gen11
>>   anv/icl: Use gen11 functions
>>   anv/icl: Enable float blend optimization
>>   anv/icl: Add render target flush after uploading binding table
>>
>>  src/intel/Android.vulkan.mk | 21 +
>>  src/intel/Makefile.sources  |  4 
>>  src/intel/Makefile.vulkan.am|  7 ++-
>>  src/intel/vulkan/anv_blorp.c|  3 +++
>>  src/intel/vulkan/anv_device.c   |  3 +++
>>  src/intel/vulkan/anv_entrypoints_gen.py |  6 +-
>>  src/intel/vulkan/anv_private.h  | 14 ++
>>  src/intel/vulkan/genX_cmd_buffer.c  | 21 +
>>  src/intel/vulkan/genX_pipeline.c| 11 +++
>>  src/intel/vulkan/genX_state.c   |  2 +-
>>  src/intel/vulkan/meson.build|  2 +-
>>  11 files changed, 90 insertions(+), 4 deletions(-)
>>
>> --
>> 2.13.6
>>
>> ___
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>
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Re: [Mesa-dev] [PATCH 10/10] anv/icl: Add render target flush after uploading binding table

[Anuj Phogat]

On Thu, Feb 15, 2018 at 6:12 PM, Jason Ekstrand <ja...@jlekstrand.net> wrote:
>
>
> On Thu, Feb 15, 2018 at 5:44 PM, Anuj Phogat <anuj.pho...@gmail.com> wrote:
>>
>> The PIPE_CONTROL command description says:
>>
>> "Whenever a Binding Table Index (BTI) used by a Render Taget Message
>> points to a different RENDER_SURFACE_STATE, SW must issue a Render
>> Target Cache Flush by enabling this bit. When render target flush
>> is set due to new association of BTI, PS Scoreboard Stall bit must
>> be set in this packet."
>>
>> Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com>
>> ---
>>  src/intel/vulkan/genX_cmd_buffer.c | 21 +
>>  1 file changed, 21 insertions(+)
>>
>> diff --git a/src/intel/vulkan/genX_cmd_buffer.c
>> b/src/intel/vulkan/genX_cmd_buffer.c
>> index ce47b8a1cc..e2b6c281e4 100644
>> --- a/src/intel/vulkan/genX_cmd_buffer.c
>> +++ b/src/intel/vulkan/genX_cmd_buffer.c
>> @@ -2001,6 +2001,27 @@ emit_binding_table(struct anv_cmd_buffer
>> *cmd_buffer,
>>   out:
>> anv_state_flush(cmd_buffer->device, *bt_state);
>>
>> +#if GEN_GEN >= 11
>> +   /* The PIPE_CONTROL command description says:
>> +*
>> +* "Whenever a Binding Table Index (BTI) used by a Render Taget
>> Message
>> +*  points to a different RENDER_SURFACE_STATE, SW must issue a Render
>> +*  Target Cache Flush by enabling this bit. When render target flush
>> +*  is set due to new association of BTI, PS Scoreboard Stall bit must
>> +*  be set in this packet."
>
>
> We usually indent block quotes like this.
>
Fixed locally.
>>
>> +*
>> +*  FINISHME: Currently we shuffle around the surface states in the
>> +*  binding table based on if they are getting used or not. So, we've
>> +*  to do below pipe control flush for every binding table upload.
>> +*  Make changes so that we do it only when we modify render target
>> +*  surface states.
>> +*/
>> +   anv_batch_emit(_buffer->batch, GENX(PIPE_CONTROL), pc) {
>> +  pc.RenderTargetCacheFlushEnable  = true;
>> +  pc.StallAtPixelScoreboard= true;
>> +   }
>> +#endif
>> +
>> return VK_SUCCESS;
>>  }
>>
>> --
>> 2.13.6
>>
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Re: [Mesa-dev] [PATCH 09/10] anv/icl: Enable float blend optimization

[Anuj Phogat]

On Thu, Feb 15, 2018 at 6:13 PM, Jason Ekstrand <ja...@jlekstrand.net> wrote:
> On Thu, Feb 15, 2018 at 5:44 PM, Anuj Phogat <anuj.pho...@gmail.com> wrote:
>>
>> Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com>
>> ---
>>  src/intel/vulkan/genX_state.c | 2 +-
>>  1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/src/intel/vulkan/genX_state.c b/src/intel/vulkan/genX_state.c
>> index 54fb8634fd..f39508034f 100644
>> --- a/src/intel/vulkan/genX_state.c
>> +++ b/src/intel/vulkan/genX_state.c
>> @@ -121,7 +121,7 @@ genX(init_device_state)(struct anv_device *device)
>> }
>>  #endif
>>
>> -#if GEN_GEN == 10
>> +#if GEN_GEN == 10 || GEN_GEN == 11
>
>
> Might as well make this GEN_GEN >= 10
>
I can see this bit going away in future generation. So, let's keep
the check unchanged.

>>
>> uint32_t cache_mode_ss;
>> anv_pack_struct(_mode_ss, GENX(CACHE_MODE_SS),
>> .FloatBlendOptimizationEnable = true,
>> --
>> 2.13.6
>>
>> ___
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[Mesa-dev] [PATCH 04/10] anv/icl: Don't use SingleVertexDispatch

[Anuj Phogat]

Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com>
---
 src/intel/vulkan/genX_pipeline.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/intel/vulkan/genX_pipeline.c b/src/intel/vulkan/genX_pipeline.c
index 784559380d..85391c93ca 100644
--- a/src/intel/vulkan/genX_pipeline.c
+++ b/src/intel/vulkan/genX_pipeline.c
@@ -1135,7 +1135,9 @@ emit_3dstate_vs(struct anv_pipeline *pipeline)
 #endif
 
   assert(!vs_prog_data->base.base.use_alt_mode);
+#if GEN_GEN < 11
   vs.SingleVertexDispatch   = false;
+#endif
   vs.VectorMaskEnable   = false;
   vs.SamplerCount   = get_sampler_count(vs_bin);
   vs.BindingTableEntryCount = get_binding_table_entry_count(vs_bin);
-- 
2.13.6

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[Mesa-dev] [PATCH 05/10] anv/icl: Don't use DISPATCH_MODE_SIMD4X2

[Anuj Phogat]

Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com>
---
 src/intel/vulkan/genX_pipeline.c | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/src/intel/vulkan/genX_pipeline.c b/src/intel/vulkan/genX_pipeline.c
index 85391c93ca..290d78e608 100644
--- a/src/intel/vulkan/genX_pipeline.c
+++ b/src/intel/vulkan/genX_pipeline.c
@@ -1124,6 +1124,9 @@ emit_3dstate_vs(struct anv_pipeline *pipeline)
   pipeline->shaders[MESA_SHADER_VERTEX];
 
assert(anv_pipeline_has_stage(pipeline, MESA_SHADER_VERTEX));
+#if GEN_GEN >= 11
+   assert(vs_prog_data->base.dispatch_mode == DISPATCH_MODE_SIMD8);
+#endif
 
anv_batch_emit(>batch, GENX(3DSTATE_VS), vs) {
   vs.Enable   = true;
@@ -1253,10 +1256,14 @@ emit_3dstate_hs_te_ds(struct anv_pipeline *pipeline,
  tes_prog_data->base.base.dispatch_grf_start_reg;
 
 #if GEN_GEN >= 8
+#if GEN_GEN < 11
   ds.DispatchMode =
  tes_prog_data->base.dispatch_mode == DISPATCH_MODE_SIMD8 ?
 DISPATCH_MODE_SIMD8_SINGLE_PATCH :
 DISPATCH_MODE_SIMD4X2;
+#else
+  ds.DispatchMode = DISPATCH_MODE_SIMD8_SINGLE_PATCH;
+#endif
 
   ds.UserClipDistanceClipTestEnableBitmask =
  tes_prog_data->base.clip_distance_mask;
-- 
2.13.6

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[Mesa-dev] [PATCH 06/10] anv/icl: Generate gen11 entry point functions

[Anuj Phogat]

Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com>
---
 src/intel/vulkan/anv_entrypoints_gen.py | 6 +-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/src/intel/vulkan/anv_entrypoints_gen.py 
b/src/intel/vulkan/anv_entrypoints_gen.py
index 1bab885180..c5a654f19b 100644
--- a/src/intel/vulkan/anv_entrypoints_gen.py
+++ b/src/intel/vulkan/anv_entrypoints_gen.py
@@ -43,7 +43,8 @@ LAYERS = [
 'gen75',
 'gen8',
 'gen9',
-'gen10'
+'gen10',
+'gen11',
 ]
 
 TEMPLATE_H = Template("""\
@@ -246,6 +247,9 @@ anv_resolve_entrypoint(const struct gen_device_info 
*devinfo, uint32_t index)
 
const struct anv_dispatch_table *genX_table;
switch (devinfo->gen) {
+   case 11:
+  genX_table = _dispatch_table;
+  break;
case 10:
   genX_table = _dispatch_table;
   break;
-- 
2.13.6

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[Mesa-dev] [PATCH 09/10] anv/icl: Enable float blend optimization

[Anuj Phogat]

Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com>
---
 src/intel/vulkan/genX_state.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/intel/vulkan/genX_state.c b/src/intel/vulkan/genX_state.c
index 54fb8634fd..f39508034f 100644
--- a/src/intel/vulkan/genX_state.c
+++ b/src/intel/vulkan/genX_state.c
@@ -121,7 +121,7 @@ genX(init_device_state)(struct anv_device *device)
}
 #endif
 
-#if GEN_GEN == 10
+#if GEN_GEN == 10 || GEN_GEN == 11
uint32_t cache_mode_ss;
anv_pack_struct(_mode_ss, GENX(CACHE_MODE_SS),
.FloatBlendOptimizationEnable = true,
-- 
2.13.6

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[Mesa-dev] [PATCH 10/10] anv/icl: Add render target flush after uploading binding table

[Anuj Phogat]

The PIPE_CONTROL command description says:

"Whenever a Binding Table Index (BTI) used by a Render Taget Message
points to a different RENDER_SURFACE_STATE, SW must issue a Render
Target Cache Flush by enabling this bit. When render target flush
is set due to new association of BTI, PS Scoreboard Stall bit must
be set in this packet."

Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com>
---
 src/intel/vulkan/genX_cmd_buffer.c | 21 +
 1 file changed, 21 insertions(+)

diff --git a/src/intel/vulkan/genX_cmd_buffer.c 
b/src/intel/vulkan/genX_cmd_buffer.c
index ce47b8a1cc..e2b6c281e4 100644
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@ -2001,6 +2001,27 @@ emit_binding_table(struct anv_cmd_buffer *cmd_buffer,
  out:
anv_state_flush(cmd_buffer->device, *bt_state);
 
+#if GEN_GEN >= 11
+   /* The PIPE_CONTROL command description says:
+*
+* "Whenever a Binding Table Index (BTI) used by a Render Taget Message
+*  points to a different RENDER_SURFACE_STATE, SW must issue a Render
+*  Target Cache Flush by enabling this bit. When render target flush
+*  is set due to new association of BTI, PS Scoreboard Stall bit must
+*  be set in this packet."
+*
+*  FINISHME: Currently we shuffle around the surface states in the
+*  binding table based on if they are getting used or not. So, we've
+*  to do below pipe control flush for every binding table upload.
+*  Make changes so that we do it only when we modify render target
+*  surface states.
+*/
+   anv_batch_emit(_buffer->batch, GENX(PIPE_CONTROL), pc) {
+  pc.RenderTargetCacheFlushEnable  = true;
+  pc.StallAtPixelScoreboard= true;
+   }
+#endif
+
return VK_SUCCESS;
 }
 
-- 
2.13.6

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[Mesa-dev] [PATCH 01/10] anv/icl: Add gen11 mocs defines

[Anuj Phogat]

Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com>
---
 src/intel/vulkan/anv_private.h | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h
index d38dd9e422..009f5304f2 100644
--- a/src/intel/vulkan/anv_private.h
+++ b/src/intel/vulkan/anv_private.h
@@ -1148,6 +1148,17 @@ _anv_combine_address(struct anv_batch *batch, void 
*location,
   .IndextoMOCSTables   = 1  \
}
 
+/* Ice Lake MOCS defines are duplicates of Skylake MOCS defines. */
+#define GEN11_MOCS (struct GEN11_MEMORY_OBJECT_CONTROL_STATE) {  \
+  /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */  \
+  .IndextoMOCSTables   = 2 \
+   }
+
+#define GEN11_MOCS_PTE { \
+  /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */   \
+  .IndextoMOCSTables   = 1  \
+   }
+
 struct anv_device_memory {
struct anv_bo *  bo;
struct anv_memory_type * type;
-- 
2.13.6

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[Mesa-dev] [PATCH 07/10] anv/icl: Build anv libs for gen11

[Anuj Phogat]

Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com>
---
 src/intel/Android.vulkan.mk  | 21 +
 src/intel/Makefile.sources   |  4 
 src/intel/Makefile.vulkan.am |  7 ++-
 src/intel/vulkan/meson.build |  2 +-
 4 files changed, 32 insertions(+), 2 deletions(-)

diff --git a/src/intel/Android.vulkan.mk b/src/intel/Android.vulkan.mk
index 32b4892e17..6fe736d397 100644
--- a/src/intel/Android.vulkan.mk
+++ b/src/intel/Android.vulkan.mk
@@ -185,6 +185,26 @@ include $(MESA_COMMON_MK)
 include $(BUILD_STATIC_LIBRARY)
 
 #
+# libanv for gen11
+#
+
+include $(CLEAR_VARS)
+LOCAL_MODULE := libmesa_anv_gen11
+LOCAL_MODULE_CLASS := STATIC_LIBRARIES
+
+LOCAL_SRC_FILES := $(VULKAN_GEN10_FILES)
+LOCAL_CFLAGS := -DGEN_VERSIONx10=110
+
+LOCAL_C_INCLUDES := $(ANV_INCLUDES)
+
+LOCAL_WHOLE_STATIC_LIBRARIES := libmesa_anv_entrypoints libmesa_genxml
+
+LOCAL_SHARED_LIBRARIES := libdrm
+
+include $(MESA_COMMON_MK)
+include $(BUILD_STATIC_LIBRARY)
+
+#
 # libmesa_vulkan_common
 #
 
@@ -270,6 +290,7 @@ LOCAL_WHOLE_STATIC_LIBRARIES := \
libmesa_anv_gen8 \
libmesa_anv_gen9 \
libmesa_anv_gen10 \
+   libmesa_anv_gen11 \
libmesa_intel_compiler \
libmesa_anv_entrypoints
 
diff --git a/src/intel/Makefile.sources b/src/intel/Makefile.sources
index 22563cac6a..692c860477 100644
--- a/src/intel/Makefile.sources
+++ b/src/intel/Makefile.sources
@@ -285,3 +285,7 @@ VULKAN_GEN9_FILES := \
 VULKAN_GEN10_FILES := \
vulkan/gen8_cmd_buffer.c \
$(VULKAN_GENX_FILES)
+
+VULKAN_GEN11_FILES := \
+   vulkan/gen8_cmd_buffer.c \
+   $(VULKAN_GENX_FILES)
diff --git a/src/intel/Makefile.vulkan.am b/src/intel/Makefile.vulkan.am
index 23fa877e77..891ee698a0 100644
--- a/src/intel/Makefile.vulkan.am
+++ b/src/intel/Makefile.vulkan.am
@@ -98,7 +98,8 @@ VULKAN_PER_GEN_LIBS = \
vulkan/libanv-gen75.la \
vulkan/libanv-gen8.la \
vulkan/libanv-gen9.la \
-   vulkan/libanv-gen10.la
+   vulkan/libanv-gen10.la \
+   vulkan/libanv-gen11.la
 
 noinst_LTLIBRARIES += $(VULKAN_PER_GEN_LIBS)
 
@@ -138,6 +139,10 @@ vulkan_libanv_gen10_la_CFLAGS = $(VULKAN_CFLAGS)
 vulkan_libanv_gen10_la_CPPFLAGS = $(VULKAN_CPPFLAGS) -DGEN_VERSIONx10=100
 vulkan_libanv_gen10_la_SOURCES = $(VULKAN_GEN10_FILES)
 
+vulkan_libanv_gen11_la_CFLAGS = $(VULKAN_CFLAGS)
+vulkan_libanv_gen11_la_CPPFLAGS = $(VULKAN_CPPFLAGS) -DGEN_VERSIONx10=110
+vulkan_libanv_gen11_la_SOURCES = $(VULKAN_GEN11_FILES)
+
 VULKAN_SOURCES = \
$(VULKAN_GENERATED_FILES) \
$(VULKAN_FILES)
diff --git a/src/intel/vulkan/meson.build b/src/intel/vulkan/meson.build
index 41dba420cb..f031723670 100644
--- a/src/intel/vulkan/meson.build
+++ b/src/intel/vulkan/meson.build
@@ -101,7 +101,7 @@ anv_gen_files = files(
 )
 foreach g : [['70', ['gen7_cmd_buffer.c']], ['75', ['gen7_cmd_buffer.c']],
  ['80', ['gen8_cmd_buffer.c']], ['90', ['gen8_cmd_buffer.c']],
- ['100', ['gen8_cmd_buffer.c']]]
+ ['100', ['gen8_cmd_buffer.c']], ['110', ['gen8_cmd_buffer.c']]]
   _gen = g[0]
   libanv_gen_libs += static_library(
 'libanv_gen@0@'.format(_gen),
-- 
2.13.6

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[Mesa-dev] [PATCH 02/10] anv/icl: Add #define genX

[Anuj Phogat]

Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com>
---
 src/intel/vulkan/anv_private.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h
index 009f5304f2..9822afb81d 100644
--- a/src/intel/vulkan/anv_private.h
+++ b/src/intel/vulkan/anv_private.h
@@ -3042,6 +3042,9 @@ ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_ycbcr_conversion, 
VkSamplerYcbcrConversionKH
 #  define genX(x) gen10_##x
 #  include "anv_genX.h"
 #  undef genX
+#  define genX(x) gen11_##x
+#  include "anv_genX.h"
+#  undef genX
 #endif
 
 #endif /* ANV_PRIVATE_H */
-- 
2.13.6

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[Mesa-dev] [PATCH 03/10] anv/icl: Don't set ResetGatewayTimer

[Anuj Phogat]

Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com>
---
 src/intel/vulkan/genX_pipeline.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/intel/vulkan/genX_pipeline.c b/src/intel/vulkan/genX_pipeline.c
index 45ebe31de6..784559380d 100644
--- a/src/intel/vulkan/genX_pipeline.c
+++ b/src/intel/vulkan/genX_pipeline.c
@@ -1820,7 +1820,9 @@ compute_pipeline_create(
   vfe.MaximumNumberofThreads =
  devinfo->max_cs_threads * subslices - 1;
   vfe.NumberofURBEntries = GEN_GEN <= 7 ? 0 : 2;
+#if GEN_GEN < 11
   vfe.ResetGatewayTimer  = true;
+#endif
 #if GEN_GEN <= 8
   vfe.BypassGatewayControl   = true;
 #endif
-- 
2.13.6

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[Mesa-dev] [PATCH 08/10] anv/icl: Use gen11 functions

[Anuj Phogat]

Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com>
---
 src/intel/vulkan/anv_blorp.c  | 3 +++
 src/intel/vulkan/anv_device.c | 3 +++
 2 files changed, 6 insertions(+)

diff --git a/src/intel/vulkan/anv_blorp.c b/src/intel/vulkan/anv_blorp.c
index d38b343671..d98bf8364d 100644
--- a/src/intel/vulkan/anv_blorp.c
+++ b/src/intel/vulkan/anv_blorp.c
@@ -111,6 +111,9 @@ anv_device_init_blorp(struct anv_device *device)
case 10:
   device->blorp.exec = gen10_blorp_exec;
   break;
+   case 11:
+  device->blorp.exec = gen11_blorp_exec;
+  break;
default:
   unreachable("Unknown hardware generation");
}
diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index 2c2cd0b2d4..00b0b65333 100644
--- a/src/intel/vulkan/anv_device.c
+++ b/src/intel/vulkan/anv_device.c
@@ -1482,6 +1482,9 @@ VkResult anv_CreateDevice(
case 10:
   result = gen10_init_device_state(device);
   break;
+   case 11:
+  result = gen11_init_device_state(device);
+  break;
default:
   /* Shouldn't get here as we don't create physical devices for any other
* gens. */
-- 
2.13.6

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[Mesa-dev] [PATCH 00/10] intel/anv: Prepare to add Ice Lake (ICL) support

[Anuj Phogat]

This series prepares the driver to enable Ice Lake support
in Vulkan driver. It wires up the build infrastructure and
make few ICL specific changes suggested by h/w documentation.
This is not everything we need to enable Vulkan on Ice Lake.

Series is also available in my review branch at github.
https://github.com/aphogat/mesa.git

Anuj Phogat (10):
  anv/icl: Add gen11 mocs defines
  anv/icl: Add #define genX
  anv/icl: Don't set ResetGatewayTimer
  anv/icl: Don't use SingleVertexDispatch
  anv/icl: Don't use DISPATCH_MODE_SIMD4X2
  anv/icl: Generate gen11 entry point functions
  anv/icl: Build anv libs for gen11
  anv/icl: Use gen11 functions
  anv/icl: Enable float blend optimization
  anv/icl: Add render target flush after uploading binding table

 src/intel/Android.vulkan.mk | 21 +
 src/intel/Makefile.sources  |  4 
 src/intel/Makefile.vulkan.am|  7 ++-
 src/intel/vulkan/anv_blorp.c|  3 +++
 src/intel/vulkan/anv_device.c   |  3 +++
 src/intel/vulkan/anv_entrypoints_gen.py |  6 +-
 src/intel/vulkan/anv_private.h  | 14 ++
 src/intel/vulkan/genX_cmd_buffer.c  | 21 +
 src/intel/vulkan/genX_pipeline.c| 11 +++
 src/intel/vulkan/genX_state.c   |  2 +-
 src/intel/vulkan/meson.build|  2 +-
 11 files changed, 90 insertions(+), 4 deletions(-)

-- 
2.13.6

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Re: [Mesa-dev] [PATCH V2 16/16] i965/icl: Add render target flush after uploading binding table

[Anuj Phogat]

+Ken

On Thu, Feb 15, 2018 at 11:11 AM, Anuj Phogat <anuj.pho...@gmail.com> wrote:
> From PIPE_CONTROL command description in gfxspecs:
>
> "Whenever a Binding Table Index (BTI) used by a Render Taget Message
>  points to a different RENDER_SURFACE_STATE, SW must issue a Render
>  Target Cache Flush by enabling this bit. When render target flush
>  is set due to new association of BTI, PS Scoreboard Stall bit must
>  be set in this packet."
>
> V2: Move the PIPE_CONTROL to update_renderbuffer_surfaces() in
> brw_wm_surface_state.c (Ken).
>
> Fixes a fulsim error and a GPU hang described in below JIRA.
> JIRA: MD5-322
> Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com>
> ---
>  src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 14 ++
>  1 file changed, 14 insertions(+)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c 
> b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
> index 44c87df17d..84c5a81227 100644
> --- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
> +++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
> @@ -971,6 +971,20 @@ update_renderbuffer_surfaces(struct brw_context *brw)
>emit_null_surface_state(brw, fb, _offsets[rt_start]);
> }
>
> +   /* From PIPE_CONTROL command description in gfxspecs:
> +
> +  "Whenever a Binding Table Index (BTI) used by a Render Taget Message
> +   points to a different RENDER_SURFACE_STATE, SW must issue a Render
> +   Target Cache Flush by enabling this bit. When render target flush
> +   is set due to new association of BTI, PS Scoreboard Stall bit must
> +   be set in this packet."
> +   */
> +   if (devinfo->gen >= 11) {
> +  brw_emit_pipe_control_flush(brw,
> +  PIPE_CONTROL_RENDER_TARGET_FLUSH |
> +  PIPE_CONTROL_STALL_AT_SCOREBOARD);
> +   }
> +
> brw->ctx.NewDriverState |= BRW_NEW_SURFACES;
>  }
>
> --
> 2.13.6
>
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[Mesa-dev] [PATCH V2 16/16] i965/icl: Add render target flush after uploading binding table

[Anuj Phogat]

From PIPE_CONTROL command description in gfxspecs:

"Whenever a Binding Table Index (BTI) used by a Render Taget Message
 points to a different RENDER_SURFACE_STATE, SW must issue a Render
 Target Cache Flush by enabling this bit. When render target flush
 is set due to new association of BTI, PS Scoreboard Stall bit must
 be set in this packet."

V2: Move the PIPE_CONTROL to update_renderbuffer_surfaces() in
brw_wm_surface_state.c (Ken).

Fixes a fulsim error and a GPU hang described in below JIRA.
JIRA: MD5-322
Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com>
---
 src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 14 ++
 1 file changed, 14 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c 
b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index 44c87df17d..84c5a81227 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -971,6 +971,20 @@ update_renderbuffer_surfaces(struct brw_context *brw)
   emit_null_surface_state(brw, fb, _offsets[rt_start]);
}
 
+   /* From PIPE_CONTROL command description in gfxspecs:
+
+  "Whenever a Binding Table Index (BTI) used by a Render Taget Message
+   points to a different RENDER_SURFACE_STATE, SW must issue a Render
+   Target Cache Flush by enabling this bit. When render target flush
+   is set due to new association of BTI, PS Scoreboard Stall bit must
+   be set in this packet."
+   */
+   if (devinfo->gen >= 11) {
+  brw_emit_pipe_control_flush(brw,
+  PIPE_CONTROL_RENDER_TARGET_FLUSH |
+  PIPE_CONTROL_STALL_AT_SCOREBOARD);
+   }
+
brw->ctx.NewDriverState |= BRW_NEW_SURFACES;
 }
 
-- 
2.13.6

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[Mesa-dev] [PATCH 14/16] intel/common/icl: Add has_sample_with_hiz flag in gen_device_info

[Anuj Phogat]

Sampling from hiz is enabled in i965 for GEN9+ but this feature has
been removed from gen11. So, this new flag will be useful to turn
the feature on/off for different gen h/w. It will be used later
in a patch adding device info for gen11.

Suggested-by: Kenneth Graunke <kenn...@whitecape.org>
Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com>
Cc: Kenneth Graunke <kenn...@whitecape.org>
---
 src/intel/common/gen_device_info.c| 7 +++
 src/intel/common/gen_device_info.h| 2 +-
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 5 +
 3 files changed, 9 insertions(+), 5 deletions(-)

diff --git a/src/intel/common/gen_device_info.c 
b/src/intel/common/gen_device_info.c
index c0eb7c3c35..a08a13a32a 100644
--- a/src/intel/common/gen_device_info.c
+++ b/src/intel/common/gen_device_info.c
@@ -311,12 +311,16 @@ static const struct gen_device_info 
gen_device_info_hsw_gt3 = {
},
 };
 
+/* It's unclear how well supported sampling from the hiz buffer is on GEN8,
+ * so keep things conservative for now and set has_sample_with_hiz = false.
+ */
 #define GEN8_FEATURES   \
.gen = 8,\
.has_hiz_and_separate_stencil = true,\
.has_resource_streamer = true,   \
.must_use_separate_stencil = true,   \
.has_llc = true, \
+   .has_sample_with_hiz = false,\
.has_pln = true, \
.supports_simd16_3src = true,\
.has_surface_tile_offset = true, \
@@ -451,6 +455,7 @@ static const struct gen_device_info gen_device_info_chv = {
GEN9_HW_INFO,   \
.gt = 1,\
.has_llc = false,   \
+   .has_sample_with_hiz = true,\
.num_slices = 1,\
.num_thread_per_eu = 6, \
.max_vs_threads = 112,  \
@@ -502,6 +507,7 @@ static const struct gen_device_info gen_device_info_chv = {
 #define GEN9_FEATURES   \
GEN8_FEATURES,   \
GEN9_HW_INFO,\
+   .has_sample_with_hiz = true, \
.num_thread_per_eu = 7
 
 static const struct gen_device_info gen_device_info_skl_gt1 = {
@@ -695,6 +701,7 @@ static const struct gen_device_info gen_device_info_cfl_gt3 
= {
 #define GEN10_FEATURES(_gt, _slices, _subslices, _l3) \
GEN8_FEATURES,   \
GEN10_HW_INFO,   \
+   .has_sample_with_hiz = true, \
.gt = _gt,   \
.num_slices = _slices,   \
.num_subslices = _subslices, \
diff --git a/src/intel/common/gen_device_info.h 
b/src/intel/common/gen_device_info.h
index 30ddd905be..fd9c17531d 100644
--- a/src/intel/common/gen_device_info.h
+++ b/src/intel/common/gen_device_info.h
@@ -55,7 +55,7 @@ struct gen_device_info
 
bool has_hiz_and_separate_stencil;
bool must_use_separate_stencil;
-
+   bool has_sample_with_hiz;
bool has_llc;
 
bool has_pln;
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index da5e3b0989..6d35c9d392 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -1911,10 +1911,7 @@ intel_miptree_sample_with_hiz(struct brw_context *brw,
 {
const struct gen_device_info *devinfo = >screen->devinfo;
 
-   /* It's unclear how well supported sampling from the hiz buffer is on GEN8,
-* so keep things conservative for now and never enable it unless we're 
SKL+.
-*/
-   if (devinfo->gen < 9) {
+   if (!devinfo->has_sample_with_hiz) {
   return false;
}
 
-- 
2.13.6

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Re: [Mesa-dev] [PATCH 02/16] intel/genxml/icl: Generate packing headers

[Anuj Phogat]

On Thu, Feb 15, 2018 at 9:49 AM, Emil Velikov <emil.l.veli...@gmail.com> wrote:
> On 13 February 2018 at 19:15, Anuj Phogat <anuj.pho...@gmail.com> wrote:
>> Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com>
>> ---
>>  src/intel/Android.genxml.mk   | 5 +
>>  src/intel/Makefile.sources| 3 ++-
>>  src/intel/genxml/genX_pack.h  | 2 ++
>>  src/intel/genxml/gen_macros.h | 3 +++
>>  4 files changed, 12 insertions(+), 1 deletion(-)
>>
>> diff --git a/src/intel/Android.genxml.mk b/src/intel/Android.genxml.mk
>> index e4d8dd8b94..8b867920c3 100644
>> --- a/src/intel/Android.genxml.mk
>> +++ b/src/intel/Android.genxml.mk
>> @@ -101,6 +101,11 @@ $(intermediates)/genxml/gen10_pack.h: PRIVATE_XML := 
>> $(LOCAL_PATH)/genxml/gen10.
>>  $(intermediates)/genxml/gen10_pack.h: $(LOCAL_PATH)/genxml/gen10.xml 
>> $(LOCAL_PATH)/genxml/gen_pack_header.py
>> $(call header-gen)
>>
>> +$(intermediates)/genxml/gen11_pack.h: PRIVATE_SCRIPT := $(MESA_PYTHON2) 
>> $(LOCAL_PATH)/genxml/gen_pack_header.py
>> +$(intermediates)/genxml/gen11_pack.h: PRIVATE_XML := 
>> $(LOCAL_PATH)/genxml/gen11.xml
>> +$(intermediates)/genxml/gen11_pack.h: $(LOCAL_PATH)/genxml/gen11.xml 
>> $(LOCAL_PATH)/genxml/gen_pack_header.py
>> +   $(call header-gen)
>> +
> ... and here it is.
>
> I second Kenneth - please keep the build bits in one patch.
> Be that squashing 1+2 or keeping git add gen10.xml in patch 01 and the
> build in 02.
>
> Thanks
> Emil
I'll move the build changes in patch 2. Thanks.
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Re: [Mesa-dev] [PATCH 16/16] i965/icl: Add render target flush after uploading binding table

[Anuj Phogat]

On Tue, Feb 13, 2018 at 4:17 PM, Kenneth Graunke <kenn...@whitecape.org> wrote:
> On Tuesday, February 13, 2018 11:15:16 AM PST Anuj Phogat wrote:
>> From PIPE_CONTROL command description in gfxspecs:
>>
>> "Whenever a Binding Table Index (BTI) used by a Render Taget Message
>>  points to a different RENDER_SURFACE_STATE, SW must issue a Render
>>  Target Cache Flush by enabling this bit. When render target flush
>>  is set due to new association of BTI, PS Scoreboard Stall bit must
>>  be set in this packet."
>>
>> Fixes a fulsim error and a GPU hang described in below JIRA.
>>
>> JIRA: MD5-322
>> Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com>
>> ---
>>  src/mesa/drivers/dri/i965/brw_binding_tables.c | 14 ++
>>  1 file changed, 14 insertions(+)
>>
>> diff --git a/src/mesa/drivers/dri/i965/brw_binding_tables.c 
>> b/src/mesa/drivers/dri/i965/brw_binding_tables.c
>> index 73f5e56010..170daebc24 100644
>> --- a/src/mesa/drivers/dri/i965/brw_binding_tables.c
>> +++ b/src/mesa/drivers/dri/i965/brw_binding_tables.c
>> @@ -93,6 +93,20 @@ brw_upload_binding_table(struct brw_context *brw,
>>OUT_BATCH(stage_state->bind_bo_offset);
>>ADVANCE_BATCH();
>> }
>> +
>> +   /* From PIPE_CONTROL command description in gfxspecs:
>> +
>> +  "Whenever a Binding Table Index (BTI) used by a Render Taget Message
>> +   points to a different RENDER_SURFACE_STATE, SW must issue a Render
>> +   Target Cache Flush by enabling this bit. When render target flush
>> +   is set due to new association of BTI, PS Scoreboard Stall bit must
>> +   be set in this packet."
>> +   */
>> +   if (devinfo->gen >= 11) {
>> +  brw_emit_pipe_control_flush(brw,
>> +  PIPE_CONTROL_RENDER_TARGET_FLUSH |
>> +  PIPE_CONTROL_STALL_AT_SCOREBOARD);
>> +   }
>>  }
>>
>>  /**
>>
>
> This is overkill.  It'll do a RT flush when we change the binding
> tables in any stage, for any reason.  Only the pixel shader's binding
> tables have render target surfaces.  And, we might change other surfaces
> (textures, UBOs, etc) without changing the render targets.
>
> I would move this to update_renderbuffer_surfaces() in
> brw_wm_surface_state.c.

I agree. I wasn't very sure either if this is the right place to do
it. Thanks for the suggestion. I'll verify if it still fixes the fulsim
error and gpu hang.
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Re: [Mesa-dev] [PATCH 14/16] i965/icl: Disable HiZ surface sampling

[Anuj Phogat]

On Tue, Feb 13, 2018 at 4:25 PM, Kenneth Graunke <kenn...@whitecape.org> wrote:
> On Tuesday, February 13, 2018 11:15:14 AM PST Anuj Phogat wrote:
>> On gen11+ AUX_HIZ is not a supported value for surfaces being
>> sampled by the 3D sampler.
>>
>> Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com>
>> ---
>>  src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 5 +++--
>>  1 file changed, 3 insertions(+), 2 deletions(-)
>>
>> diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
>> b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
>> index f27d559149..9c6f166677 100644
>> --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
>> +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
>> @@ -1912,9 +1912,10 @@ intel_miptree_sample_with_hiz(struct brw_context *brw,
>> const struct gen_device_info *devinfo = >screen->devinfo;
>>
>> /* It's unclear how well supported sampling from the hiz buffer is on 
>> GEN8,
>> -* so keep things conservative for now and never enable it unless we're 
>> SKL+.
>> +* so keep things conservative for now and never enable it unless we're 
>> GEN9+.
>> +* Also, disable the sampling from the hiz buffer for GEN11+.
>>  */
>> -   if (devinfo->gen < 9) {
>> +   if (devinfo->gen < 9 || devinfo->gen > 10) {
>>return false;
>> }
>
> Sad to see this go :(
>
> I think we should add a devinfo->has_aux_hiz boolean, set it on Gen9-10,
> leave it false on Gen8 with this "it's unclear how well supported..."
> comment, then change this code to use the flag.
>
> That will disable it for Gen11 but gives us a bit more flexibility.

Sounds good. I think 'has_sample_with_hiz' a better name for the flag?
has_aux_hiz can be easily misinterpreted as a flag to check if
mt->hiz_buf is valid or not.
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Re: [Mesa-dev] [PATCH] i965: Add ICL to test_eu_validate.cpp

[Anuj Phogat]

Sent this patch to ML by mistake :(. Reviewers can ignore this one for now.
Matt can send it out later with rest of his compiler changes.

On Tue, Feb 13, 2018 at 2:41 PM, Anuj Phogat <anuj.pho...@gmail.com> wrote:
> From: Matt Turner <matts...@gmail.com>
>
> ---
>  src/intel/compiler/test_eu_validate.cpp | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/src/intel/compiler/test_eu_validate.cpp 
> b/src/intel/compiler/test_eu_validate.cpp
> index f6c2b35625..d987311ef8 100644
> --- a/src/intel/compiler/test_eu_validate.cpp
> +++ b/src/intel/compiler/test_eu_validate.cpp
> @@ -56,6 +56,7 @@ static const struct gen_info {
> { "glk", 9, IS_GLK },
> { "cfl", 9, IS_CFL },
> { "cnl", 10 },
> +   { "icl", 11 },
>  };
>
>  class validation_test: public ::testing::TestWithParam {
> --
> 2.13.6
>
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[Mesa-dev] [PATCH] i965: Add ICL to test_eu_validate.cpp

[Anuj Phogat]

From: Matt Turner 

---
 src/intel/compiler/test_eu_validate.cpp | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/intel/compiler/test_eu_validate.cpp 
b/src/intel/compiler/test_eu_validate.cpp
index f6c2b35625..d987311ef8 100644
--- a/src/intel/compiler/test_eu_validate.cpp
+++ b/src/intel/compiler/test_eu_validate.cpp
@@ -56,6 +56,7 @@ static const struct gen_info {
{ "glk", 9, IS_GLK },
{ "cfl", 9, IS_CFL },
{ "cnl", 10 },
+   { "icl", 11 },
 };
 
 class validation_test: public ::testing::TestWithParam {
-- 
2.13.6

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[Mesa-dev] [PATCH 01/16] intel/genxml/icl: Add gen11.xml

[Anuj Phogat]

Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com>
---
This patch adds a big xml file. So I couldn't send the patch
to the list. Clamping down the patch so that reviewers can
actually see what i'm doing in [PATCH 01/16 ]. The whole
patch can be found in my 'review' branch on github.

 src/intel/Makefile.sources   |3 +-
 src/intel/genxml/gen11.xml   | 3787 ++
 src/intel/genxml/meson.build |1 +
 3 files changed, 3790 insertions(+), 1 deletion(-)
 create mode 100644 src/intel/genxml/gen11.xml

diff --git a/src/intel/Makefile.sources b/src/intel/Makefile.sources
index 9595bf4258..2d76c93e56 100644
--- a/src/intel/Makefile.sources
+++ b/src/intel/Makefile.sources
@@ -132,7 +132,8 @@ GENXML_XML_FILES = \
genxml/gen75.xml \
genxml/gen8.xml \
genxml/gen9.xml \
-   genxml/gen10.xml
+   genxml/gen10.xml \
+   genxml/gen11.xml
 
 GENXML_GENERATED_PACK_FILES = \
genxml/gen4_pack.h \
diff --git a/src/intel/genxml/gen11.xml b/src/intel/genxml/gen11.xml
new file mode 100644
index 00..2490b0e25b
--- /dev/null
+++ b/src/intel/genxml/gen11.xml
@@ -0,0 +1,3787 @@
+
+
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
...
+
diff --git a/src/intel/genxml/meson.build b/src/intel/genxml/meson.build
index 371f85307c..970d565471 100644
--- a/src/intel/genxml/meson.build
+++ b/src/intel/genxml/meson.build
@@ -28,6 +28,7 @@ gen_xml_files = [
   'gen8.xml',
   'gen9.xml',
   'gen10.xml',
+  'gen11.xml',
 ]
 
 genX_xml_h = custom_target(
-- 
2.13.6

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[Mesa-dev] [PATCH 1.5/16] intel/genxml/icl: Add Cache Mode SubSlice Register to gen11.xml

[Anuj Phogat]

Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com>
---
This patch will be squashed with [PATCH 01/16]

 src/intel/genxml/gen11.xml | 12 
 1 file changed, 12 insertions(+)

diff --git a/src/intel/genxml/gen11.xml b/src/intel/genxml/gen11.xml
index 2490b0e25b..84020f7015 100644
--- a/src/intel/genxml/gen11.xml
+++ b/src/intel/genxml/gen11.xml
@@ -3784,4 +3784,16 @@
 
   
 
+  
+
+
+
+
+
+
+
+
+
+  
+
 
-- 
2.13.6

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Re: [Mesa-dev] [PATCH 3/3] docs: Add Cannonlake support to 18.0 release notes.

[Anuj Phogat]

On Tue, Feb 13, 2018 at 1:51 PM, Rafael Antognolli
<rafael.antogno...@intel.com> wrote:
> 17.4 is actually 18.0.
>
> Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com>
> Cc: "18.0" mesa-sta...@lists.freedesktop.org
> ---
>  docs/relnotes/17.4.0.html | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/docs/relnotes/17.4.0.html b/docs/relnotes/17.4.0.html
> index 412c0fc455e..6bebb514bd2 100644
> --- a/docs/relnotes/17.4.0.html
> +++ b/docs/relnotes/17.4.0.html
> @@ -54,6 +54,7 @@ Note: some of the new features are only available with 
> certain drivers.
>  GL_ARB_bindless_texture on nvc0/kepler
>  OpenGL 4.3 on r600/evergreen with hw fp64 support
>  Support 1 binary format for GL_ARB_get_program_binary on i965
> +Cannonlake support on i965 and anv
>  
>
>  Bug fixes
> --
> 2.14.3
>
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Series-is: Reviewed-by: Anuj Phogat <anuj.pho...@gmail.com>
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Re: [Mesa-dev] [PATCH 00/16] Prepare to add Ice Lake (ICL) support

[Anuj Phogat]

This series is also available at:
https://github.com/aphogat/mesa.git
Branch: review

On Tue, Feb 13, 2018 at 11:15 AM, Anuj Phogat <anuj.pho...@gmail.com> wrote:
>
> This series prepares the driver to enable Ice Lake support
> in i965 driver. It adds gen11.xml, wires up the build
> infrastructure and make ICL specific changes suggested by
> h/w documentation. This series carry about 50% of all
> the changes required to enable Ice Lake. I (or someone else
> in the team) will send out more patches later in another
> series.
>
> Anuj Phogat (16):
>   intel/genxml/icl: Add gen11.xml
>   intel/genxml/icl: Generate packing headers
>   intel/genxml/icl: Update genx_bits header
>   intel/isl/icl: Add the maximum surface size limit
>   intel/isl/icl: Build and use gen11 surface state emit functions
>   intel/icl: Do StateCacheInvalidation for indirect clear color
>   i965/icl: Don't set ResetGatewayTimer
>   i965/icl: Build and use gen11 functions for genxml state-upload and
> blorp
>   i965/icl: Update the comment for maximum number of threads per PSD
>   i965/icl: Define and use icl mocs settings
>   i965/icl: Update the assert in brw_memory_barrier()
>   i965/icl: Update switch statements
>   i965/icl: Add assertions to check dispatch mode is SIMD8
>   i965/icl: Disable HiZ surface sampling
>   i965/icl: Enable float blend optimization and Wa3DStateMode
>   i965/icl: Add render target flush after uploading binding table
>
>  src/intel/Android.genxml.mk  |5 +
>  src/intel/Android.isl.mk |   20 +
>  src/intel/Makefile.isl.am|4 +
>  src/intel/Makefile.sources   |   10 +-
>  src/intel/blorp/blorp_genX_exec.h|   15 +-
>  src/intel/genxml/gen11.xml   | 3788 
> ++
>  src/intel/genxml/genX_pack.h |2 +
>  src/intel/genxml/gen_bits_header.py  |1 +
>  src/intel/genxml/gen_macros.h|3 +
>  src/intel/genxml/meson.build |1 +
>  src/intel/isl/isl.c  |9 +-
>  src/intel/isl/isl_priv.h |3 +
>  src/intel/isl/meson.build|2 +-
>  src/mesa/drivers/dri/i965/Android.mk |   24 +-
>  src/mesa/drivers/dri/i965/Makefile.am|6 +-
>  src/mesa/drivers/dri/i965/Makefile.sources   |4 +
>  src/mesa/drivers/dri/i965/brw_binding_tables.c   |   14 +
>  src/mesa/drivers/dri/i965/brw_blorp.c|4 +
>  src/mesa/drivers/dri/i965/brw_blorp.h|2 +
>  src/mesa/drivers/dri/i965/brw_formatquery.c  |1 +
>  src/mesa/drivers/dri/i965/brw_program.c  |2 +-
>  src/mesa/drivers/dri/i965/brw_state.h|7 +
>  src/mesa/drivers/dri/i965/brw_state_upload.c |6 +-
>  src/mesa/drivers/dri/i965/brw_wm_surface_state.c |2 +
>  src/mesa/drivers/dri/i965/genX_state_upload.c|   20 +-
>  src/mesa/drivers/dri/i965/intel_mipmap_tree.c|5 +-
>  src/mesa/drivers/dri/i965/intel_screen.c |1 +
>  src/mesa/drivers/dri/i965/meson.build|2 +-
>  28 files changed, 3941 insertions(+), 22 deletions(-)
>  create mode 100644 src/intel/genxml/gen11.xml
>
> --
> 2.13.6
>
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[Mesa-dev] [PATCH 14/16] i965/icl: Disable HiZ surface sampling

[Anuj Phogat]

On gen11+ AUX_HIZ is not a supported value for surfaces being
sampled by the 3D sampler.

Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com>
---
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index f27d559149..9c6f166677 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -1912,9 +1912,10 @@ intel_miptree_sample_with_hiz(struct brw_context *brw,
const struct gen_device_info *devinfo = >screen->devinfo;
 
/* It's unclear how well supported sampling from the hiz buffer is on GEN8,
-* so keep things conservative for now and never enable it unless we're 
SKL+.
+* so keep things conservative for now and never enable it unless we're 
GEN9+.
+* Also, disable the sampling from the hiz buffer for GEN11+.
 */
-   if (devinfo->gen < 9) {
+   if (devinfo->gen < 9 || devinfo->gen > 10) {
   return false;
}
 
-- 
2.13.6

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[Mesa-dev] [PATCH 06/16] intel/icl: Do StateCacheInvalidation for indirect clear color

[Anuj Phogat]

StateCacheInvalidation is required on all gen7+ platforms. We
don't need to update this check for every new gen h/w unless
this requirement is changed. So, dropping the check for latest
gen h/w.

Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com>
---
 src/intel/blorp/blorp_genX_exec.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/intel/blorp/blorp_genX_exec.h 
b/src/intel/blorp/blorp_genX_exec.h
index 1968460be0..7420b9d91a 100644
--- a/src/intel/blorp/blorp_genX_exec.h
+++ b/src/intel/blorp/blorp_genX_exec.h
@@ -1389,7 +1389,7 @@ blorp_emit_surface_states(struct blorp_batch *batch,
   }
}
 
-#if GEN_GEN >= 7 && GEN_GEN <= 10
+#if GEN_GEN >= 7
if (has_indirect_clear_color) {
   /* Updating a surface state object may require that the state cache be
* invalidated. From the SKL PRM, Shared Functions -> State -> State
-- 
2.13.6

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[Mesa-dev] [PATCH 16/16] i965/icl: Add render target flush after uploading binding table

[Anuj Phogat]

From PIPE_CONTROL command description in gfxspecs:

"Whenever a Binding Table Index (BTI) used by a Render Taget Message
 points to a different RENDER_SURFACE_STATE, SW must issue a Render
 Target Cache Flush by enabling this bit. When render target flush
 is set due to new association of BTI, PS Scoreboard Stall bit must
 be set in this packet."

Fixes a fulsim error and a GPU hang described in below JIRA.

JIRA: MD5-322
Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com>
---
 src/mesa/drivers/dri/i965/brw_binding_tables.c | 14 ++
 1 file changed, 14 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/brw_binding_tables.c 
b/src/mesa/drivers/dri/i965/brw_binding_tables.c
index 73f5e56010..170daebc24 100644
--- a/src/mesa/drivers/dri/i965/brw_binding_tables.c
+++ b/src/mesa/drivers/dri/i965/brw_binding_tables.c
@@ -93,6 +93,20 @@ brw_upload_binding_table(struct brw_context *brw,
   OUT_BATCH(stage_state->bind_bo_offset);
   ADVANCE_BATCH();
}
+
+   /* From PIPE_CONTROL command description in gfxspecs:
+
+  "Whenever a Binding Table Index (BTI) used by a Render Taget Message
+   points to a different RENDER_SURFACE_STATE, SW must issue a Render
+   Target Cache Flush by enabling this bit. When render target flush
+   is set due to new association of BTI, PS Scoreboard Stall bit must
+   be set in this packet."
+   */
+   if (devinfo->gen >= 11) {
+  brw_emit_pipe_control_flush(brw,
+  PIPE_CONTROL_RENDER_TARGET_FLUSH |
+  PIPE_CONTROL_STALL_AT_SCOREBOARD);
+   }
 }
 
 /**
-- 
2.13.6

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[Mesa-dev] [PATCH 13/16] i965/icl: Add assertions to check dispatch mode is SIMD8

[Anuj Phogat]

SIMD4x2 dispatch mode has been removed in GEN11. We're not using
it anyways in Mesa. Adding few asserts to make it explicit.

Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com>
---
 src/intel/blorp/blorp_genX_exec.h | 4 
 src/mesa/drivers/dri/i965/genX_state_upload.c | 5 +
 2 files changed, 9 insertions(+)

diff --git a/src/intel/blorp/blorp_genX_exec.h 
b/src/intel/blorp/blorp_genX_exec.h
index 85cd74f915..aa2baf6c6f 100644
--- a/src/intel/blorp/blorp_genX_exec.h
+++ b/src/intel/blorp/blorp_genX_exec.h
@@ -572,6 +572,10 @@ blorp_emit_vs_config(struct blorp_batch *batch,
  const struct blorp_params *params)
 {
struct brw_vs_prog_data *vs_prog_data = params->vs_prog_data;
+#if GEN_GEN >= 11
+   assert(!vs_prog_data ||
+  vs_prog_data->base.dispatch_mode == DISPATCH_MODE_SIMD8);
+#endif
 
blorp_emit(batch, GENX(3DSTATE_VS), vs) {
   if (vs_prog_data) {
diff --git a/src/mesa/drivers/dri/i965/genX_state_upload.c 
b/src/mesa/drivers/dri/i965/genX_state_upload.c
index fa7dded8df..8f28052505 100644
--- a/src/mesa/drivers/dri/i965/genX_state_upload.c
+++ b/src/mesa/drivers/dri/i965/genX_state_upload.c
@@ -2044,6 +2044,8 @@ genX(upload_vs_state)(struct brw_context *brw)
 
assert(vue_prog_data->dispatch_mode == DISPATCH_MODE_SIMD8 ||
   vue_prog_data->dispatch_mode == DISPATCH_MODE_4X2_DUAL_OBJECT);
+   assert(devinfo->gen < 11 ||
+  vue_prog_data->dispatch_mode == DISPATCH_MODE_SIMD8);
 
 #if GEN_GEN == 6
/* From the BSpec, 3D Pipeline > Geometry > Vertex Shader > State,
@@ -3961,6 +3963,9 @@ genX(upload_ds_state)(struct brw_context *brw)
if (!tes_prog_data) {
   brw_batch_emit(brw, GENX(3DSTATE_DS), ds);
} else {
+  assert(devinfo->gen < 11 ||
+ vue_prog_data->dispatch_mode == DISPATCH_MODE_SIMD8);
+
   brw_batch_emit(brw, GENX(3DSTATE_DS), ds) {
  INIT_THREAD_DISPATCH_FIELDS(ds, Patch);
 
-- 
2.13.6

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[Mesa-dev] [PATCH 15/16] i965/icl: Enable float blend optimization and Wa3DStateMode

[Anuj Phogat]

Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com>
---
 src/mesa/drivers/dri/i965/brw_state_upload.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c 
b/src/mesa/drivers/dri/i965/brw_state_upload.c
index 2c8c0f4b27..86c12e4d35 100644
--- a/src/mesa/drivers/dri/i965/brw_state_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_state_upload.c
@@ -62,7 +62,7 @@ brw_upload_initial_gpu_state(struct brw_context *brw)
 
brw_upload_invariant_state(brw);
 
-   if (devinfo->gen == 10) {
+   if (devinfo->gen == 10 || devinfo->gen == 11) {
   brw_load_register_imm32(brw, GEN10_CACHE_MODE_SS,
   REG_MASK(GEN10_FLOAT_BLEND_OPTIMIZATION_ENABLE) |
   GEN10_FLOAT_BLEND_OPTIMIZATION_ENABLE);
-- 
2.13.6

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[Mesa-dev] [PATCH 11/16] i965/icl: Update the assert in brw_memory_barrier()

[Anuj Phogat]

Nothing is changed here from gen10 to gen11. So, just update
the assert.

Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com>
---
 src/mesa/drivers/dri/i965/brw_program.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/brw_program.c 
b/src/mesa/drivers/dri/i965/brw_program.c
index 7fae22c620..381cc2887d 100644
--- a/src/mesa/drivers/dri/i965/brw_program.c
+++ b/src/mesa/drivers/dri/i965/brw_program.c
@@ -280,7 +280,7 @@ brw_memory_barrier(struct gl_context *ctx, GLbitfield 
barriers)
unsigned bits = (PIPE_CONTROL_DATA_CACHE_FLUSH |
 PIPE_CONTROL_NO_WRITE |
 PIPE_CONTROL_CS_STALL);
-   assert(devinfo->gen >= 7 && devinfo->gen <= 10);
+   assert(devinfo->gen >= 7 && devinfo->gen <= 11);
 
if (barriers & (GL_VERTEX_ATTRIB_ARRAY_BARRIER_BIT |
GL_ELEMENT_ARRAY_BARRIER_BIT |
-- 
2.13.6

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[Mesa-dev] [PATCH 02/16] intel/genxml/icl: Generate packing headers

[Anuj Phogat]

Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com>
---
 src/intel/Android.genxml.mk   | 5 +
 src/intel/Makefile.sources| 3 ++-
 src/intel/genxml/genX_pack.h  | 2 ++
 src/intel/genxml/gen_macros.h | 3 +++
 4 files changed, 12 insertions(+), 1 deletion(-)

diff --git a/src/intel/Android.genxml.mk b/src/intel/Android.genxml.mk
index e4d8dd8b94..8b867920c3 100644
--- a/src/intel/Android.genxml.mk
+++ b/src/intel/Android.genxml.mk
@@ -101,6 +101,11 @@ $(intermediates)/genxml/gen10_pack.h: PRIVATE_XML := 
$(LOCAL_PATH)/genxml/gen10.
 $(intermediates)/genxml/gen10_pack.h: $(LOCAL_PATH)/genxml/gen10.xml 
$(LOCAL_PATH)/genxml/gen_pack_header.py
$(call header-gen)
 
+$(intermediates)/genxml/gen11_pack.h: PRIVATE_SCRIPT := $(MESA_PYTHON2) 
$(LOCAL_PATH)/genxml/gen_pack_header.py
+$(intermediates)/genxml/gen11_pack.h: PRIVATE_XML := 
$(LOCAL_PATH)/genxml/gen11.xml
+$(intermediates)/genxml/gen11_pack.h: $(LOCAL_PATH)/genxml/gen11.xml 
$(LOCAL_PATH)/genxml/gen_pack_header.py
+   $(call header-gen)
+
 $(intermediates)/genxml/genX_xml.h: $(addprefix 
$(MESA_TOP)/src/intel/,$(GENXML_XML_FILES)) 
$(MESA_TOP)/src/intel/genxml/gen_zipped_file.py
@mkdir -p $(dir $@)
@echo "Gen Header: $(PRIVATE_MODULE) <= $(notdir $(@))"
diff --git a/src/intel/Makefile.sources b/src/intel/Makefile.sources
index 2d76c93e56..4c0240bdf1 100644
--- a/src/intel/Makefile.sources
+++ b/src/intel/Makefile.sources
@@ -144,7 +144,8 @@ GENXML_GENERATED_PACK_FILES = \
genxml/gen75_pack.h \
genxml/gen8_pack.h \
genxml/gen9_pack.h \
-   genxml/gen10_pack.h
+   genxml/gen10_pack.h \
+   genxml/gen11_pack.h
 
 GENXML_GENERATED_FILES = \
$(GENXML_GENERATED_PACK_FILES) \
diff --git a/src/intel/genxml/genX_pack.h b/src/intel/genxml/genX_pack.h
index 187e75c598..cf39973db1 100644
--- a/src/intel/genxml/genX_pack.h
+++ b/src/intel/genxml/genX_pack.h
@@ -46,6 +46,8 @@
 #  include "genxml/gen9_pack.h"
 #elif (GEN_VERSIONx10 == 100)
 #  include "genxml/gen10_pack.h"
+#elif (GEN_VERSIONx10 == 110)
+#  include "genxml/gen11_pack.h"
 #else
 #  error "Need to add a pack header include for this gen"
 #endif
diff --git a/src/intel/genxml/gen_macros.h b/src/intel/genxml/gen_macros.h
index a85c08250c..43449a41a4 100644
--- a/src/intel/genxml/gen_macros.h
+++ b/src/intel/genxml/gen_macros.h
@@ -88,6 +88,9 @@
 #elif (GEN_VERSIONx10 == 100)
 #  define GENX(X) GEN10_##X
 #  define genX(x) gen10_##x
+#elif (GEN_VERSIONx10 == 110)
+#  define GENX(X) GEN11_##X
+#  define genX(x) gen11_##x
 #else
 #  error "Need to add prefixing macros for this gen"
 #endif
-- 
2.13.6

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[Mesa-dev] [PATCH 05/16] intel/isl/icl: Build and use gen11 surface state emit functions

[Anuj Phogat]

Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com>
---
 src/intel/Android.isl.mk   | 20 
 src/intel/Makefile.isl.am  |  4 
 src/intel/Makefile.sources |  4 
 src/intel/isl/isl.c|  3 +++
 src/intel/isl/isl_priv.h   |  3 +++
 src/intel/isl/meson.build  |  2 +-
 6 files changed, 35 insertions(+), 1 deletion(-)

diff --git a/src/intel/Android.isl.mk b/src/intel/Android.isl.mk
index 516ac3a210..23cff55d25 100644
--- a/src/intel/Android.isl.mk
+++ b/src/intel/Android.isl.mk
@@ -180,6 +180,25 @@ include $(MESA_COMMON_MK)
 include $(BUILD_STATIC_LIBRARY)
 
 # ---
+# Build libmesa_isl_gen11
+# ---
+
+include $(CLEAR_VARS)
+
+LOCAL_MODULE := libmesa_isl_gen11
+
+LOCAL_SRC_FILES := $(ISL_GEN11_FILES)
+
+LOCAL_CFLAGS := -DGEN_VERSIONx10=110
+
+LOCAL_C_INCLUDES := $(LIBISL_GENX_COMMON_INCLUDES)
+
+LOCAL_WHOLE_STATIC_LIBRARIES := libmesa_genxml
+
+include $(MESA_COMMON_MK)
+include $(BUILD_STATIC_LIBRARY)
+
+# ---
 # Build libmesa_isl
 # ---
 
@@ -207,6 +226,7 @@ LOCAL_WHOLE_STATIC_LIBRARIES := \
libmesa_isl_gen8 \
libmesa_isl_gen9 \
libmesa_isl_gen10 \
+   libmesa_isl_gen11 \
libmesa_genxml
 
 # Autogenerated sources
diff --git a/src/intel/Makefile.isl.am b/src/intel/Makefile.isl.am
index 31273af36c..9525f9e990 100644
--- a/src/intel/Makefile.isl.am
+++ b/src/intel/Makefile.isl.am
@@ -28,6 +28,7 @@ ISL_GEN_LIBS =   \
isl/libisl-gen8.la   \
isl/libisl-gen9.la   \
isl/libisl-gen10.la  \
+   isl/libisl-gen11.la  \
$(NULL)
 
 noinst_LTLIBRARIES += $(ISL_GEN_LIBS) isl/libisl.la
@@ -59,6 +60,9 @@ isl_libisl_gen9_la_CFLAGS = $(AM_CFLAGS) -DGEN_VERSIONx10=90
 isl_libisl_gen10_la_SOURCES = $(ISL_GEN10_FILES)
 isl_libisl_gen10_la_CFLAGS = $(AM_CFLAGS) -DGEN_VERSIONx10=100
 
+isl_libisl_gen11_la_SOURCES = $(ISL_GEN11_FILES)
+isl_libisl_gen11_la_CFLAGS = $(AM_CFLAGS) -DGEN_VERSIONx10=110
+
 BUILT_SOURCES += $(ISL_GENERATED_FILES)
 
 isl/isl_format_layout.c: isl/gen_format_layout.py \
diff --git a/src/intel/Makefile.sources b/src/intel/Makefile.sources
index 4c0240bdf1..22563cac6a 100644
--- a/src/intel/Makefile.sources
+++ b/src/intel/Makefile.sources
@@ -203,6 +203,10 @@ ISL_GEN10_FILES = \
isl/isl_emit_depth_stencil.c \
isl/isl_surface_state.c
 
+ISL_GEN11_FILES = \
+   isl/isl_emit_depth_stencil.c \
+   isl/isl_surface_state.c
+
 ISL_GENERATED_FILES = \
isl/isl_format_layout.c
 
diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
index c9873d96df..0d8db37bb5 100644
--- a/src/intel/isl/isl.c
+++ b/src/intel/isl/isl.c
@@ -1778,6 +1778,9 @@ isl_surf_get_ccs_surf(const struct isl_device *dev,
case 10:\
   isl_gen10_##func(__VA_ARGS__);   \
   break;   \
+   case 11:\
+  isl_gen11_##func(__VA_ARGS__);   \
+  break;   \
default:\
   assert(!"Unknown hardware generation");  \
}
diff --git a/src/intel/isl/isl_priv.h b/src/intel/isl/isl_priv.h
index 2122e7cb75..b86167bb3a 100644
--- a/src/intel/isl/isl_priv.h
+++ b/src/intel/isl/isl_priv.h
@@ -190,6 +190,9 @@ isl_extent3d_el_to_sa(enum isl_format fmt, struct 
isl_extent3d extent_el)
 #  define genX(x) gen10_##x
 #  include "isl_genX_priv.h"
 #  undef genX
+#  define genX(x) gen11_##x
+#  include "isl_genX_priv.h"
+#  undef genX
 #endif
 
 #endif /* ISL_PRIV_H */
diff --git a/src/intel/isl/meson.build b/src/intel/isl/meson.build
index 0838c32af3..36b8b8ffa2 100644
--- a/src/intel/isl/meson.build
+++ b/src/intel/isl/meson.build
@@ -51,7 +51,7 @@ isl_gen9_files = files(
 isl_gen_libs = []
 foreach g : [['40', isl_gen4_files], ['50', []], ['60', isl_gen6_files],
  ['70', isl_gen7_files], ['75', []], ['80', isl_gen8_files],
- ['90', isl_gen9_files], ['100', []]]
+ ['90', isl_gen9_files], ['100', []], ['110', []]]
   _gen = g[0]
   isl_gen_libs += static_library(
 'libisl_gen@0@'.format(_gen),
-- 
2.13.6

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