Re: [Mesa-dev] [PATCH 1/3] mesa/main/shaderapi: Use generate_sha1() unconditionally

On 05/17/2018 02:00 PM, Benedikt Schemmer wrote: Ok I found the commit. But it says: "Until we have a proper fix." So this would be a good time I guess ;) Agreed, using ENABLE_SHADER_CACHE to guard some OS specifics is dirty, it should be only guarding shader cache itself. --- author

Re: [Mesa-dev] [PATCH] vulkan: update vk_icd.h to current upstream

Acked-by: Jason Ekstrand On Thu, May 17, 2018 at 10:05 PM, Tapani Pälli wrote: > Import from commit eb0c1fd on branch 'master' > of https://github.com/KhronosGroup/Vulkan-Headers.git. > > Signed-off-by: Tapani Pälli > --- >

[Mesa-dev] [PATCH 1/1] travis: Adapt to radeonsi dropping support for LLVM 4

meson Vulkan, Clover, and autotools Vulkan need to be switched to llvm 5 Fixes: f9eb1ef870eba9fdacf9a8cbd815ec3bff81db05 Signed-off-by: Jan Vesely --- .travis.yml | 14 +++--- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/.travis.yml b/.travis.yml

Re: [Mesa-dev] [PATCH 1/2] dri_util: Add R10G10B10{A, X}2 translation between DRI and mesa_format.

Series Reviewed-by: Tapani Pälli On 05/07/2018 06:45 PM, Miguel Casas wrote: Add R10G10B10{A,X}2 translation between mesa_format and DRI format to driGLFormatToImageFormat() and driImageFormatToGLFormat(). Bug: https://crbug.com/776093 ---

[Mesa-dev] [PATCH] vulkan: update vk_icd.h to current upstream

Import from commit eb0c1fd on branch 'master' of https://github.com/KhronosGroup/Vulkan-Headers.git. Signed-off-by: Tapani Pälli --- include/vulkan/vk_icd.h | 67 ++--- 1 file changed, 53 insertions(+), 14 deletions(-) diff

Re: [Mesa-dev] [PATCH] draw: get rid of special logic to not emit null tris

Tested-by: Dieter Nützel on RX580 with UH, UV, glmark2, Blender 2.79, FreeCAD 0.17, Gimp 2.10, digikam 5.9.0, Krita 4.0.3 and some Mesa-demos Dieter Am 17.05.2018 18:30, schrieb srol...@vmware.com: From: Roland Scheidegger I've confirmed after

Re: [Mesa-dev] [PATCH 6/6] radeonsi: set DB_EQAA.MAX_ANCHOR_SAMPLES correctly

For the series: Tested-by: Dieter Nützel on RX580 with UH, UV, glmark2, Blender 2.79, FreeCAD 0.17, Gimp 2.10, digikam 5.9.0, Krita 4.0.3 and some Mesa-demos Dieter 17.05.2018 03:47, schrieb Marek Olšák: From: Marek Olšák ---

Re: [Mesa-dev] [PATCH] radeonsi: skip ES output stores for undefined output components

Tested-by: Dieter Nützel on RX580 with UH, UV, glmark2, Blender 2.79, FreeCAD 0.17, Gimp 2.10, digikam 5.9.0, Krita 4.0.3 and some Mesa-demos Dieter Am 18.05.2018 00:14, schrieb Marek Olšák: From: Marek Olšák ---

[Mesa-dev] [RFC PATCH] gallium: add interface for advanced MSAA

From: Marek Olšák The interface only uses general MSAA terms, so it's "advanced MSAA" and not something vendor-specific. It's a proper subset of EQAA, and a proper superset of CSAA, so it's neither. Changes: - pipe_resource is changed - is_format_supported is changed - a

Re: [Mesa-dev] [PATCH] vbo: remove MaxVertexAttribStride assert check.

On 15 May 2018 at 16:31, Mathias Fröhlich wrote: > Hi Dave, > > On Tuesday, 15 May 2018 07:44:44 CEST Dave Airlie wrote: >> From: Dave Airlie >> >> Some drivers (virgl) don't support GL4.4 or GLES3.1 yet, >> so never fill in this const. > > May be I

Re: [Mesa-dev] [PATCH 3/3] mesa/main/shaderapi: purely non-functional cleanups, like whitespace errors and cleanups

On 05/10/2018 12:05 PM, Benedikt Schemmer wrote: remove a memset too and yes, this is all functionally identical --- src/mesa/main/shaderapi.c | 40 1 file changed, 20 insertions(+), 20 deletions(-) diff --git a/src/mesa/main/shaderapi.c

Re: [Mesa-dev] [PATCH 1/3] mesa/main/shaderapi: Use generate_sha1() unconditionally

On 05/10/2018 12:05 PM, Benedikt Schemmer wrote: Move shader-cache code from back to front and make generate_sha1() usable unconditionally to avoid code duplication in the following patch --- src/mesa/main/shaderapi.c | 228 +++--- 1 file changed,

[Mesa-dev] [PATCH] radv: only pass the global BO list at submit time if enabled

That way the winsys might use a faster path when the global BO list is NULL. Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_device.c | 8 ++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/src/amd/vulkan/radv_device.c

Re: [Mesa-dev] [PATCH] radv: only pass the global BO list at submit time if enabled

Reviewed-by: Bas Nieuwenhuizen On Thu, May 17, 2018 at 11:36 AM, Samuel Pitoiset wrote: > That way the winsys might use a faster path when the global > BO list is NULL. > > Signed-off-by: Samuel Pitoiset > --- >

Re: [Mesa-dev] [PATCH 2/2] radv: remove the radv_finishme() when compiling shaders

Reviewed-by: Bas Nieuwenhuizen for both. On Thu, May 17, 2018 at 9:56 AM, Samuel Pitoiset wrote: > Having an entrypoint different than "main" doesn't mean we > have multiple shaders per module. > > Signed-off-by: Samuel Pitoiset

Re: [Mesa-dev] [PATCH v2] android: enable VK_ANDROID_native_buffer

Ok, so long as the current build isn't broken without it, rb. On May 17, 2018 00:16:44 Tapani Pälli wrote: On 05/17/2018 09:38 AM, Jason Ekstrand wrote: What happened to the vk_icd.h bit? That's going here: https://github.com/KhronosGroup/Vulkan-Headers/pull/2 On

[Mesa-dev] [PATCH 16/22] compiler/spirv: implement 16-bit hyperbolic trigonometric functions

--- src/compiler/spirv/vtn_glsl450.c | 29 +++-- 1 file changed, 19 insertions(+), 10 deletions(-) diff --git a/src/compiler/spirv/vtn_glsl450.c b/src/compiler/spirv/vtn_glsl450.c index 324e8b5874a..738f1ea93f1 100644 --- a/src/compiler/spirv/vtn_glsl450.c +++

[Mesa-dev] [PATCH 20/22] compiler/nir: add lowering for 16-bit flrp

--- src/compiler/nir/nir.h| 1 + src/compiler/nir/nir_opt_algebraic.py | 1 + 2 files changed, 2 insertions(+) diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h index 59c84bde268..7e4c78cc1b7 100644 --- a/src/compiler/nir/nir.h +++ b/src/compiler/nir/nir.h @@ -1871,6

[Mesa-dev] [PATCH 21/22] intel/compiler: lower 16-bit flrp

--- src/intel/compiler/brw_compiler.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/intel/compiler/brw_compiler.c b/src/intel/compiler/brw_compiler.c index 36a870ece0d..250e4695ded 100644 --- a/src/intel/compiler/brw_compiler.c +++ b/src/intel/compiler/brw_compiler.c @@ -33,6 +33,7 @@

[Mesa-dev] [PATCH 22/22] intel/compiler: Extended Math is limited to SIMD8 on half-float

From the Skylake PRM, Extended Math Function: "The execution size must be no more than 8 when half-floats are used in source or destination operand." Earlier generations do not support Extended Math with half-float. --- src/intel/compiler/brw_fs.cpp | 30 +++--- 1

[Mesa-dev] [PATCH 17/22] compiler/spirv: implement 16-bit frexp

--- src/compiler/spirv/vtn_glsl450.c | 48 ++-- 1 file changed, 46 insertions(+), 2 deletions(-) diff --git a/src/compiler/spirv/vtn_glsl450.c b/src/compiler/spirv/vtn_glsl450.c index 738f1ea93f1..88d2dcfb0fd 100644 --- a/src/compiler/spirv/vtn_glsl450.c +++

[Mesa-dev] [PATCH 18/22] compiler/nir: add lowering option for 16-bit fmod

--- src/compiler/nir/nir.h| 1 + src/compiler/nir/nir_opt_algebraic.py | 1 + 2 files changed, 2 insertions(+) diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h index a379928cdcd..59c84bde268 100644 --- a/src/compiler/nir/nir.h +++ b/src/compiler/nir/nir.h @@ -1877,6

[Mesa-dev] [PATCH 19/22] intel/compiler: lower 16-bit fmod

--- src/intel/compiler/brw_compiler.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/intel/compiler/brw_compiler.c b/src/intel/compiler/brw_compiler.c index 6480dbefbf6..36a870ece0d 100644 --- a/src/intel/compiler/brw_compiler.c +++ b/src/intel/compiler/brw_compiler.c @@ -33,6 +33,7 @@

Re: [Mesa-dev] [PATCH] amd: remove support for LLVM 4.0

Acked-by: Samuel Pitoiset On 05/17/2018 04:25 AM, Marek Olšák wrote: From: Marek Olšák It doesn't support GFX9. --- .travis.yml | 6 +- configure.ac | 4 +- meson.build

Re: [Mesa-dev] [PATCH 2/6] radeonsi: disable primitive binning for all blitter ops

On Thu, May 17, 2018 at 4:47 AM, Marek Olšák wrote: > From: Marek Olšák > > same as Vulkan. Ambiguous. Did you mean amdvlk? Gražvydas > --- > src/gallium/drivers/radeonsi/si_blit.c | 10 ++ > src/gallium/drivers/radeonsi/si_pipe.h

Re: [Mesa-dev] [PATCH 2/3] mesa/main/shaderapi: Use sha as part of captured shaders name

Am 17.05.2018 um 09:11 schrieb Tapani Pälli: > some nitpicking below .. I'll do some testing to see that things work as > before but overall these changes look good to me. Would be nice to hear > comments from active shader-db users. > > On 05/10/2018 12:05 PM, Benedikt Schemmer wrote: >> It

Re: [Mesa-dev] [PATCH 2/3] mesa/main/shaderapi: Use sha as part of captured shaders name

On 05/17/2018 11:49 AM, Benedikt Schemmer wrote: Am 17.05.2018 um 09:11 schrieb Tapani Pälli: some nitpicking below .. I'll do some testing to see that things work as before but overall these changes look good to me. Would be nice to hear comments from active shader-db users. On

[Mesa-dev] [PATCH] i965/disasm: Always print message descriptor and SFID for SEND instructions

Having the disassembly always show the message descriptor and SFID makes it easier to debug what data is actually fed to the external units. Descriptor format was changed to unsigned so that immediate values as 'src1' will get printed out in a readable format. --- src/intel/compiler/brw_disasm.c

Re: [Mesa-dev] [PATCH v2] android: enable VK_ANDROID_native_buffer

What happened to the vk_icd.h bit? On May 16, 2018 22:30:55 Tapani Pälli wrote: Patch changes entrypoints generator to not skip this extension even though it is set as disabled in the xml. We also need compilation flag VK_USE_PLATFORM_ANDROID_KHR to be enabled. It

[Mesa-dev] [PATCH 1/4] mesa: Remove FLUSH_VERTICES from VAO state changes.

From: Mathias Fröhlich Pending draw calls on immediate mode or display list calls do not depend on changes of the VAO state. So, remove calls to FLUSH_VERTICES and flag _NEW_ARRAY as appropriate. Signed-off-by: Mathias Fröhlich ---

[Mesa-dev] [PATCH 0/4] Some cleanup in state invalidation around VAOs.

From: Mathias Fröhlich Hi Brian, The patch series mostly takes care of FLUSH_VERTICES and signalling _NEW_ARRAY changes in the context of the VAO. The FLUSH_VERTICES macro is used to finally carry a set of pending immediate mode draw calls to the hardware for

[Mesa-dev] [PATCH 4/4] mesa: The glArrayElement api is independent of the current program.

From: Mathias Fröhlich All the shader program dependent handling is done on the level of the gl_Context::Array._DrawVAO/_DrawVAOEnabledAttribs. So, skip array element invalidation on _NEW_PROGRAM. Signed-off-by: Mathias Fröhlich ---

[Mesa-dev] [PATCH 3/4] mesa: Flag _NEW_ARRAY only if we are changing ctx->Array.VAO.

From: Mathias Fröhlich For the VAO internal helper functions that may be called with a non current VAO, flag the _NEW_ARRAY state only if it is the current ctx->Array.VAO. Signed-off-by: Mathias Fröhlich --- src/mesa/main/varray.c | 20

Re: [Mesa-dev] [PATCH v2] docs: add 18.0.5 in the release calendar

On Mon, 2018-05-14 at 16:18 +0200, Juan A. Suarez Romero wrote: > Mesa 18.1 series has not been released yet, so let's extend 18.0 lifetime. > > v2: Add missing closing TR tags (Eric Engestrom) > > CC: Andres Gomez > CC: Emil Velikov Gently ping.

Re: [Mesa-dev] [PATCH 2/3] mesa/main/shaderapi: Use sha as part of captured shaders name

some nitpicking below .. I'll do some testing to see that things work as before but overall these changes look good to me. Would be nice to hear comments from active shader-db users. On 05/10/2018 12:05 PM, Benedikt Schemmer wrote: It is inconvenient to capture shaders by program name alone

[Mesa-dev] [PATCH 03/22] compiler/spirv: fix SpvOpIsInf for 16-bit float

--- src/compiler/spirv/vtn_alu.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/compiler/spirv/vtn_alu.c b/src/compiler/spirv/vtn_alu.c index 5f9cc97fdfb..62a5149797a 100644 --- a/src/compiler/spirv/vtn_alu.c +++ b/src/compiler/spirv/vtn_alu.c @@ -578,7 +578,9 @@

[Mesa-dev] [PATCH 04/22] intel/compiler: lower some 16-bit float operations to 32-bit

The hardware doesn't support half-float for these. --- src/intel/compiler/brw_nir.c | 5 + 1 file changed, 5 insertions(+) diff --git a/src/intel/compiler/brw_nir.c b/src/intel/compiler/brw_nir.c index dfeea73b06a..ff245b59b81 100644 --- a/src/intel/compiler/brw_nir.c +++

[Mesa-dev] [PATCH 09/22] intel/compiler: implement 16-bit multiply-add

The PRM for MAD states that F, DF and HF are supported, however, then it requires that the instruction includes a 2-bit mask specifying the types of each operand like this: 00: 32-bit float 01: 32-bit signed integer 10: 32-bit unsigned integer 11: 64-bit float So 16-bit float would not be

[Mesa-dev] [PATCH 10/22] intel/compiler: allow extended math functions with HF operands

The PRM states that half-float operands are supported since gen9. --- src/intel/compiler/brw_eu_emit.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c index ee5a048bcaa..20c3f9fa933 100644 ---

[Mesa-dev] [PATCH 15/22] compiler/spirv: implement 16-bit exp and log

--- src/compiler/spirv/vtn_glsl450.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/compiler/spirv/vtn_glsl450.c b/src/compiler/spirv/vtn_glsl450.c index 70e3eb80c4c..324e8b5874a 100644 --- a/src/compiler/spirv/vtn_glsl450.c +++ b/src/compiler/spirv/vtn_glsl450.c @@

[Mesa-dev] [PATCH 14/22] compiler/spirv: implement 16-bit atan2

--- src/compiler/spirv/vtn_glsl450.c | 22 +++--- 1 file changed, 15 insertions(+), 7 deletions(-) diff --git a/src/compiler/spirv/vtn_glsl450.c b/src/compiler/spirv/vtn_glsl450.c index 9e565ef9e5a..70e3eb80c4c 100644 --- a/src/compiler/spirv/vtn_glsl450.c +++

[Mesa-dev] [PATCH 13/22] compiler/spirv: implement 16-bit atan

--- src/compiler/spirv/vtn_glsl450.c | 37 + 1 file changed, 25 insertions(+), 12 deletions(-) diff --git a/src/compiler/spirv/vtn_glsl450.c b/src/compiler/spirv/vtn_glsl450.c index 8cbdaad3998..9e565ef9e5a 100644 --- a/src/compiler/spirv/vtn_glsl450.c +++

[Mesa-dev] [PATCH 08/22] intel/compiler: implement 16-bit fsign

--- src/intel/compiler/brw_fs_nir.cpp | 27 +-- 1 file changed, 21 insertions(+), 6 deletions(-) diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index fb5ad7a614a..91283ab4911 100644 --- a/src/intel/compiler/brw_fs_nir.cpp +++

[Mesa-dev] [PATCH 06/22] compiler/nir: support 16-bit float in nir_imm_floatN_t

--- src/compiler/nir/nir_builder.h | 29 - 1 file changed, 16 insertions(+), 13 deletions(-) diff --git a/src/compiler/nir/nir_builder.h b/src/compiler/nir/nir_builder.h index 02a9dbfb040..198c42dd823 100644 --- a/src/compiler/nir/nir_builder.h +++

[Mesa-dev] [PATCH 07/22] compiler/spirv: handle 16-bit float in radians() and degrees()

--- src/compiler/spirv/vtn_glsl450.c | 10 -- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/src/compiler/spirv/vtn_glsl450.c b/src/compiler/spirv/vtn_glsl450.c index 6fa759b1bba..ffe12a71818 100644 --- a/src/compiler/spirv/vtn_glsl450.c +++

[Mesa-dev] [PATCH 12/22] compiler/spirv: implement 16-bit acos

--- src/compiler/spirv/vtn_glsl450.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/compiler/spirv/vtn_glsl450.c b/src/compiler/spirv/vtn_glsl450.c index 845e5a9e517..8cbdaad3998 100644 --- a/src/compiler/spirv/vtn_glsl450.c +++ b/src/compiler/spirv/vtn_glsl450.c @@

[Mesa-dev] [PATCH 11/22] compiler/spirv: implement 16-bit asin

--- src/compiler/spirv/vtn_glsl450.c | 20 +--- 1 file changed, 13 insertions(+), 7 deletions(-) diff --git a/src/compiler/spirv/vtn_glsl450.c b/src/compiler/spirv/vtn_glsl450.c index ffe12a71818..845e5a9e517 100644 --- a/src/compiler/spirv/vtn_glsl450.c +++

[Mesa-dev] [PATCH 2/4] mesa: Remove flush_vertrices argument from VAO methods.

From: Mathias Fröhlich The flush_vertices argument is now unused, remove it. Signed-off-by: Mathias Fröhlich --- src/mesa/drivers/common/meta.c | 32 ++- src/mesa/main/bufferobj.c| 2 +-

Re: [Mesa-dev] threading in OSMesa and gallium swr driver

Thank you for your answer. I understand I can control the number of threads and prevent them to be assigned to actual hardware threads. Preventing oversubscription of the hardware threads is challenging when using OpenMP/TBB/OpenSWR in hybrid environments. I am wondering if having N SWR

[Mesa-dev] [PATCH 1/2] radv: remove radv_device::llvm_supports_spill

It's always true. Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_device.c | 2 -- src/amd/vulkan/radv_private.h | 1 - src/amd/vulkan/radv_shader.c | 5 + 3 files changed, 1 insertion(+), 7 deletions(-) diff --git a/src/amd/vulkan/radv_device.c

[Mesa-dev] [PATCH 2/2] radv: remove the radv_finishme() when compiling shaders

Having an entrypoint different than "main" doesn't mean we have multiple shaders per module. Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_shader.c | 4 1 file changed, 4 deletions(-) diff --git a/src/amd/vulkan/radv_shader.c

[Mesa-dev] [RFC PATCH] virgl: Always assume that ORIGIN_UPPER_LEFT and PIXEL_CENTER* are supported

The driver must support at least one of PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT and one of PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER otherwise glsl_to_tgsi will fire an assert.

[Mesa-dev] [PATCH 3/3] i965: Use the VAOs binding information in array setup.

From: Mathias Fröhlich The change basically reimplements array setup by walking the gl_contex::Array._DrawVAO on a per binding sequence. In this way we can make direct use of the application provided minimum set of buffer objects and emit fewer relocs. Signed-off-by:

[Mesa-dev] [PATCH 0/3] Make use of VAO information in i965.

From: Mathias Fröhlich Hi all, This change finally makes use of the binding/attribute information now present in the VAO. The big part is basically a rewrite of brw_draw_upload in a way that traverses in an outer loop the bindings and for each binding the attached

[Mesa-dev] [PATCH 1/3] i965: Move down genX_upload_sbe in profiles.

From: Mathias Fröhlich Avoid looping over all VARYING_SLOT_MAX urb_setup array entries from genX_upload_sbe. Prepare an array indirection to the active entries of urb_setup already in the compile step. On upload only walk the active arrays. Signed-off-by: Mathias

[Mesa-dev] [PATCH 2/3] i965: Split merge_inputs and clear_buffers.

From: Mathias Fröhlich The merge_inputs function handles that part that changes when the inputs change. The clear_buffers function triggers when we may need a new upload. Thus the merge_inputs can be limited to be once per brw_draw_prims. Signed-off-by: Mathias

Re: [Mesa-dev] [PATCH v2 16/21] nir/linker: Add nir_build_program_resource_list()

On 15/05/18 01:05, Alejandro Piñeiro wrote: On 14/05/18 01:26, Timothy Arceri wrote: On 12/05/18 19:40, Alejandro Piñeiro wrote: From: Eduardo Lima Mitev This function is equivalent to the linker.cpp build_program_resource_list() but will extract the resources from NIR

Re: [Mesa-dev] [PATCH v2] android: enable VK_ANDROID_native_buffer

On 05/17/2018 09:38 AM, Jason Ekstrand wrote: What happened to the vk_icd.h bit? That's going here: https://github.com/KhronosGroup/Vulkan-Headers/pull/2 On May 16, 2018 22:30:55 Tapani Pälli wrote: Patch changes entrypoints generator to not skip this extension

[Mesa-dev] [Bug 106337] eglWaitClient() doesn't work as documented using DRI2 backend

https://bugs.freedesktop.org/show_bug.cgi?id=106337 --- Comment #12 from Tapani Pälli --- There has been some discussion in the mesa-dev mailing list, consensus there was one should rather use glFinish on the client side in this case. Mesa-dev discussion:

Re: [Mesa-dev] [PATCH 3/3] mesa/main/shaderapi: purely non-functional cleanups, like whitespace errors and cleanups

Am 17.05.2018 um 08:59 schrieb Tapani Pälli: > > > On 05/10/2018 12:05 PM, Benedikt Schemmer wrote: >> remove a memset too and yes, this is all functionally identical >> >> --- >>   src/mesa/main/shaderapi.c | 40 >>   1 file changed, 20 insertions(+),

Re: [Mesa-dev] [PATCH 6/9] intel/blorp: Make blorp_ccs_ambiguate just an internal helper

On Wed, 2018-05-16 at 08:44 -0700, Jason Ekstrand wrote: > On Wed, May 16, 2018 at 4:00 AM, Iago Toral > wrote: > > On Tue, 2018-05-15 at 15:28 -0700, Jason Ekstrand wrote: > > > > > Now that anv uses blorp_ccs_op for everything, we no longer need > > to > > > > > expose the

[Mesa-dev] [PATCH 00/22] spirv/intel: half-float compiler enablement

Most of our compiler was already 16-bit aware thanks to previous work on VK_KHR_16bit_storage and shaderInt16, but specifically for 16-bit floating point, we were missing a few things such as some lowerings that depend on the specific bit representation of the float or some hardware restrictions

[Mesa-dev] [PATCH 01/22] i965/fs: implement conversions from float16 to 64 bits data types

From: Samuel Iglesias Gonsálvez Signed-off-by: Samuel Iglesias Gonsálvez --- src/intel/compiler/brw_fs_nir.cpp | 32 1 file changed, 32 insertions(+) diff --git a/src/intel/compiler/brw_fs_nir.cpp

[Mesa-dev] [PATCH 05/22] intel/compiler: lower 16-bit extended math to 32-bit prior to gen9

Extended math desn't support half-float on these generations. --- src/intel/compiler/brw_nir.c | 13 - 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/src/intel/compiler/brw_nir.c b/src/intel/compiler/brw_nir.c index ff245b59b81..8337da57585 100644 ---

[Mesa-dev] [PATCH 02/22] i965/fs: Implement float64 to float16 conversion

From: Samuel Iglesias Gonsálvez It is not supported directly in the HW, we need to convert to float32 first as intermediate step. Signed-off-by: Samuel Iglesias Gonsálvez --- src/intel/compiler/brw_fs_nir.cpp | 17 + 1 file changed,

Re: [Mesa-dev] [PATCH] mesa: drop GL_EXT_polygon_offset support

Ping! On 11/05/18 15:38, Timothy Arceri wrote: glPolygonOffset() has been part of the GL standard since 1.1. Also niether AMD or Nvidia support this in their binary drivers. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=61761 --- docs/relnotes/18.2.0.html | 64

Re: [Mesa-dev] [PATCH v2] android: enable VK_ANDROID_native_buffer

On 05/17/2018 10:23 AM, Jason Ekstrand wrote: Ok, so long as the current build isn't broken without it, rb. Well TBH it does not compile but I thought you wanted the change to come as a pull from upstream header. I can put it back here temporarily or just later update the header. On May

Re: [Mesa-dev] [PATCH 1/3] mesa/main/shaderapi: Use generate_sha1() unconditionally

Thanks for reviewing! Am 17.05.2018 um 08:42 schrieb Tapani Pälli: > > > On 05/10/2018 12:05 PM, Benedikt Schemmer wrote: >> Move shader-cache code from back to front and make generate_sha1() usable >> unconditionally to avoid code duplication in the following patch >> >> --- >>  

Re: [Mesa-dev] [PATCH 1/3] mesa/main/shaderapi: Use generate_sha1() unconditionally

On 05/17/2018 11:38 AM, Benedikt Schemmer wrote: Thanks for reviewing! Am 17.05.2018 um 08:42 schrieb Tapani Pälli: On 05/10/2018 12:05 PM, Benedikt Schemmer wrote: Move shader-cache code from back to front and make generate_sha1() usable unconditionally to avoid code duplication in the

[Mesa-dev] [PATCH 2/2] radv: add radv_emit_shader_pointer() helper

For future work (support for 32-bit GPU pointers). Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_cmd_buffer.c | 13 ++--- src/amd/vulkan/radv_device.c | 17 +++-- src/amd/vulkan/radv_private.h| 3 +++ 3 files changed, 20

Re: [Mesa-dev] [PATCH 2/4] mesa: Remove flush_vertrices argument from VAO methods.

In the subject line "flush_vertices" For this series, Reviewed-by: Brian Paul More nice clean-ups! -Brian On 05/17/2018 12:37 AM, mathias.froehl...@gmx.net wrote: From: Mathias Fröhlich The flush_vertices argument is now unused, remove it.

Re: [Mesa-dev] [PATCH 1/3] mesa/main/shaderapi: Use generate_sha1() unconditionally

I looked at the appveyor log for that specific build https://ci.appveyor.com/project/mesa3d/mesa/build/3186 It seems to only complain about disk_cache.c src\util\disk_cache.c(28) : fatal error C1083: Cannot open include file: 'sys/file.h': No such file or directory scons: ***

Re: [Mesa-dev] [PATCH] autotools, meson: add tileset.h

On Monday, 2018-05-14 11:05:34 -0700, Dylan Baker wrote: > Quoting Eric Engestrom (2018-05-14 06:09:59) > > > > Dylan, what do you think? Do we want to remove all the unnecessary > > files() from meson, or keep them to mirror what was needed by autotools? > > I'd vote 'remove', but the "let's do

Re: [Mesa-dev] [PATCH 09/22] intel/compiler: implement 16-bit multiply-add

Hi, On 17.05.2018 11:46, Iago Toral Quiroga wrote: The PRM for MAD states that F, DF and HF are supported, however, then it requires that the instruction includes a 2-bit mask specifying the types of each operand like this: > 00: 32-bit float 01: 32-bit signed integer 10: 32-bit unsigned

Re: [Mesa-dev] [PATCH 06/22] compiler/nir: support 16-bit float in nir_imm_floatN_t

Why did the function move? On May 17, 2018 01:47:51 Iago Toral Quiroga wrote: --- src/compiler/nir/nir_builder.h | 29 - 1 file changed, 16 insertions(+), 13 deletions(-) diff --git a/src/compiler/nir/nir_builder.h

Re: [Mesa-dev] [PATCH 07/22] compiler/spirv: handle 16-bit float in radians() and degrees()

Rb On May 17, 2018 01:48:03 Iago Toral Quiroga wrote: --- src/compiler/spirv/vtn_glsl450.c | 10 -- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/src/compiler/spirv/vtn_glsl450.c b/src/compiler/spirv/vtn_glsl450.c index 6fa759b1bba..ffe12a71818

Re: [Mesa-dev] [PATCH 03/22] compiler/spirv: fix SpvOpIsInf for 16-bit float

On May 17, 2018 01:47:11 Iago Toral Quiroga wrote: --- src/compiler/spirv/vtn_alu.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/compiler/spirv/vtn_alu.c b/src/compiler/spirv/vtn_alu.c index 5f9cc97fdfb..62a5149797a 100644 ---

Re: [Mesa-dev] [PATCH 18/22] compiler/nir: add lowering option for 16-bit fmod

Rb On May 17, 2018 01:48:27 Iago Toral Quiroga wrote: --- src/compiler/nir/nir.h| 1 + src/compiler/nir/nir_opt_algebraic.py | 1 + 2 files changed, 2 insertions(+) diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h index a379928cdcd..59c84bde268

Re: [Mesa-dev] [PATCH 15/22] compiler/spirv: implement 16-bit exp and log

Rb On May 17, 2018 01:48:43 Iago Toral Quiroga wrote: --- src/compiler/spirv/vtn_glsl450.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/compiler/spirv/vtn_glsl450.c b/src/compiler/spirv/vtn_glsl450.c index 70e3eb80c4c..324e8b5874a 100644 ---

Re: [Mesa-dev] [PATCH v2] android: enable VK_ANDROID_native_buffer

Whatever. If there isn't too much of a rush, my preference would be to pull in the vk_icd.h fix as a pull from upstream and then do this afterwards. I guess this doesn't help anyone without the vk_icd.h fix. If we are in a rush, I'd be ok with making the fix in our tree so long as it's in

[Mesa-dev] [PATCH 0/2] st/dri format handling cleanups

Hi all, those 2 patches clean up and align the format handling in the dri state tracker to how the intel driver implements some details of the interface. This is mostly in preparation for etnaviv to support native planar YUV import without needing any of the R8/RG88 sampler rewrites, as those

[Mesa-dev] [PATCH 2/2] st/dri: replace format conversion functions with single mapping table

Each time I have to touch the buffer import/export functions in the dri state tracker I get lost in the maze of functions converting between DRI_IMAGE_FOURCC, DRI_IMAGE_FORMAT, DRI_IMAGE_COMPONENTS and pipe format. Rip it out and replace by a single table, which defines the correspondence between

[Mesa-dev] [PATCH 1/2] st/dri: allow both render and sampler compatible dma-buf formats

Currently all the EGL APIs are missing a way to specify how an imported dma-buf is intended to be used. Demanding the format to be both usable for sampling and rendering artificially restricts the list of formats a driver is able to import. Looking at how the Intel driver implements those DRI2

[Mesa-dev] [PATCH mesa] i965: Check result of make_surface() for miptree_create

From: Andrea Azzarone Since make_surface() can fail we need to check the result before dereferencing it. Bug: https://github.com/mesa3d/mesa/pull/5 Bug: https://bugs.launchpad.net/ubuntu/+source/gnome-shell/+bug/1760415 Reviewed-by: Eric Engestrom

Re: [Mesa-dev] [PATCH 06/22] compiler/nir: support 16-bit float in nir_imm_floatN_t

After sending this, I realized that it's probably because you depend on nir_imm_intN_t(). Alternatively, we could make a nir_imm_float16() helper which may be nicer for cases where you know you need 16-bit floats. This is fine though. Rb. On May 17, 2018 07:01:53 Jason Ekstrand

Re: [Mesa-dev] [PATCH 9.5/17] squash! i965/miptree: Unify aux buffer allocation

On Thu, May 17, 2018 at 07:44:34AM +0300, Pohjolainen, Topi wrote: > On Wed, May 16, 2018 at 09:33:34AM -0700, Nanley Chery wrote: > > On Wed, May 16, 2018 at 09:11:38AM +0300, Pohjolainen, Topi wrote: > > > On Wed, May 09, 2018 at 10:47:24AM -0700, Nanley Chery wrote: > > > > v2: Inline the

Re: [Mesa-dev] [PATCH 1/3] mesa/main/shaderapi: Use generate_sha1() unconditionally

Ok I found the commit. But it says: "Until we have a proper fix." So this would be a good time I guess ;) --- author Emil Velikov 2017-01-18 19:40:31 + committer Emil Velikov 2017-01-18 20:09:01 + commit

[Mesa-dev] [PATCH 1/2] radv: add some helpers for cleaning up radv_get_preamble_cs()

Because this function looks a bit ugly to me. Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_device.c | 214 +-- 1 file changed, 128 insertions(+), 86 deletions(-) diff --git a/src/amd/vulkan/radv_device.c

Re: [Mesa-dev] [PATCH 20/22] compiler/nir: add lowering for 16-bit flrp

Rb On May 17, 2018 01:49:07 Iago Toral Quiroga wrote: --- src/compiler/nir/nir.h| 1 + src/compiler/nir/nir_opt_algebraic.py | 1 + 2 files changed, 2 insertions(+) diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h index 59c84bde268..7e4c78cc1b7

Re: [Mesa-dev] [PATCH 21/22] intel/compiler: lower 16-bit flrp

Rb On May 17, 2018 01:48:43 Iago Toral Quiroga wrote: --- src/intel/compiler/brw_compiler.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/intel/compiler/brw_compiler.c b/src/intel/compiler/brw_compiler.c index 36a870ece0d..250e4695ded 100644 ---

Re: [Mesa-dev] [PATCH 19/22] intel/compiler: lower 16-bit fmod

Rb On May 17, 2018 01:48:33 Iago Toral Quiroga wrote: --- src/intel/compiler/brw_compiler.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/intel/compiler/brw_compiler.c b/src/intel/compiler/brw_compiler.c index 6480dbefbf6..36a870ece0d 100644 ---

[Mesa-dev] [Bug 78097] glUniform1ui and friends not supported by display lists

https://bugs.freedesktop.org/show_bug.cgi?id=78097 Lionel Landwerlin changed: What|Removed |Added Resolution|---

[Mesa-dev] [Bug 78097] glUniform1ui and friends not supported by display lists

https://bugs.freedesktop.org/show_bug.cgi?id=78097 --- Comment #4 from Lionel Landwerlin --- Arg apologies, I was running against the wrong version of Mesa. -- You are receiving this mail because: You are the assignee for the

Re: [Mesa-dev] [PATCH 2/6] radeonsi: disable primitive binning for all blitter ops

On Thu, May 17, 2018 at 4:35 AM, Grazvydas Ignotas wrote: > On Thu, May 17, 2018 at 4:47 AM, Marek Olšák wrote: > > From: Marek Olšák > > > > same as Vulkan. > > Ambiguous. Did you mean amdvlk? > Of course. Marek

Re: [Mesa-dev] [Mesa-stable] [PATCH 01/17] i965/miptree: Fix handling of uninitialized MCS buffers

Quoting Nanley Chery (2018-05-03 12:03:48) > Before this patch, if we failed to initialize an MCS buffer, we'd > end up in a state in which the miptree thinks it has an MCS buffer, > but doesn't. We also leaked the clear_color_bo if it existed. > > With this patch, we now free the miptree aux

Re: [Mesa-dev] [PATCH 2/2] radv: add radv_emit_shader_pointer() helper

Do we want the new function inlined? Reviewed-by: Bas Nieuwenhuizen On Thu, May 17, 2018 at 2:16 PM, Samuel Pitoiset wrote: > For future work (support for 32-bit GPU pointers). > > Signed-off-by: Samuel Pitoiset >

[Mesa-dev] [Bug 78097] glUniform1ui and friends not supported by display lists

https://bugs.freedesktop.org/show_bug.cgi?id=78097 --- Comment #3 from Lionel Landwerlin --- $ ./bin/gl-3.0-dlist-uint-uniforms -auto -fbo Testing glUniformui GL_COMPILE: scalar mode pre-initialize compiling post-compile verify

Re: [Mesa-dev] [PATCH 1/5] swr/rast: Remove unneeded virtual from methods

Whole series Reviewed-By: George Kyriazis > Thanks! On May 16, 2018, at 11:14 AM, Alok Hota > wrote: --- src/gallium/drivers/swr/rasterizer/jitter/JitManager.h | 4 ++-- 1 file

Re: [Mesa-dev] [PATCH v2 0/6] broadcom/vc4: Native fence fd support

Stefan Schake writes: > v2 drops the submit flags, directly moves in fence handling to the > job submit function and queries for the syncobj cap instead of using > a separate support parameter. > > This series adds support for the native fence fd extension to vc4. > The

Re: [Mesa-dev] [PATCH] mesa: drop GL_EXT_polygon_offset support

Reviewed-by: Marek Olšák Marek On Fri, May 11, 2018 at 1:38 AM, Timothy Arceri wrote: > glPolygonOffset() has been part of the GL standard since 1.1. Also > niether AMD or Nvidia support this in their binary drivers. > > Bugzilla:

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