Rolf,
I don't know PCoC6, so I don't know if it accepts "connect under reset".
But if the only way to achieve it is through the time critical sequence you
have described, then I'm afraid that no user space tool will be able to
reliably produce it.
It's not a problem due to OpenOCD, but due to
Wind
Hi all,
I am working on PSoC6, dual core CM0+ / CM4 and I need a reset (toggle pulse:
high > low 10 ms > high > wait 100ms > attach SWD on CM4). So the CPU won’t
attach under reset but will attach after about 10-40ms. I will need set up the
.cfg file to have a SRST because the CPU can be in sle
Rolf,
you can try with
reset_config srst_only srst_nogate connect_assert_srst
but this is not valid for every SoC, so give it a try.
You can find more details in OpenOCD documentation, but shortly this
command will instruct OpenOCD to:
1) start and keep the SoC under reset
2) while the SoC is und
> How can I implement an SRST procedure of let’s say 10mS assert
Using the `adapter assert/deassert` and `sleep` commands maybe?
*
https://openocd.org/doc/html/General-Commands.html#:~:text=Command%3A%20adapter%20assert%20%5Bsignal,%5Bsignal%20%5Bassert%7Cdeassert%20signal%5D%5D
*
http
Hi Oleksij,
I understand this is a somewhat special procedure and as resetting is a
destructive procedure this isn’t wished for generally. The updating of the
flash drivers is not related to this, but I like to implement SRST into the
.cfg file to check complete functionality as well.
So maybe
Am 07.12.23 um 13:33 schrieb Rolf | Onethinx:
Hi Oleksij,
I understand this is a somewhat special procedure and as resetting is a
destructive procedure this isn’t wished for generally. The updating of the
flash drivers is not related to this, but I like to implement SRST into the
.cfg file to
Hi Rolf,
Am 05.12.23 um 12:37 schrieb Rolf | Onethinx:
Hi,
I am looking to updating the OpenOCD flash drivers for Infineon PSoC6 and
syncing with the latest Infineon branch.
I have an issue with chip SRST reset which seems to work differently on several
adapters (CMSIS-DAP / KitProg / JLink)
Hi,
I am looking to updating the OpenOCD flash drivers for Infineon PSoC6 and
syncing with the latest Infineon branch.
I have an issue with chip SRST reset which seems to work differently on several
adapters (CMSIS-DAP / KitProg / JLink). For the cases where the CPU is in
sleep, a SRST reset i
