Re: [PEDA] RF footprints

[Brian Guralnick]

Don't forget my Smooth Transition track size generator.

Open this link in your internet explorer:
ftp://ftp.point-lab.com/quartus/Public/ProtelUsers/

SmoothTrackSizeTransitionProtel.bas

Free Others:
InductorGeneratorProtelScript.bas - Generates continuous 'S' shaped inductors.
SpiralGeneratorProtelScript.bas - Spiral shaped inductor generator.
QFPfootprintGeneratorScript.bas - Protel ClientBasic script.
QFPfootprintGeneratorScript.txt   - added documentation.

SuperCompact.zip - Complete set of super compact symbols which I made for Protel
Schematic.


All free, no login or membership required!


Brian Guralnick
-
---
Comedy clips:
ftp://ftp.point-lab.com/quartus/Public/MP3/Simpsons-FatFingers.mp3  -53K
ftp://ftp.point-lab.com/quartus/Public/MP3/Simpsons-Moe-LieDetector.mp3 -166K

RedDwarf fans only - Year 8 - Shrink Kryten interview...
ftp://ftp.point-lab.com/quartus/Public/MP3/Shrink-Kryten-16kbit.mp3  -450K
ftp://ftp.point-lab.com/quartus/Public/MP3/Shrink-Kryten-48kbit.mp3  -1.4M
-
---


- Original Message -
From: "Darren Moore" <[EMAIL PROTECTED]>
To: "'Protel EDA Forum'" <[EMAIL PROTECTED]>
Sent: Thursday, February 21, 2002 5:44 PM
Subject: Re: [PEDA] RF footprints


|
| Hi Randol,
|
| > > Brian G.  and others wrote a spiral track generator for
| > > Protel.  Use that.
| >
| > OOooo!!  Where's that?!  Does it lock the tracks together so
| > that they don't get independently pulled and the group can be
| > drug together?  I've not tried to make a "footprint" like
| > this, I've just drawn the thing and had to redo it if I want
| > to move it.  Hopefully there's a better way.  I don't live
| > and breathe Protel.
|
| The following link is where the latest version of the spiral
| track generator.
|
| http://groups.yahoo.com/group/protel-users/files/
|
| SpiralGen20.zip (spiral track inductor generator GOLD)
|
| You may have to register with yahoo to get access.
|
| If you what the spiral track to move as one item, then
| you should make a new library footprint and cut the
| spiral from pcb and paste it into the library.
|
| Regards,
| Darren Moore
|
|

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Re: [PEDA] RF footprints

[Darren Moore]

Hi Randol,

> > Brian G.  and others wrote a spiral track generator for
> > Protel.  Use that.  
> 
> OOooo!!  Where's that?!  Does it lock the tracks together so 
> that they don't get independently pulled and the group can be 
> drug together?  I've not tried to make a "footprint" like 
> this, I've just drawn the thing and had to redo it if I want 
> to move it.  Hopefully there's a better way.  I don't live 
> and breathe Protel.

The following link is where the latest version of the spiral
track generator.

http://groups.yahoo.com/group/protel-users/files/

SpiralGen20.zip (spiral track inductor generator GOLD)

You may have to register with yahoo to get access.

If you what the spiral track to move as one item, then
you should make a new library footprint and cut the 
spiral from pcb and paste it into the library.

Regards,
Darren Moore

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Re: [PEDA] RF footprints

[Randol Mark-ryvw50]

> A typical RF CHOKE is lossy (deliberately) and hence one 
> would not normally 
> use a relatively high-Q PCB track to implement a choke.  

Er, not necessarily.  Having a lossy choke (series DC) is good in that it widens the 
bandwidth, but note that if you have a high power amplifier, drawing oodles of 
current, that series R is going to dissipate LOTS of power.  Not really what you want 
either from an efficiency or thermal management standpoint.  For "de-Qing" the feed 
from a hi-Q inductor, I've often seen a resistor applied in parallel to it.  That way 
most of the DC current goes through the inductor, but as the Z of the inductor 
increases with frequency, the resistor adds a resistive component to the parallel pair 
of components.

> 1/4 wavelength line is not what I would call a choke.  Choke 
> to me is a 
> soggy inductor.  A 1/4 wavelength line is more likely to be a 
> moderate to 
> High-Q resonator and has a different function to the old-stye 
> broadband, 
> flat response chokes.

They're used a "bias feeds" at higher frequencies (microwave especially).  Hi-Z at the 
desired frequency, low-Z at DC.

> Brian G.  and others wrote a spiral track generator for 
> Protel.  Use that.  

OOooo!!  Where's that?!  Does it lock the tracks together so that they don't get 
independently pulled and the group can be drug together?  I've not tried to make a 
"footprint" like this, I've just drawn the thing and had to redo it if I want to move 
it.  Hopefully there's a better way.  I don't live and breathe Protel.

Sorry if the comments are nit picks, but just wanted to provide another POV.

Thanks & regards,
-- 
Mark Randol, RF Evaluation Engineer
Motorola SPS, Inc.
M/S EL536
2100 E. Elliot Road
Tempe, AZ 85284
(480)413-8052 Voice
(480)413-8690 FAX
 

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Re: [PEDA] RF footprints

[Mike Ingle]

I place a split plane with a 1 mil (or smaller) border.  Then I trace around
the border with a track on the plane of the desired width (50 mil).  I leave
an opening where I want it (say under the ADC for example).  Effectively
this shors there and still passes DRC.

 Mike

-Original Message-
From: Damon Kelly [mailto:[EMAIL PROTECTED]]
Sent: Wednesday, February 20, 2002 5:51 PM
To: Protel EDA Forum
Subject: Re: [PEDA] RF footprints


Yes, I would really like a "Tie Net" entity!

Particularly (or most commonly) for the "analog ground" and "digital ground"
situation. I set different nets in the schematic, but when it comes time to
layout the PCB, the DRC spits the dummy when I tie the two grounds together
at the star point.

Does anyone have a work-around for this?
i.e. keep the two grounds (AGND and DGND) separate, EXCEPT for the nominated
tie point

Damon Kelly
Hardware Engineer


> -Original Message-
> From: Ian Wilson [mailto:[EMAIL PROTECTED]]
> Sent: Thursday, 21 February 2002 11:25
> To: Protel EDA Forum
> Subject: Re: [PEDA] RF footprints
>
>
> On 04:25 PM 20/02/2002 -0800, JaMi Smith said:
>
> >In view of your understanding of the problem, I take it then that you
> >too agree that there is a need for this issue to be
> presented to Protel.
> >
> >Really, not ranting,
> >
> >JaMi
>
> No, but care must be taken with language - mine was carefully
> chosen to be
> rude.  I am not sure if you wanted to create the impression of
> superciliousness but I am afraid that is the impression I
> took away from a
> reply that starts:
>
> >Abdul,
> >
> >Well ~
> >
> >You're almost right . . .
> >
> >A typical RF Choke on a PCB is a certain length conductor
> (typically 1/4
>
> (Especially after the last recent round of email designed to
> goad the only
> list member who *really* takes that time to understand the
> subtleties of
> each persons questions and responses.)
>
> Anyway on to matters of substance - Yes, I would like a Tie
> entity that was
> able to safely control the shorting of nets. This entity should be
> embeddable in library components as well as be able to be
> used as a free
> entity.  It should not constrain us as to what width it has
> and ideally
> what shape it can take.  IMO, it should certainly allow for safe net
> collisions in the following forms:
> 1) track to track  (tracks include arcs)
> 2) track to pad
> 3) track to fill
> 4) fill to fill
> 5) pad to pad may be difficult but may also be a nice feature.
>
> I would also like the Allow Short Circuits design rule to
> have region and
> object scopes.  This has been discussed before.  At the time it was
> discussed in the manner in which we have found has results
> with Protel now
> Altium.  That is constructive discussion about where the flaw
> maybe and
> then suggestions for how it can be better.
>
> Many of us who were part of the debacle of P99 and then the major
> improvements in P99SE have learnt that cryptic comments like "Go ask
> Protel" have no beneficial effect.  Much better to present the
> issue,  state what you would like and then have a calm, warts-and-all
> discussion.  Protel do watch this list and, I am sure,note
> when consensus
> is forming and also, I am sure, go away and think about methods of
> implementing some of the features that we have not been able
> to agree on
> how best to implement.
>
> Lecture off,
> Ian Wilson
>

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Re: [PEDA] RF footprints

[Damon Kelly]

Yes, I would really like a "Tie Net" entity!

Particularly (or most commonly) for the "analog ground" and "digital ground"
situation. I set different nets in the schematic, but when it comes time to
layout the PCB, the DRC spits the dummy when I tie the two grounds together
at the star point.

Does anyone have a work-around for this?
i.e. keep the two grounds (AGND and DGND) separate, EXCEPT for the nominated
tie point

Damon Kelly
Hardware Engineer


> -Original Message-
> From: Ian Wilson [mailto:[EMAIL PROTECTED]]
> Sent: Thursday, 21 February 2002 11:25
> To: Protel EDA Forum
> Subject: Re: [PEDA] RF footprints
> 
> 
> On 04:25 PM 20/02/2002 -0800, JaMi Smith said:
> 
> >In view of your understanding of the problem, I take it then that you
> >too agree that there is a need for this issue to be 
> presented to Protel.
> >
> >Really, not ranting,
> >
> >JaMi
> 
> No, but care must be taken with language - mine was carefully 
> chosen to be 
> rude.  I am not sure if you wanted to create the impression of 
> superciliousness but I am afraid that is the impression I 
> took away from a 
> reply that starts:
> 
> >Abdul,
> >
> >Well ~
> >
> >You're almost right . . .
> >
> >A typical RF Choke on a PCB is a certain length conductor 
> (typically 1/4
> 
> (Especially after the last recent round of email designed to 
> goad the only 
> list member who *really* takes that time to understand the 
> subtleties of 
> each persons questions and responses.)
> 
> Anyway on to matters of substance - Yes, I would like a Tie 
> entity that was 
> able to safely control the shorting of nets. This entity should be 
> embeddable in library components as well as be able to be 
> used as a free 
> entity.  It should not constrain us as to what width it has 
> and ideally 
> what shape it can take.  IMO, it should certainly allow for safe net 
> collisions in the following forms:
> 1) track to track  (tracks include arcs)
> 2) track to pad
> 3) track to fill
> 4) fill to fill
> 5) pad to pad may be difficult but may also be a nice feature.
> 
> I would also like the Allow Short Circuits design rule to 
> have region and 
> object scopes.  This has been discussed before.  At the time it was 
> discussed in the manner in which we have found has results 
> with Protel now 
> Altium.  That is constructive discussion about where the flaw 
> maybe and 
> then suggestions for how it can be better.
> 
> Many of us who were part of the debacle of P99 and then the major 
> improvements in P99SE have learnt that cryptic comments like "Go ask 
> Protel" have no beneficial effect.  Much better to present the 
> issue,  state what you would like and then have a calm, warts-and-all 
> discussion.  Protel do watch this list and, I am sure,note 
> when consensus 
> is forming and also, I am sure, go away and think about methods of 
> implementing some of the features that we have not been able 
> to agree on 
> how best to implement.
> 
> Lecture off,
> Ian Wilson
> 

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Re: [PEDA] RF footprints

[Andrew Jenkins]

Re: [PEDA] RF footprints

[Ian Wilson]

On 04:25 PM 20/02/2002 -0800, JaMi Smith said:

>In view of your understanding of the problem, I take it then that you
>too agree that there is a need for this issue to be presented to Protel.
>
>Really, not ranting,
>
>JaMi

No, but care must be taken with language - mine was carefully chosen to be 
rude.  I am not sure if you wanted to create the impression of 
superciliousness but I am afraid that is the impression I took away from a 
reply that starts:

>Abdul,
>
>Well ~
>
>You're almost right . . .
>
>A typical RF Choke on a PCB is a certain length conductor (typically 1/4

(Especially after the last recent round of email designed to goad the only 
list member who *really* takes that time to understand the subtleties of 
each persons questions and responses.)

Anyway on to matters of substance - Yes, I would like a Tie entity that was 
able to safely control the shorting of nets. This entity should be 
embeddable in library components as well as be able to be used as a free 
entity.  It should not constrain us as to what width it has and ideally 
what shape it can take.  IMO, it should certainly allow for safe net 
collisions in the following forms:
1) track to track  (tracks include arcs)
2) track to pad
3) track to fill
4) fill to fill
5) pad to pad may be difficult but may also be a nice feature.

I would also like the Allow Short Circuits design rule to have region and 
object scopes.  This has been discussed before.  At the time it was 
discussed in the manner in which we have found has results with Protel now 
Altium.  That is constructive discussion about where the flaw maybe and 
then suggestions for how it can be better.

Many of us who were part of the debacle of P99 and then the major 
improvements in P99SE have learnt that cryptic comments like "Go ask 
Protel" have no beneficial effect.  Much better to present the 
issue,  state what you would like and then have a calm, warts-and-all 
discussion.  Protel do watch this list and, I am sure,note when consensus 
is forming and also, I am sure, go away and think about methods of 
implementing some of the features that we have not been able to agree on 
how best to implement.

Lecture off,
Ian Wilson

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Re: [PEDA] RF footprints

[Don Ingram]

>
> What the hell is your point - are you deliberately being  prickly?  My
turn
> to be pedantic and pick up on your misconceptions. Am I peeved - yes.
JaMi
> (I persist in this weird spelling since you do but I must admit that I
> thought it was a typo when I first saw it)


Might either be a troll or an employee of a somewhat larger cad company ;-)


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Re: [PEDA] RF footprints

[JaMi Smith]

Bravo Ian,

It is nice to know that someone here knows something about RF, and no, I
am not ranting.

Unfortunately I have already written one response to a post by Lloyd
Good, which apparently hasn't shown up yet, so I will wait and let that
be my response. 

We appear to be suffering from list lag.

The issue is not what an RF Choke is, but how to make a component with a
short and have Protel use it like a regular footprint and not complain
about it being a short or messing up the netlist.

Respecting "Abdul's way" which he has presented here in the past as a
workrkaround for shorts with "small gap", I don't think that that is the
real answer, but rather I believe that Protel should address the
problem. I ment nothing more or nothing less

In view of your understanding of the problem, I take it then that you
too agree that there is a need for this issue to be presented to Protel.

Really, not ranting,

JaMi


-Original Message-
From: Ian Wilson [mailto:[EMAIL PROTECTED]] 
Sent: Wednesday, February 20, 2002 3:25 PM
To: Protel EDA Forum
Subject: Re: [PEDA] RF footprints

On 02:46 PM 20/02/2002 -0800, JaMi Smith said:
>Abdul,
>
>Well ~
>
>You're almost right . . .


Rant On

What the hell is your point - are you deliberately being  prickly?  My
turn 
to be pedantic and pick up on your misconceptions. Am I peeved - yes.
JaMi 
(I persist in this weird spelling since you do but I must admit that I 
thought it was a typo when I first saw it)


>A typical RF Choke on a PCB is a certain length conductor (typically
1/4
>wavelength), which is acting as an inductor, from one active part of an
>RF circuit (typically the Collector of an RF Transistor) to another
part
>of the circuit, typically power (or sometimes ground), such that it is
a
>"short" at DC, and isolated (or open) at a given frequency.

A typical RF CHOKE is lossy (deliberately) and hence one would not
normally 
use a relatively high-Q PCB track to implement a choke.  Inductor yes, 
choke no.  At least not below a few GHz where line edge accuracy,
surface 
finish of the copper, losses in the dielectric etc etc start to lower Q 
into the choke realm.

Now I use chokes to reduce the chance of oscillations in amps etc often
in 
the base cct, usually in the collector feed (before the collector 
inductor).  Since I have not designed many truely broadband amps in the 
recent years I have not placed a choke in a collector cct for many 
years.  Yes, I use them for supply filtering before I get to the hot 
collector cct.

(To elaborate, many old HF and VHF amplifiers used chokes in the
collector 
cct to provide bias and then use high-Q input and output matching ccts
to 
give the freq response desired.  Moderm design for many RF engineers 
consists of narrow fractional bandwidths, low power operation and
miniature 
design.  The use of RF collector chokes is not really an option for many
of 
us.  Hence my beef with the word "Typically" in JaMi's rant.)

1/4 wavelength line is not what I would call a choke.  Choke to me is a 
soggy inductor.  A 1/4 wavelength line is more likely to be a moderate
to 
High-Q resonator and has a different function to the old-stye broadband,

flat response chokes.

>Thus one can
>pass power thru the Choke to the Transistor, but it does not appear to
>be a short at RF frequencies. There are other applications, but this is
>probably the most common one you will find on a PCB, and is actually
>quite common today.
>
>Now - Go ask Protel how to make it . . .

Use a track.  Protel supports tracks, you know.  Used a curved 
meander.  Protel supports curved meanders (autorouter ripping them up
not 
withstanding).  Been there done that as have many other on this list.
You 
are by no means the only one with significant RF experience.  I know I
am 
counting 15 years and others here have more than that.

Brian G.  and others wrote a spiral track generator for Protel.  Use 
that.  Up to the knowledgeable designer to figure out the details of the

spiral though, not that PCB CAD package.  Now, some of the other CAE 
packages will help in designing RF ccts with copper elements.  Agilent, 
Eagle and others.  But Protel is not an RF CAE package, still it
certainly 
supports the track-based inductors that I need; I design them, I place 
them.  Bingo!

If you want a EM simulator then Protel is not it.  You can use Eagle etc
to 
design the layout from a RF POV.



>No, don't give us your version (which we have already seen here in the
>list), but go ask Protel how to make it.

What exactly is your point?  Protel knows very well how to put copper
onto 
a PCB.  It is the designers job to do the design, you know.

JaMi, you can take the above in two ways.  1) You think I am an bastard
or 
2) a warning that this is usually a very polite place, welcoming people 
from everywhere, and you have simply niggled enough people t

Re: [PEDA] RF footprints

[Ian Wilson]

On 02:46 PM 20/02/2002 -0800, JaMi Smith said:
>Abdul,
>
>Well ~
>
>You're almost right . . .
>
>A typical RF Choke on a PCB is a certain length conductor (typically 1/4
>wavelength), which is acting as an inductor, from one active part of an
>RF circuit (typically the Collector of an RF Transistor) to another part
>of the circuit, typically power (or sometimes ground), such that it is a
>"short" at DC, and isolated (or open) at a given frequency. Thus one can
>pass power thru the Choke to the Transistor, but it does not appear to
>be a short at RF frequencies. There are other applications, but this is
>probably the most common one you will find on a PCB, and is actually
>quite common today.
>
>Now - Go ask Protel how to make it . . .
>
>No, don't give us your version (which we have already seen here in the
>list), but go ask Protel how to make it.
>
>JaMi Smith

One few other points,

Abd ul-Rahman was the developer of the virtual short concept.  I leave it 
to you (as your are such a clever duck) to work out the relevance.

Protel allows you define a short cct rule permitting nets to short - I 
leave it to you to work out the relevance.

Mechanical layers can be used set to merge with other layers when producing 
gerbers - I leave it to you  .

Ian Wilson
(PS my rudeness for the day is exhausted, all sweetness and light from me 
for a while.)

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Re: [PEDA] RF footprints

[JaMi Smith]

Lloyd,

Thanks for the real world example.

My point is that this is a real world component, and Protel needs to
make a real world accommodation for it without saying "go make some
workaround yourself".

"Workarounds" take time to do each time they are needed, and also
produce errors, or minimally "Special Circumstances" which may not be
understood by the next engineer or designer that works on the board.

JaMi Smith

-Original Message-
From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED]] 
Sent: Wednesday, February 20, 2002 3:21 PM
To: Protel EDA Forum
Subject: Re: [PEDA] RF footprints

Not all problems in design are solved by software tools, however finding
an
adequate work around is often easier than adding the functionality to
the
tool set. 
I have only had limited experience in RF layout and coincidentally it
did
involve an inductor supplying power to an RF transistor.  In schematic I
placed an inductor in the cct to show the function, but using wires
shorted
the two nodes together with an explanation on the sheet as to why the
shorting wires were present. They were there to solve the netlist
problem
that would exist without their presence. 
On the PCB I created a component with two pads and shorted them with a
fill
of calculated length and width, given that I knew what material,
frequency
etc the design was for.
When running the DRC the check accepted the short as correct and having
manually routed the PCB I was confident that it was right. BTW the
transceiver did work and passed FCC/DOC testing.

Regards,

Lloyd Good
Engineering Systems Co-ordinator
GE Substation Automation Systems
2728 Hopewell Place NE
Calgary, Alberta, Canada
T1Y 7J7
Tel: (403) 214-4777
Fax:(403) 287-7946
email: [EMAIL PROTECTED]



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Re: [PEDA] RF footprints

[Ian Wilson]

On 02:46 PM 20/02/2002 -0800, JaMi Smith said:
>Abdul,
>
>Well ~
>
>You're almost right . . .


Rant On

What the hell is your point - are you deliberately being  prickly?  My turn 
to be pedantic and pick up on your misconceptions. Am I peeved - yes.  JaMi 
(I persist in this weird spelling since you do but I must admit that I 
thought it was a typo when I first saw it)


>A typical RF Choke on a PCB is a certain length conductor (typically 1/4
>wavelength), which is acting as an inductor, from one active part of an
>RF circuit (typically the Collector of an RF Transistor) to another part
>of the circuit, typically power (or sometimes ground), such that it is a
>"short" at DC, and isolated (or open) at a given frequency.

A typical RF CHOKE is lossy (deliberately) and hence one would not normally 
use a relatively high-Q PCB track to implement a choke.  Inductor yes, 
choke no.  At least not below a few GHz where line edge accuracy, surface 
finish of the copper, losses in the dielectric etc etc start to lower Q 
into the choke realm.

Now I use chokes to reduce the chance of oscillations in amps etc often in 
the base cct, usually in the collector feed (before the collector 
inductor).  Since I have not designed many truely broadband amps in the 
recent years I have not placed a choke in a collector cct for many 
years.  Yes, I use them for supply filtering before I get to the hot 
collector cct.

(To elaborate, many old HF and VHF amplifiers used chokes in the collector 
cct to provide bias and then use high-Q input and output matching ccts to 
give the freq response desired.  Moderm design for many RF engineers 
consists of narrow fractional bandwidths, low power operation and miniature 
design.  The use of RF collector chokes is not really an option for many of 
us.  Hence my beef with the word "Typically" in JaMi's rant.)

1/4 wavelength line is not what I would call a choke.  Choke to me is a 
soggy inductor.  A 1/4 wavelength line is more likely to be a moderate to 
High-Q resonator and has a different function to the old-stye broadband, 
flat response chokes.

>Thus one can
>pass power thru the Choke to the Transistor, but it does not appear to
>be a short at RF frequencies. There are other applications, but this is
>probably the most common one you will find on a PCB, and is actually
>quite common today.
>
>Now - Go ask Protel how to make it . . .

Use a track.  Protel supports tracks, you know.  Used a curved 
meander.  Protel supports curved meanders (autorouter ripping them up not 
withstanding).  Been there done that as have many other on this list.  You 
are by no means the only one with significant RF experience.  I know I am 
counting 15 years and others here have more than that.

Brian G.  and others wrote a spiral track generator for Protel.  Use 
that.  Up to the knowledgeable designer to figure out the details of the 
spiral though, not that PCB CAD package.  Now, some of the other CAE 
packages will help in designing RF ccts with copper elements.  Agilent, 
Eagle and others.  But Protel is not an RF CAE package, still it certainly 
supports the track-based inductors that I need; I design them, I place 
them.  Bingo!

If you want a EM simulator then Protel is not it.  You can use Eagle etc to 
design the layout from a RF POV.



>No, don't give us your version (which we have already seen here in the
>list), but go ask Protel how to make it.

What exactly is your point?  Protel knows very well how to put copper onto 
a PCB.  It is the designers job to do the design, you know.

JaMi, you can take the above in two ways.  1) You think I am an bastard or 
2) a warning that this is usually a very polite place, welcoming people 
from everywhere, and you have simply niggled enough people to piss me off 
sufficiently to write the above. Pull your head in or go away.

I welcome your reasonable, friendly input in the future - but I am close to 
adding a JaMi filter to my email...

Rant Off

Cranky,
Ian Wilson

Considered Solutions Pty Ltd mailto:[EMAIL PROTECTED]
ABN: 96 088 410 002
5 The Crescent
CHATSWOOD   2067
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Re: [PEDA] RF footprints

[JaMi Smith]

Ian and the group,

Shapes, be they spiral, oblong, obtuse, or whatever, are not the issue.

The issue is that an RF Choke is a legitimate device made with a copper
connection of some geometric shape from one point (terminal) to another
point (terminal), which Protel considers to be a direct short and
therefore an error.

Other types of "shorts" have been discussed here in the list in the
past.

I was hoping to entice someone into convincing Protel that they need to
make a provision for a person to be able to design such a footprint, and
tell the program that yes, you know it is a direct short in copper, but
that nonetheless you as a designer need to be able to tell the software
that believe it or not in this case you are smarter than the software
and therefore that as far as this component footprint is concerned,
ignore the short, if for no other reason than I told you so, and use
this component footprint just like any other 2 terminal component
footprint, and don't screw up my netlist, and don't tell me it is an
error, but I could probably live with a warning that I would have to
override when the component was first used.

JaMi Smith


-Original Message-
From: Ian Wilson [mailto:[EMAIL PROTECTED]] 
Sent: Wednesday, February 20, 2002 2:38 PM
To: Protel EDA Forum
Subject: Re: [PEDA] RF footprints

On 04:43 PM 20/02/2002 -0500, Abd ul-Rahman Lomax said:

>At 12:42 PM 2/20/2002 -0800, JaMi Smith wrote:
>
>>(Go ahead, ask Protel what
>>an RF Choke is, and how to make one in Protel).
 . . .

 . . .

There are Client Basic macros around to help in laying out spirals -
thanks 
mainly to Brian Guralnick (I think) plus a host of others that added
their 
tuppence worth.  This is but one example of what is possible.  Others
could 
be created to create meanders, transmissions lines with chamfers as 
desired.  Client basic is (almost) powerful enough to do this.

Functions such as laying down RF components are best left the users to 
develop rather than Protel trying to add to the core program. Protel, 
though, should ensure that even the simple macro language has some 
reasonable access into the database and the user interface.  The big
gaps 
here in Client Basics access to the database, mostly the lack of a
process 
in PCB to prompt the user to select a location (fixed by a third party 
server), and, in both Sch and PCB, the lack of  access to component
fields 
(currently no server that I know has this capability - but it could
easily 
be provided).

I think that such wizards and servers and macros are best left to the
users 
to create and Protel to concentrate on making the underlying SDK and
core 
processes reliable.

The area of users co-operating on creating macros and servers is one
area I 
think the user community can go much further than it currently does.

Ian Wilson

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Re: [PEDA] RF footprints

[lloyd . good]

Not all problems in design are solved by software tools, however finding an
adequate work around is often easier than adding the functionality to the
tool set. 
I have only had limited experience in RF layout and coincidentally it did
involve an inductor supplying power to an RF transistor.  In schematic I
placed an inductor in the cct to show the function, but using wires shorted
the two nodes together with an explanation on the sheet as to why the
shorting wires were present. They were there to solve the netlist problem
that would exist without their presence. 
On the PCB I created a component with two pads and shorted them with a fill
of calculated length and width, given that I knew what material, frequency
etc the design was for.
When running the DRC the check accepted the short as correct and having
manually routed the PCB I was confident that it was right. BTW the
transceiver did work and passed FCC/DOC testing.

Regards,

Lloyd Good
Engineering Systems Co-ordinator
GE Substation Automation Systems
2728 Hopewell Place NE
Calgary, Alberta, Canada
T1Y 7J7
Tel: (403) 214-4777
Fax:(403) 287-7946
email: [EMAIL PROTECTED]


-

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Re: [PEDA] RF footprints

[JaMi Smith]

Abdul,

Well ~

You're almost right . . .

A typical RF Choke on a PCB is a certain length conductor (typically 1/4
wavelength), which is acting as an inductor, from one active part of an
RF circuit (typically the Collector of an RF Transistor) to another part
of the circuit, typically power (or sometimes ground), such that it is a
"short" at DC, and isolated (or open) at a given frequency. Thus one can
pass power thru the Choke to the Transistor, but it does not appear to
be a short at RF frequencies. There are other applications, but this is
probably the most common one you will find on a PCB, and is actually
quite common today.

Now - Go ask Protel how to make it . . .

No, don't give us your version (which we have already seen here in the
list), but go ask Protel how to make it.

JaMi Smith

-Original Message-
From: Abd ul-Rahman Lomax [mailto:[EMAIL PROTECTED]] 
Sent: Wednesday, February 20, 2002 1:44 PM
To: Protel EDA Forum
Cc: JaMi Smith; JaMi Smith
Subject: RF footprints

At 12:42 PM 2/20/2002 -0800, JaMi Smith wrote:

>(Go ahead, ask Protel what
>an RF Choke is, and how to make one in Protel).

Printed components tend to not have fixed sizes, unless they have fixed 
values or functions. If one wanted to make an RF choke footprint, one
would 
have to have a separate footprint for each value, with variations on
that 
for various choke parameters.

Instead, one would provide a wizard for generating such parts; feed the 
wizard the PCB parameters -- which is already in the PCB file --, type
of 
pattern, desired parameters, and the wizard would attempt to create a 
pattern that satisfied the conditions. I have in the past been given 
dimensions for creating series of certain narrowly defined parts, the 
dimensions came from work with a field solver or other similar programs.

(I'm not an RF engineer, but I work closely with one.)

All this would fit very nicely into the Protel mission, but it is not a 
simple piece of work.

[EMAIL PROTECTED]
Abdulrahman Lomax
Easthampton, Massachusetts USA


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Re: [PEDA] RF footprints

[Ian Wilson]

On 04:43 PM 20/02/2002 -0500, Abd ul-Rahman Lomax said:

>At 12:42 PM 2/20/2002 -0800, JaMi Smith wrote:
>
>>(Go ahead, ask Protel what
>>an RF Choke is, and how to make one in Protel).
>
>Printed components tend to not have fixed sizes, unless they have fixed 
>values or functions. If one wanted to make an RF choke footprint, one 
>would have to have a separate footprint for each value, with variations on 
>that for various choke parameters.
>
>Instead, one would provide a wizard for generating such parts; feed the 
>wizard the PCB parameters -- which is already in the PCB file --, type of 
>pattern, desired parameters, and the wizard would attempt to create a 
>pattern that satisfied the conditions. I have in the past been given 
>dimensions for creating series of certain narrowly defined parts, the 
>dimensions came from work with a field solver or other similar programs. 
>(I'm not an RF engineer, but I work closely with one.)
>
>All this would fit very nicely into the Protel mission, but it is not a 
>simple piece of work.

There are Client Basic macros around to help in laying out spirals - thanks 
mainly to Brian Guralnick (I think) plus a host of others that added their 
tuppence worth.  This is but one example of what is possible.  Others could 
be created to create meanders, transmissions lines with chamfers as 
desired.  Client basic is (almost) powerful enough to do this.

Functions such as laying down RF components are best left the users to 
develop rather than Protel trying to add to the core program. Protel, 
though, should ensure that even the simple macro language has some 
reasonable access into the database and the user interface.  The big gaps 
here in Client Basics access to the database, mostly the lack of a process 
in PCB to prompt the user to select a location (fixed by a third party 
server), and, in both Sch and PCB, the lack of  access to component fields 
(currently no server that I know has this capability - but it could easily 
be provided).

I think that such wizards and servers and macros are best left to the users 
to create and Protel to concentrate on making the underlying SDK and core 
processes reliable.

The area of users co-operating on creating macros and servers is one area I 
think the user community can go much further than it currently does.

Ian Wilson

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[PEDA] RF footprints

[Abd ul-Rahman Lomax]

At 12:42 PM 2/20/2002 -0800, JaMi Smith wrote:

>(Go ahead, ask Protel what
>an RF Choke is, and how to make one in Protel).

Printed components tend to not have fixed sizes, unless they have fixed 
values or functions. If one wanted to make an RF choke footprint, one would 
have to have a separate footprint for each value, with variations on that 
for various choke parameters.

Instead, one would provide a wizard for generating such parts; feed the 
wizard the PCB parameters -- which is already in the PCB file --, type of 
pattern, desired parameters, and the wizard would attempt to create a 
pattern that satisfied the conditions. I have in the past been given 
dimensions for creating series of certain narrowly defined parts, the 
dimensions came from work with a field solver or other similar programs. 
(I'm not an RF engineer, but I work closely with one.)

All this would fit very nicely into the Protel mission, but it is not a 
simple piece of work.

[EMAIL PROTECTED]
Abdulrahman Lomax
Easthampton, Massachusetts USA

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