I also use a simple staircase pattern to check layer order and spacing. I
make sure that all traces at the edge of the board are ground to avoid any
problems. A few strokes with a file are usually all it takes to make them
visible. It would be easy to use an aligned pattern of narrow traces on
Account Manager or call 1-800-NII-4LNB or email
[EMAIL PROTECTED]
> -Original Message-
> From: Brian Guralnick [mailto:[EMAIL PROTECTED]]
> Sent: Monday, December 16, 2002 12:31 PM
> To: Protel EDA Forum
> Subject: Re: [PEDA] PCB Layout Tricks to help identi
In a message dated 12/16/2002 2:30:48 PM Eastern Standard Time,
[EMAIL PROTECTED] writes:
> Last year, I had a run of 1000 PCB's (4 layer) where 80% initially
> passed QC, then 90% of the pass PCBs failed after a few days
> of use. After exhaustive investigation, I cut right through the PC
MAIL PROTECTED]>
Sent: Monday, December 16, 2002 3:00 PM
Subject: Re: [PEDA] PCB Layout Tricks to help identify Lemmon PCB's.
> Brian,
> yes there are various IPC coupons that can be used for all of your
> issues. However in order to proper inspect those coupons you will have to
>
Brian,
yes there are various IPC coupons that can be used for all of your
issues. However in order to proper inspect those coupons you will have to
have the fabricator perform microsections (as opposed to you having to
"slice" the board) for you to verify the build. Sorry I don't know the
s
use IPC 2221, and use the coupons. This will allow you to follow the build
up of layers through plating and drilling. Any destructive testing can be
done on these avoiding having to destroy a sample of the production board.
Regards,
Ted
-Original Message-
From: Brian Guralnick [mailto:[E
