Re: [Qemu-devel] [PATCH] hw/intc/arm_gicv3_kvm: Check KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS in reset

Hi Eric, On Tue, Mar 28, 2017 at 7:28 PM, Eric Auger wrote: > KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS needs to be checked before > attempting to read ICC_CTLR_EL1; otherwise kernel versions not > exposing this kvm device group will be incompatible with qemu 2.9. > > Fixes:

[Qemu-devel] [PATCH v9 2/5] hw/intc/arm_gicv3_kvm: Add ICC_SRE_EL1 register to vmstate

From: Vijaya Kumar K To Save and Restore ICC_SRE_EL1 register introduce vmstate subsection and load only if non-zero. Also initialize icc_sre_el1 with to 0x7 in pre_load function. Signed-off-by: Vijaya Kumar K --- hw/intc/arm_gicv3_common.c

[Qemu-devel] [PATCH v9 5/5] hw/intc/arm_gicv3_kvm: Reset GICv3 cpu interface registers

From: Vijaya Kumar K Reset CPU interface registers of GICv3 when CPU is reset. For this, ARMCPRegInfo struct is registered with one ICC register whose resetfn is called when cpu is reset. All the ICC registers are reset under one single register reset function instead

[Qemu-devel] [PATCH v9 0/5] GICv3 live migration support

From: Vijaya Kumar K This series introduces support for GICv3 live migration with new VGIC implementation in 4.7-rc3 kernel. In this series, patch 1 of the previous implementation are ported. https://lists.nongnu.org/archive/html/qemu-devel/2015-10/msg05284.html Patch

[Qemu-devel] [PATCH v9 3/5] hw/intc/arm_gicv3_kvm: Implement get/put functions

From: Vijaya Kumar K This actually implements pre_save and post_load methods for in-kernel vGICv3. Signed-off-by: Pavel Fedin Signed-off-by: Peter Maydell [PMM: * use decimal, not 0bnnn * fixed typo in names of

[Qemu-devel] [PATCH v9 1/5] kernel: Add definitions for GICv3 attributes

From: Vijaya Kumar K This temporary patch adds kernel API definitions. Use proper header update procedure after these features are released. Signed-off-by: Pavel Fedin Signed-off-by: Vijaya Kumar K ---

[Qemu-devel] [PATCH v9 4/5] target-arm: Add GICv3CPUState in CPUARMState struct

From: Vijaya Kumar K Add gicv3state void pointer to CPUARMState struct to store GICv3CPUState. In case of usecase like CPU reset, we need to reset GICv3CPUState of the CPU. In such scenario, this pointer becomes handy. Signed-off-by: Vijaya Kumar K

Re: [Qemu-devel] [PATCH v8 2/5] hw/intc/arm_gicv3_kvm: Add ICC_SRE_EL1 register to vmstate

Hi Christoffer, On Mon, Feb 20, 2017 at 3:21 PM, Peter Maydell <peter.mayd...@linaro.org> wrote: > On 20 February 2017 at 06:21, Vijay Kilari <vijay.kil...@gmail.com> wrote: >> Hi Peter, >> >> On Fri, Feb 17, 2017 at 7:25 PM, Peter Maydell <peter.mayd...@li

Re: [Qemu-devel] [PATCH v8 2/5] hw/intc/arm_gicv3_kvm: Add ICC_SRE_EL1 register to vmstate

Hi Peter, On Fri, Feb 17, 2017 at 7:25 PM, Peter Maydell wrote: > On 17 February 2017 at 06:31, wrote: >> From: Vijaya Kumar K >> >> To Save and Restore ICC_SRE_EL1 register introduce vmstate >> subsection and load

Re: [Qemu-devel] [PATCH v7 RESEND 2/5] hw/intc/arm_gicv3_kvm: Add ICC_SRE_EL1 register to vmstate

On Fri, Feb 17, 2017 at 2:30 PM, Auger Eric <eric.au...@redhat.com> wrote: > Hi Vijaya, > > On 13/02/2017 13:17, Vijay Kilari wrote: >> On Tue, Feb 7, 2017 at 8:09 PM, Peter Maydell <peter.mayd...@linaro.org> >> wrote: >>> On 31 January 2017 at 16:22,

[Qemu-devel] [PATCH v8 3/5] hw/intc/arm_gicv3_kvm: Implement get/put functions

From: Vijaya Kumar K This actually implements pre_save and post_load methods for in-kernel vGICv3. Signed-off-by: Pavel Fedin Signed-off-by: Peter Maydell [PMM: * use decimal, not 0bnnn * fixed typo in names of

[Qemu-devel] [PATCH v8 4/5] target-arm: Add GICv3CPUState in CPUARMState struct

From: Vijaya Kumar K Add gicv3state void pointer to CPUARMState struct to store GICv3CPUState. In case of usecase like CPU reset, we need to reset GICv3CPUState of the CPU. In such scenario, this pointer becomes handy. This patch take care of only GICv3.

[Qemu-devel] [PATCH v8 1/5] kernel: Add definitions for GICv3 attributes

From: Vijaya Kumar K This temporary patch adds kernel API definitions. Use proper header update procedure after these features are released. Signed-off-by: Pavel Fedin Signed-off-by: Vijaya Kumar K ---

[Qemu-devel] [PATCH v8 5/5] hw/intc/arm_gicv3_kvm: Reset GICv3 cpu interface registers

From: Vijaya Kumar K Reset CPU interface registers of GICv3 when CPU is reset. For this, ARMCPRegInfo struct is registered with one ICC register whose resetfn is called when cpu is reset. All the ICC registers are reset under one single register reset function instead

[Qemu-devel] [PATCH v8 2/5] hw/intc/arm_gicv3_kvm: Add ICC_SRE_EL1 register to vmstate

From: Vijaya Kumar K To Save and Restore ICC_SRE_EL1 register introduce vmstate subsection and load only if non-zero. Also initialize icc_sre_el1 with to 0x7 in pre_load function. Signed-off-by: Vijaya Kumar K --- hw/intc/arm_gicv3_common.c

[Qemu-devel] [PATCH v8 0/5] GICv3 live migration support

From: Vijaya Kumar K This series introduces support for GICv3 live migration with new VGIC implementation in 4.7-rc3 kernel. In this series, patch 1 of the previous implementation are ported. https://lists.nongnu.org/archive/html/qemu-devel/2015-10/msg05284.html Patch

Re: [Qemu-devel] [PATCH v7 RESEND 5/5] hw/intc/arm_gicv3_kvm: Reset GICv3 cpu interface registers

On Thu, Feb 16, 2017 at 3:39 PM, Peter Maydell <peter.mayd...@linaro.org> wrote: > On 16 February 2017 at 09:54, Vijay Kilari <vijay.kil...@gmail.com> wrote: >> On Tue, Feb 7, 2017 at 8:19 PM, Peter Maydell <peter.mayd...@linaro.org> >> wrote: >>>

Re: [Qemu-devel] [PATCH v7 RESEND 5/5] hw/intc/arm_gicv3_kvm: Reset GICv3 cpu interface registers

On Tue, Feb 7, 2017 at 8:19 PM, Peter Maydell wrote: > On 31 January 2017 at 16:23, wrote: >> From: Vijaya Kumar K >> >> Reset CPU interface registers of GICv3 when CPU is reset. >> For this, ARMCPRegInfo struct is

Re: [Qemu-devel] [PATCH v7 RESEND 2/5] hw/intc/arm_gicv3_kvm: Add ICC_SRE_EL1 register to vmstate

On Tue, Feb 7, 2017 at 8:09 PM, Peter Maydell wrote: > On 31 January 2017 at 16:22, wrote: >> From: Vijaya Kumar K >> >> To Save and Restore ICC_SRE_EL1 register Add ICC_SRE_EL1 register >> to vmstate and GICv3CPUState

[Qemu-devel] [PATCH v7 RESEND 4/5] target-arm: Add GICv3CPUState in CPUARMState struct

From: Vijaya Kumar K Add gicv3state void pointer to CPUARMState struct to store GICv3CPUState. In case of usecase like CPU reset, we need to reset GICv3CPUState of the CPU. In such scenario, this pointer becomes handy. This patch take care of only GICv3.

[Qemu-devel] [PATCH v7 RESEND 2/5] hw/intc/arm_gicv3_kvm: Add ICC_SRE_EL1 register to vmstate

From: Vijaya Kumar K To Save and Restore ICC_SRE_EL1 register Add ICC_SRE_EL1 register to vmstate and GICv3CPUState struct. Signed-off-by: Vijaya Kumar K --- hw/intc/arm_gicv3_common.c | 1 + include/hw/intc/arm_gicv3_common.h | 1 + 2

[Qemu-devel] [PATCH v7 RESEND 5/5] hw/intc/arm_gicv3_kvm: Reset GICv3 cpu interface registers

From: Vijaya Kumar K Reset CPU interface registers of GICv3 when CPU is reset. For this, ARMCPRegInfo struct is registered with one ICC register whose resetfn is called when cpu is reset. All the ICC registers are reset under one single register reset function instead

[Qemu-devel] [PATCH v7 RESEND 3/5] hw/intc/arm_gicv3_kvm: Implement get/put functions

From: Vijaya Kumar K This actually implements pre_save and post_load methods for in-kernel vGICv3. Signed-off-by: Pavel Fedin Signed-off-by: Peter Maydell [PMM: * use decimal, not 0bnnn * fixed typo in names of

[Qemu-devel] [PATCH v7 RESEND 0/5] GICv3 live migration support

From: Vijaya Kumar K This series introduces support for GICv3 live migration with new VGIC implementation in 4.7-rc3 kernel. In this series, patch 1 of the previous implementation are ported. https://lists.nongnu.org/archive/html/qemu-devel/2015-10/msg05284.html Patch

[Qemu-devel] [PATCH v7 RESEND 1/5] kernel: Add definitions for GICv3 attributes

From: Vijaya Kumar K This temporary patch adds kernel API definitions. Use proper header update procedure after these features are released. Signed-off-by: Pavel Fedin Signed-off-by: Vijaya Kumar K ---

Re: [Qemu-devel] [PATCH v7 0/4] GICv3 live migration support

Please ignore this patch series. Missed out one patch of this series. Will resend the full patch series On Tue, Jan 31, 2017 at 9:35 PM, wrote: > From: Vijaya Kumar K > > This series introduces support for GICv3 live migration with > new VGIC

[Qemu-devel] [PATCH v7 1/4] hw/intc/arm_gicv3_kvm: Add ICC_SRE_EL1 register to vmstate

From: Vijaya Kumar K To Save and Restore ICC_SRE_EL1 register Add ICC_SRE_EL1 register to vmstate and GICv3CPUState struct. Signed-off-by: Vijaya Kumar K --- hw/intc/arm_gicv3_common.c | 1 + include/hw/intc/arm_gicv3_common.h | 1 + 2

[Qemu-devel] [PATCH v7 4/4] hw/intc/arm_gicv3_kvm: Reset GICv3 cpu interface registers

From: Vijaya Kumar K Reset CPU interface registers of GICv3 when CPU is reset. For this, ARMCPRegInfo struct is registered with one ICC register whose resetfn is called when cpu is reset. All the ICC registers are reset under one single register reset function instead

[Qemu-devel] [PATCH v7 2/4] hw/intc/arm_gicv3_kvm: Implement get/put functions

From: Vijaya Kumar K This actually implements pre_save and post_load methods for in-kernel vGICv3. Signed-off-by: Pavel Fedin Signed-off-by: Peter Maydell [PMM: * use decimal, not 0bnnn * fixed typo in names of

[Qemu-devel] [PATCH v7 3/4] target-arm: Add GICv3CPUState in CPUARMState struct

From: Vijaya Kumar K Add gicv3state void pointer to CPUARMState struct to store GICv3CPUState. In case of usecase like CPU reset, we need to reset GICv3CPUState of the CPU. In such scenario, this pointer becomes handy. This patch take care of only GICv3.

[Qemu-devel] [PATCH v7 0/4] GICv3 live migration support

From: Vijaya Kumar K This series introduces support for GICv3 live migration with new VGIC implementation in 4.7-rc3 kernel. In this series, patch 1 of the previous implementation are ported. https://lists.nongnu.org/archive/html/qemu-devel/2015-10/msg05284.html Patch

Re: [Qemu-devel] [RFC 3/4] hw/intc/arm_gicv3_its: Implement state save/restore

Hi Eric, On Thu, Jan 26, 2017 at 2:49 PM, Eric Auger wrote: > We need to handle both registers and ITS tables. While > register handling is standard, ITS table handling is more > challenging since the kernel API is devised so that the > tables are flushed into guest RAM

Re: [Qemu-devel] [RFC 2/4] hw/intc/arm_gicv3_kvm: Rename KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS

Hi Eric, On Thu, Jan 26, 2017 at 2:49 PM, Eric Auger wrote: > Rename KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS into KVM_DEV_ARM_VGIC_CPU_SYSREGS > as exposed in the kernel user API and pulled by update-linux-headers.sh. I will fix it in my next qemu patch series. I have updated

Re: [Qemu-devel] [PATCH v5 2/3] utils: Add helper to read arm MIDR_EL1 register

On Fri, Dec 16, 2016 at 7:34 PM, Peter Maydell wrote: > On 7 December 2016 at 17:06, wrote: >> From: Vijaya Kumar K >> >> Add helper API to read MIDR_EL1 registers to fetch >> cpu identification information. This helps

[Qemu-devel] [PATCH v5 3/3] utils: Add prefetch for Thunderx platform

From: Vijaya Kumar K Thunderx pass2 chip requires explicit prefetch instruction to give prefetch hint. To speed up live migration on Thunderx platform, prefetch instruction is added in zero buffer check function.The below results show live migration time improvement

[Qemu-devel] [PATCH v5 2/3] utils: Add helper to read arm MIDR_EL1 register

From: Vijaya Kumar K Add helper API to read MIDR_EL1 registers to fetch cpu identification information. This helps in adding errata's and architecture specific features. This is implemented only for arm architecture. Signed-off-by: Vijaya Kumar K

[Qemu-devel] [PATCH v5 0/3] Live migration optimization for Thunderx platform

From: Vijaya Kumar K The CPU MIDR_EL1 register is exposed to userspace for arm64 with the below patch. https://lkml.org/lkml/2016/7/8/467 Thunderx platform requires explicit prefetch instruction to provide prefetch hint. Using MIDR_EL1 information, provided by above

[Qemu-devel] [PATCH v5 1/3] cutils: Set __builtin_prefetch optional parameters

From: Vijaya Kumar K Optional parameters of __builtin_prefetch() which specifies rw and locality to 0's. For checking buffer is zero, set rw as read and temporal locality to 0. On arm64, __builtin_prefetch(addr) generates 'prfmpldl1keep' where

Re: [Qemu-devel] [PATCH v6 4/4] hw/intc/arm_gicv3_kvm: Reset GICv3 cpu interface registers

Hi Peter, On Thu, Dec 1, 2016 at 3:40 PM, Vijay Kilari <vijay.kil...@gmail.com> wrote: > On Wed, Nov 30, 2016 at 10:29 PM, Peter Maydell > <peter.mayd...@linaro.org> wrote: >> On 30 November 2016 at 16:23, Vijay Kilari <vijay.kil...@gmail.com> wrote: >>>

Re: [Qemu-devel] [PATCH v6 4/4] hw/intc/arm_gicv3_kvm: Reset GICv3 cpu interface registers

On Wed, Nov 30, 2016 at 10:29 PM, Peter Maydell <peter.mayd...@linaro.org> wrote: > On 30 November 2016 at 16:23, Vijay Kilari <vijay.kil...@gmail.com> wrote: >> On Mon, Nov 28, 2016 at 10:05 PM, Peter Maydell >> <peter.mayd...@linaro.org> wrote: >

Re: [Qemu-devel] [PATCH v6 4/4] hw/intc/arm_gicv3_kvm: Reset GICv3 cpu interface registers

On Mon, Nov 28, 2016 at 10:05 PM, Peter Maydell <peter.mayd...@linaro.org> wrote: > On 28 November 2016 at 16:01, Vijay Kilari <vijay.kil...@gmail.com> wrote: >> On Mon, Nov 28, 2016 at 6:31 PM, Peter Maydell <peter.mayd...@linaro.org> >> wrote: >>>

Re: [Qemu-devel] [PATCH v6 4/4] hw/intc/arm_gicv3_kvm: Reset GICv3 cpu interface registers

On Mon, Nov 28, 2016 at 6:31 PM, Peter Maydell wrote: > On 23 November 2016 at 12:39, wrote: >> From: Vijaya Kumar K >> >> Reset CPU interface registers of GICv3 when CPU is reset. >> For this, object interface is used,

Re: [Qemu-devel] [PATCH v6 1/4] kernel: Add definitions for GICv3 attributes

On Fri, Nov 25, 2016 at 1:27 PM, Auger Eric wrote: > Hi Vijay, > > On 23/11/2016 13:39, vijay.kil...@gmail.com wrote: >> From: Vijaya Kumar K >> >> This temporary patch adds kernel API definitions. Use proper header update >> procedure after these

[Qemu-devel] [PATCH v6 4/4] hw/intc/arm_gicv3_kvm: Reset GICv3 cpu interface registers

From: Vijaya Kumar K Reset CPU interface registers of GICv3 when CPU is reset. For this, object interface is used, which is called from arm_cpu_reset function. Signed-off-by: Vijaya Kumar K --- hw/intc/arm_gicv3_kvm.c| 37

[Qemu-devel] [PATCH v6 1/4] kernel: Add definitions for GICv3 attributes

From: Vijaya Kumar K This temporary patch adds kernel API definitions. Use proper header update procedure after these features are released. Signed-off-by: Pavel Fedin Signed-off-by: Vijaya Kumamr K ---

Re: [Qemu-devel] [RFC PATCH v5 2/2] hw/intc/arm_gicv3_kvm: Implement get/put functions

On Fri, Oct 7, 2016 at 9:00 PM, Peter Maydell wrote: > On 20 September 2016 at 07:55, wrote: >> From: Vijaya Kumar K >> >> This actually implements pre_save and post_load methods for in-kernel >> vGICv3. >> >>

Re: [Qemu-devel] [PATCH v4 2/3] utils: Add helper to read arm MIDR_EL1 register

Hi Peter On Fri, Oct 28, 2016 at 3:39 PM, Vijay Kilari <vijay.kil...@gmail.com> wrote: > On Fri, Oct 28, 2016 at 2:33 PM, Peter Maydell <peter.mayd...@linaro.org> > wrote: >> On 28 October 2016 at 08:00, Vijay Kilari <vijay.kil...@gmail.com> wrote: >>>

Re: [Qemu-devel] [PATCH v4 2/3] utils: Add helper to read arm MIDR_EL1 register

On Fri, Oct 28, 2016 at 2:33 PM, Peter Maydell <peter.mayd...@linaro.org> wrote: > On 28 October 2016 at 08:00, Vijay Kilari <vijay.kil...@gmail.com> wrote: >> On Thu, Oct 27, 2016 at 9:33 PM, Peter Maydell <peter.mayd...@linaro.org> >> wrote: >>>

Re: [Qemu-devel] [PATCH v4 2/3] utils: Add helper to read arm MIDR_EL1 register

On Thu, Oct 27, 2016 at 9:33 PM, Peter Maydell wrote: > On 25 October 2016 at 13:12, wrote: >> From: Vijaya Kumar K >> >> Add helper API to read MIDR_EL1 registers to fetch >> cpu identification information. This helps

Re: [Qemu-devel] [PATCH v3 2/3] utils: Add helper to read arm MIDR_EL1 register

On Mon, Oct 24, 2016 at 3:09 PM, Dr. David Alan Gilbert wrote: > * vijay.kil...@gmail.com (vijay.kil...@gmail.com) wrote: >> From: Vijaya Kumar K >> >> Add helper API to read MIDR_EL1 registers to fetch >> cpu identification information. This helps

[Qemu-devel] [PATCH v3 3/3] utils: Add prefetch for Thunderx platform

From: Vijaya Kumar K Thunderx pass2 chip requires explicit prefetch instruction to give prefetch hint. To speed up live migration on Thunderx platform, prefetch instruction is added in zero buffer check function.The below results show live migration time improvement

[Qemu-devel] [PATCH v3 0/3] Live migration optimization for Thunderx platform

From: Vijaya Kumar K The CPU MIDR_EL1 register is exposed to userspace for arm64 with the below patch. https://lkml.org/lkml/2016/7/8/467 Thunderx platform requires explicit prefetch instruction to provide prefetch hint. Using MIDR_EL1 information, provided by above

[Qemu-devel] [PATCH v3 2/3] utils: Add helper to read arm MIDR_EL1 register

From: Vijaya Kumar K Add helper API to read MIDR_EL1 registers to fetch cpu identification information. This helps in adding errata's and architecture specific features. This is implemented only for arm architecture. Signed-off-by: Vijaya Kumar K

[Qemu-devel] [PATCH v3 1/3] cutils: Set __builtin_prefetch optional parameters

From: Vijaya Kumar K Optional parameters of __builtin_prefetch() which specifies rw and locality to 0's. For checking buffer is zero, set rw as read and temporal locality to 0. On arm64, __builtin_prefetch(addr) generates 'prfmpldl1keep' where

Re: [Qemu-devel] Fw: [Qemu-arm] [PATCH v2 0/6] Runtime pagesize computation

Hi Peter, On Fri, Oct 7, 2016 at 7:50 PM, Peter Maydell <peter.mayd...@linaro.org> wrote: > On 19 July 2016 at 12:04, Peter Maydell <peter.mayd...@linaro.org> wrote: >> On 19 July 2016 at 12:01, Vijay Kilari <vijay.kil...@gmail.com> wrote: >>> Hi Peter, &g

[Qemu-devel] [RFC PATCH v4 1/2] kernel: Add definitions for GICv3 attributes

From: Vijaya Kumar K This temporary patch adds kernel API definitions. Use proper header update procedure after these features are released. Signed-off-by: Pavel Fedin Signed-off-by: Vijaya Kumamr K ---

[Qemu-devel] [RFC PATCH v4 2/2] hw/intc/arm_gicv3_kvm: Implement get/put functions

From: Vijaya Kumar K This actually implements pre_save and post_load methods for in-kernel vGICv3. Signed-off-by: Pavel Fedin Signed-off-by: Peter Maydell Signed-off-by: Vijaya Kumamr K [PMM: *

[Qemu-devel] [RFC PATCH v4 0/2] GICv3 live migration support

From: Vijaya Kumar K This series introduces support for GICv3 live migration with new VGIC implementation in 4.7-rc3 kernel. In this series, patch 1 of the previous implementation are ported. https://lists.nongnu.org/archive/html/qemu-devel/2015-10/msg05284.html Patch

Re: [Qemu-devel] [PATCH 0/7] Improve buffer_is_zero

On Thu, Aug 25, 2016 at 12:07 PM, Vijay Kilari <vijay.kil...@gmail.com> wrote: > Hi Richard, > > Migration fails on arm64 with these patches. > On the destination VM, follow errors are appearing. > > qemu-system-aarch64: VQ 0 size 0x400 Guest index 0x0 inconsistent

Re: [Qemu-devel] [PATCH 0/7] Improve buffer_is_zero

Hi Richard, Migration fails on arm64 with these patches. On the destination VM, follow errors are appearing. qemu-system-aarch64: VQ 0 size 0x400 Guest index 0x0 inconsistent with Host index 0x1937: delta 0xe6c9 qemu-system-aarch64: error while loading state for instance 0x0 of device

[Qemu-devel] [RFC PATCH v3 2/2] hw/intc/arm_gicv3_kvm: Implement get/put functions

From: Vijaya Kumar K This actually implements pre_save and post_load methods for in-kernel vGICv3. Signed-off-by: Pavel Fedin Signed-off-by: Peter Maydell [PMM: * use decimal, not 0bnnn * fixed typo in names of

[Qemu-devel] [RFC PATCH v3 1/2] kernel: Add definitions for GICv3 attributes

From: Vijaya Kumar K This temporary patch adds kernel API definitions. Use proper header update procedure after these features are released. Signed-off-by: Pavel Fedin --- linux-headers/asm-arm64/kvm.h | 24 +--- 1 file

[Qemu-devel] [RFC PATCH v3 0/2] GICv3 live migration support

From: Vijaya Kumar K This series introduces support for GICv3 live migration with new VGIC implementation in 4.7-rc3 kernel. In this series, patch 1 of the previous implementation are ported. https://lists.nongnu.org/archive/html/qemu-devel/2015-10/msg05284.html Patch

Re: [Qemu-devel] [RFC PATCH v2 1/2] utils: Add helper to read arm MIDR_EL1 register

On Thu, Aug 18, 2016 at 8:26 PM, Peter Maydell wrote: > On 18 August 2016 at 15:46, Richard Henderson wrote: >> On 08/18/2016 07:14 AM, Peter Maydell wrote: >>> While we're on the subject, can somebody explain to me why we >>> use ifuncs at all? I

Re: [Qemu-devel] [RFC PATCH v2 1/2] utils: Add helper to read arm MIDR_EL1 register

On Thu, Aug 18, 2016 at 2:20 PM, Paolo Bonzini <pbonz...@redhat.com> wrote: > > > On 18/08/2016 09:56, Vijay Kilari wrote: >> The get_aarch_cpu_id() has check " if (unlikely(!cpu_info_read)) ". >> If we call get_aarch_cpu_id() from is_thunderx_pass2_cpu() wh

Re: [Qemu-devel] [RFC PATCH v2 1/2] utils: Add helper to read arm MIDR_EL1 register

On Wed, Aug 17, 2016 at 7:09 PM, Paolo Bonzini wrote: > > > On 16/08/2016 14:02, vijay.kil...@gmail.com wrote: >> From: Vijaya Kumar K >> >> Add helper API to read MIDR_EL1 registers to fetch >> cpu identification information. This helps in >> adding

Re: [Qemu-devel] [RFC PATCH v2 2/2] utils: Add prefetch for Thunderx platform

On Tue, Aug 16, 2016 at 11:32 PM, Richard Henderson wrote: > On 08/16/2016 05:02 AM, vijay.kil...@gmail.com wrote: >> >> +static inline void prefetch_vector_loop(const VECTYPE *p, int index) >> +{ >> +#if defined(__aarch64__) >> +if (is_thunderx_pass2_cpu()) { >> +/*

[Qemu-devel] [RFC PATCH v2 2/2] utils: Add prefetch for Thunderx platform

From: Vijaya Kumar K Thunderx pass2 chip requires explicit prefetch instruction to give prefetch hint. To speed up live migration on Thunderx platform, prefetch instruction is added in zero buffer check function. The below results show live migration time improvement

[Qemu-devel] [RFC PATCH v2 1/2] utils: Add helper to read arm MIDR_EL1 register

From: Vijaya Kumar K Add helper API to read MIDR_EL1 registers to fetch cpu identification information. This helps in adding errata's and architecture specific features. This is implemented only for arm architecture. Signed-off-by: Vijaya Kumar K

[Qemu-devel] [RFC PATCH v2 0/2] Live migration optimization for Thunderx platform

From: Vijaya Kumar K The CPU MIDR_EL1 register is exposed to userspace for arm64 with the below patch. https://lkml.org/lkml/2016/7/8/467 Thunderx platform requires explicit prefetch instruction to provide prefetch hint. Using MIDR_EL1 information, provided by above

Re: [Qemu-devel] [RFC PATCH v1 2/2] utils: Add prefetch for Thunderx platform

On Sat, Aug 6, 2016 at 3:47 PM, Richard Henderson wrote: > On 08/02/2016 03:50 PM, vijay.kil...@gmail.com wrote: >> >> +#define VEC_PREFETCH(base, index) \ >> +asm volatile ("prfm pldl1strm, [%x[a]]\n" : : >> [a]"r"([(index)])) > > > Is this not __builtin_prefetch(base +

Re: [Qemu-devel] [RFC PATCH v2 2/2] hw/intc/arm_gicv3_kvm: Implement get/put functions

On Mon, Aug 8, 2016 at 10:27 PM, Peter Maydell wrote: > On 8 August 2016 at 17:51, wrote: >> From: Vijaya Kumar K >> >> This actually implements pre_save and post_load methods for in-kernel >> vGICv3. >> >>

[Qemu-devel] [RFC PATCH v2 1/2] kernel: Add definitions for GICv3 attributes

From: Vijaya Kumar K This temporary patch adds kernel API definitions. Use proper header update procedure after these features are released. Signed-off-by: Pavel Fedin --- linux-headers/asm-arm64/kvm.h | 17 ++--- 1 file changed, 14

[Qemu-devel] [RFC PATCH v2 2/2] hw/intc/arm_gicv3_kvm: Implement get/put functions

From: Vijaya Kumar K This actually implements pre_save and post_load methods for in-kernel vGICv3. Signed-off-by: Pavel Fedin Signed-off-by: Peter Maydell [PMM: * use decimal, not 0bnnn * fixed typo in names of

[Qemu-devel] [RFC PATCH v2 0/2] GICv3 live migration support

From: Vijaya Kumar K This series introduces support for GICv3 live migration with new VGIC implementation in 4.7-rc3 kernel. In this series, patch 1 of the previous implementation are ported. https://lists.nongnu.org/archive/html/qemu-devel/2015-10/msg05284.html Patch

Re: [Qemu-devel] [RFC PATCH v1 1/2] utils: Add helper to read arm MIDR_EL1 register

Hi Paolo, On Tue, Aug 2, 2016 at 4:18 PM, Paolo Bonzini <pbonz...@redhat.com> wrote: > - Original Message - >> From: "vijay kilari" <vijay.kil...@gmail.com> >> To: qemu-...@nongnu.org, "peter maydell" <peter.mayd...@linaro.org>,

[Qemu-devel] [RFC PATCH v1 2/2] utils: Add prefetch for Thunderx platform

From: Vijaya Kumar K Thunderx pass2 chip requires explicit prefetch instruction to give prefetch hint. To speed up live migration on Thunderx platform, prefetch instruction is added in zero buffer check function. The below results show live migration time improvement

[Qemu-devel] [RFC PATCH v1 1/2] utils: Add helper to read arm MIDR_EL1 register

From: Vijaya Kumar K Add helper API to read MIDR_EL1 registers to fetch cpu identification information. This helps in adding errata's and architecture specific features. This is implemented only for arm architecture. Signed-off-by: Vijaya Kumar K

[Qemu-devel] [RFC PATCH v1 0/2] Live migration optimization for Thunderx platform

From: Vijaya Kumar K The CPU MIDR_EL1 register is exposed to userspace for arm64 with the below patch. https://lkml.org/lkml/2016/7/8/467 Thunderx platform requires explicit prefetch instruction to provide prefetch hint. Using MIDR_EL1 information, provided by above

[Qemu-devel] [RFC PATCH v1 2/2] hw/intc/arm_gicv3_kvm: Implement get/put functions

From: Vijaya Kumar K This actually implements pre_save and post_load methods for in-kernel vGICv3. Signed-off-by: Pavel Fedin Signed-off-by: Vijaya Kumar K [Vijay: - Adjusted macros to handle gicr variables - Used

[Qemu-devel] [RFC PATCH v1 1/2] kernel: Add definitions for GICv3 attributes

From: Vijaya Kumar K This temporary patch adds kernel API definitions. Use proper header update procedure after these features are released. Signed-off-by: Pavel Fedin --- linux-headers/asm-arm64/kvm.h | 22 +- 1 file

[Qemu-devel] [RFC PATCH v1 0/2] GICv3 live migration support

From: Vijaya Kumar K This series introduces support for GICv3 live migration with new VGIC implementation in 4.7-rc3 kernel. In this series, patch 2 & 3 of the previous implementation are ported. https://lists.nongnu.org/archive/html/qemu-devel/2015-10/msg05284.html

Re: [Qemu-devel] Fw: [Qemu-arm] [PATCH v2 0/6] Runtime pagesize computation

Hi Peter, Any update on this patch set. Is it merged? On Wed, Jun 29, 2016 at 12:30 PM, Vijay Kilari <vijay.kil...@gmail.com> wrote: > On Wed, Jun 29, 2016 at 12:24 PM, Kumar, Vijaya <vijaya.ku...@cavium.com> > wrote: >> >> >> >> _

Re: [Qemu-devel] [PATCH v3 1/1] target-arm: Use Neon for zero checking

On Sat, Jul 2, 2016 at 3:37 AM, Richard Henderson wrote: > On 06/30/2016 06:45 AM, Peter Maydell wrote: >> >> On 29 June 2016 at 09:47, wrote: >>> >>> From: Vijay >>> >>> Use Neon instructions to perform zero checking of >>> buffer.

Re: [Qemu-devel] Fw: [Qemu-arm] [PATCH v2 0/6] Runtime pagesize computation

On Wed, Jun 29, 2016 at 12:24 PM, Kumar, Vijaya wrote: > > > > > From: Peter Maydell > Sent: Tuesday, June 28, 2016 1:46 PM > To: qemu-arm; QEMU Developers > Cc: Paolo Bonzini; Kumar, Vijaya; Patch Tracking >

Re: [Qemu-devel] Fw: [Qemu-arm] [PATCH v2 2/6] exec.c: Remove static allocation of sub_section of sub_page

> > From: Qemu-arm on > behalf of Peter Maydell > Sent: Tuesday, June 21, 2016 10:39 PM > To: qemu-...@nongnu.org; qemu-devel@nongnu.org > Cc: Paolo Bonzini; Kumar, Vijaya;

Re: [Qemu-devel] [RFC PATCH v1 4/4] target-arm: Compute page size based on ARM target cpu type

On Fri, Jun 17, 2016 at 4:00 PM, Peter Maydell <peter.mayd...@linaro.org> wrote: > On 17 June 2016 at 11:20, Vijay Kilari <vijay.kil...@gmail.com> wrote: >> On Fri, Jun 17, 2016 at 1:12 AM, Richard Henderson <r...@twiddle.net> wrote: >>> On 06/14/2016 04:36 AM

Re: [Qemu-devel] [RFC PATCH v1 4/4] target-arm: Compute page size based on ARM target cpu type

On Fri, Jun 17, 2016 at 1:12 AM, Richard Henderson wrote: > On 06/14/2016 04:36 AM, Peter Maydell wrote: >> It would be better to delay the point at which we allocate >> the data structures which care about page size, rather than >> moving init of the CPU earlier. > > It would

Re: [Qemu-devel] [RFC PATCH v1 2/4] exec.c: Remove static allocation of sub_section of sub_page

Hi Paolo, On Mon, Jun 13, 2016 at 3:22 PM, Paolo Bonzini wrote: > > > On 13/06/2016 11:08, vija...@caviumnetworks.com wrote: >> From: Vijaya Kumar K >> >> Allocate sub_section dynamically. Remove dependency >> on TARGET_PAGE_SIZE to make

Re: [Qemu-devel] [RFC PATCH v1 4/4] target-arm: Compute page size based on ARM target cpu type

On Mon, Jun 13, 2016 at 3:40 PM, Peter Maydell wrote: > On 13 June 2016 at 10:43, Peter Maydell wrote: >> On 13 June 2016 at 10:08, wrote: >>> +/* >>> + * Holds TARGET_AARCH_64_PAGE_BITS or TARGET_ARM_PAGE_BITS >>>

Re: [Qemu-devel] [RFC PATCH v1 1/2] target-arm: Update page size for aarch64

Hi Peter On Wed, Apr 6, 2016 at 8:31 PM, Vijay Kilari <vijay.kil...@gmail.com> wrote: > On Mon, Apr 4, 2016 at 10:14 PM, Peter Maydell <peter.mayd...@linaro.org> > wrote: >> On 4 April 2016 at 17:40, Vijay Kilari <vijay.kil...@gmail.com> wrote: >>> On Mon

Re: [Qemu-devel] [RFC PATCH v2 2/3] utils: Add cpuinfo helper to fetch /proc/cpuinfo

Hi Suzuki/Peter, On Wed, Apr 13, 2016 at 5:59 PM, Suzuki K Poulose <suzuki.poul...@arm.com> wrote: > On 13/04/16 10:54, Vijay Kilari wrote: >> >> On Mon, Apr 11, 2016 at 3:07 PM, Suzuki K Poulose >> <suzuki.poul...@arm.com> wrote: >>> >>> On 11/0

Re: [Qemu-devel] [RFC PATCH v2 2/3] utils: Add cpuinfo helper to fetch /proc/cpuinfo

On Mon, Apr 11, 2016 at 3:07 PM, Suzuki K Poulose <suzuki.poul...@arm.com> wrote: > On 11/04/16 07:52, Vijay Kilari wrote: >> >> Adding Suzuki Poulose. >> >> Hi Suzuki, >> >> On Fri, Apr 8, 2016 at 3:13 PM, Peter Maydell <peter.mayd...@linaro.org>

Re: [Qemu-devel] [RFC PATCH v2 2/3] utils: Add cpuinfo helper to fetch /proc/cpuinfo

Adding Suzuki Poulose. Hi Suzuki, On Fri, Apr 8, 2016 at 3:13 PM, Peter Maydell <peter.mayd...@linaro.org> wrote: > On 8 April 2016 at 07:21, Vijay Kilari <vijay.kil...@gmail.com> wrote: >> On Thu, Apr 7, 2016 at 5:15 PM, Peter Maydell <peter.mayd...@linaro.org&

Re: [Qemu-devel] [RFC PATCH v2 2/3] utils: Add cpuinfo helper to fetch /proc/cpuinfo

Hi Peter, On Thu, Apr 7, 2016 at 5:15 PM, Peter Maydell <peter.mayd...@linaro.org> wrote: > On 7 April 2016 at 11:56, Vijay Kilari <vijay.kil...@gmail.com> wrote: >> On Thu, Apr 7, 2016 at 3:41 PM, Peter Maydell <peter.mayd...@linaro.org> >> wrote: >

Re: [Qemu-devel] [RFC PATCH v2 2/3] utils: Add cpuinfo helper to fetch /proc/cpuinfo

On Thu, Apr 7, 2016 at 3:41 PM, Peter Maydell wrote: > On 7 April 2016 at 10:58, wrote: >> From: Vijaya Kumar K >> >> utils cannot read target cpu information to >> fetch cpu information to implement cpu

Re: [Qemu-devel] [RFC PATCH v1 1/2] target-arm: Update page size for aarch64

On Mon, Apr 4, 2016 at 10:14 PM, Peter Maydell <peter.mayd...@linaro.org> wrote: > On 4 April 2016 at 17:40, Vijay Kilari <vijay.kil...@gmail.com> wrote: >> On Mon, Apr 4, 2016 at 7:14 PM, Peter Maydell <peter.mayd...@linaro.org> >> wrote: >>>

Re: [Qemu-devel] [RFC PATCH v1 2/2] target-arm: Use Neon for zero checking

On Tue, Apr 5, 2016 at 8:06 PM, Peter Maydell wrote: > On 4 April 2016 at 14:39, wrote: >> From: Vijay >> >> Use Neon instructions to perform zero checking of >> buffer. This is helps in reducing downtime during >> live

Re: [Qemu-devel] [RFC PATCH v1 1/2] target-arm: Update page size for aarch64

On Mon, Apr 4, 2016 at 7:14 PM, Peter Maydell wrote: > On 4 April 2016 at 14:39, wrote: >> From: Vijay >> >> Set target page size to minimum 4K for aarch64. >> This helps to reduce live migration downtime significantly.