Hi
Am Donnerstag, 28. Juli 2016, 14:11:45 schrieb Andrea Galbusera:
> Hi all,
>
> On Tue, Jul 26, 2016 at 12:49 PM, Phil Reid wrote:
> > On 26/07/2016 18:22, Teoh Choon Zone wrote:
> >> Hi all,
> >>
> >> Finally I have everything working (kernel 4.1.22-ltsi, overlay, LW
> >> bridge,
> >> H2F br
Hi all,
On Tue, Jul 26, 2016 at 12:49 PM, Phil Reid wrote:
> On 26/07/2016 18:22, Teoh Choon Zone wrote:
>>
>> Hi all,
>>
>> Finally I have everything working (kernel 4.1.22-ltsi, overlay, LW bridge,
>> H2F bridge etc). I write out my steps to save others precious time:
>>
>> 1. Nothing needs to
On 26/07/2016 18:22, Teoh Choon Zone wrote:
Hi all,
Finally I have everything working (kernel 4.1.22-ltsi, overlay, LW bridge, H2F
bridge etc). I write out my steps to save others precious time:
1. Nothing needs to be changed in socfpga.dtsi, socfpga_cyclone5.dtsi. Craft
your own dts and over
Hi all,
Finally I have everything working (kernel 4.1.22-ltsi, overlay, LW bridge,
H2F bridge etc). I write out my steps to save others precious time:
1. Nothing needs to be changed in socfpga.dtsi, socfpga_cyclone5.dtsi.
Craft your own dts and overlay. I attached them for your reference. To
comp
Hi Phil, Alan
Am Montag, 25. Juli 2016, 17:28:08 schrieb Phil Reid:
> >> So looks like possible fpga region is not getting mapped correctly and
> >> I'm
> >> not sure where this is done. New one for me. The fpga-region stuff may be
> >> related:
> >>
> >> base_fpga_region {
> >>
> >>compatibl
On 25/07/2016 16:58, Tim Sander wrote:
Hi Phil
Am Montag, 25. Juli 2016, 16:47:22 schrieb Phil Reid:
On 25/07/2016 15:09, Teoh Choon Zone wrote:
Whats in brgmodrst (0xFFD0501C)?
0xFF401FD0 is the lw hps2fpga bridge.
0xC00D looks a bit odd for lw hps2fpga bridge devices.
Th
Hi Phil
Am Montag, 25. Juli 2016, 16:47:22 schrieb Phil Reid:
> On 25/07/2016 15:09, Teoh Choon Zone wrote:
> > Whats in brgmodrst (0xFFD0501C)?
> >
> > 0xFF401FD0 is the lw hps2fpga bridge.
> >
> > 0xC00D looks a bit odd for lw hps2fpga bridge devices.
> > That should
On 25/07/2016 15:09, Teoh Choon Zone wrote:
Whats in brgmodrst (0xFFD0501C)?
0xFF401FD0 is the lw hps2fpga bridge.
0xC00D looks a bit odd for lw hps2fpga bridge devices.
That should be for the high speed hps2fpga bridge.
lw hps2fpga is at base 0xFF20
root@linaro-
Hi Teoh
Am Montag, 25. Juli 2016, 15:09:06 schrieb Teoh Choon Zone:
> >> Whats in brgmodrst (0xFFD0501C)?
> >
> > 0xFF401FD0 is the lw hps2fpga bridge.
> >
> > 0xC00D looks a bit odd for lw hps2fpga bridge devices.
> > That should be for the high speed hps2fpga bridge.
> >
> > lw hps2fpga is
>
>
>> Whats in brgmodrst (0xFFD0501C)?
>
> 0xFF401FD0 is the lw hps2fpga bridge.
>
> 0xC00D looks a bit odd for lw hps2fpga bridge devices.
> That should be for the high speed hps2fpga bridge.
>
> lw hps2fpga is at base 0xFF20
>
>
root@linaro-developer:~/test# devmem2 0xFFD0501C
/dev/mem o
On 25/07/2016 14:10, Teoh Choon Zone wrote:
On Mon, Jul 25, 2016 at 8:43 AM, Phil Reid mailto:pr...@electromag.com.au>> wrote:
G'day Tim,
On 22/07/2016 23:09, Tim Sander wrote:
Hi Phil
Am Freitag, 22. Juli 2016, 16:52:25 schrieb Phil Reid:
G'da Teoh,
On Mon, Jul 25, 2016 at 8:43 AM, Phil Reid wrote:
> G'day Tim,
>
> On 22/07/2016 23:09, Tim Sander wrote:
>
>> Hi Phil
>>
>>
>> Am Freitag, 22. Juli 2016, 16:52:25 schrieb Phil Reid:
>>
>>> G'da Teoh,
>>>
>>> On 22/07/2016 15:09, Teoh Choon Zone wrote:
>>>
Hi Tim,
Just some update,
Hi Phil
Am Freitag, 22. Juli 2016, 16:52:25 schrieb Phil Reid:
> G'da Teoh,
>
> On 22/07/2016 15:09, Teoh Choon Zone wrote:
> > Hi Tim,
> >
> > Just some update, so my problem currently narrows down to HPS could not
> > access FPGA via H2Fbridge. The LWH2Fbridge is now working as I could see
>
G'da Teoh,
On 22/07/2016 15:09, Teoh Choon Zone wrote:
Hi Tim,
Just some update, so my problem currently narrows down to HPS could not access
FPGA via H2Fbridge. The LWH2Fbridge is now working as I could see the interrupt
from FPGA.
Same here. I could access my FPGA register exposed via H2Fbr
Hi Tim,
Just some update, so my problem currently narrows down to HPS could not
access FPGA via H2Fbridge. The LWH2Fbridge is now working as I could see
the interrupt from FPGA.
Same here. I could access my FPGA register exposed via H2Fbridge in kernel
3.10-ltsi but not in 4.1-ltsi. It's tested u
Hi
Teoh can you access your fpga registers with devmem?
If not can you access the fpga bridge registers with "devmem 0xFF401FD0"?
I am currently fighting with the problem that i can't access the bridge device
with the 4.1.22 ltsi kernel nor any fpga registers. So i even can't access the
regist
Hi,
Although I have successfully program the FPGA, but I still could not access
the FPGA register which I ioremap in my driver and mmap in user space
program. FYI, the FPGA register is accessed via H2Fbridge.
Apart from that, the FPGA will also interrupt the HPS via LWF2Hbridge. I
have compile a
Yes, 16.0 does not generatea valid device tree for the 4.1 ltsi kernel.
Next, there is a mistake in my device tree, the fpga-bridges should be with
the base region, av update to the kernel will be pushed soon that allows
the bridges and regions to be in the overlay.
As far as the three bridges, t
I've my setup working too. I made a silly mistake whereby the rbf is
corrupted when I transfer it to my board.
Referring to your overlay,
fpga-bridges = <&fpga_bridge0>, <&fpga_bridge1>,
<&fpga_bridge2>;
#address-cells = <2>;
#size-cells = <1>;
ranges = <0 0x0 0xc000 0x2000>,
<1 0x
This definitely is working for me, i just tested with the 4.1.22 LTSI
kernel on the DE0 Nano / Atlas board.
Attached are my device trees, and below you can the output from adding the
dtbo
# ls /lib/firmware/
soc_system.rbf
socfpga_cyclone5_socwks_fpga_overlay.dtb
# mkdir config/device-tree/overla
ill give this a go...
On Wed, Jun 29, 2016 at 10:16 PM, Teoh Choon Zone <
choon-zone.t...@vie.com.my> wrote:
> Hi Phil,
>
> I didn't do anything to the 50-firmware.rules. My rules content is
> exactly same as yours. Maybe Dalon can provide us more guidance?
>
> On Thu, Jun 30, 2016 at 12:05 PM, P
Hi Phil,
I didn't do anything to the 50-firmware.rules. My rules content is exactly
same as yours. Maybe Dalon can provide us more guidance?
On Thu, Jun 30, 2016 at 12:05 PM, Phil Reid wrote:
> G'day Teoh,
>
> On 30/06/2016 11:47, Teoh Choon Zone wrote:
>
>> I rechecked and found out that I did
G'day Teoh,
On 30/06/2016 11:47, Teoh Choon Zone wrote:
I rechecked and found out that I didn't use fpga_bridge3. I disabled and
regenerate the DTB but the error still happened. The error looks like the
fpga_manager
cannot find my rbf, no? Am I putting it at the correct place, which is
"/lib/
I rechecked and found out that I didn't use fpga_bridge3. I disabled and
regenerate the DTB but the error still happened. The error looks like the
fpga_manager cannot find my rbf, no? Am I putting it at the correct place,
which is "/lib/firmware"?
Another question, do I configure the DTS correctly
Are you really using all of the FPGA bridges?
fpga-bridges = <&fpga_bridge0>, <&fpga_bridge1>,
<&fpga_bridge2>, <&fpga_bridge3>;
??
On Wed, Jun 29, 2016 at 2:11 AM, Teoh Choon Zone wrote:
> I'm testing the new framework to program FPGA through DTB overlay. But
> after I execute "echo socfpga_g
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