CVS commit: src/sys/arch/aarch64/aarch64
Module Name:src
Committed By: skrll
Date: Thu Jun 3 07:02:59 UTC 2021
Modified Files:
src/sys/arch/aarch64/aarch64: aarch64_machdep.c
Log Message:
Two fixes for loading free pages into UVM
- Only consider a boot_physmem (inner loop) range that has its end
(bp_end) after the bootconfig.dram (outer loop) range start (start).
This was harmless as a later condition correctly checks there is only
something to do if start < bp_end.
- Stop processing boot_physmem ranges if all the bootconfig.dram range has
been passed to UVM. This fixes a boot problem for simon@
To generate a diff of this commit:
cvs rdiff -u -r1.60 -r1.61 src/sys/arch/aarch64/aarch64/aarch64_machdep.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/aarch64/aarch64/aarch64_machdep.c
diff -u src/sys/arch/aarch64/aarch64/aarch64_machdep.c:1.60 src/sys/arch/aarch64/aarch64/aarch64_machdep.c:1.61
--- src/sys/arch/aarch64/aarch64/aarch64_machdep.c:1.60 Thu Mar 25 07:31:56 2021
+++ src/sys/arch/aarch64/aarch64/aarch64_machdep.c Thu Jun 3 07:02:59 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: aarch64_machdep.c,v 1.60 2021/03/25 07:31:56 skrll Exp $ */
+/* $NetBSD: aarch64_machdep.c,v 1.61 2021/06/03 07:02:59 skrll Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
*/
#include
-__KERNEL_RCSID(1, "$NetBSD: aarch64_machdep.c,v 1.60 2021/03/25 07:31:56 skrll Exp $");
+__KERNEL_RCSID(1, "$NetBSD: aarch64_machdep.c,v 1.61 2021/06/03 07:02:59 skrll Exp $");
#include "opt_arm_debug.h"
#include "opt_cpuoptions.h"
@@ -391,12 +391,15 @@ initarm_common(vaddr_t kvm_base, vsize_t
* order.
*/
paddr_t segend = end;
- for (size_t j = 0; j < nbp; j++) {
+ for (size_t j = 0; j < nbp && start < end; j++) {
paddr_t bp_start = bp[j].bp_start;
paddr_t bp_end = bp_start + bp[j].bp_pages;
+ VPRINTF(" bp %2zu start %08lx end %08lx\n",
+ j, ptoa(bp_start), ptoa(bp_end));
+
KASSERT(bp_start < bp_end);
- if (start > bp_end || segend < bp_start)
+ if (start >= bp_end || segend < bp_start)
continue;
if (start < bp_start)
@@ -414,6 +417,7 @@ initarm_common(vaddr_t kvm_base, vsize_t
uvm_page_physload(start, segend, start, segend,
vm_freelist);
+
memsize_total += ptoa(segend - start);
start = segend;
segend = end;
CVS commit: src/sys/arch/aarch64/aarch64
Module Name:src
Committed By: rin
Date: Sun May 30 05:40:57 UTC 2021
Modified Files:
src/sys/arch/aarch64/aarch64: netbsd32_machdep.c
Log Message:
Fix conversion between aarch64 and aarch32 fpreg's; in aarch32 mode,
d0-d31 are packed into v0-v15 (== q0-q15).
This fixes crashes in VFP-optimized codes running on COMPAT_NETBSD32.
OK ryo
To generate a diff of this commit:
cvs rdiff -u -r1.17 -r1.18 src/sys/arch/aarch64/aarch64/netbsd32_machdep.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/aarch64/aarch64/netbsd32_machdep.c
diff -u src/sys/arch/aarch64/aarch64/netbsd32_machdep.c:1.17 src/sys/arch/aarch64/aarch64/netbsd32_machdep.c:1.18
--- src/sys/arch/aarch64/aarch64/netbsd32_machdep.c:1.17 Fri Dec 11 18:03:33 2020
+++ src/sys/arch/aarch64/aarch64/netbsd32_machdep.c Sun May 30 05:40:56 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: netbsd32_machdep.c,v 1.17 2020/12/11 18:03:33 skrll Exp $ */
+/* $NetBSD: netbsd32_machdep.c,v 1.18 2021/05/30 05:40:56 rin Exp $ */
/*
* Copyright (c) 2018 Ryo Shimizu
@@ -27,7 +27,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: netbsd32_machdep.c,v 1.17 2020/12/11 18:03:33 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: netbsd32_machdep.c,v 1.18 2021/05/30 05:40:56 rin Exp $");
#if defined(_KERNEL_OPT)
#include "opt_compat_netbsd.h"
@@ -158,7 +158,7 @@ netbsd32_process_read_fpregs(struct lwp
{
struct proc * const p = l->l_proc;
struct pcb * const pcb = lwp_getpcb(l);
- int i;
+ int i, j;
if ((p->p_flag & PK_32) == 0)
return EINVAL;
@@ -180,11 +180,17 @@ netbsd32_process_read_fpregs(struct lwp
fpregs->fpr_vfp.vfp_fpinst = 0;
fpregs->fpr_vfp.vfp_fpinst2 = 0;
- for (i = 0; i < 32; i++) {
+ for (i = j = 0; i < 16; i++) {
#ifdef __AARCH64EB__
- fpregs->fpr_vfp.vfp_regs[i] = pcb->pcb_fpregs.fp_reg[i].u64[1];
+ fpregs->fpr_vfp.vfp_regs[j++] =
+ pcb->pcb_fpregs.fp_reg[i].u64[1];
+ fpregs->fpr_vfp.vfp_regs[j++] =
+ pcb->pcb_fpregs.fp_reg[i].u64[0];
#else
- fpregs->fpr_vfp.vfp_regs[i] = pcb->pcb_fpregs.fp_reg[i].u64[0];
+ fpregs->fpr_vfp.vfp_regs[j++] =
+ pcb->pcb_fpregs.fp_reg[i].u64[0];
+ fpregs->fpr_vfp.vfp_regs[j++] =
+ pcb->pcb_fpregs.fp_reg[i].u64[1];
#endif
}
@@ -226,7 +232,7 @@ netbsd32_process_write_fpregs(struct lwp
{
struct proc * const p = l->l_proc;
struct pcb * const pcb = lwp_getpcb(l);
- int i;
+ int i, j;
if ((p->p_flag & PK_32) == 0)
return EINVAL;
@@ -237,17 +243,18 @@ netbsd32_process_write_fpregs(struct lwp
pcb->pcb_fpregs.fpsr = fpregs->fpr_vfp.vfp_fpscr & FPSR_BITS;
pcb->pcb_fpregs.fpcr = fpregs->fpr_vfp.vfp_fpscr & FPCR_BITS;
- CTASSERT(__arraycount(fpregs->fpr_vfp.vfp_regs) ==
- __arraycount(pcb->pcb_fpregs.fp_reg) + 1);
- for (i = 0; i < __arraycount(pcb->pcb_fpregs.fp_reg); i++) {
+ for (i = j = 0; i < 16; i++) {
#ifdef __AARCH64EB__
- pcb->pcb_fpregs.fp_reg[i].u64[0] = 0;
pcb->pcb_fpregs.fp_reg[i].u64[1] =
+ fpregs->fpr_vfp.vfp_regs[j++];
+ pcb->pcb_fpregs.fp_reg[i].u64[0] =
+ fpregs->fpr_vfp.vfp_regs[j++];
#else
- pcb->pcb_fpregs.fp_reg[i].u64[1] = 0;
pcb->pcb_fpregs.fp_reg[i].u64[0] =
+ fpregs->fpr_vfp.vfp_regs[j++];
+ pcb->pcb_fpregs.fp_reg[i].u64[1] =
+ fpregs->fpr_vfp.vfp_regs[j++];
#endif
- fpregs->fpr_vfp.vfp_regs[i];
}
return 0;
@@ -458,18 +465,21 @@ cpu_getmcontext32(struct lwp *l, mcontex
/* fpu context */
if (fpu_used_p(l)) {
const struct pcb * const pcb = lwp_getpcb(l);
- int i;
+ int i, j;
fpu_save(l);
- CTASSERT(__arraycount(mcp->__vfpregs.__vfp_fstmx) ==
- __arraycount(pcb->pcb_fpregs.fp_reg));
- for (i = 0; i < __arraycount(pcb->pcb_fpregs.fp_reg); i++) {
- mcp->__vfpregs.__vfp_fstmx[i] =
+ for (i = j = 0; i < 16; i++) {
#ifdef __AARCH64EB__
+ mcp->__vfpregs.__vfp_fstmx[j++] =
pcb->pcb_fpregs.fp_reg[i].u64[1];
+ mcp->__vfpregs.__vfp_fstmx[j++] =
+ pcb->pcb_fpregs.fp_reg[i].u64[0];
#else
+ mcp->__vfpregs.__vfp_fstmx[j++] =
pcb->pcb_fpregs.fp_reg[i].u64[0];
+ mcp->__vfpregs.__vfp_fstmx[j++] =
+ pcb->pcb_fpregs.fp_reg[i].u64[1];
#endif
}
@@ -491,7 +501,7 @@ cpu_setmcontext32(struct lwp *l, const m
struct trapframe * const tf = l->l_md.md_utf;
const __greg32_t * const gr = mcp->__gregs;
struct proc * const p = l->l_proc;
- int error, i;
+ int error, i, j;
if (flags & _UC_CPU) {
error = cpu_mcontext32_validate(l, mcp);
@@ -521,17 +531,18 @@ cpu_setmcontext32(struct lwp *l, const m
struct pcb * const pcb = lwp_getpcb(l);
fpu_discard(l, true);
- CTASSERT(__arraycount(mcp->__vfpregs.__vfp_fstmx) ==
- __arraycount(pcb->pcb_fpregs.fp_reg));
- for (i = 0; i < __arraycount(pcb->pcb_fpregs.fp_reg); i++) {
+ for (i = j = 0; i < 16; i++) {
#ifdef __AARCH64EB__
- pcb->pcb_fpregs.fp_reg[i].u64[0] = 0;
pcb->pcb_fpregs.fp_reg[i].u64[1] =
+ mcp->__vfpregs.__vfp_fstmx[j++];
+ pcb->pcb_fpregs.fp_reg[i].u64[0]
CVS commit: src/sys/arch/aarch64/aarch64
Module Name:src
Committed By: skrll
Date: Wed May 19 11:54:18 UTC 2021
Modified Files:
src/sys/arch/aarch64/aarch64: db_interface.c
Log Message:
Reduce characters to print in db_pte_print and unwrap some short lines.
To generate a diff of this commit:
cvs rdiff -u -r1.14 -r1.15 src/sys/arch/aarch64/aarch64/db_interface.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/aarch64/aarch64/db_interface.c
diff -u src/sys/arch/aarch64/aarch64/db_interface.c:1.14 src/sys/arch/aarch64/aarch64/db_interface.c:1.15
--- src/sys/arch/aarch64/aarch64/db_interface.c:1.14 Mon May 3 19:33:09 2021
+++ src/sys/arch/aarch64/aarch64/db_interface.c Wed May 19 11:54:17 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: db_interface.c,v 1.14 2021/05/03 19:33:09 skrll Exp $ */
+/* $NetBSD: db_interface.c,v 1.15 2021/05/19 11:54:17 skrll Exp $ */
/*
* Copyright (c) 2017 Ryo Shimizu
@@ -27,7 +27,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: db_interface.c,v 1.14 2021/05/03 19:33:09 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: db_interface.c,v 1.15 2021/05/19 11:54:17 skrll Exp $");
#include
#include
@@ -360,15 +360,13 @@ db_pte_print(pt_entry_t pte, int level,
pr(", PA=%lx", l3pte_pa(pte));
- pr(", %s", (pte & LX_BLKPAG_UXN) ?
- "UXN" : "UX ");
- pr(", %s", (pte & LX_BLKPAG_PXN) ?
- "PXN" : "PX ");
+ pr(", %s", (pte & LX_BLKPAG_UXN) ? "UXN" : "UX");
+ pr(", %s", (pte & LX_BLKPAG_PXN) ? "PXN" : "PX");
if (pte & LX_BLKPAG_CONTIG)
pr(", CONTIG");
- pr(", %s", (pte & LX_BLKPAG_NG) ? "NG" : "global");
+ pr(", %s", (pte & LX_BLKPAG_NG) ? "nG" : "G");
pr(", %s", (pte & LX_BLKPAG_AF) ?
"accessible" :
"**fault** ");
@@ -403,10 +401,10 @@ db_pte_print(pt_entry_t pte, int level,
pr(", WT");
break;
case LX_BLKPAG_ATTR_DEVICE_MEM:
- pr(", DEVICE");
+ pr(", DEV");
break;
case LX_BLKPAG_ATTR_DEVICE_MEM_SO:
- pr(", DEVICE(SO)");
+ pr(", DEV(SO)");
break;
default:
pr(", ATTR(%lu)", __SHIFTOUT(pte, LX_BLKPAG_ATTR_INDX));
CVS commit: src/sys/arch/aarch64/aarch64
Module Name:src
Committed By: rin
Date: Sat May 15 11:39:20 UTC 2021
Modified Files:
src/sys/arch/aarch64/aarch64: aarch32_syscall.c
Log Message:
Wrap long line. No binary changes.
To generate a diff of this commit:
cvs rdiff -u -r1.4 -r1.5 src/sys/arch/aarch64/aarch64/aarch32_syscall.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/aarch64/aarch64/aarch32_syscall.c
diff -u src/sys/arch/aarch64/aarch64/aarch32_syscall.c:1.4 src/sys/arch/aarch64/aarch64/aarch32_syscall.c:1.5
--- src/sys/arch/aarch64/aarch64/aarch32_syscall.c:1.4 Sat May 15 11:38:26 2021
+++ src/sys/arch/aarch64/aarch64/aarch32_syscall.c Sat May 15 11:39:20 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: aarch32_syscall.c,v 1.4 2021/05/15 11:38:26 rin Exp $ */
+/* $NetBSD: aarch32_syscall.c,v 1.5 2021/05/15 11:39:20 rin Exp $ */
/*
* Copyright (c) 2018 Ryo Shimizu
@@ -27,7 +27,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: aarch32_syscall.c,v 1.4 2021/05/15 11:38:26 rin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: aarch32_syscall.c,v 1.5 2021/05/15 11:39:20 rin Exp $");
#include
#include
@@ -151,7 +151,8 @@ EMULNAME(syscall)(struct trapframe *tf)
do_trace = p->p_trace_enabled &&
((callp->sy_flags & SYCALL_INDIRECT) == 0);
if (__predict_false(do_trace ||
- KDTRACE_ENTRY(callp->sy_entry) || KDTRACE_ENTRY(callp->sy_return))) {
+ KDTRACE_ENTRY(callp->sy_entry) ||
+ KDTRACE_ENTRY(callp->sy_return))) {
/* build 64bit args for trace_enter()/trace_exit() */
int nargs = callp->sy_narg;
for (i = 0; i < nargs; i++)
CVS commit: src/sys/arch/aarch64/aarch64
Module Name:src
Committed By: rin
Date: Sat May 15 11:38:26 UTC 2021
Modified Files:
src/sys/arch/aarch64/aarch64: aarch32_syscall.c
Log Message:
Fix __syscall(2) for COMPAT_NETBSD32 on aarch64{,eb}.
The 1st argument for __syscall(2) is quad_t, which is stored in r0 and r1.
Now, tests/lib/libc/t_syscall:mmap___syscall passes for COMPAT_NETBSD32.
To generate a diff of this commit:
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/aarch64/aarch64/aarch32_syscall.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/aarch64/aarch64/aarch32_syscall.c
diff -u src/sys/arch/aarch64/aarch64/aarch32_syscall.c:1.3 src/sys/arch/aarch64/aarch64/aarch32_syscall.c:1.4
--- src/sys/arch/aarch64/aarch64/aarch32_syscall.c:1.3 Fri Apr 12 09:29:26 2019
+++ src/sys/arch/aarch64/aarch64/aarch32_syscall.c Sat May 15 11:38:26 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: aarch32_syscall.c,v 1.3 2019/04/12 09:29:26 ryo Exp $ */
+/* $NetBSD: aarch32_syscall.c,v 1.4 2021/05/15 11:38:26 rin Exp $ */
/*
* Copyright (c) 2018 Ryo Shimizu
@@ -27,7 +27,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: aarch32_syscall.c,v 1.3 2019/04/12 09:29:26 ryo Exp $");
+__KERNEL_RCSID(0, "$NetBSD: aarch32_syscall.c,v 1.4 2021/05/15 11:38:26 rin Exp $");
#include
#include
@@ -91,9 +91,24 @@ EMULNAME(syscall)(struct trapframe *tf)
code %= EMULNAMEU(SYS_NSYSENT);
callp = p->p_emul->e_sysent + code;
if (__predict_false(callp->sy_flags & SYCALL_INDIRECT)) {
- nargs_reg -= 1;
- regstart = 1; /* args start from r1 */
- code = tf->tf_reg[0] % EMULNAMEU(SYS_NSYSENT);
+ int off = 1;
+#ifdef NETBSD32_SYS_netbsd32syscall /* XXX ugly: apply only for NETBSD32 */
+ /*
+ * For __syscall(2), 1st argument is quad_t, which is
+ * stored in r0 and r1.
+ */
+ if (code == NETBSD32_SYS_netbsd32syscall)
+ off = 2;
+#endif
+ nargs_reg -= off;
+ regstart = off; /* args start from r1 or r2 */
+#ifdef __AARCH64EB__
+ if (off == 2)
+ code = tf->tf_reg[1];
+ else
+#endif
+ code = tf->tf_reg[0];
+ code %= EMULNAMEU(SYS_NSYSENT);
callp = p->p_emul->e_sysent + code;
/* don't allow nested syscall */
CVS commit: src/sys/arch/aarch64/aarch64
Module Name:src
Committed By: skrll
Date: Mon May 3 19:33:09 UTC 2021
Modified Files:
src/sys/arch/aarch64/aarch64: db_interface.c
Log Message:
Remove unnecssary brackets. Same binary before and after.
To generate a diff of this commit:
cvs rdiff -u -r1.13 -r1.14 src/sys/arch/aarch64/aarch64/db_interface.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/aarch64/aarch64/db_interface.c
diff -u src/sys/arch/aarch64/aarch64/db_interface.c:1.13 src/sys/arch/aarch64/aarch64/db_interface.c:1.14
--- src/sys/arch/aarch64/aarch64/db_interface.c:1.13 Fri Apr 30 20:07:22 2021
+++ src/sys/arch/aarch64/aarch64/db_interface.c Mon May 3 19:33:09 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: db_interface.c,v 1.13 2021/04/30 20:07:22 skrll Exp $ */
+/* $NetBSD: db_interface.c,v 1.14 2021/05/03 19:33:09 skrll Exp $ */
/*
* Copyright (c) 2017 Ryo Shimizu
@@ -27,7 +27,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: db_interface.c,v 1.13 2021/04/30 20:07:22 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: db_interface.c,v 1.14 2021/05/03 19:33:09 skrll Exp $");
#include
#include
@@ -93,17 +93,17 @@ db_read_bytes(vaddr_t addr, size_t size,
reg_pan_write(0); /* disable PAN */
tmp = (uintptr_t)src | (uintptr_t)data;
- if ((size >= 8) && ((tmp & 7) == 0)) {
+ if (size >= 8 && (tmp & 7) == 0) {
*(uint64_t *)data = *(const uint64_t *)src;
src += 8;
data += 8;
size -= 8;
- } else if ((size >= 4) && ((tmp & 3) == 0)) {
+ } else if (size >= 4 && (tmp & 3) == 0) {
*(uint32_t *)data = *(const uint32_t *)src;
src += 4;
data += 4;
size -= 4;
- } else if ((size >= 2) && ((tmp & 1) == 0)) {
+ } else if (size >= 2 && (tmp & 1) == 0) {
*(uint16_t *)data = *(const uint16_t *)src;
src += 2;
data += 2;
@@ -202,17 +202,17 @@ db_write_bytes(vaddr_t addr, size_t size
lastpage = atop(va);
tmp = (uintptr_t)dst | (uintptr_t)data;
- if ((size >= 8) && ((tmp & 7) == 0)) {
+ if (size >= 8 && (tmp & 7) == 0) {
*(uint64_t *)dst = *(const uint64_t *)data;
dst += 8;
data += 8;
size -= 8;
- } else if ((size >= 4) && ((tmp & 3) == 0)) {
+ } else if (size >= 4 && (tmp & 3) == 0) {
*(uint32_t *)dst = *(const uint32_t *)data;
dst += 4;
data += 4;
size -= 4;
- } else if ((size >= 2) && ((tmp & 1) == 0)) {
+ } else if (size >= 2 && (tmp & 1) == 0) {
*(uint16_t *)dst = *(const uint16_t *)data;
dst += 2;
data += 2;
@@ -261,25 +261,25 @@ db_branch_taken(db_expr_t inst, db_addr_
#define INSN_FMT_IMM19(insn) (((insn) >> 5) & 0x7)
#define INSN_FMT_IMM14(insn) (((insn) >> 5) & 0x3fff)
- if (((inst & 0xfc1f) == 0xd65f) || /* ret xN */
- ((inst & 0xfc1f) == 0xd63f) || /* blr xN */
- ((inst & 0xfc1f) == 0xd61f)) { /* br xN */
+ if ((inst & 0xfc1f) == 0xd65f || /* ret xN */
+ (inst & 0xfc1f) == 0xd63f || /* blr xN */
+ (inst & 0xfc1f) == 0xd61f) { /* br xN */
return db_fetch_reg(INSN_FMT_RN(inst), regs, false);
}
- if (((inst & 0xfc00) == 0x9400) || /* bl imm */
- ((inst & 0xfc00) == 0x1400)) { /* b imm */
+ if ((inst & 0xfc00) == 0x9400 || /* bl imm */
+ (inst & 0xfc00) == 0x1400) { /* b imm */
return SignExtend(26, INSN_FMT_IMM26(inst), 4) + pc;
}
- if (((inst & 0xff10) == 0x5400) || /* b.cond */
- ((inst & 0x7f00) == 0x3500) || /* cbnz */
- ((inst & 0x7f00) == 0x3400)) { /* cbz */
+ if ((inst & 0xff10) == 0x5400 || /* b.cond */
+ (inst & 0x7f00) == 0x3500 || /* cbnz */
+ (inst & 0x7f00) == 0x3400) { /* cbz */
return SignExtend(19, INSN_FMT_IMM19(inst), 4) + pc;
}
- if (((inst & 0x7f00) == 0x3700) || /* tbnz */
- ((inst & 0x7f00) == 0x3600)) { /* tbz */
+ if ((inst & 0x7f00) == 0x3700 || /* tbnz */
+ (inst & 0x7f00) == 0x3600) { /* tbz */
return SignExtend(14, INSN_FMT_IMM14(inst), 4) + pc;
}
@@ -291,18 +291,18 @@ db_inst_unconditional_flow_transfer(db_e
{
LE32TOH(inst);
- if (((inst & 0xfc1f) == 0xd65f) || /* ret xN */
- ((inst & 0xfc00) == 0x9400) || /* bl */
- ((inst & 0xfc1f) == 0xd63f) || /* blr */
- ((inst & 0xfc00) == 0x1400) || /* b imm */
- ((inst & 0xfc1f) == 0xd61f)) /* br */
+ if ((inst & 0xfc1f) == 0xd65f || /* ret xN */
+ (inst & 0xfc00) == 0x9400 || /* bl */
+ (inst & 0xfc1f) == 0xd63f || /* blr */
+ (inst & 0xfc00) == 0x1400 || /* b imm */
+ (inst & 0xfc1f) == 0xd61f) /* br */
return true;
#define INSN_FMT_COND(insn) ((insn) & 0xf)
#define CONDITION_AL 14
- if (((inst & 0xff10) == 0x5400) && /* b.cond */
- (INSN_FMT_COND(inst) == CONDITION_AL)) /* always? */
+ if ((inst & 0xff10) == 0x5400 && /* b.cond */
+ INSN_FMT_COND(inst)
CVS commit: src/sys/arch/aarch64/aarch64
Module Name:src
Committed By: ryo
Date: Wed Apr 21 09:52:21 UTC 2021
Modified Files:
src/sys/arch/aarch64/aarch64: pmap.c
Log Message:
added more attributes of PTE displayed by "ddb>machine pte"
To generate a diff of this commit:
cvs rdiff -u -r1.104 -r1.105 src/sys/arch/aarch64/aarch64/pmap.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/aarch64/aarch64/pmap.c
diff -u src/sys/arch/aarch64/aarch64/pmap.c:1.104 src/sys/arch/aarch64/aarch64/pmap.c:1.105
--- src/sys/arch/aarch64/aarch64/pmap.c:1.104 Sat Apr 17 01:53:58 2021
+++ src/sys/arch/aarch64/aarch64/pmap.c Wed Apr 21 09:52:20 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: pmap.c,v 1.104 2021/04/17 01:53:58 mrg Exp $ */
+/* $NetBSD: pmap.c,v 1.105 2021/04/21 09:52:20 ryo Exp $ */
/*
* Copyright (c) 2017 Ryo Shimizu
@@ -27,7 +27,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.104 2021/04/17 01:53:58 mrg Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.105 2021/04/21 09:52:20 ryo Exp $");
#include "opt_arm_debug.h"
#include "opt_ddb.h"
@@ -2779,6 +2779,12 @@ pmap_db_pte_print(pt_entry_t pte, int le
case LX_BLKPAG_ATTR_DEVICE_MEM:
pr(", DEVICE");
break;
+ case LX_BLKPAG_ATTR_DEVICE_MEM_SO:
+ pr(", DEVICE(SO)");
+ break;
+ default:
+ pr(", ATTR(%lu)", __SHIFTOUT(pte, LX_BLKPAG_ATTR_INDX));
+ break;
}
if (pte & LX_BLKPAG_OS_BOOT)
CVS commit: src/sys/arch/aarch64/aarch64
Module Name:src
Committed By: ryo
Date: Wed Apr 14 05:43:09 UTC 2021
Modified Files:
src/sys/arch/aarch64/aarch64: bus_space.c trap.c
Log Message:
Fix the problem "pcictl pci0 list" causes "panic: trap_el1h_error" on rockpro64.
The panic occures in bus_space_barrier() in rk3399_pcie.c:rkpcie_conf_read().
We expected bus_space_peek_4() to trap and recover in the path
trap_el1h_sync() -> data_abort_handler(), but In fact, the read is delayed
until bus_space_barrier(), and we get an SError interrupt (trap_el1h_error)
instead of a Synchronous Exception (trap_el1h_sync).
To catch this correctly, An implicit barrier in bus_space_peek have been added,
and trap the SError interrupt to recover from.
To generate a diff of this commit:
cvs rdiff -u -r1.15 -r1.16 src/sys/arch/aarch64/aarch64/bus_space.c
cvs rdiff -u -r1.45 -r1.46 src/sys/arch/aarch64/aarch64/trap.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/aarch64/aarch64/bus_space.c
diff -u src/sys/arch/aarch64/aarch64/bus_space.c:1.15 src/sys/arch/aarch64/aarch64/bus_space.c:1.16
--- src/sys/arch/aarch64/aarch64/bus_space.c:1.15 Mon Dec 14 19:32:29 2020
+++ src/sys/arch/aarch64/aarch64/bus_space.c Wed Apr 14 05:43:09 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: bus_space.c,v 1.15 2020/12/14 19:32:29 skrll Exp $ */
+/* $NetBSD: bus_space.c,v 1.16 2021/04/14 05:43:09 ryo Exp $ */
/*
* Copyright (c) 2017 Ryo Shimizu
@@ -27,7 +27,7 @@
*/
#include
-__KERNEL_RCSID(1, "$NetBSD: bus_space.c,v 1.15 2020/12/14 19:32:29 skrll Exp $");
+__KERNEL_RCSID(1, "$NetBSD: bus_space.c,v 1.16 2021/04/14 05:43:09 ryo Exp $");
#include
#include
@@ -702,6 +702,7 @@ generic_bs_pe_1(void *t, bus_space_handl
if ((error = cpu_set_onfault()) == 0) {
*datap = generic_dsb_bs_r_1(t, bsh, offset);
+ dsb(ld);
cpu_unset_onfault();
}
return error;
@@ -716,6 +717,7 @@ generic_bs_pe_2(void *t, bus_space_handl
if ((error = cpu_set_onfault()) == 0) {
*datap = NSWAP(generic_dsb_bs_r_2)(t, bsh, offset);
+ dsb(ld);
cpu_unset_onfault();
}
return error;
@@ -730,6 +732,7 @@ generic_bs_pe_4(void *t, bus_space_handl
if ((error = cpu_set_onfault()) == 0) {
*datap = NSWAP(generic_dsb_bs_r_4)(t, bsh, offset);
+ dsb(ld);
cpu_unset_onfault();
}
return error;
@@ -744,6 +747,7 @@ generic_bs_pe_8(void *t, bus_space_handl
if ((error = cpu_set_onfault()) == 0) {
*datap = NSWAP(generic_dsb_bs_r_8)(t, bsh, offset);
+ dsb(ld);
cpu_unset_onfault();
}
return error;
Index: src/sys/arch/aarch64/aarch64/trap.c
diff -u src/sys/arch/aarch64/aarch64/trap.c:1.45 src/sys/arch/aarch64/aarch64/trap.c:1.46
--- src/sys/arch/aarch64/aarch64/trap.c:1.45 Tue Mar 9 16:44:27 2021
+++ src/sys/arch/aarch64/aarch64/trap.c Wed Apr 14 05:43:09 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: trap.c,v 1.45 2021/03/09 16:44:27 ryo Exp $ */
+/* $NetBSD: trap.c,v 1.46 2021/04/14 05:43:09 ryo Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -31,7 +31,7 @@
#include
-__KERNEL_RCSID(1, "$NetBSD: trap.c,v 1.45 2021/03/09 16:44:27 ryo Exp $");
+__KERNEL_RCSID(1, "$NetBSD: trap.c,v 1.46 2021/04/14 05:43:09 ryo Exp $");
#include "opt_arm_intr_impl.h"
#include "opt_compat_netbsd32.h"
@@ -861,6 +861,26 @@ unknown:
}
}
+void
+trap_el1h_error(struct trapframe *tf)
+{
+ /*
+ * Normally, we should panic unconditionally,
+ * but SError interrupt may occur when accessing to unmapped(?) I/O
+ * spaces. bus_space_{peek,poke}_{1,2,4,8}() should trap these case.
+ */
+ struct faultbuf *fb;
+
+ if (curcpu()->ci_intr_depth == 0) {
+ fb = cpu_disable_onfault();
+ if (fb != NULL) {
+ cpu_jump_onfault(tf, fb, EFAULT);
+ return;
+ }
+ }
+ panic("%s", __func__);
+}
+
#define bad_trap_panic(trapfunc) \
void \
trapfunc(struct trapframe *tf) \
@@ -872,7 +892,6 @@ bad_trap_panic(trap_el1t_irq)
bad_trap_panic(trap_el1t_fiq)
bad_trap_panic(trap_el1t_error)
bad_trap_panic(trap_el1h_fiq)
-bad_trap_panic(trap_el1h_error)
bad_trap_panic(trap_el0_fiq)
bad_trap_panic(trap_el0_error)
bad_trap_panic(trap_el0_32fiq)
CVS commit: src/sys/arch/aarch64/aarch64
Module Name:src
Committed By: skrll
Date: Thu Mar 25 07:31:57 UTC 2021
Modified Files:
src/sys/arch/aarch64/aarch64: aarch64_machdep.c
Log Message:
More debug
To generate a diff of this commit:
cvs rdiff -u -r1.59 -r1.60 src/sys/arch/aarch64/aarch64/aarch64_machdep.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/aarch64/aarch64/aarch64_machdep.c
diff -u src/sys/arch/aarch64/aarch64/aarch64_machdep.c:1.59 src/sys/arch/aarch64/aarch64/aarch64_machdep.c:1.60
--- src/sys/arch/aarch64/aarch64/aarch64_machdep.c:1.59 Thu Mar 25 07:30:16 2021
+++ src/sys/arch/aarch64/aarch64/aarch64_machdep.c Thu Mar 25 07:31:56 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: aarch64_machdep.c,v 1.59 2021/03/25 07:30:16 skrll Exp $ */
+/* $NetBSD: aarch64_machdep.c,v 1.60 2021/03/25 07:31:56 skrll Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
*/
#include
-__KERNEL_RCSID(1, "$NetBSD: aarch64_machdep.c,v 1.59 2021/03/25 07:30:16 skrll Exp $");
+__KERNEL_RCSID(1, "$NetBSD: aarch64_machdep.c,v 1.60 2021/03/25 07:31:56 skrll Exp $");
#include "opt_arm_debug.h"
#include "opt_cpuoptions.h"
@@ -251,7 +251,7 @@ initarm_common(vaddr_t kvm_base, vsize_t
vaddr_t kernstart, kernend;
vaddr_t kernstart_l2 __unused, kernend_l2; /* L2 table 2MB aligned */
vaddr_t kernelvmstart;
- int i;
+ size_t i;
cputype = cpu_idnum(); /* for compatible arm */
@@ -382,6 +382,10 @@ initarm_common(vaddr_t kvm_base, vsize_t
end = start + bootconfig.dram[i].pages;
int vm_freelist = VM_FREELIST_DEFAULT;
+
+ VPRINTF("block %2zu start %08lx end %08lx\n", i, ptoa(start),
+ ptoa(end));
+
/*
* This assumes the bp list is sorted in ascending
* order.
@@ -404,6 +408,10 @@ initarm_common(vaddr_t kvm_base, vsize_t
}
vm_freelist = bp[j].bp_freelist;
+VPRINTF(" start %08lx end %08lx"
+"... loading in freelist %d\n", ptoa(start),
+ptoa(segend), vm_freelist);
+
uvm_page_physload(start, segend, start, segend,
vm_freelist);
memsize_total += ptoa(segend - start);
CVS commit: src/sys/arch/aarch64/aarch64
Module Name:src Committed By: skrll Date: Thu Mar 25 07:30:16 UTC 2021 Modified Files: src/sys/arch/aarch64/aarch64: aarch64_machdep.c Log Message: Update a comment to reflect reality To generate a diff of this commit: cvs rdiff -u -r1.58 -r1.59 src/sys/arch/aarch64/aarch64/aarch64_machdep.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/aarch64/aarch64/aarch64_machdep.c diff -u src/sys/arch/aarch64/aarch64/aarch64_machdep.c:1.58 src/sys/arch/aarch64/aarch64/aarch64_machdep.c:1.59 --- src/sys/arch/aarch64/aarch64/aarch64_machdep.c:1.58 Sun Mar 21 07:32:44 2021 +++ src/sys/arch/aarch64/aarch64/aarch64_machdep.c Thu Mar 25 07:30:16 2021 @@ -1,4 +1,4 @@ -/* $NetBSD: aarch64_machdep.c,v 1.58 2021/03/21 07:32:44 skrll Exp $ */ +/* $NetBSD: aarch64_machdep.c,v 1.59 2021/03/25 07:30:16 skrll Exp $ */ /*- * Copyright (c) 2014 The NetBSD Foundation, Inc. @@ -30,7 +30,7 @@ */ #include -__KERNEL_RCSID(1, "$NetBSD: aarch64_machdep.c,v 1.58 2021/03/21 07:32:44 skrll Exp $"); +__KERNEL_RCSID(1, "$NetBSD: aarch64_machdep.c,v 1.59 2021/03/25 07:30:16 skrll Exp $"); #include "opt_arm_debug.h" #include "opt_cpuoptions.h" @@ -215,12 +215,14 @@ cpu_kernel_vm_init(uint64_t memory_start * 0x__ffe0_ End of KVA * = VM_MAX_KERNEL_ADDRESS * + * 0x_c000_4000_ Start of KVA + * * 0x_c000_0???_ End of kernel * = _end[] * 0x_c000_00??_ Start of kernel * = __kernel_text[] * - * 0x_c000__ Kernel base address & start of KVA + * 0x_c000__ Kernel base address * = VM_MIN_KERNEL_ADDRESS * * 0x_bfff__ End of direct mapped
CVS commit: src/sys/arch/aarch64/aarch64
Module Name:src
Committed By: skrll
Date: Sun Mar 21 09:08:40 UTC 2021
Modified Files:
src/sys/arch/aarch64/aarch64: locore.S
Log Message:
Fix a comment
To generate a diff of this commit:
cvs rdiff -u -r1.77 -r1.78 src/sys/arch/aarch64/aarch64/locore.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/aarch64/aarch64/locore.S
diff -u src/sys/arch/aarch64/aarch64/locore.S:1.77 src/sys/arch/aarch64/aarch64/locore.S:1.78
--- src/sys/arch/aarch64/aarch64/locore.S:1.77 Sat Mar 20 14:30:50 2021
+++ src/sys/arch/aarch64/aarch64/locore.S Sun Mar 21 09:08:40 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: locore.S,v 1.77 2021/03/20 14:30:50 skrll Exp $ */
+/* $NetBSD: locore.S,v 1.78 2021/03/21 09:08:40 skrll Exp $ */
/*
* Copyright (c) 2017 Ryo Shimizu
@@ -38,7 +38,7 @@
#include
#include "assym.h"
-RCSID("$NetBSD: locore.S,v 1.77 2021/03/20 14:30:50 skrll Exp $")
+RCSID("$NetBSD: locore.S,v 1.78 2021/03/21 09:08:40 skrll Exp $")
#ifdef AARCH64_DEVICE_MEM_STRONGLY_ORDERED
#define MAIR_DEVICE_MEM MAIR_DEVICE_nGnRnE
@@ -175,7 +175,7 @@ vstart:
msr tpidr_el0, xzr
msr tpidrro_el0, xzr
- /* set curcpu() */
+ /* set curlwp() */
adrl x0, lwp0 /* curlwp is lwp0 */
msr tpidr_el1, x0
DPRINTREG("curlwp = ", x0);
CVS commit: src/sys/arch/aarch64/aarch64
Module Name:src Committed By: skrll Date: Sun Mar 21 07:17:12 UTC 2021 Modified Files: src/sys/arch/aarch64/aarch64: aarch64_machdep.c Log Message: Tweak a comment To generate a diff of this commit: cvs rdiff -u -r1.56 -r1.57 src/sys/arch/aarch64/aarch64/aarch64_machdep.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/aarch64/aarch64/aarch64_machdep.c diff -u src/sys/arch/aarch64/aarch64/aarch64_machdep.c:1.56 src/sys/arch/aarch64/aarch64/aarch64_machdep.c:1.57 --- src/sys/arch/aarch64/aarch64/aarch64_machdep.c:1.56 Sat Dec 12 09:27:31 2020 +++ src/sys/arch/aarch64/aarch64/aarch64_machdep.c Sun Mar 21 07:17:12 2021 @@ -1,4 +1,4 @@ -/* $NetBSD: aarch64_machdep.c,v 1.56 2020/12/12 09:27:31 skrll Exp $ */ +/* $NetBSD: aarch64_machdep.c,v 1.57 2021/03/21 07:17:12 skrll Exp $ */ /*- * Copyright (c) 2014 The NetBSD Foundation, Inc. @@ -30,7 +30,7 @@ */ #include -__KERNEL_RCSID(1, "$NetBSD: aarch64_machdep.c,v 1.56 2020/12/12 09:27:31 skrll Exp $"); +__KERNEL_RCSID(1, "$NetBSD: aarch64_machdep.c,v 1.57 2021/03/21 07:17:12 skrll Exp $"); #include "opt_arm_debug.h" #include "opt_cpuoptions.h" @@ -180,7 +180,7 @@ cpu_kernel_vm_init(uint64_t memory_start * *text rwx => r-x *rodata rwx => r-- - *data rwx => rw- + *data rwx => rw- (.bss included) * * kernel image has mapped by L2 block. (2Mbyte) */
CVS commit: src/sys/arch/aarch64/aarch64
Module Name:src
Committed By: skrll
Date: Sun Mar 21 07:09:54 UTC 2021
Modified Files:
src/sys/arch/aarch64/aarch64: efi_machdep.c
Log Message:
Remove the unnecessary invalidation code in arm_efirt_md_map_range.
pmapboot_enter will panic if any overlapping mappings existed before and
a full TLB invalidate was done as part of turning the MMU on in locore.
To generate a diff of this commit:
cvs rdiff -u -r1.9 -r1.10 src/sys/arch/aarch64/aarch64/efi_machdep.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/aarch64/aarch64/efi_machdep.c
diff -u src/sys/arch/aarch64/aarch64/efi_machdep.c:1.9 src/sys/arch/aarch64/aarch64/efi_machdep.c:1.10
--- src/sys/arch/aarch64/aarch64/efi_machdep.c:1.9 Sat Mar 20 06:48:23 2021
+++ src/sys/arch/aarch64/aarch64/efi_machdep.c Sun Mar 21 07:09:54 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: efi_machdep.c,v 1.9 2021/03/20 06:48:23 skrll Exp $ */
+/* $NetBSD: efi_machdep.c,v 1.10 2021/03/21 07:09:54 skrll Exp $ */
/*-
* Copyright (c) 2018 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: efi_machdep.c,v 1.9 2021/03/20 06:48:23 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: efi_machdep.c,v 1.10 2021/03/21 07:09:54 skrll Exp $");
#include
#include
@@ -69,11 +69,6 @@ arm_efirt_md_map_range(vaddr_t va, paddr
}
pmapboot_enter(va, pa, sz, L3_SIZE, attr, NULL);
- while (sz >= PAGE_SIZE) {
- aarch64_tlbi_by_va(va);
- va += PAGE_SIZE;
- sz -= PAGE_SIZE;
- }
}
int
CVS commit: src/sys/arch/aarch64/aarch64
Module Name:src
Committed By: skrll
Date: Sat Mar 20 06:48:23 UTC 2021
Modified Files:
src/sys/arch/aarch64/aarch64: efi_machdep.c
Log Message:
Don't mark EFI runtime pages LX_BLKPAG_OS_READ | LX_BLKPAG_OS_WRITE as
these bits are only used by the current pmap fault code and these are
wired pages which will never fault.
To generate a diff of this commit:
cvs rdiff -u -r1.8 -r1.9 src/sys/arch/aarch64/aarch64/efi_machdep.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/aarch64/aarch64/efi_machdep.c
diff -u src/sys/arch/aarch64/aarch64/efi_machdep.c:1.8 src/sys/arch/aarch64/aarch64/efi_machdep.c:1.9
--- src/sys/arch/aarch64/aarch64/efi_machdep.c:1.8 Thu Oct 22 07:31:15 2020
+++ src/sys/arch/aarch64/aarch64/efi_machdep.c Sat Mar 20 06:48:23 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: efi_machdep.c,v 1.8 2020/10/22 07:31:15 skrll Exp $ */
+/* $NetBSD: efi_machdep.c,v 1.9 2021/03/20 06:48:23 skrll Exp $ */
/*-
* Copyright (c) 2018 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: efi_machdep.c,v 1.8 2020/10/22 07:31:15 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: efi_machdep.c,v 1.9 2021/03/20 06:48:23 skrll Exp $");
#include
#include
@@ -53,18 +53,15 @@ arm_efirt_md_map_range(vaddr_t va, paddr
switch (type) {
case ARM_EFIRT_MEM_CODE:
- attr = LX_BLKPAG_OS_READ | LX_BLKPAG_OS_WRITE |
- LX_BLKPAG_AF | LX_BLKPAG_AP_RW | LX_BLKPAG_UXN |
+ attr = LX_BLKPAG_AF | LX_BLKPAG_AP_RW | LX_BLKPAG_UXN |
LX_BLKPAG_ATTR_NORMAL_WB;
break;
case ARM_EFIRT_MEM_DATA:
- attr = LX_BLKPAG_OS_READ | LX_BLKPAG_OS_WRITE |
- LX_BLKPAG_AF | LX_BLKPAG_AP_RW | LX_BLKPAG_UXN | LX_BLKPAG_PXN |
+ attr = LX_BLKPAG_AF | LX_BLKPAG_AP_RW | LX_BLKPAG_UXN | LX_BLKPAG_PXN |
LX_BLKPAG_ATTR_NORMAL_WB;
break;
case ARM_EFIRT_MEM_MMIO:
- attr = LX_BLKPAG_OS_READ | LX_BLKPAG_OS_WRITE |
- LX_BLKPAG_AF | LX_BLKPAG_AP_RW | LX_BLKPAG_UXN | LX_BLKPAG_PXN |
+ attr = LX_BLKPAG_AF | LX_BLKPAG_AP_RW | LX_BLKPAG_UXN | LX_BLKPAG_PXN |
LX_BLKPAG_ATTR_DEVICE_MEM;
break;
default:
CVS commit: src/sys/arch/aarch64/aarch64
Module Name:src
Committed By: ryo
Date: Tue Mar 9 16:43:13 UTC 2021
Modified Files:
src/sys/arch/aarch64/aarch64: db_machdep.c
Log Message:
"machine cpu" command shows pc of trapframe and the symbol
To generate a diff of this commit:
cvs rdiff -u -r1.35 -r1.36 src/sys/arch/aarch64/aarch64/db_machdep.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/aarch64/aarch64/db_machdep.c
diff -u src/sys/arch/aarch64/aarch64/db_machdep.c:1.35 src/sys/arch/aarch64/aarch64/db_machdep.c:1.36
--- src/sys/arch/aarch64/aarch64/db_machdep.c:1.35 Tue Mar 9 16:42:36 2021
+++ src/sys/arch/aarch64/aarch64/db_machdep.c Tue Mar 9 16:43:13 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: db_machdep.c,v 1.35 2021/03/09 16:42:36 ryo Exp $ */
+/* $NetBSD: db_machdep.c,v 1.36 2021/03/09 16:43:13 ryo Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: db_machdep.c,v 1.35 2021/03/09 16:42:36 ryo Exp $");
+__KERNEL_RCSID(0, "$NetBSD: db_machdep.c,v 1.36 2021/03/09 16:43:13 ryo Exp $");
#ifdef _KERNEL_OPT
#include "opt_compat_netbsd32.h"
@@ -944,11 +944,16 @@ db_md_switch_cpu_cmd(db_expr_t addr, boo
if (!have_addr) {
for (i = 0; i < ncpu; i++) {
- if (db_readytoswitch[i] != NULL)
-db_printf("cpu%d: ready. tf=%p\n", i,
-db_readytoswitch[i]);
- else
+ if (db_readytoswitch[i] != NULL) {
+db_printf("cpu%d: ready. tf=%p, pc=%016lx ", i,
+ db_readytoswitch[i],
+ db_readytoswitch[i]->tf_pc);
+db_printsym(db_readytoswitch[i]->tf_pc,
+ DB_STGY_ANY, db_printf);
+db_printf("\n");
+ } else {
db_printf("cpu%d: not responding\n", i);
+ }
}
return;
}
CVS commit: src/sys/arch/aarch64/aarch64
Module Name:src
Committed By: ryo
Date: Tue Mar 9 16:42:36 UTC 2021
Modified Files:
src/sys/arch/aarch64/aarch64: db_machdep.c
Log Message:
match the macro name to the order of the arguments. NFC.
To generate a diff of this commit:
cvs rdiff -u -r1.34 -r1.35 src/sys/arch/aarch64/aarch64/db_machdep.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/aarch64/aarch64/db_machdep.c
diff -u src/sys/arch/aarch64/aarch64/db_machdep.c:1.34 src/sys/arch/aarch64/aarch64/db_machdep.c:1.35
--- src/sys/arch/aarch64/aarch64/db_machdep.c:1.34 Tue Feb 23 07:13:51 2021
+++ src/sys/arch/aarch64/aarch64/db_machdep.c Tue Mar 9 16:42:36 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: db_machdep.c,v 1.34 2021/02/23 07:13:51 mrg Exp $ */
+/* $NetBSD: db_machdep.c,v 1.35 2021/03/09 16:42:36 ryo Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: db_machdep.c,v 1.34 2021/02/23 07:13:51 mrg Exp $");
+__KERNEL_RCSID(0, "$NetBSD: db_machdep.c,v 1.35 2021/03/09 16:42:36 ryo Exp $");
#ifdef _KERNEL_OPT
#include "opt_compat_netbsd32.h"
@@ -606,58 +606,58 @@ db_md_sysreg_cmd(db_expr_t addr, bool ha
static void
aarch64_set_bcr_bvr(int n, uint64_t bcr, uint64_t bvr)
{
-#define DBG_BVR_BCR_SET(regno, bcr, bvr) \
+#define DBG_BCR_BVR_SET(regno, bcr, bvr) \
do { \
reg_dbgbcr ## regno ## _el1_write(bcr); \
reg_dbgbvr ## regno ## _el1_write(bvr); \
} while (0 /* CONSTCOND */)
switch (n) {
- case 0: DBG_BVR_BCR_SET(0, bcr, bvr); break;
- case 1: DBG_BVR_BCR_SET(1, bcr, bvr); break;
- case 2: DBG_BVR_BCR_SET(2, bcr, bvr); break;
- case 3: DBG_BVR_BCR_SET(3, bcr, bvr); break;
- case 4: DBG_BVR_BCR_SET(4, bcr, bvr); break;
- case 5: DBG_BVR_BCR_SET(5, bcr, bvr); break;
- case 6: DBG_BVR_BCR_SET(6, bcr, bvr); break;
- case 7: DBG_BVR_BCR_SET(7, bcr, bvr); break;
- case 8: DBG_BVR_BCR_SET(8, bcr, bvr); break;
- case 9: DBG_BVR_BCR_SET(9, bcr, bvr); break;
- case 10: DBG_BVR_BCR_SET(10, bcr, bvr); break;
- case 11: DBG_BVR_BCR_SET(11, bcr, bvr); break;
- case 12: DBG_BVR_BCR_SET(12, bcr, bvr); break;
- case 13: DBG_BVR_BCR_SET(13, bcr, bvr); break;
- case 14: DBG_BVR_BCR_SET(14, bcr, bvr); break;
- case 15: DBG_BVR_BCR_SET(15, bcr, bvr); break;
+ case 0: DBG_BCR_BVR_SET(0, bcr, bvr); break;
+ case 1: DBG_BCR_BVR_SET(1, bcr, bvr); break;
+ case 2: DBG_BCR_BVR_SET(2, bcr, bvr); break;
+ case 3: DBG_BCR_BVR_SET(3, bcr, bvr); break;
+ case 4: DBG_BCR_BVR_SET(4, bcr, bvr); break;
+ case 5: DBG_BCR_BVR_SET(5, bcr, bvr); break;
+ case 6: DBG_BCR_BVR_SET(6, bcr, bvr); break;
+ case 7: DBG_BCR_BVR_SET(7, bcr, bvr); break;
+ case 8: DBG_BCR_BVR_SET(8, bcr, bvr); break;
+ case 9: DBG_BCR_BVR_SET(9, bcr, bvr); break;
+ case 10: DBG_BCR_BVR_SET(10, bcr, bvr); break;
+ case 11: DBG_BCR_BVR_SET(11, bcr, bvr); break;
+ case 12: DBG_BCR_BVR_SET(12, bcr, bvr); break;
+ case 13: DBG_BCR_BVR_SET(13, bcr, bvr); break;
+ case 14: DBG_BCR_BVR_SET(14, bcr, bvr); break;
+ case 15: DBG_BCR_BVR_SET(15, bcr, bvr); break;
}
}
static void
aarch64_set_wcr_wvr(int n, uint64_t wcr, uint64_t wvr)
{
-#define DBG_WVR_WCR_SET(regno, wcr, wvr) \
+#define DBG_WCR_WVR_SET(regno, wcr, wvr) \
do { \
reg_dbgwcr ## regno ## _el1_write(wcr); \
reg_dbgwvr ## regno ## _el1_write(wvr); \
} while (0 /* CONSTCOND */)
switch (n) {
- case 0: DBG_WVR_WCR_SET(0, wcr, wvr); break;
- case 1: DBG_WVR_WCR_SET(1, wcr, wvr); break;
- case 2: DBG_WVR_WCR_SET(2, wcr, wvr); break;
- case 3: DBG_WVR_WCR_SET(3, wcr, wvr); break;
- case 4: DBG_WVR_WCR_SET(4, wcr, wvr); break;
- case 5: DBG_WVR_WCR_SET(5, wcr, wvr); break;
- case 6: DBG_WVR_WCR_SET(6, wcr, wvr); break;
- case 7: DBG_WVR_WCR_SET(7, wcr, wvr); break;
- case 8: DBG_WVR_WCR_SET(8, wcr, wvr); break;
- case 9: DBG_WVR_WCR_SET(9, wcr, wvr); break;
- case 10: DBG_WVR_WCR_SET(10, wcr, wvr); break;
- case 11: DBG_WVR_WCR_SET(11, wcr, wvr); break;
- case 12: DBG_WVR_WCR_SET(12, wcr, wvr); break;
- case 13: DBG_WVR_WCR_SET(13, wcr, wvr); break;
- case 14: DBG_WVR_WCR_SET(14, wcr, wvr); break;
- case 15: DBG_WVR_WCR_SET(15, wcr, wvr); break;
+ case 0: DBG_WCR_WVR_SET(0, wcr, wvr); break;
+ case 1: DBG_WCR_WVR_SET(1, wcr, wvr); break;
+ case 2: DBG_WCR_WVR_SET(2, wcr, wvr); break;
+ case 3: DBG_WCR_WVR_SET(3, wcr, wvr); break;
+ case 4: DBG_WCR_WVR_SET(4, wcr, wvr); break;
+ case 5: DBG_WCR_WVR_SET(5, wcr, wvr); break;
+ case 6: DBG_WCR_WVR_SET(6, wcr, wvr); break;
+ case 7: DBG_WCR_WVR_SET(7, wcr, wvr); break;
+ case 8: DBG_WCR_WVR_SET(8, wcr, wvr); break;
+ case 9: DBG_WCR_WVR_SET(9, wcr, wvr); break;
+ case 10: DBG_WCR_WVR_SET(10, wcr, wvr); break;
+ case 11: DBG_WCR_WVR_SET(11, wcr, wvr); break;
+ case 12: DBG_WCR_WVR_SET(12, wcr, wvr); break;
+ case 13: DBG_WCR_WVR_SET(13, wcr, wvr); break;
+ case 14: DBG_WCR_WVR_SET(14,
CVS commit: src/sys/arch/aarch64/aarch64
Module Name:src Committed By: ryo Date: Tue Mar 9 16:40:59 UTC 2021 Modified Files: src/sys/arch/aarch64/aarch64: pmap.c Log Message: fix build error without options DDB. kvtopte() is referenced from arm/acpi/acpi_machdep.c To generate a diff of this commit: cvs rdiff -u -r1.102 -r1.103 src/sys/arch/aarch64/aarch64/pmap.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/aarch64/aarch64/pmap.c diff -u src/sys/arch/aarch64/aarch64/pmap.c:1.102 src/sys/arch/aarch64/aarch64/pmap.c:1.103 --- src/sys/arch/aarch64/aarch64/pmap.c:1.102 Sat Feb 13 18:13:53 2021 +++ src/sys/arch/aarch64/aarch64/pmap.c Tue Mar 9 16:40:59 2021 @@ -1,4 +1,4 @@ -/* $NetBSD: pmap.c,v 1.102 2021/02/13 18:13:53 ryo Exp $ */ +/* $NetBSD: pmap.c,v 1.103 2021/03/09 16:40:59 ryo Exp $ */ /* * Copyright (c) 2017 Ryo Shimizu @@ -27,7 +27,7 @@ */ #include -__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.102 2021/02/13 18:13:53 ryo Exp $"); +__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.103 2021/03/09 16:40:59 ryo Exp $"); #include "opt_arm_debug.h" #include "opt_ddb.h" @@ -2632,8 +2632,6 @@ pmap_is_referenced(struct vm_page *pg) return (pp->pp_pv.pv_va & VM_PROT_READ); } -#ifdef DDB - /* get pointer to kernel segment L2 or L3 table entry */ pt_entry_t * kvtopte(vaddr_t va) @@ -2643,6 +2641,8 @@ kvtopte(vaddr_t va) return _pmap_pte_lookup_bs(pmap_kernel(), va, NULL); } +#ifdef DDB + /* change attribute of kernel segment */ pt_entry_t pmap_kvattr(vaddr_t va, vm_prot_t prot)
CVS commit: src/sys/arch/aarch64/aarch64
Module Name:src Committed By: jmcneill Date: Mon Mar 1 11:37:31 UTC 2021 Modified Files: src/sys/arch/aarch64/aarch64: vm_machdep.c Log Message: cpu_lwp_fork: KASSERT -> KASSERTMSG to print the actual value of DAIF if it is not 0 in cpu_lwp_fork To generate a diff of this commit: cvs rdiff -u -r1.9 -r1.10 src/sys/arch/aarch64/aarch64/vm_machdep.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/aarch64/aarch64/vm_machdep.c diff -u src/sys/arch/aarch64/aarch64/vm_machdep.c:1.9 src/sys/arch/aarch64/aarch64/vm_machdep.c:1.10 --- src/sys/arch/aarch64/aarch64/vm_machdep.c:1.9 Thu Oct 15 22:52:08 2020 +++ src/sys/arch/aarch64/aarch64/vm_machdep.c Mon Mar 1 11:37:31 2021 @@ -1,4 +1,4 @@ -/* $NetBSD: vm_machdep.c,v 1.9 2020/10/15 22:52:08 rin Exp $ */ +/* $NetBSD: vm_machdep.c,v 1.10 2021/03/01 11:37:31 jmcneill Exp $ */ /*- * Copyright (c) 2014 The NetBSD Foundation, Inc. @@ -33,7 +33,7 @@ #include "opt_ddb.h" #include -__KERNEL_RCSID(0, "$NetBSD: vm_machdep.c,v 1.9 2020/10/15 22:52:08 rin Exp $"); +__KERNEL_RCSID(0, "$NetBSD: vm_machdep.c,v 1.10 2021/03/01 11:37:31 jmcneill Exp $"); #include #include @@ -163,7 +163,7 @@ cpu_lwp_fork(struct lwp *l1, struct lwp ktf->tf_reg[27] = (uint64_t)func; ktf->tf_reg[28] = (uint64_t)arg; ktf->tf_reg[29] = 0; - KASSERT(reg_daif_read() == 0); + KASSERTMSG(reg_daif_read() == 0, "DAIF=0x%lx", reg_daif_read()); ktf->tf_lr = (uintptr_t)lwp_trampoline; #ifdef DDB ktf->tf_pc = (uint64_t)&_here;
CVS commit: src/sys/arch/aarch64/aarch64
Module Name:src
Committed By: ryo
Date: Tue Feb 23 20:34:54 UTC 2021
Modified Files:
src/sys/arch/aarch64/aarch64: disasm.c
Log Message:
adjust tab. NFC
To generate a diff of this commit:
cvs rdiff -u -r1.14 -r1.15 src/sys/arch/aarch64/aarch64/disasm.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/aarch64/aarch64/disasm.c
diff -u src/sys/arch/aarch64/aarch64/disasm.c:1.14 src/sys/arch/aarch64/aarch64/disasm.c:1.15
--- src/sys/arch/aarch64/aarch64/disasm.c:1.14 Tue Feb 23 20:26:50 2021
+++ src/sys/arch/aarch64/aarch64/disasm.c Tue Feb 23 20:34:54 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: disasm.c,v 1.14 2021/02/23 20:26:50 ryo Exp $ */
+/* $NetBSD: disasm.c,v 1.15 2021/02/23 20:34:54 ryo Exp $ */
/*
* Copyright (c) 2018 Ryo Shimizu
@@ -27,7 +27,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: disasm.c,v 1.14 2021/02/23 20:26:50 ryo Exp $");
+__KERNEL_RCSID(0, "$NetBSD: disasm.c,v 1.15 2021/02/23 20:34:54 ryo Exp $");
#include
#include
@@ -1324,8 +1324,8 @@ static struct op_sys_table op_sys_table[
{ SYSREG_ENC(1, 0, 7, 8, 1), OPE_XT, "at\ts1e1w" },
{ SYSREG_ENC(1, 0, 7, 8, 2), OPE_XT, "at\ts1e0r" },
{ SYSREG_ENC(1, 0, 7, 8, 3), OPE_XT, "at\ts1e0w" },
- { SYSREG_ENC(1, 0, 7, 9, 0), OPE_XT, "at\ts1e1rp" },
- { SYSREG_ENC(1, 0, 7, 9, 1), OPE_XT, "at\ts1e1wp" },
+ { SYSREG_ENC(1, 0, 7, 9, 0), OPE_XT, "at\ts1e1rp" },
+ { SYSREG_ENC(1, 0, 7, 9, 1), OPE_XT, "at\ts1e1wp" },
{ SYSREG_ENC(1, 4, 7, 8, 0), OPE_XT, "at\ts1e2r" },
{ SYSREG_ENC(1, 4, 7, 8, 1), OPE_XT, "at\ts1e2w" },
{ SYSREG_ENC(1, 4, 7, 8, 4), OPE_XT, "at\ts12e1r" },
@@ -1335,9 +1335,9 @@ static struct op_sys_table op_sys_table[
{ SYSREG_ENC(1, 6, 7, 8, 0), OPE_XT, "at\ts1e3r" },
{ SYSREG_ENC(1, 6, 7, 8, 1), OPE_XT, "at\ts1e3w" },
- { SYSREG_ENC(1, 3, 7, 3, 4), OPE_XT, "cfp\trctx" },
- { SYSREG_ENC(1, 3, 7, 3, 5), OPE_XT, "dvp\trctx" },
- { SYSREG_ENC(1, 3, 7, 3, 7), OPE_XT, "cpp\trctx" },
+ { SYSREG_ENC(1, 3, 7, 3, 4), OPE_XT, "cfp\trctx" },
+ { SYSREG_ENC(1, 3, 7, 3, 5), OPE_XT, "dvp\trctx" },
+ { SYSREG_ENC(1, 3, 7, 3, 7), OPE_XT, "cpp\trctx" },
{ SYSREG_ENC(1, 0, 8, 3, 0), OPE_NONE, "tlbi\tvmalle1is" },
{ SYSREG_ENC(1, 0, 8, 3, 1), OPE_XT, "tlbi\tvae1is" },
CVS commit: src/sys/arch/aarch64/aarch64
Module Name:src
Committed By: ryo
Date: Tue Feb 23 20:26:50 UTC 2021
Modified Files:
src/sys/arch/aarch64/aarch64: disasm.c
Log Message:
fix wrong target register size of "ldrsh"
"ldrsh Xt, [Xn, Xm]" was being output as "ldrsh Wt, [Xn, Xm]"
To generate a diff of this commit:
cvs rdiff -u -r1.13 -r1.14 src/sys/arch/aarch64/aarch64/disasm.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/aarch64/aarch64/disasm.c
diff -u src/sys/arch/aarch64/aarch64/disasm.c:1.13 src/sys/arch/aarch64/aarch64/disasm.c:1.14
--- src/sys/arch/aarch64/aarch64/disasm.c:1.13 Tue Feb 23 20:15:04 2021
+++ src/sys/arch/aarch64/aarch64/disasm.c Tue Feb 23 20:26:50 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: disasm.c,v 1.13 2021/02/23 20:15:04 ryo Exp $ */
+/* $NetBSD: disasm.c,v 1.14 2021/02/23 20:26:50 ryo Exp $ */
/*
* Copyright (c) 2018 Ryo Shimizu
@@ -27,7 +27,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: disasm.c,v 1.13 2021/02/23 20:15:04 ryo Exp $");
+__KERNEL_RCSID(0, "$NetBSD: disasm.c,v 1.14 2021/02/23 20:26:50 ryo Exp $");
#include
#include
@@ -919,7 +919,7 @@ regoffset_b_common(const disasm_interfac
static void
regoffset_h_common(const disasm_interface_t *di, uint64_t pc, uint32_t insn,
uint64_t Rm, uint64_t option, uint64_t shift, uint64_t Rn, uint64_t Rt,
-const char *op)
+uint64_t RtSz, const char *op)
{
int r;
@@ -931,13 +931,13 @@ regoffset_h_common(const disasm_interfac
if ((shift == 0) && (option == 3)) {
PRINTF("%s\t%s, [%s,%s]\n",
op,
- ZREGNAME(0, Rt),
+ ZREGNAME(RtSz, Rt),
SREGNAME(1, Rn),
ZREGNAME(r, Rm));
} else if (shift == 0) {
PRINTF("%s\t%s, [%s,%s,%s]\n",
op,
- ZREGNAME(0, Rt),
+ ZREGNAME(RtSz, Rt),
SREGNAME(1, Rn),
ZREGNAME(r, Rm),
SHIFTOP8(option,
@@ -945,7 +945,7 @@ regoffset_h_common(const disasm_interfac
} else {
PRINTF("%s\t%s, [%s,%s,%s #%u]\n",
op,
- ZREGNAME(0, Rt),
+ ZREGNAME(RtSz, Rt),
SREGNAME(1, Rn),
ZREGNAME(r, Rm),
SHIFTOP8(option,
@@ -2030,7 +2030,7 @@ OP3FUNC(op_ldrh_immunsign, imm12, Rn, Rt
OP5FUNC(op_ldrh_reg, Rm, option, shift, Rn, Rt)
{
- regoffset_h_common(di, pc, insn, Rm, option, shift, Rn, Rt, "ldrh");
+ regoffset_h_common(di, pc, insn, Rm, option, shift, Rn, Rt, 0, "ldrh");
}
OP4FUNC(op_ldrsb_immpostidx, opc, imm9, Rn, Rt)
@@ -2100,7 +2100,8 @@ OP4FUNC(op_ldrsh_immunsign, opc, imm12,
OP6FUNC(op_ldrsh_reg, opc, Rm, option, shift, Rn, Rt)
{
- regoffset_h_common(di, pc, insn, Rm, option, shift, Rn, Rt, "ldrsh");
+ regoffset_h_common(di, pc, insn, Rm, option, shift, Rn, Rt, opc ^ 1,
+ "ldrsh");
}
OP3FUNC(op_ldrsw_immpostidx, imm9, Rn, Rt)
@@ -3016,7 +3017,7 @@ OP3FUNC(op_strh_immunsign, imm12, Rn, Rt
OP5FUNC(op_strh_reg, Rm, option, shift, Rn, Rt)
{
- regoffset_h_common(di, pc, insn, Rm, option, shift, Rn, Rt, "strh");
+ regoffset_h_common(di, pc, insn, Rm, option, shift, Rn, Rt, 0, "strh");
}
OP4FUNC(op_sttr, size, imm9, Rn, Rt)
CVS commit: src/sys/arch/aarch64/aarch64
Module Name:src
Committed By: ryo
Date: Tue Feb 23 20:15:04 UTC 2021
Modified Files:
src/sys/arch/aarch64/aarch64: disasm.c
Log Message:
make more system registers are disassemblable
To generate a diff of this commit:
cvs rdiff -u -r1.12 -r1.13 src/sys/arch/aarch64/aarch64/disasm.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/aarch64/aarch64/disasm.c
diff -u src/sys/arch/aarch64/aarch64/disasm.c:1.12 src/sys/arch/aarch64/aarch64/disasm.c:1.13
--- src/sys/arch/aarch64/aarch64/disasm.c:1.12 Tue Feb 23 17:48:46 2021
+++ src/sys/arch/aarch64/aarch64/disasm.c Tue Feb 23 20:15:04 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: disasm.c,v 1.12 2021/02/23 17:48:46 ryo Exp $ */
+/* $NetBSD: disasm.c,v 1.13 2021/02/23 20:15:04 ryo Exp $ */
/*
* Copyright (c) 2018 Ryo Shimizu
@@ -27,7 +27,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: disasm.c,v 1.12 2021/02/23 17:48:46 ryo Exp $");
+__KERNEL_RCSID(0, "$NetBSD: disasm.c,v 1.13 2021/02/23 20:15:04 ryo Exp $");
#include
#include
@@ -323,9 +323,14 @@ const struct sysreg_table sysreg_table[]
{ SYSREG_ENC(3, 0, 0, 2, 3), "id_isar3_el1" },
{ SYSREG_ENC(3, 0, 0, 2, 4), "id_isar4_el1" },
{ SYSREG_ENC(3, 0, 0, 2, 5), "id_isar5_el1" },
+ { SYSREG_ENC(3, 0, 0, 2, 6), "id_mmfr4_el1" },
+ { SYSREG_ENC(3, 0, 0, 2, 7), "id_isar6_el1" },
{ SYSREG_ENC(3, 0, 0, 3, 0), "mvfr0_el1" },
{ SYSREG_ENC(3, 0, 0, 3, 1), "mvfr1_el1" },
{ SYSREG_ENC(3, 0, 0, 3, 2), "mvfr2_el1" },
+ { SYSREG_ENC(3, 0, 0, 3, 4), "id_pfr2_el1" },
+ { SYSREG_ENC(3, 0, 0, 3, 5), "id_dfr1_el1" },
+ { SYSREG_ENC(3, 0, 0, 3, 6), "id_mmfr5_el1" },
{ SYSREG_ENC(3, 0, 0, 4, 0), "id_aa64pfr0_el1" },
{ SYSREG_ENC(3, 0, 0, 4, 1), "id_aa64pfr1_el1" },
{ SYSREG_ENC(3, 0, 0, 5, 0), "id_aa64dfr0_el1" },
@@ -336,9 +341,12 @@ const struct sysreg_table sysreg_table[]
{ SYSREG_ENC(3, 0, 0, 6, 1), "id_aa64isar1_el1" },
{ SYSREG_ENC(3, 0, 0, 7, 0), "id_aa64mmfr0_el1" },
{ SYSREG_ENC(3, 0, 0, 7, 1), "id_aa64mmfr1_el1" },
+ { SYSREG_ENC(3, 0, 0, 7, 2), "id_aa64mmfr2_el1" },
{ SYSREG_ENC(3, 0, 1, 0, 0), "sctlr_el1" },
{ SYSREG_ENC(3, 0, 1, 0, 1), "actlr_el1" },
{ SYSREG_ENC(3, 0, 1, 0, 2), "cpacr_el1" },
+ { SYSREG_ENC(3, 0, 1, 0, 5), "rgsr_el1" },
+ { SYSREG_ENC(3, 0, 1, 0, 6), "gcr_el1" },
{ SYSREG_ENC(3, 0, 2, 0, 0), "ttbr0_el1" },
{ SYSREG_ENC(3, 0, 2, 0, 1), "ttbr1_el1" },
{ SYSREG_ENC(3, 0, 2, 0, 2), "tcr_el1" },
@@ -362,21 +370,31 @@ const struct sysreg_table sysreg_table[]
{ SYSREG_ENC(3, 0, 5, 1, 0), "afsr0_el1" },
{ SYSREG_ENC(3, 0, 5, 1, 1), "afsr1_el1" },
{ SYSREG_ENC(3, 0, 5, 2, 0), "esr_el1" },
+ { SYSREG_ENC(3, 0, 5, 6, 0), "tfsr_el1" },
+ { SYSREG_ENC(3, 0, 5, 6, 1), "tfsre0_el1" },
{ SYSREG_ENC(3, 0, 6, 0, 0), "far_el1" },
{ SYSREG_ENC(3, 0, 7, 4, 0), "par_el1" },
{ SYSREG_ENC(3, 0, 9, 14, 1), "pmintenset_el1" },
{ SYSREG_ENC(3, 0, 9, 14, 2), "pmintenclr_el1" },
{ SYSREG_ENC(3, 0, 10, 2, 0), "mair_el1" },
{ SYSREG_ENC(3, 0, 10, 3, 0), "amair_el1" },
+ { SYSREG_ENC(3, 0, 10, 4, 0), "lorsa_el1" },
+ { SYSREG_ENC(3, 0, 10, 4, 1), "lorea_el1" },
+ { SYSREG_ENC(3, 0, 10, 4, 2), "lorn_el1" },
+ { SYSREG_ENC(3, 0, 10, 4, 3), "lorc_el1" },
+ { SYSREG_ENC(3, 0, 10, 4, 7), "lorid_el1" },
{ SYSREG_ENC(3, 0, 12, 0, 0), "vbar_el1" },
{ SYSREG_ENC(3, 0, 12, 0, 1), "rvbar_el1" },
{ SYSREG_ENC(3, 0, 12, 0, 2), "rmr_el1" },
{ SYSREG_ENC(3, 0, 12, 1, 0), "isr_el1" },
{ SYSREG_ENC(3, 0, 13, 0, 1), "contextidr_el1" },
{ SYSREG_ENC(3, 0, 13, 0, 4), "tpidr_el1" },
+ { SYSREG_ENC(3, 0, 13, 0, 7), "scxtnum_el1" },
{ SYSREG_ENC(3, 0, 14, 1, 0), "cntkctl_el1" },
{ SYSREG_ENC(3, 1, 0, 0, 0), "ccsidr_el1" },
{ SYSREG_ENC(3, 1, 0, 0, 1), "clidr_el1" },
+ { SYSREG_ENC(3, 1, 0, 0, 2), "ccsidr2_el1" },
+ { SYSREG_ENC(3, 1, 0, 0, 4), "gmid_el1" },
{ SYSREG_ENC(3, 1, 0, 0, 7), "aidr_el1" },
{ SYSREG_ENC(3, 2, 0, 0, 0), "csselr_el1" },
{ SYSREG_ENC(3, 3, 0, 0, 1), "ctr_el0" },
@@ -407,6 +425,7 @@ const struct sysreg_table sysreg_table[]
{ SYSREG_ENC(3, 3, 9, 14, 3), "pmovsset_el0" },
{ SYSREG_ENC(3, 3, 13, 0, 2), "tpidr_el0" },
{ SYSREG_ENC(3, 3, 13, 0, 3), "tpidrro_el0" },
+ { SYSREG_ENC(3, 3, 13, 0, 7), "scxtnum_el0" },
{ SYSREG_ENC(3, 3, 14, 0, 0), "cntfrq_el0" },
{ SYSREG_ENC(3, 3, 14, 0, 1), "cntpct_el0" },
{ SYSREG_ENC(3, 3, 14, 0, 2), "cntvct_el0" },
@@ -487,12 +506,22 @@ const struct sysreg_table sysreg_table[]
{ SYSREG_ENC(3, 4, 1, 1, 1), "mdcr_el2" },
{ SYSREG_ENC(3, 4, 1, 1, 2), "cptr_el2" },
{ SYSREG_ENC(3, 4, 1, 1, 3), "hstr_el2" },
+ { SYSREG_ENC(3, 4, 1, 1, 4), "hfgrtr_el2" },
+ { SYSREG_ENC(3, 4, 1, 1, 5), "hfgwtr_el2" },
+ { SYSREG_ENC(3, 4, 1, 1, 6), "hfgitr_el2" },
{ SYSREG_ENC(3, 4, 1, 1, 7), "hacr_el2"
CVS commit: src/sys/arch/aarch64/aarch64
Module Name:src
Committed By: ryo
Date: Tue Feb 23 17:48:46 UTC 2021
Modified Files:
src/sys/arch/aarch64/aarch64: disasm.c
Log Message:
The immediate offset of "ldtrb", "ldtrh", "sttrb", and "sttrh" was always
output as unsigned.
Correctly, it is 9bit signed.
To generate a diff of this commit:
cvs rdiff -u -r1.11 -r1.12 src/sys/arch/aarch64/aarch64/disasm.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/aarch64/aarch64/disasm.c
diff -u src/sys/arch/aarch64/aarch64/disasm.c:1.11 src/sys/arch/aarch64/aarch64/disasm.c:1.12
--- src/sys/arch/aarch64/aarch64/disasm.c:1.11 Tue Feb 23 17:30:56 2021
+++ src/sys/arch/aarch64/aarch64/disasm.c Tue Feb 23 17:48:46 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: disasm.c,v 1.11 2021/02/23 17:30:56 ryo Exp $ */
+/* $NetBSD: disasm.c,v 1.12 2021/02/23 17:48:46 ryo Exp $ */
/*
* Copyright (c) 2018 Ryo Shimizu
@@ -27,7 +27,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: disasm.c,v 1.11 2021/02/23 17:30:56 ryo Exp $");
+__KERNEL_RCSID(0, "$NetBSD: disasm.c,v 1.12 2021/02/23 17:48:46 ryo Exp $");
#include
#include
@@ -2126,7 +2126,7 @@ OP3FUNC(op_ldtrb, imm9, Rn, Rt)
PRINTF("ldtrb\t%s, [%s,#%"PRId64"]\n",
ZREGNAME(0, Rt),
SREGNAME(1, Rn),
- SignExtend(12, imm9, 1));
+ SignExtend(9, imm9, 1));
}
}
@@ -2140,7 +2140,7 @@ OP3FUNC(op_ldtrh, imm9, Rn, Rt)
PRINTF("ldtrh\t%s, [%s,#%"PRId64"]\n",
ZREGNAME(0, Rt),
SREGNAME(1, Rn),
- SignExtend(12, imm9, 1));
+ SignExtend(9, imm9, 1));
}
}
@@ -3000,7 +3000,7 @@ OP3FUNC(op_sttrb, imm9, Rn, Rt)
PRINTF("sttrb\t%s, [%s,#%"PRId64"]\n",
ZREGNAME(0, Rt),
SREGNAME(1, Rn),
- SignExtend(12, imm9, 1));
+ SignExtend(9, imm9, 1));
}
}
@@ -3014,7 +3014,7 @@ OP3FUNC(op_sttrh, imm9, Rn, Rt)
PRINTF("sttrh\t%s, [%s,#%"PRId64"]\n",
ZREGNAME(0, Rt),
SREGNAME(1, Rn),
- SignExtend(12, imm9, 1));
+ SignExtend(9, imm9, 1));
}
}
CVS commit: src/sys/arch/aarch64/aarch64
Module Name:src
Committed By: ryo
Date: Tue Feb 23 17:30:56 UTC 2021
Modified Files:
src/sys/arch/aarch64/aarch64: disasm.c
Log Message:
The register operand size for "smnegl" and "smsubl' was wrong.
not "smsubl Xd, Xn, Xm, Xa", but "smsubl Xd, Wn, Wm, Xa".
To generate a diff of this commit:
cvs rdiff -u -r1.10 -r1.11 src/sys/arch/aarch64/aarch64/disasm.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/aarch64/aarch64/disasm.c
diff -u src/sys/arch/aarch64/aarch64/disasm.c:1.10 src/sys/arch/aarch64/aarch64/disasm.c:1.11
--- src/sys/arch/aarch64/aarch64/disasm.c:1.10 Sat Sep 5 15:59:09 2020
+++ src/sys/arch/aarch64/aarch64/disasm.c Tue Feb 23 17:30:56 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: disasm.c,v 1.10 2020/09/05 15:59:09 jakllsch Exp $ */
+/* $NetBSD: disasm.c,v 1.11 2021/02/23 17:30:56 ryo Exp $ */
/*
* Copyright (c) 2018 Ryo Shimizu
@@ -27,7 +27,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: disasm.c,v 1.10 2020/09/05 15:59:09 jakllsch Exp $");
+__KERNEL_RCSID(0, "$NetBSD: disasm.c,v 1.11 2021/02/23 17:30:56 ryo Exp $");
#include
#include
@@ -2751,13 +2751,13 @@ OP4FUNC(op_smsubl, Rm, Ra, Rn, Rd)
if (Ra == 31) {
PRINTF("smnegl\t%s, %s, %s\n",
ZREGNAME(1, Rd),
- ZREGNAME(1, Rn),
- ZREGNAME(1, Rm));
+ ZREGNAME(0, Rn),
+ ZREGNAME(0, Rm));
} else {
PRINTF("smsubl\t%s, %s, %s, %s\n",
ZREGNAME(1, Rd),
- ZREGNAME(1, Rn),
- ZREGNAME(1, Rm),
+ ZREGNAME(0, Rn),
+ ZREGNAME(0, Rm),
ZREGNAME(1, Ra));
}
}
CVS commit: src/sys/arch/aarch64/aarch64
Module Name:src
Committed By: ryo
Date: Tue Feb 23 14:50:33 UTC 2021
Modified Files:
src/sys/arch/aarch64/aarch64: idle_machdep.S
Log Message:
Just a few optimizations.
- in cpu_idle(), ci_intr_depth is always 0, so there is no need to fetch for
increment or conditional branch.
- curcpu() is immutable in idle lwp, there is no need to consider KPREEMPT.
Therefore, get curcpu() first and keep using it.
- add more comment.
To generate a diff of this commit:
cvs rdiff -u -r1.8 -r1.9 src/sys/arch/aarch64/aarch64/idle_machdep.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/aarch64/aarch64/idle_machdep.S
diff -u src/sys/arch/aarch64/aarch64/idle_machdep.S:1.8 src/sys/arch/aarch64/aarch64/idle_machdep.S:1.9
--- src/sys/arch/aarch64/aarch64/idle_machdep.S:1.8 Sun Feb 21 23:37:09 2021
+++ src/sys/arch/aarch64/aarch64/idle_machdep.S Tue Feb 23 14:50:33 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: idle_machdep.S,v 1.8 2021/02/21 23:37:09 jmcneill Exp $ */
+/* $NetBSD: idle_machdep.S,v 1.9 2021/02/23 14:50:33 ryo Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -36,7 +36,7 @@
#include
#include "assym.h"
-RCSID("$NetBSD: idle_machdep.S,v 1.8 2021/02/21 23:37:09 jmcneill Exp $");
+RCSID("$NetBSD: idle_machdep.S,v 1.9 2021/02/23 14:50:33 ryo Exp $");
#ifdef ARM_INTR_IMPL
#include ARM_INTR_IMPL
@@ -75,28 +75,34 @@ ENTRY(cpu_idle)
adr x0, 1f
str x0, [sp, #TF_PC] /* CLKF_PC refer to tf_pc */
+ /*
+ * "idle/N" lwp is allocated on a per-CPU basis,
+ * curcpu() always return the same, and there is no need to
+ * consider KPREEMPT. safe even with interrupt enabled.
+ */
mrs x1, tpidr_el1 /* get curlwp */
- ldr x1, [x1, #L_CPU] /* get curcpu */
- ldr w28, [x1, #CI_INTR_DEPTH] /* w28 = ci->ci_intr_depth */
- add w2, w28, #1 /* w2 = intr_depth + 1 */
+ ldr x28, [x1, #L_CPU] /* get curcpu */
+ mov w2, #1
mov x0, sp/* get pointer to trapframe */
DISABLE_INTERRUPT
- wfi
+ /*
+ * assert(ci->ci_intr_depth == 0),
+ * therefore, ci->ci_intr_depth++ would be definitely 1.
+ */
+ str w2, [x28, #CI_INTR_DEPTH] /* ci->ci_intr_depth = 1 */
- str w2, [x1, #CI_INTR_DEPTH] /* ci->ci_intr_depth++ */
+ wfi
bl ARM_IRQ_HANDLER /* irqhandler(trapframe) */
1:
- mrs x1, tpidr_el1 /* get curlwp */
- ldr x1, [x1, #L_CPU] /* get curcpu */
- str w28, [x1, #CI_INTR_DEPTH] /* ci->ci_intr_depth = old */
+ /* x28 is curcpu() */
+ str wzr, [x28, #CI_INTR_DEPTH] /* ci->ci_intr_depth = 0 */
#if defined(__HAVE_FAST_SOFTINTS) && !defined(__HAVE_PIC_FAST_SOFTINTS)
- cbnz w28, 1f/* Skip if intr_depth > 0 */
- ldr w3, [x1, #CI_SOFTINTS] /* Get pending softint mask */
+ ldr w3, [x28, #CI_SOFTINTS] /* Get pending softint mask */
/* CPL should be 0 */
- ldr w2, [x1, #CI_CPL] /* Get current priority level */
+ ldr w2, [x28, #CI_CPL] /* Get current priority level */
lsr w3, w3, w2 /* shift mask by cpl */
cbz w3, 1f
bl _C_LABEL(dosoftints) /* dosoftints() */
CVS commit: src/sys/arch/aarch64/aarch64
Module Name:src Committed By: jmcneill Date: Mon Feb 22 02:18:33 UTC 2021 Modified Files: src/sys/arch/aarch64/aarch64: trap.c Log Message: KNF To generate a diff of this commit: cvs rdiff -u -r1.43 -r1.44 src/sys/arch/aarch64/aarch64/trap.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/aarch64/aarch64/trap.c diff -u src/sys/arch/aarch64/aarch64/trap.c:1.43 src/sys/arch/aarch64/aarch64/trap.c:1.44 --- src/sys/arch/aarch64/aarch64/trap.c:1.43 Thu Feb 18 11:23:15 2021 +++ src/sys/arch/aarch64/aarch64/trap.c Mon Feb 22 02:18:33 2021 @@ -1,4 +1,4 @@ -/* $NetBSD: trap.c,v 1.43 2021/02/18 11:23:15 jmcneill Exp $ */ +/* $NetBSD: trap.c,v 1.44 2021/02/22 02:18:33 jmcneill Exp $ */ /*- * Copyright (c) 2014 The NetBSD Foundation, Inc. @@ -31,7 +31,7 @@ #include -__KERNEL_RCSID(1, "$NetBSD: trap.c,v 1.43 2021/02/18 11:23:15 jmcneill Exp $"); +__KERNEL_RCSID(1, "$NetBSD: trap.c,v 1.44 2021/02/22 02:18:33 jmcneill Exp $"); #include "opt_arm_intr_impl.h" #include "opt_compat_netbsd32.h" @@ -919,7 +919,8 @@ sigdebug(const struct trapframe *tf, con } #endif -void do_trapsignal1( +void +do_trapsignal1( #ifdef TRAP_SIGDEBUG const char *func, size_t line,
CVS commit: src/sys/arch/aarch64/aarch64
Module Name:src
Committed By: jmcneill
Date: Sun Feb 21 23:37:10 UTC 2021
Modified Files:
src/sys/arch/aarch64/aarch64: idle_machdep.S
Log Message:
When waking from cpu_idle(), only call dosoftints if ci_intr_depth == 0
To generate a diff of this commit:
cvs rdiff -u -r1.7 -r1.8 src/sys/arch/aarch64/aarch64/idle_machdep.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/aarch64/aarch64/idle_machdep.S
diff -u src/sys/arch/aarch64/aarch64/idle_machdep.S:1.7 src/sys/arch/aarch64/aarch64/idle_machdep.S:1.8
--- src/sys/arch/aarch64/aarch64/idle_machdep.S:1.7 Thu Feb 11 08:35:12 2021
+++ src/sys/arch/aarch64/aarch64/idle_machdep.S Sun Feb 21 23:37:09 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: idle_machdep.S,v 1.7 2021/02/11 08:35:12 ryo Exp $ */
+/* $NetBSD: idle_machdep.S,v 1.8 2021/02/21 23:37:09 jmcneill Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -36,7 +36,7 @@
#include
#include "assym.h"
-RCSID("$NetBSD: idle_machdep.S,v 1.7 2021/02/11 08:35:12 ryo Exp $");
+RCSID("$NetBSD: idle_machdep.S,v 1.8 2021/02/21 23:37:09 jmcneill Exp $");
#ifdef ARM_INTR_IMPL
#include ARM_INTR_IMPL
@@ -93,6 +93,7 @@ ENTRY(cpu_idle)
str w28, [x1, #CI_INTR_DEPTH] /* ci->ci_intr_depth = old */
#if defined(__HAVE_FAST_SOFTINTS) && !defined(__HAVE_PIC_FAST_SOFTINTS)
+ cbnz w28, 1f/* Skip if intr_depth > 0 */
ldr w3, [x1, #CI_SOFTINTS] /* Get pending softint mask */
/* CPL should be 0 */
ldr w2, [x1, #CI_CPL] /* Get current priority level */
CVS commit: src/sys/arch/aarch64/aarch64
Module Name:src
Committed By: jmcneill
Date: Thu Feb 18 11:23:15 UTC 2021
Modified Files:
src/sys/arch/aarch64/aarch64: trap.c
Log Message:
revert previous; user reports of panics under load
To generate a diff of this commit:
cvs rdiff -u -r1.42 -r1.43 src/sys/arch/aarch64/aarch64/trap.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/aarch64/aarch64/trap.c
diff -u src/sys/arch/aarch64/aarch64/trap.c:1.42 src/sys/arch/aarch64/aarch64/trap.c:1.43
--- src/sys/arch/aarch64/aarch64/trap.c:1.42 Mon Feb 15 17:46:36 2021
+++ src/sys/arch/aarch64/aarch64/trap.c Thu Feb 18 11:23:15 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: trap.c,v 1.42 2021/02/15 17:46:36 jmcneill Exp $ */
+/* $NetBSD: trap.c,v 1.43 2021/02/18 11:23:15 jmcneill Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -31,7 +31,7 @@
#include
-__KERNEL_RCSID(1, "$NetBSD: trap.c,v 1.42 2021/02/15 17:46:36 jmcneill Exp $");
+__KERNEL_RCSID(1, "$NetBSD: trap.c,v 1.43 2021/02/18 11:23:15 jmcneill Exp $");
#include "opt_arm_intr_impl.h"
#include "opt_compat_netbsd32.h"
@@ -521,10 +521,7 @@ interrupt(struct trapframe *tf)
ARM_IRQ_HANDLER(tf);
ci->ci_intr_depth--;
- if (ci->ci_intr_depth == 0 && (ci->ci_softints >> ci->ci_cpl) > 0) {
- ENABLE_INTERRUPT();
- cpu_dosoftints();
- }
+ cpu_dosoftints();
}
#ifdef COMPAT_NETBSD32
CVS commit: src/sys/arch/aarch64/aarch64
Module Name:src
Committed By: jmcneill
Date: Mon Feb 15 17:46:36 UTC 2021
Modified Files:
src/sys/arch/aarch64/aarch64: trap.c
Log Message:
interrupt: enable interrupts before running soft intr handlers. To avoid
stack usage going out of control, only do this at ci_intr_depth==0.
To generate a diff of this commit:
cvs rdiff -u -r1.41 -r1.42 src/sys/arch/aarch64/aarch64/trap.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/aarch64/aarch64/trap.c
diff -u src/sys/arch/aarch64/aarch64/trap.c:1.41 src/sys/arch/aarch64/aarch64/trap.c:1.42
--- src/sys/arch/aarch64/aarch64/trap.c:1.41 Fri Dec 11 18:03:33 2020
+++ src/sys/arch/aarch64/aarch64/trap.c Mon Feb 15 17:46:36 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: trap.c,v 1.41 2020/12/11 18:03:33 skrll Exp $ */
+/* $NetBSD: trap.c,v 1.42 2021/02/15 17:46:36 jmcneill Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -31,7 +31,7 @@
#include
-__KERNEL_RCSID(1, "$NetBSD: trap.c,v 1.41 2020/12/11 18:03:33 skrll Exp $");
+__KERNEL_RCSID(1, "$NetBSD: trap.c,v 1.42 2021/02/15 17:46:36 jmcneill Exp $");
#include "opt_arm_intr_impl.h"
#include "opt_compat_netbsd32.h"
@@ -521,7 +521,10 @@ interrupt(struct trapframe *tf)
ARM_IRQ_HANDLER(tf);
ci->ci_intr_depth--;
- cpu_dosoftints();
+ if (ci->ci_intr_depth == 0 && (ci->ci_softints >> ci->ci_cpl) > 0) {
+ ENABLE_INTERRUPT();
+ cpu_dosoftints();
+ }
}
#ifdef COMPAT_NETBSD32
CVS commit: src/sys/arch/aarch64/aarch64
Module Name:src
Committed By: ryo
Date: Sat Feb 13 18:13:54 UTC 2021
Modified Files:
src/sys/arch/aarch64/aarch64: pmap.c
Log Message:
No assignment is needed here.
the loop in pmap_page_remove() always removes the first pv,
and since the list is managed by _pmap_remove_pv(), pp->pp_pv.pv_next always
points to the first.
To generate a diff of this commit:
cvs rdiff -u -r1.101 -r1.102 src/sys/arch/aarch64/aarch64/pmap.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/aarch64/aarch64/pmap.c
diff -u src/sys/arch/aarch64/aarch64/pmap.c:1.101 src/sys/arch/aarch64/aarch64/pmap.c:1.102
--- src/sys/arch/aarch64/aarch64/pmap.c:1.101 Mon Feb 1 18:12:11 2021
+++ src/sys/arch/aarch64/aarch64/pmap.c Sat Feb 13 18:13:53 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: pmap.c,v 1.101 2021/02/01 18:12:11 ryo Exp $ */
+/* $NetBSD: pmap.c,v 1.102 2021/02/13 18:13:53 ryo Exp $ */
/*
* Copyright (c) 2017 Ryo Shimizu
@@ -27,7 +27,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.101 2021/02/01 18:12:11 ryo Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.102 2021/02/13 18:13:53 ryo Exp $");
#include "opt_arm_debug.h"
#include "opt_ddb.h"
@@ -2237,7 +2237,7 @@ pmap_page_remove(struct pmap_page *pp, v
KASSERT(pv == >pp_pv);
} else {
KASSERT(pv == pvtmp);
- pp->pp_pv.pv_next = pv->pv_next;
+ KASSERT(pp->pp_pv.pv_next == pv->pv_next);
pv->pv_next = pvtofree;
pvtofree = pv;
}
CVS commit: src/sys/arch/aarch64/aarch64
Module Name:src
Committed By: ryo
Date: Thu Feb 11 08:35:12 UTC 2021
Modified Files:
src/sys/arch/aarch64/aarch64: copyinout.S cpufunc_asm_armv8.S fusu.S
idle_machdep.S lock_stubs.S pmap_page.S
Log Message:
include "opt_gprof.h" so that _PROF_PROLOGUE works properly in ENTRY() macro in
*.S files
To generate a diff of this commit:
cvs rdiff -u -r1.15 -r1.16 src/sys/arch/aarch64/aarch64/copyinout.S
cvs rdiff -u -r1.7 -r1.8 src/sys/arch/aarch64/aarch64/cpufunc_asm_armv8.S
cvs rdiff -u -r1.10 -r1.11 src/sys/arch/aarch64/aarch64/fusu.S
cvs rdiff -u -r1.6 -r1.7 src/sys/arch/aarch64/aarch64/idle_machdep.S
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/aarch64/aarch64/lock_stubs.S
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/aarch64/aarch64/pmap_page.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/aarch64/aarch64/copyinout.S
diff -u src/sys/arch/aarch64/aarch64/copyinout.S:1.15 src/sys/arch/aarch64/aarch64/copyinout.S:1.16
--- src/sys/arch/aarch64/aarch64/copyinout.S:1.15 Wed Aug 12 13:19:35 2020
+++ src/sys/arch/aarch64/aarch64/copyinout.S Thu Feb 11 08:35:11 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: copyinout.S,v 1.15 2020/08/12 13:19:35 skrll Exp $ */
+/* $NetBSD: copyinout.S,v 1.16 2021/02/11 08:35:11 ryo Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -29,11 +29,12 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
+#include "opt_gprof.h"
#include
#include
#include "assym.h"
-RCSID("$NetBSD: copyinout.S,v 1.15 2020/08/12 13:19:35 skrll Exp $");
+RCSID("$NetBSD: copyinout.S,v 1.16 2021/02/11 08:35:11 ryo Exp $");
#ifdef ARMV81_PAN
#define PAN_ENABLE \
Index: src/sys/arch/aarch64/aarch64/cpufunc_asm_armv8.S
diff -u src/sys/arch/aarch64/aarch64/cpufunc_asm_armv8.S:1.7 src/sys/arch/aarch64/aarch64/cpufunc_asm_armv8.S:1.8
--- src/sys/arch/aarch64/aarch64/cpufunc_asm_armv8.S:1.7 Sun Jul 19 07:18:07 2020
+++ src/sys/arch/aarch64/aarch64/cpufunc_asm_armv8.S Thu Feb 11 08:35:11 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: cpufunc_asm_armv8.S,v 1.7 2020/07/19 07:18:07 ryo Exp $ */
+/* $NetBSD: cpufunc_asm_armv8.S,v 1.8 2021/02/11 08:35:11 ryo Exp $ */
/*-
* Copyright (c) 2014 Robin Randhawa
@@ -33,6 +33,7 @@
*/
#include "opt_cputypes.h"
+#include "opt_gprof.h"
#include "opt_multiprocessor.h"
#include
Index: src/sys/arch/aarch64/aarch64/fusu.S
diff -u src/sys/arch/aarch64/aarch64/fusu.S:1.10 src/sys/arch/aarch64/aarch64/fusu.S:1.11
--- src/sys/arch/aarch64/aarch64/fusu.S:1.10 Wed Aug 12 13:19:35 2020
+++ src/sys/arch/aarch64/aarch64/fusu.S Thu Feb 11 08:35:11 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: fusu.S,v 1.10 2020/08/12 13:19:35 skrll Exp $ */
+/* $NetBSD: fusu.S,v 1.11 2021/02/11 08:35:11 ryo Exp $ */
/*-
* Copyright (c) 2014, 2019 The NetBSD Foundation, Inc.
@@ -29,10 +29,11 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
+#include "opt_gprof.h"
#include
#include "assym.h"
-RCSID("$NetBSD: fusu.S,v 1.10 2020/08/12 13:19:35 skrll Exp $");
+RCSID("$NetBSD: fusu.S,v 1.11 2021/02/11 08:35:11 ryo Exp $");
#ifdef ARMV81_PAN
#define PAN_ENABLE \
Index: src/sys/arch/aarch64/aarch64/idle_machdep.S
diff -u src/sys/arch/aarch64/aarch64/idle_machdep.S:1.6 src/sys/arch/aarch64/aarch64/idle_machdep.S:1.7
--- src/sys/arch/aarch64/aarch64/idle_machdep.S:1.6 Wed Aug 12 13:19:35 2020
+++ src/sys/arch/aarch64/aarch64/idle_machdep.S Thu Feb 11 08:35:12 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: idle_machdep.S,v 1.6 2020/08/12 13:19:35 skrll Exp $ */
+/* $NetBSD: idle_machdep.S,v 1.7 2021/02/11 08:35:12 ryo Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -29,13 +29,14 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
+#include "opt_arm_intr_impl.h"
+#include "opt_ddb.h"
+#include "opt_gprof.h"
#include
#include
#include "assym.h"
-#include "opt_arm_intr_impl.h"
-#include "opt_ddb.h"
-RCSID("$NetBSD: idle_machdep.S,v 1.6 2020/08/12 13:19:35 skrll Exp $");
+RCSID("$NetBSD: idle_machdep.S,v 1.7 2021/02/11 08:35:12 ryo Exp $");
#ifdef ARM_INTR_IMPL
#include ARM_INTR_IMPL
Index: src/sys/arch/aarch64/aarch64/lock_stubs.S
diff -u src/sys/arch/aarch64/aarch64/lock_stubs.S:1.3 src/sys/arch/aarch64/aarch64/lock_stubs.S:1.4
--- src/sys/arch/aarch64/aarch64/lock_stubs.S:1.3 Tue Oct 13 21:27:18 2020
+++ src/sys/arch/aarch64/aarch64/lock_stubs.S Thu Feb 11 08:35:12 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: lock_stubs.S,v 1.3 2020/10/13 21:27:18 skrll Exp $ */
+/* $NetBSD: lock_stubs.S,v 1.4 2021/02/11 08:35:12 ryo Exp $ */
/*-
* Copyright (c) 2014, 2020 The NetBSD Foundation, Inc.
@@ -29,13 +29,14 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
+#include "opt_gprof.h"
#include "opt_lockdebug.h"
#include
#include "assym.h"
-RCSID("$NetBSD: lock_stubs.S,v 1.3 2020/10/13 21:27:18 skrll Exp $")
+RCSID("$NetBSD: lock_stubs.S,v 1.4 2021/02/11 08:35:12 ryo Exp $")
#ifndef LOCKDEBUG
/*
Index: src/sys/arch/aarch64/aarch64/pmap_page.S
diff -u
CVS commit: src/sys/arch/aarch64/aarch64
Module Name:src
Committed By: joerg
Date: Fri Feb 5 21:44:34 UTC 2021
Modified Files:
src/sys/arch/aarch64/aarch64: db_interface.c db_machdep.c
Log Message:
Avoid duplicate definition of ddb_regs in crash(8).
To generate a diff of this commit:
cvs rdiff -u -r1.11 -r1.12 src/sys/arch/aarch64/aarch64/db_interface.c
cvs rdiff -u -r1.32 -r1.33 src/sys/arch/aarch64/aarch64/db_machdep.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/aarch64/aarch64/db_interface.c
diff -u src/sys/arch/aarch64/aarch64/db_interface.c:1.11 src/sys/arch/aarch64/aarch64/db_interface.c:1.12
--- src/sys/arch/aarch64/aarch64/db_interface.c:1.11 Fri Dec 11 18:03:33 2020
+++ src/sys/arch/aarch64/aarch64/db_interface.c Fri Feb 5 21:44:34 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: db_interface.c,v 1.11 2020/12/11 18:03:33 skrll Exp $ */
+/* $NetBSD: db_interface.c,v 1.12 2021/02/05 21:44:34 joerg Exp $ */
/*
* Copyright (c) 2017 Ryo Shimizu
@@ -27,7 +27,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: db_interface.c,v 1.11 2020/12/11 18:03:33 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: db_interface.c,v 1.12 2021/02/05 21:44:34 joerg Exp $");
#include
#include
@@ -51,6 +51,8 @@ __KERNEL_RCSID(0, "$NetBSD: db_interface
#include
+db_regs_t ddb_regs;
+
void
db_read_bytes(vaddr_t addr, size_t size, char *data)
{
Index: src/sys/arch/aarch64/aarch64/db_machdep.c
diff -u src/sys/arch/aarch64/aarch64/db_machdep.c:1.32 src/sys/arch/aarch64/aarch64/db_machdep.c:1.33
--- src/sys/arch/aarch64/aarch64/db_machdep.c:1.32 Mon Jan 18 01:38:44 2021
+++ src/sys/arch/aarch64/aarch64/db_machdep.c Fri Feb 5 21:44:34 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: db_machdep.c,v 1.32 2021/01/18 01:38:44 rin Exp $ */
+/* $NetBSD: db_machdep.c,v 1.33 2021/02/05 21:44:34 joerg Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: db_machdep.c,v 1.32 2021/01/18 01:38:44 rin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: db_machdep.c,v 1.33 2021/02/05 21:44:34 joerg Exp $");
#ifdef _KERNEL_OPT
#include "opt_compat_netbsd32.h"
@@ -207,9 +207,7 @@ const struct db_variable db_regs[] = {
};
const struct db_variable * const db_eregs = db_regs + __arraycount(db_regs);
-
int db_active;
-db_regs_t ddb_regs;
void
CVS commit: src/sys/arch/aarch64/aarch64
Module Name:src
Committed By: ryo
Date: Mon Feb 1 18:12:11 UTC 2021
Modified Files:
src/sys/arch/aarch64/aarch64: pmap.c
Log Message:
It is enough to make a page accessible instead of writable.
same fix as r1.76
To generate a diff of this commit:
cvs rdiff -u -r1.100 -r1.101 src/sys/arch/aarch64/aarch64/pmap.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/aarch64/aarch64/pmap.c
diff -u src/sys/arch/aarch64/aarch64/pmap.c:1.100 src/sys/arch/aarch64/aarch64/pmap.c:1.101
--- src/sys/arch/aarch64/aarch64/pmap.c:1.100 Sun Jan 31 04:51:29 2021
+++ src/sys/arch/aarch64/aarch64/pmap.c Mon Feb 1 18:12:11 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: pmap.c,v 1.100 2021/01/31 04:51:29 ryo Exp $ */
+/* $NetBSD: pmap.c,v 1.101 2021/02/01 18:12:11 ryo Exp $ */
/*
* Copyright (c) 2017 Ryo Shimizu
@@ -27,7 +27,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.100 2021/01/31 04:51:29 ryo Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.101 2021/02/01 18:12:11 ryo Exp $");
#include "opt_arm_debug.h"
#include "opt_ddb.h"
@@ -960,20 +960,17 @@ pmap_icache_sync_range(pmap_t pm, vaddr_
vaddr_t eob = (va + blocksize) & ~(blocksize - 1);
vsize_t len = ulmin(eva, eob) - va;
- if (l3pte_writable(pte)) {
+ if (l3pte_readable(pte)) {
cpu_icache_sync_range(va, len);
} else {
/*
- * change to writable temporally
+ * change to accessible temporally
* to do cpu_icache_sync_range()
*/
-pt_entry_t opte = pte;
-pte = pte & ~(LX_BLKPAG_AF|LX_BLKPAG_AP);
-pte |= (LX_BLKPAG_AF|LX_BLKPAG_AP_RW);
-atomic_swap_64(ptep, pte);
+atomic_swap_64(ptep, pte | LX_BLKPAG_AF);
AARCH64_TLBI_BY_ASID_VA(pm->pm_asid, va, true);
cpu_icache_sync_range(va, len);
-atomic_swap_64(ptep, opte);
+atomic_swap_64(ptep, pte);
AARCH64_TLBI_BY_ASID_VA(pm->pm_asid, va, true);
}
}
CVS commit: src/sys/arch/aarch64/aarch64
Module Name:src
Committed By: rin
Date: Mon Jan 18 01:38:44 UTC 2021
Modified Files:
src/sys/arch/aarch64/aarch64: db_machdep.c
Log Message:
Fix build as crash(8); Protect db_md_meminfo_cmd() by defined(_KERNEL).
To generate a diff of this commit:
cvs rdiff -u -r1.31 -r1.32 src/sys/arch/aarch64/aarch64/db_machdep.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/aarch64/aarch64/db_machdep.c
diff -u src/sys/arch/aarch64/aarch64/db_machdep.c:1.31 src/sys/arch/aarch64/aarch64/db_machdep.c:1.32
--- src/sys/arch/aarch64/aarch64/db_machdep.c:1.31 Sun Jan 17 00:23:59 2021
+++ src/sys/arch/aarch64/aarch64/db_machdep.c Mon Jan 18 01:38:44 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: db_machdep.c,v 1.31 2021/01/17 00:23:59 mrg Exp $ */
+/* $NetBSD: db_machdep.c,v 1.32 2021/01/18 01:38:44 rin Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: db_machdep.c,v 1.31 2021/01/17 00:23:59 mrg Exp $");
+__KERNEL_RCSID(0, "$NetBSD: db_machdep.c,v 1.32 2021/01/18 01:38:44 rin Exp $");
#ifdef _KERNEL_OPT
#include "opt_compat_netbsd32.h"
@@ -79,7 +79,9 @@ void db_md_watch_cmd(db_expr_t, bool, db
#if defined(_KERNEL) && defined(MULTIPROCESSOR)
void db_md_switch_cpu_cmd(db_expr_t, bool, db_expr_t, const char *);
#endif
+#if defined(_KERNEL)
static void db_md_meminfo_cmd(db_expr_t, bool, db_expr_t, const char *);
+#endif
const struct db_command db_machine_command_table[] = {
#if defined(_KERNEL) && defined(MULTIPROCESSOR)
@@ -1083,6 +1085,7 @@ kdb_trap(int type, struct trapframe *tf)
}
#endif
+#if defined(_KERNEL)
static void
db_md_meminfo_cmd(db_expr_t addr, bool have_addr, db_expr_t count,
const char *modif)
@@ -1097,3 +1100,4 @@ db_md_meminfo_cmd(db_expr_t addr, bool h
bootconfig.dram[blk].pages);
}
}
+#endif
CVS commit: src/sys/arch/aarch64/aarch64
Module Name:src
Committed By: mrg
Date: Sun Jan 17 00:23:59 UTC 2021
Modified Files:
src/sys/arch/aarch64/aarch64: db_machdep.c
Log Message:
add a command to dump the bootconfig passed meminfo.
To generate a diff of this commit:
cvs rdiff -u -r1.30 -r1.31 src/sys/arch/aarch64/aarch64/db_machdep.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/aarch64/aarch64/db_machdep.c
diff -u src/sys/arch/aarch64/aarch64/db_machdep.c:1.30 src/sys/arch/aarch64/aarch64/db_machdep.c:1.31
--- src/sys/arch/aarch64/aarch64/db_machdep.c:1.30 Fri Dec 11 18:03:33 2020
+++ src/sys/arch/aarch64/aarch64/db_machdep.c Sun Jan 17 00:23:59 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: db_machdep.c,v 1.30 2020/12/11 18:03:33 skrll Exp $ */
+/* $NetBSD: db_machdep.c,v 1.31 2021/01/17 00:23:59 mrg Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: db_machdep.c,v 1.30 2020/12/11 18:03:33 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: db_machdep.c,v 1.31 2021/01/17 00:23:59 mrg Exp $");
#ifdef _KERNEL_OPT
#include "opt_compat_netbsd32.h"
@@ -79,6 +79,7 @@ void db_md_watch_cmd(db_expr_t, bool, db
#if defined(_KERNEL) && defined(MULTIPROCESSOR)
void db_md_switch_cpu_cmd(db_expr_t, bool, db_expr_t, const char *);
#endif
+static void db_md_meminfo_cmd(db_expr_t, bool, db_expr_t, const char *);
const struct db_command db_machine_command_table[] = {
#if defined(_KERNEL) && defined(MULTIPROCESSOR)
@@ -152,6 +153,12 @@ const struct db_command db_machine_comma
"\t#: watchpoint number to remove"
"\t/1..8: size of data\n")
},
+ {
+ DDB_ADD_CMD(
+ "meminfo", db_md_meminfo_cmd, 0,
+ "Dump info about memory ranges",
+ NULL, NULL)
+ },
#endif
{
DDB_ADD_CMD(NULL, NULL, 0,
@@ -1075,3 +1082,18 @@ kdb_trap(int type, struct trapframe *tf)
return 1;
}
#endif
+
+static void
+db_md_meminfo_cmd(db_expr_t addr, bool have_addr, db_expr_t count,
+const char *modif)
+{
+ unsigned blk;
+
+ for (blk = 0; blk < bootconfig.dramblocks; blk++) {
+ db_printf("blk[%u]: start %lx end %lx (pages %x)\n",
+ blk, bootconfig.dram[blk].address,
+ bootconfig.dram[blk].address +
+ (uint64_t)bootconfig.dram[blk].pages * PAGE_SIZE,
+ bootconfig.dram[blk].pages);
+ }
+}
CVS commit: src/sys/arch/aarch64/aarch64
Module Name:src
Committed By: skrll
Date: Mon Jan 11 21:58:31 UTC 2021
Modified Files:
src/sys/arch/aarch64/aarch64: cpu.c
Log Message:
Improve a comment
To generate a diff of this commit:
cvs rdiff -u -r1.57 -r1.58 src/sys/arch/aarch64/aarch64/cpu.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/aarch64/aarch64/cpu.c
diff -u src/sys/arch/aarch64/aarch64/cpu.c:1.57 src/sys/arch/aarch64/aarch64/cpu.c:1.58
--- src/sys/arch/aarch64/aarch64/cpu.c:1.57 Fri Dec 11 18:03:33 2020
+++ src/sys/arch/aarch64/aarch64/cpu.c Mon Jan 11 21:58:31 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu.c,v 1.57 2020/12/11 18:03:33 skrll Exp $ */
+/* $NetBSD: cpu.c,v 1.58 2021/01/11 21:58:31 skrll Exp $ */
/*
* Copyright (c) 2017 Ryo Shimizu
@@ -27,7 +27,7 @@
*/
#include
-__KERNEL_RCSID(1, "$NetBSD: cpu.c,v 1.57 2020/12/11 18:03:33 skrll Exp $");
+__KERNEL_RCSID(1, "$NetBSD: cpu.c,v 1.58 2021/01/11 21:58:31 skrll Exp $");
#include "locators.h"
#include "opt_arm_debug.h"
@@ -86,8 +86,8 @@ static void cpu_setup_chacha(device_t, s
#endif /* MULTIPROCESSOR */
/*
- * Our exported CPU info;
- * these will be refered from secondary cpus in the middle of hatching.
+ * Our exported cpu_info structs; these will be first used by the
+ * secondary cpus as part of cpu_mpstart and the hatching process.
*/
struct cpu_info cpu_info_store[NCPUINFO] = {
[0] = {
CVS commit: src/sys/arch/aarch64/aarch64
Module Name:src Committed By: skrll Date: Mon Jan 11 17:12:13 UTC 2021 Modified Files: src/sys/arch/aarch64/aarch64: cpufunc.c Log Message: Small simplification To generate a diff of this commit: cvs rdiff -u -r1.26 -r1.27 src/sys/arch/aarch64/aarch64/cpufunc.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/aarch64/aarch64/cpufunc.c diff -u src/sys/arch/aarch64/aarch64/cpufunc.c:1.26 src/sys/arch/aarch64/aarch64/cpufunc.c:1.27 --- src/sys/arch/aarch64/aarch64/cpufunc.c:1.26 Thu Oct 22 07:31:15 2020 +++ src/sys/arch/aarch64/aarch64/cpufunc.c Mon Jan 11 17:12:13 2021 @@ -1,4 +1,4 @@ -/* $NetBSD: cpufunc.c,v 1.26 2020/10/22 07:31:15 skrll Exp $ */ +/* $NetBSD: cpufunc.c,v 1.27 2021/01/11 17:12:13 skrll Exp $ */ /* * Copyright (c) 2017 Ryo Shimizu @@ -30,7 +30,7 @@ #include "opt_multiprocessor.h" #include -__KERNEL_RCSID(0, "$NetBSD: cpufunc.c,v 1.26 2020/10/22 07:31:15 skrll Exp $"); +__KERNEL_RCSID(0, "$NetBSD: cpufunc.c,v 1.27 2021/01/11 17:12:13 skrll Exp $"); #include #include @@ -439,7 +439,6 @@ set_cpufuncs(void) struct cpu_info * const ci = curcpu(); const uint64_t ctr = reg_ctr_el0_read(); const uint64_t clidr = reg_clidr_el1_read(); - const uint32_t midr __unused = reg_midr_el1_read(); /* install default functions */ ci->ci_cpufuncs.cf_set_ttbr0 = aarch64_set_ttbr0; @@ -463,6 +462,8 @@ set_cpufuncs(void) } #ifdef CPU_THUNDERX + const uint32_t midr = reg_midr_el1_read(); + /* Cavium erratum 27456 */ if ((midr == CPU_ID_THUNDERXP1d0) || (midr == CPU_ID_THUNDERXP1d1) ||
CVS commit: src/sys/arch/aarch64/aarch64
Module Name:src
Committed By: jmcneill
Date: Sat Jan 9 15:07:42 UTC 2021
Modified Files:
src/sys/arch/aarch64/aarch64: locore.S
Log Message:
Avoid mismatched memory attributes for kernel and page table memory.
The initial page table code enters mappings first through an identity
mapped normal-NC mapping. Then later on, additional mappings are added
through a KVA-mapped normal-WB mapping. There is a warning about this
in the Armv8 ARM:
Bytes written without the Write-Back cacheable attribute within the
same Write-Back granule as bytes written with the Write-Back cacheable
attribute might have their values reverted to the old values as a result
of cache Write-Back.
Change the identity mapping attributes to match the KVA-mapping. This
fixes an issue where the kernel often doesn't start under ESXi-Arm Fling.
To generate a diff of this commit:
cvs rdiff -u -r1.75 -r1.76 src/sys/arch/aarch64/aarch64/locore.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/aarch64/aarch64/locore.S
diff -u src/sys/arch/aarch64/aarch64/locore.S:1.75 src/sys/arch/aarch64/aarch64/locore.S:1.76
--- src/sys/arch/aarch64/aarch64/locore.S:1.75 Sat Dec 26 00:55:26 2020
+++ src/sys/arch/aarch64/aarch64/locore.S Sat Jan 9 15:07:42 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: locore.S,v 1.75 2020/12/26 00:55:26 jmcneill Exp $ */
+/* $NetBSD: locore.S,v 1.76 2021/01/09 15:07:42 jmcneill Exp $ */
/*
* Copyright (c) 2017 Ryo Shimizu
@@ -38,7 +38,7 @@
#include
#include "assym.h"
-RCSID("$NetBSD: locore.S,v 1.75 2020/12/26 00:55:26 jmcneill Exp $")
+RCSID("$NetBSD: locore.S,v 1.76 2021/01/09 15:07:42 jmcneill Exp $")
#ifdef AARCH64_DEVICE_MEM_STRONGLY_ORDERED
#define MAIR_DEVICE_MEM MAIR_DEVICE_nGnRnE
@@ -865,7 +865,8 @@ init_mmutable:
sub x2, x2, x1 /* size = _end - start */
add x2, x2, #PMAPBOOT_PAGEALLOCMAX /* for pmapboot_pagealloc() */
mov x3, #L2_SIZE /* blocksize */
- mov x4, #LX_BLKPAG_ATTR_NORMAL_NC | LX_BLKPAG_AP_RW /* attr */
+ mov x4, #LX_BLKPAG_ATTR_NORMAL_WB | LX_BLKPAG_AP_RW /* attr */
+ orr x4, x4, #LX_BLKPAG_UXN
mov x5, x26/* pr func */
bl pmapboot_enter
cbnz x0, init_mmutable_error
@@ -879,7 +880,7 @@ init_mmutable:
mov x1, x8/* pa */
mov x2, #L2_SIZE /* size */
mov x3, #L2_SIZE /* blocksize */
- mov x4, #LX_BLKPAG_ATTR_NORMAL_NC | LX_BLKPAG_AP_RW
+ mov x4, #LX_BLKPAG_ATTR_NORMAL_WB | LX_BLKPAG_AP_RW
orr x4, x4, #LX_BLKPAG_UXN | LX_BLKPAG_PXN /* attr */
mov x5, x26/* pr func */
bl pmapboot_enter
CVS commit: src/sys/arch/aarch64/aarch64
Module Name:src Committed By: jmcneill Date: Sat Jan 9 13:42:25 UTC 2021 Modified Files: src/sys/arch/aarch64/aarch64: pmapboot.c Log Message: Fix a potential issue in pmapboot_enter_range and pmapboot_enter where if the va and size are not page aligned, there is a possibility of the last page not being taken into consideration. To generate a diff of this commit: cvs rdiff -u -r1.14 -r1.15 src/sys/arch/aarch64/aarch64/pmapboot.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/aarch64/aarch64/pmapboot.c diff -u src/sys/arch/aarch64/aarch64/pmapboot.c:1.14 src/sys/arch/aarch64/aarch64/pmapboot.c:1.15 --- src/sys/arch/aarch64/aarch64/pmapboot.c:1.14 Fri Dec 11 18:03:33 2020 +++ src/sys/arch/aarch64/aarch64/pmapboot.c Sat Jan 9 13:42:25 2021 @@ -1,4 +1,4 @@ -/* $NetBSD: pmapboot.c,v 1.14 2020/12/11 18:03:33 skrll Exp $ */ +/* $NetBSD: pmapboot.c,v 1.15 2021/01/09 13:42:25 jmcneill Exp $ */ /* * Copyright (c) 2018 Ryo Shimizu @@ -27,7 +27,7 @@ */ #include -__KERNEL_RCSID(0, "$NetBSD: pmapboot.c,v 1.14 2020/12/11 18:03:33 skrll Exp $"); +__KERNEL_RCSID(0, "$NetBSD: pmapboot.c,v 1.15 2021/01/09 13:42:25 jmcneill Exp $"); #include "opt_arm_debug.h" #include "opt_ddb.h" @@ -240,8 +240,8 @@ pmapboot_enter(vaddr_t va, paddr_t pa, p va, pa, size, blocksize, attr); pa &= ~(blocksize - 1); + va_end = (va + size + blocksize - 1) & ~(blocksize - 1); va &= ~(blocksize - 1); - va_end = (va + size + blocksize- 1) & ~(blocksize - 1); #ifdef OPTIMIZE_TLB_CONTIG va_start = va; #endif @@ -473,8 +473,8 @@ pmapboot_enter_range(vaddr_t va, paddr_t vsize_t left, mapsize, nblocks; int nskip = 0; - va = trunc_page(va); vend = round_page(va + size); + va = trunc_page(va); left = vend - va; /* align the start address to L2 blocksize */
CVS commit: src/sys/arch/aarch64/aarch64
Module Name:src
Committed By: jmcneill
Date: Sat Dec 26 00:55:26 UTC 2020
Modified Files:
src/sys/arch/aarch64/aarch64: cpuswitch.S locore.S locore_el2.S
Log Message:
Always issue isb after cpacr_el1 writes since it is a context-changing
operation.
To generate a diff of this commit:
cvs rdiff -u -r1.31 -r1.32 src/sys/arch/aarch64/aarch64/cpuswitch.S
cvs rdiff -u -r1.74 -r1.75 src/sys/arch/aarch64/aarch64/locore.S
cvs rdiff -u -r1.7 -r1.8 src/sys/arch/aarch64/aarch64/locore_el2.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/aarch64/aarch64/cpuswitch.S
diff -u src/sys/arch/aarch64/aarch64/cpuswitch.S:1.31 src/sys/arch/aarch64/aarch64/cpuswitch.S:1.32
--- src/sys/arch/aarch64/aarch64/cpuswitch.S:1.31 Thu Oct 22 07:36:02 2020
+++ src/sys/arch/aarch64/aarch64/cpuswitch.S Sat Dec 26 00:55:26 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: cpuswitch.S,v 1.31 2020/10/22 07:36:02 skrll Exp $ */
+/* $NetBSD: cpuswitch.S,v 1.32 2020/12/26 00:55:26 jmcneill Exp $ */
/*-
* Copyright (c) 2014, 2020 The NetBSD Foundation, Inc.
@@ -38,7 +38,7 @@
#include "opt_ddb.h"
#include "opt_kasan.h"
-RCSID("$NetBSD: cpuswitch.S,v 1.31 2020/10/22 07:36:02 skrll Exp $")
+RCSID("$NetBSD: cpuswitch.S,v 1.32 2020/12/26 00:55:26 jmcneill Exp $")
ARMV8_DEFINE_OPTIONS
@@ -86,6 +86,7 @@ ENTRY_NP(cpu_switchto)
DISABLE_INTERRUPT
mov sp, x4 /* restore stack pointer */
msr cpacr_el1, x5 /* restore cpacr_el1 */
+ isb
#ifdef ARMV83_PAC
/* Switch the PAC key. */
@@ -191,6 +192,7 @@ ENTRY_NP(cpu_switchto_softint)
mov x5, #CPACR_FPEN_NONE
msr cpacr_el1, x5 /* cpacr_el1 = CPACR_FPEN_NONE */
+ isb
#ifdef ARMV83_PAC
/* Switch the PAC key. */
@@ -223,6 +225,7 @@ ENTRY_NP(cpu_switchto_softint)
mov sp, x4 /* restore pinned_lwp sp */
msr cpacr_el1, x5 /* restore pinned_lwp cpacr */
+ isb
#ifdef ARMV83_PAC
/* Restore the PAC key. */
Index: src/sys/arch/aarch64/aarch64/locore.S
diff -u src/sys/arch/aarch64/aarch64/locore.S:1.74 src/sys/arch/aarch64/aarch64/locore.S:1.75
--- src/sys/arch/aarch64/aarch64/locore.S:1.74 Thu Oct 22 07:16:06 2020
+++ src/sys/arch/aarch64/aarch64/locore.S Sat Dec 26 00:55:26 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: locore.S,v 1.74 2020/10/22 07:16:06 ryo Exp $ */
+/* $NetBSD: locore.S,v 1.75 2020/12/26 00:55:26 jmcneill Exp $ */
/*
* Copyright (c) 2017 Ryo Shimizu
@@ -38,7 +38,7 @@
#include
#include "assym.h"
-RCSID("$NetBSD: locore.S,v 1.74 2020/10/22 07:16:06 ryo Exp $")
+RCSID("$NetBSD: locore.S,v 1.75 2020/12/26 00:55:26 jmcneill Exp $")
#ifdef AARCH64_DEVICE_MEM_STRONGLY_ORDERED
#define MAIR_DEVICE_MEM MAIR_DEVICE_nGnRnE
@@ -250,6 +250,7 @@ init_sysregs:
/* No trap system register access, and Trap FP/SIMD access */
msr cpacr_el1, xzr
+ isb
/* allow to read CNTVCT_EL0 and CNTFRQ_EL0 from EL0 */
mrs x0, cntkctl_el1
Index: src/sys/arch/aarch64/aarch64/locore_el2.S
diff -u src/sys/arch/aarch64/aarch64/locore_el2.S:1.7 src/sys/arch/aarch64/aarch64/locore_el2.S:1.8
--- src/sys/arch/aarch64/aarch64/locore_el2.S:1.7 Tue Sep 15 09:28:20 2020
+++ src/sys/arch/aarch64/aarch64/locore_el2.S Sat Dec 26 00:55:26 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: locore_el2.S,v 1.7 2020/09/15 09:28:20 ryo Exp $ */
+/* $NetBSD: locore_el2.S,v 1.8 2020/12/26 00:55:26 jmcneill Exp $ */
/*-
* Copyright (c) 2012-2014 Andrew Turner
@@ -32,7 +32,7 @@
#include
#include "assym.h"
-RCSID("$NetBSD: locore_el2.S,v 1.7 2020/09/15 09:28:20 ryo Exp $")
+RCSID("$NetBSD: locore_el2.S,v 1.8 2020/12/26 00:55:26 jmcneill Exp $")
/*
* For use in #include "locore_el2.S".
@@ -85,6 +85,7 @@ in_el2:
bic x2, x2, #CPACR_FPEN
orr x2, x2, #CPACR_FPEN_ALL
msr cpacr_el1, x2
+ isb
/* Don't trap to EL2 on access to various registers. */
mov x2, #CPTR_RES1
CVS commit: src/sys/arch/aarch64/aarch64
Module Name:src
Committed By: skrll
Date: Sun Dec 20 08:26:33 UTC 2020
Modified Files:
src/sys/arch/aarch64/aarch64: pmap.c
Log Message:
Improve the English in the previous comment fix.
To generate a diff of this commit:
cvs rdiff -u -r1.98 -r1.99 src/sys/arch/aarch64/aarch64/pmap.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/aarch64/aarch64/pmap.c
diff -u src/sys/arch/aarch64/aarch64/pmap.c:1.98 src/sys/arch/aarch64/aarch64/pmap.c:1.99
--- src/sys/arch/aarch64/aarch64/pmap.c:1.98 Sat Dec 19 09:02:32 2020
+++ src/sys/arch/aarch64/aarch64/pmap.c Sun Dec 20 08:26:32 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: pmap.c,v 1.98 2020/12/19 09:02:32 skrll Exp $ */
+/* $NetBSD: pmap.c,v 1.99 2020/12/20 08:26:32 skrll Exp $ */
/*
* Copyright (c) 2017 Ryo Shimizu
@@ -27,7 +27,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.98 2020/12/19 09:02:32 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.99 2020/12/20 08:26:32 skrll Exp $");
#include "opt_arm_debug.h"
#include "opt_ddb.h"
@@ -632,7 +632,7 @@ pmap_alloc_pdp(struct pmap *pm, struct v
PMAP_COUNT(pdp_alloc);
PMAP_PAGE_INIT(VM_PAGE_TO_PP(pg));
} else {
- /* uvm_pageboot_alloc() returns direct mapping address */
+ /* uvm_pageboot_alloc() returns a direct mapping address */
pg = NULL;
pa = AARCH64_KVA_TO_PA(
uvm_pageboot_alloc(Ln_TABLE_SIZE));
CVS commit: src/sys/arch/aarch64/aarch64
Module Name:src
Committed By: skrll
Date: Sat Dec 19 09:02:32 UTC 2020
Modified Files:
src/sys/arch/aarch64/aarch64: pmap.c
Log Message:
Tweak a comment
To generate a diff of this commit:
cvs rdiff -u -r1.97 -r1.98 src/sys/arch/aarch64/aarch64/pmap.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/aarch64/aarch64/pmap.c
diff -u src/sys/arch/aarch64/aarch64/pmap.c:1.97 src/sys/arch/aarch64/aarch64/pmap.c:1.98
--- src/sys/arch/aarch64/aarch64/pmap.c:1.97 Fri Dec 11 18:03:33 2020
+++ src/sys/arch/aarch64/aarch64/pmap.c Sat Dec 19 09:02:32 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: pmap.c,v 1.97 2020/12/11 18:03:33 skrll Exp $ */
+/* $NetBSD: pmap.c,v 1.98 2020/12/19 09:02:32 skrll Exp $ */
/*
* Copyright (c) 2017 Ryo Shimizu
@@ -27,7 +27,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.97 2020/12/11 18:03:33 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.98 2020/12/19 09:02:32 skrll Exp $");
#include "opt_arm_debug.h"
#include "opt_ddb.h"
@@ -632,7 +632,7 @@ pmap_alloc_pdp(struct pmap *pm, struct v
PMAP_COUNT(pdp_alloc);
PMAP_PAGE_INIT(VM_PAGE_TO_PP(pg));
} else {
- /* uvm_pageboot_alloc() returns AARCH64 direct mapping address */
+ /* uvm_pageboot_alloc() returns direct mapping address */
pg = NULL;
pa = AARCH64_KVA_TO_PA(
uvm_pageboot_alloc(Ln_TABLE_SIZE));
CVS commit: src/sys/arch/aarch64/aarch64
Module Name:src
Committed By: skrll
Date: Mon Dec 14 19:32:29 UTC 2020
Modified Files:
src/sys/arch/aarch64/aarch64: bus_space.c
Log Message:
Add a note about completion vs ordering barrier as well.
To generate a diff of this commit:
cvs rdiff -u -r1.14 -r1.15 src/sys/arch/aarch64/aarch64/bus_space.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/aarch64/aarch64/bus_space.c
diff -u src/sys/arch/aarch64/aarch64/bus_space.c:1.14 src/sys/arch/aarch64/aarch64/bus_space.c:1.15
--- src/sys/arch/aarch64/aarch64/bus_space.c:1.14 Mon Dec 14 19:25:28 2020
+++ src/sys/arch/aarch64/aarch64/bus_space.c Mon Dec 14 19:32:29 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: bus_space.c,v 1.14 2020/12/14 19:25:28 skrll Exp $ */
+/* $NetBSD: bus_space.c,v 1.15 2020/12/14 19:32:29 skrll Exp $ */
/*
* Copyright (c) 2017 Ryo Shimizu
@@ -27,7 +27,7 @@
*/
#include
-__KERNEL_RCSID(1, "$NetBSD: bus_space.c,v 1.14 2020/12/14 19:25:28 skrll Exp $");
+__KERNEL_RCSID(1, "$NetBSD: bus_space.c,v 1.15 2020/12/14 19:32:29 skrll Exp $");
#include
#include
@@ -638,6 +638,10 @@ generic_bs_barrier(void *t, bus_space_ha
* consulting the page tables), so just issue the barrier
* unconditionally. Chances are either it's necessary or the
* cost is small in comparison to device register I/O.
+ *
+ * The bus_space(9) man page is not clear whether barriers
+ * should enforce ordering or completion. To be safe, use dsb
+ * (ensure completion) here instead of dmb (ordering).
*/
switch (flags) {
case BUS_SPACE_BARRIER_READ:
CVS commit: src/sys/arch/aarch64/aarch64
Module Name:src
Committed By: skrll
Date: Mon Dec 14 19:25:28 UTC 2020
Modified Files:
src/sys/arch/aarch64/aarch64: bus_space.c
Log Message:
Add a big comment in generic_bs_barrier about mappings and what barriers
are really required and why we cheat. Inspired by a similar comment in
x86/bus_space.c
To generate a diff of this commit:
cvs rdiff -u -r1.13 -r1.14 src/sys/arch/aarch64/aarch64/bus_space.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/aarch64/aarch64/bus_space.c
diff -u src/sys/arch/aarch64/aarch64/bus_space.c:1.13 src/sys/arch/aarch64/aarch64/bus_space.c:1.14
--- src/sys/arch/aarch64/aarch64/bus_space.c:1.13 Mon Dec 14 11:42:44 2020
+++ src/sys/arch/aarch64/aarch64/bus_space.c Mon Dec 14 19:25:28 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: bus_space.c,v 1.13 2020/12/14 11:42:44 jmcneill Exp $ */
+/* $NetBSD: bus_space.c,v 1.14 2020/12/14 19:25:28 skrll Exp $ */
/*
* Copyright (c) 2017 Ryo Shimizu
@@ -27,7 +27,7 @@
*/
#include
-__KERNEL_RCSID(1, "$NetBSD: bus_space.c,v 1.13 2020/12/14 11:42:44 jmcneill Exp $");
+__KERNEL_RCSID(1, "$NetBSD: bus_space.c,v 1.14 2020/12/14 19:25:28 skrll Exp $");
#include
#include
@@ -613,6 +613,32 @@ generic_bs_barrier(void *t, bus_space_ha
{
flags &= BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE;
+ /*
+ * For default mappings, which are mapped with nGnRE memory
+ * regions, all loads and stores are issued in program order
+ * (non-reordered).
+ *
+ * For strongly ordered mappings, which are mapped with nGnRnE
+ * regions, all loads and stores are issued in program order
+ * (non-reordered) and will complete at the endpoint, thus
+ * not requiring any barrier.
+ *
+ * For BUS_SPACE_MAP_PREFETCHABLE mappings, which are mapped
+ * as normal memory with the non-cacheable cacheability attr-
+ * ibute, loads and stores may be issued out of order, and
+ * writes may be buffered, potentially requiring any of the
+ * read, write, and read/write barriers.
+ *
+ * For BUS_SPACE_MAP_CACHEABLE mappings, which are mapped as
+ * normal memory with the write-back cacheability attribute
+ * (just like normal memory), the same potential for any of
+ * the barriers exists.
+ *
+ * We can't easily tell here how the region was mapped (without
+ * consulting the page tables), so just issue the barrier
+ * unconditionally. Chances are either it's necessary or the
+ * cost is small in comparison to device register I/O.
+ */
switch (flags) {
case BUS_SPACE_BARRIER_READ:
dsb(ld);
CVS commit: src/sys/arch/aarch64/aarch64
Module Name:src
Committed By: jmcneill
Date: Mon Dec 14 11:42:44 UTC 2020
Modified Files:
src/sys/arch/aarch64/aarch64: bus_space.c
Log Message:
Use full system DSB ops for bs barrier.
To generate a diff of this commit:
cvs rdiff -u -r1.12 -r1.13 src/sys/arch/aarch64/aarch64/bus_space.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/aarch64/aarch64/bus_space.c
diff -u src/sys/arch/aarch64/aarch64/bus_space.c:1.12 src/sys/arch/aarch64/aarch64/bus_space.c:1.13
--- src/sys/arch/aarch64/aarch64/bus_space.c:1.12 Mon Dec 14 11:16:33 2020
+++ src/sys/arch/aarch64/aarch64/bus_space.c Mon Dec 14 11:42:44 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: bus_space.c,v 1.12 2020/12/14 11:16:33 jmcneill Exp $ */
+/* $NetBSD: bus_space.c,v 1.13 2020/12/14 11:42:44 jmcneill Exp $ */
/*
* Copyright (c) 2017 Ryo Shimizu
@@ -27,7 +27,7 @@
*/
#include
-__KERNEL_RCSID(1, "$NetBSD: bus_space.c,v 1.12 2020/12/14 11:16:33 jmcneill Exp $");
+__KERNEL_RCSID(1, "$NetBSD: bus_space.c,v 1.13 2020/12/14 11:42:44 jmcneill Exp $");
#include
#include
@@ -615,13 +615,13 @@ generic_bs_barrier(void *t, bus_space_ha
switch (flags) {
case BUS_SPACE_BARRIER_READ:
- dsb(ishld);
+ dsb(ld);
break;
case BUS_SPACE_BARRIER_WRITE:
- dsb(ishst);
+ dsb(st);
break;
case BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE:
- dsb(ish);
+ dsb(sy);
break;
}
}
CVS commit: src/sys/arch/aarch64/aarch64
Module Name:src
Committed By: jmcneill
Date: Mon Dec 14 11:16:33 UTC 2020
Modified Files:
src/sys/arch/aarch64/aarch64: bus_space.c
Log Message:
The bus_space(9) man page is not clear whether barriers should enforce
ordering or completion. To be safe, use dsb here instead of dmb.
To generate a diff of this commit:
cvs rdiff -u -r1.11 -r1.12 src/sys/arch/aarch64/aarch64/bus_space.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/aarch64/aarch64/bus_space.c
diff -u src/sys/arch/aarch64/aarch64/bus_space.c:1.11 src/sys/arch/aarch64/aarch64/bus_space.c:1.12
--- src/sys/arch/aarch64/aarch64/bus_space.c:1.11 Thu Oct 15 21:14:15 2020
+++ src/sys/arch/aarch64/aarch64/bus_space.c Mon Dec 14 11:16:33 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: bus_space.c,v 1.11 2020/10/15 21:14:15 jmcneill Exp $ */
+/* $NetBSD: bus_space.c,v 1.12 2020/12/14 11:16:33 jmcneill Exp $ */
/*
* Copyright (c) 2017 Ryo Shimizu
@@ -27,7 +27,7 @@
*/
#include
-__KERNEL_RCSID(1, "$NetBSD: bus_space.c,v 1.11 2020/10/15 21:14:15 jmcneill Exp $");
+__KERNEL_RCSID(1, "$NetBSD: bus_space.c,v 1.12 2020/12/14 11:16:33 jmcneill Exp $");
#include
#include
@@ -615,13 +615,13 @@ generic_bs_barrier(void *t, bus_space_ha
switch (flags) {
case BUS_SPACE_BARRIER_READ:
- dmb(ishld);
+ dsb(ishld);
break;
case BUS_SPACE_BARRIER_WRITE:
- dmb(ishst);
+ dsb(ishst);
break;
case BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE:
- dmb(ish);
+ dsb(ish);
break;
}
}
CVS commit: src/sys/arch/aarch64/aarch64
Module Name:src Committed By: skrll Date: Wed Dec 9 08:51:05 UTC 2020 Modified Files: src/sys/arch/aarch64/aarch64: aarch64_machdep.c Log Message: Remove unnecessary aarch64_dcache_wbinv_all now that pmapboot_enter does dsb(ish) To generate a diff of this commit: cvs rdiff -u -r1.54 -r1.55 src/sys/arch/aarch64/aarch64/aarch64_machdep.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/aarch64/aarch64/aarch64_machdep.c diff -u src/sys/arch/aarch64/aarch64/aarch64_machdep.c:1.54 src/sys/arch/aarch64/aarch64/aarch64_machdep.c:1.55 --- src/sys/arch/aarch64/aarch64/aarch64_machdep.c:1.54 Tue Nov 10 07:51:19 2020 +++ src/sys/arch/aarch64/aarch64/aarch64_machdep.c Wed Dec 9 08:51:05 2020 @@ -1,4 +1,4 @@ -/* $NetBSD: aarch64_machdep.c,v 1.54 2020/11/10 07:51:19 skrll Exp $ */ +/* $NetBSD: aarch64_machdep.c,v 1.55 2020/12/09 08:51:05 skrll Exp $ */ /*- * Copyright (c) 2014 The NetBSD Foundation, Inc. @@ -30,7 +30,7 @@ */ #include -__KERNEL_RCSID(1, "$NetBSD: aarch64_machdep.c,v 1.54 2020/11/10 07:51:19 skrll Exp $"); +__KERNEL_RCSID(1, "$NetBSD: aarch64_machdep.c,v 1.55 2020/12/09 08:51:05 skrll Exp $"); #include "opt_arm_debug.h" #include "opt_cpuoptions.h" @@ -166,7 +166,6 @@ cpu_kernel_vm_init(uint64_t memory_start pmapboot_enter_range(AARCH64_PA_TO_KVA(start), start, end - start, dmattr, printf); } - aarch64_dcache_wbinv_all(); /* Disable translation table walks using TTBR0 */ uint64_t tcr = reg_tcr_el1_read();
CVS commit: src/sys/arch/aarch64/aarch64
Module Name:src Committed By: skrll Date: Fri Dec 4 08:24:41 UTC 2020 Modified Files: src/sys/arch/aarch64/aarch64: pmapboot.c Log Message: Ensure translation table updates are visible to the hardware walker(s) in pmapboot_enter. To generate a diff of this commit: cvs rdiff -u -r1.12 -r1.13 src/sys/arch/aarch64/aarch64/pmapboot.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/aarch64/aarch64/pmapboot.c diff -u src/sys/arch/aarch64/aarch64/pmapboot.c:1.12 src/sys/arch/aarch64/aarch64/pmapboot.c:1.13 --- src/sys/arch/aarch64/aarch64/pmapboot.c:1.12 Tue Nov 10 07:51:19 2020 +++ src/sys/arch/aarch64/aarch64/pmapboot.c Fri Dec 4 08:24:41 2020 @@ -1,4 +1,4 @@ -/* $NetBSD: pmapboot.c,v 1.12 2020/11/10 07:51:19 skrll Exp $ */ +/* $NetBSD: pmapboot.c,v 1.13 2020/12/04 08:24:41 skrll Exp $ */ /* * Copyright (c) 2018 Ryo Shimizu @@ -27,7 +27,7 @@ */ #include -__KERNEL_RCSID(0, "$NetBSD: pmapboot.c,v 1.12 2020/11/10 07:51:19 skrll Exp $"); +__KERNEL_RCSID(0, "$NetBSD: pmapboot.c,v 1.13 2020/12/04 08:24:41 skrll Exp $"); #include "opt_arm_debug.h" #include "opt_ddb.h" @@ -40,6 +40,8 @@ __KERNEL_RCSID(0, "$NetBSD: pmapboot.c,v #include +#include + #include #include #include @@ -435,6 +437,8 @@ pmapboot_enter(vaddr_t va, paddr_t pa, p } } + dsb(ish); + return nskip; }
CVS commit: src/sys/arch/aarch64/aarch64
Module Name:src
Committed By: jmcneill
Date: Thu Nov 12 11:28:39 UTC 2020
Modified Files:
src/sys/arch/aarch64/aarch64: bus_space_asm_generic.S
Log Message:
Fix typo in comment
To generate a diff of this commit:
cvs rdiff -u -r1.4 -r1.5 src/sys/arch/aarch64/aarch64/bus_space_asm_generic.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/aarch64/aarch64/bus_space_asm_generic.S
diff -u src/sys/arch/aarch64/aarch64/bus_space_asm_generic.S:1.4 src/sys/arch/aarch64/aarch64/bus_space_asm_generic.S:1.5
--- src/sys/arch/aarch64/aarch64/bus_space_asm_generic.S:1.4 Thu Sep 24 16:15:49 2020
+++ src/sys/arch/aarch64/aarch64/bus_space_asm_generic.S Thu Nov 12 11:28:39 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: bus_space_asm_generic.S,v 1.4 2020/09/24 16:15:49 ryo Exp $ */
+/* $NetBSD: bus_space_asm_generic.S,v 1.5 2020/11/12 11:28:39 jmcneill Exp $ */
/*
* Copyright (c) 2017 Ryo Shimizu
@@ -29,7 +29,7 @@
#include
#include "assym.h"
-RCSID("$NetBSD: bus_space_asm_generic.S,v 1.4 2020/09/24 16:15:49 ryo Exp $")
+RCSID("$NetBSD: bus_space_asm_generic.S,v 1.5 2020/11/12 11:28:39 jmcneill Exp $")
.macro generate_bsfunc funcname, dsbop
/* uint8_t {funcname}_bs_r_1(x0:tag, x1:addr, x2:offset) */
@@ -83,7 +83,7 @@ ENTRY_NP(\funcname\()_bs_r_2_swap)
END(\funcname\()_bs_r_2_swap)
-/* uint32_t {funcname}_bs_r_4_swap(x0:tag, x2:addr, x3:offset) */
+/* uint32_t {funcname}_bs_r_4_swap(x0:tag, x1:addr, x2:offset) */
ENTRY_NP(\funcname\()_bs_r_4_swap)
\dsbop
ldr w8, [x0, #BS_STRIDE]
CVS commit: src/sys/arch/aarch64/aarch64
Module Name:src
Committed By: skrll
Date: Sat Nov 7 08:48:11 UTC 2020
Modified Files:
src/sys/arch/aarch64/aarch64: pmapboot.c
Log Message:
Fix the use of the contiguous bit by checking the output address as well.
To generate a diff of this commit:
cvs rdiff -u -r1.10 -r1.11 src/sys/arch/aarch64/aarch64/pmapboot.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/aarch64/aarch64/pmapboot.c
diff -u src/sys/arch/aarch64/aarch64/pmapboot.c:1.10 src/sys/arch/aarch64/aarch64/pmapboot.c:1.11
--- src/sys/arch/aarch64/aarch64/pmapboot.c:1.10 Fri Jul 17 07:21:44 2020
+++ src/sys/arch/aarch64/aarch64/pmapboot.c Sat Nov 7 08:48:11 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: pmapboot.c,v 1.10 2020/07/17 07:21:44 ryo Exp $ */
+/* $NetBSD: pmapboot.c,v 1.11 2020/11/07 08:48:11 skrll Exp $ */
/*
* Copyright (c) 2018 Ryo Shimizu
@@ -27,7 +27,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: pmapboot.c,v 1.10 2020/07/17 07:21:44 ryo Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pmapboot.c,v 1.11 2020/11/07 08:48:11 skrll Exp $");
#include "opt_arm_debug.h"
#include "opt_ddb.h"
@@ -46,7 +46,6 @@ __KERNEL_RCSID(0, "$NetBSD: pmapboot.c,v
#include
#include
-
#define OPTIMIZE_TLB_CONTIG
static void
@@ -180,16 +179,23 @@ pmapboot_pte_print(pt_entry_t pte, int l
#ifdef OPTIMIZE_TLB_CONTIG
static inline bool
-tlb_contiguous_p(vaddr_t addr, vaddr_t start, vaddr_t end, vsize_t blocksize)
+tlb_contiguous_p(vaddr_t va, paddr_t pa, vaddr_t start, vaddr_t end,
+vsize_t blocksize)
{
/*
* when using 4KB granule, 16 adjacent and aligned entries can be
* unified to one TLB cache entry.
* in other size of granule, not supported.
*/
- if (((addr & ~((blocksize << 4) - 1)) >= start) &&
- ((addr | ((blocksize << 4) - 1)) <= end))
+ const vaddr_t mask = (blocksize << 4) - 1;
+
+ /* if the output address doesn't align it can't be contiguous */
+ if ((va & mask) != (pa & mask))
+ return false;
+
+ if ((va & ~mask) >= start && (va | mask) <= end)
return true;
+
return false;
}
#endif /* OPTIMIZE_TLB_CONTIG */
@@ -288,7 +294,7 @@ pmapboot_enter(vaddr_t va, paddr_t pa, p
#endif
attr;
#ifdef OPTIMIZE_TLB_CONTIG
- if (tlb_contiguous_p(va, va_start, va_end, blocksize))
+ if (tlb_contiguous_p(va, pa, va_start, va_end, blocksize))
pte |= LX_BLKPAG_CONTIG;
ll = l1;
llidx = idx1;
@@ -333,7 +339,7 @@ pmapboot_enter(vaddr_t va, paddr_t pa, p
#endif
attr;
#ifdef OPTIMIZE_TLB_CONTIG
- if (tlb_contiguous_p(va, va_start, va_end, blocksize))
+ if (tlb_contiguous_p(va, pa, va_start, va_end, blocksize))
pte |= LX_BLKPAG_CONTIG;
ll = l2;
llidx = idx2;
@@ -377,7 +383,7 @@ pmapboot_enter(vaddr_t va, paddr_t pa, p
#endif
attr;
#ifdef OPTIMIZE_TLB_CONTIG
- if (tlb_contiguous_p(va, va_start, va_end, blocksize))
+ if (tlb_contiguous_p(va, pa, va_start, va_end, blocksize))
pte |= LX_BLKPAG_CONTIG;
ll = l3;
llidx = idx3;
CVS commit: src/sys/arch/aarch64/aarch64
Module Name:src
Committed By: skrll
Date: Sat Nov 7 08:33:50 UTC 2020
Modified Files:
src/sys/arch/aarch64/aarch64: pmap.c
Log Message:
In pmap_devmap_bootstrap only set pmap_devmap_bootstrap_done if there
is an entry and ALL of the entries have been done. The entry required
for EARLYCONS might not be the first/only one...
To generate a diff of this commit:
cvs rdiff -u -r1.94 -r1.95 src/sys/arch/aarch64/aarch64/pmap.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/aarch64/aarch64/pmap.c
diff -u src/sys/arch/aarch64/aarch64/pmap.c:1.94 src/sys/arch/aarch64/aarch64/pmap.c:1.95
--- src/sys/arch/aarch64/aarch64/pmap.c:1.94 Sun Nov 1 10:58:59 2020
+++ src/sys/arch/aarch64/aarch64/pmap.c Sat Nov 7 08:33:50 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: pmap.c,v 1.94 2020/11/01 10:58:59 jmcneill Exp $ */
+/* $NetBSD: pmap.c,v 1.95 2020/11/07 08:33:50 skrll Exp $ */
/*
* Copyright (c) 2017 Ryo Shimizu
@@ -27,7 +27,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.94 2020/11/01 10:58:59 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.95 2020/11/07 08:33:50 skrll Exp $");
#include "opt_arm_debug.h"
#include "opt_ddb.h"
@@ -348,6 +348,7 @@ pmap_devmap_register(const struct pmap_d
void
pmap_devmap_bootstrap(vaddr_t l0pt, const struct pmap_devmap *table)
{
+ bool done = false;
vaddr_t va;
int i;
@@ -375,8 +376,10 @@ pmap_devmap_bootstrap(vaddr_t l0pt, cons
table[i].pd_size,
table[i].pd_prot,
table[i].pd_flags);
- pmap_devmap_bootstrap_done = true;
+ done = true;
}
+ if (done)
+ pmap_devmap_bootstrap_done = true;
}
const struct pmap_devmap *
CVS commit: src/sys/arch/aarch64/aarch64
Module Name:src Committed By: jmcneill Date: Sun Nov 1 10:58:59 UTC 2020 Modified Files: src/sys/arch/aarch64/aarch64: pmap.c Log Message: No need to disable translation table walks in pmap_activate(). To generate a diff of this commit: cvs rdiff -u -r1.93 -r1.94 src/sys/arch/aarch64/aarch64/pmap.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/aarch64/aarch64/pmap.c diff -u src/sys/arch/aarch64/aarch64/pmap.c:1.93 src/sys/arch/aarch64/aarch64/pmap.c:1.94 --- src/sys/arch/aarch64/aarch64/pmap.c:1.93 Thu Oct 22 07:34:18 2020 +++ src/sys/arch/aarch64/aarch64/pmap.c Sun Nov 1 10:58:59 2020 @@ -1,4 +1,4 @@ -/* $NetBSD: pmap.c,v 1.93 2020/10/22 07:34:18 skrll Exp $ */ +/* $NetBSD: pmap.c,v 1.94 2020/11/01 10:58:59 jmcneill Exp $ */ /* * Copyright (c) 2017 Ryo Shimizu @@ -27,7 +27,7 @@ */ #include -__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.93 2020/10/22 07:34:18 skrll Exp $"); +__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.94 2020/11/01 10:58:59 jmcneill Exp $"); #include "opt_arm_debug.h" #include "opt_ddb.h" @@ -1439,11 +1439,6 @@ pmap_activate(struct lwp *l) UVMHIST_LOG(pmaphist, "lwp=%p (pid=%d)", l, l->l_proc->p_pid, 0, 0); - /* Disable translation table walks using TTBR0 */ - tcr = reg_tcr_el1_read(); - reg_tcr_el1_write(tcr | TCR_EPD0); - isb(); - /* XXX: allocate asid, and regenerate if needed */ if (pm->pm_asid == -1) pm->pm_asid = l->l_proc->p_pid;
CVS commit: src/sys/arch/aarch64/aarch64
Module Name:src
Committed By: skrll
Date: Thu Oct 22 07:36:02 UTC 2020
Modified Files:
src/sys/arch/aarch64/aarch64: cpuswitch.S
Log Message:
Use the correct (more relaxed) membar_exit barrier in cpu_switchto_softint
To generate a diff of this commit:
cvs rdiff -u -r1.30 -r1.31 src/sys/arch/aarch64/aarch64/cpuswitch.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/aarch64/aarch64/cpuswitch.S
diff -u src/sys/arch/aarch64/aarch64/cpuswitch.S:1.30 src/sys/arch/aarch64/aarch64/cpuswitch.S:1.31
--- src/sys/arch/aarch64/aarch64/cpuswitch.S:1.30 Tue Oct 13 21:24:22 2020
+++ src/sys/arch/aarch64/aarch64/cpuswitch.S Thu Oct 22 07:36:02 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: cpuswitch.S,v 1.30 2020/10/13 21:24:22 skrll Exp $ */
+/* $NetBSD: cpuswitch.S,v 1.31 2020/10/22 07:36:02 skrll Exp $ */
/*-
* Copyright (c) 2014, 2020 The NetBSD Foundation, Inc.
@@ -38,7 +38,7 @@
#include "opt_ddb.h"
#include "opt_kasan.h"
-RCSID("$NetBSD: cpuswitch.S,v 1.30 2020/10/13 21:24:22 skrll Exp $")
+RCSID("$NetBSD: cpuswitch.S,v 1.31 2020/10/22 07:36:02 skrll Exp $")
ARMV8_DEFINE_OPTIONS
@@ -219,7 +219,7 @@ ENTRY_NP(cpu_switchto_softint)
msr tpidr_el1, x19 /* curlwp = pinned_lwp */
ldr x3, [x19, #L_CPU] /* x3 = curlwp->l_cpu */
str x19, [x3, #CI_CURLWP] /* curlwp->l_cpu->ci_curlwp := x19 */
- dmb st /* see comments in kern_mutex.c */
+ dmb ishst /* see comments in kern_mutex.c */
mov sp, x4 /* restore pinned_lwp sp */
msr cpacr_el1, x5 /* restore pinned_lwp cpacr */
CVS commit: src/sys/arch/aarch64/aarch64
Module Name:src
Committed By: skrll
Date: Thu Oct 22 07:34:18 UTC 2020
Modified Files:
src/sys/arch/aarch64/aarch64: pmap.c
Log Message:
Use the isb macro - missed in previous commit
To generate a diff of this commit:
cvs rdiff -u -r1.92 -r1.93 src/sys/arch/aarch64/aarch64/pmap.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/aarch64/aarch64/pmap.c
diff -u src/sys/arch/aarch64/aarch64/pmap.c:1.92 src/sys/arch/aarch64/aarch64/pmap.c:1.93
--- src/sys/arch/aarch64/aarch64/pmap.c:1.92 Thu Oct 22 07:31:15 2020
+++ src/sys/arch/aarch64/aarch64/pmap.c Thu Oct 22 07:34:18 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: pmap.c,v 1.92 2020/10/22 07:31:15 skrll Exp $ */
+/* $NetBSD: pmap.c,v 1.93 2020/10/22 07:34:18 skrll Exp $ */
/*
* Copyright (c) 2017 Ryo Shimizu
@@ -27,7 +27,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.92 2020/10/22 07:31:15 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.93 2020/10/22 07:34:18 skrll Exp $");
#include "opt_arm_debug.h"
#include "opt_ddb.h"
@@ -1478,7 +1478,7 @@ pmap_deactivate(struct lwp *l)
/* Disable translation table walks using TTBR0 */
tcr = reg_tcr_el1_read();
reg_tcr_el1_write(tcr | TCR_EPD0);
- __asm __volatile("isb" ::: "memory");
+ isb();
/* XXX */
pm->pm_activated = false;
CVS commit: src/sys/arch/aarch64/aarch64
Module Name:src
Committed By: skrll
Date: Thu Oct 22 07:31:15 UTC 2020
Modified Files:
src/sys/arch/aarch64/aarch64: aarch64_machdep.c cpufunc.c db_machdep.c
efi_machdep.c fpu.c pmap.c trap.c
Log Message:
Use the dmb/dsb/isb macros... if nothing else they're all now consistent
about the "memory" assembler contraint.
No binary change
To generate a diff of this commit:
cvs rdiff -u -r1.52 -r1.53 src/sys/arch/aarch64/aarch64/aarch64_machdep.c
cvs rdiff -u -r1.25 -r1.26 src/sys/arch/aarch64/aarch64/cpufunc.c
cvs rdiff -u -r1.27 -r1.28 src/sys/arch/aarch64/aarch64/db_machdep.c
cvs rdiff -u -r1.7 -r1.8 src/sys/arch/aarch64/aarch64/efi_machdep.c
cvs rdiff -u -r1.9 -r1.10 src/sys/arch/aarch64/aarch64/fpu.c
cvs rdiff -u -r1.91 -r1.92 src/sys/arch/aarch64/aarch64/pmap.c
cvs rdiff -u -r1.39 -r1.40 src/sys/arch/aarch64/aarch64/trap.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/aarch64/aarch64/aarch64_machdep.c
diff -u src/sys/arch/aarch64/aarch64/aarch64_machdep.c:1.52 src/sys/arch/aarch64/aarch64/aarch64_machdep.c:1.53
--- src/sys/arch/aarch64/aarch64/aarch64_machdep.c:1.52 Thu Oct 22 07:23:24 2020
+++ src/sys/arch/aarch64/aarch64/aarch64_machdep.c Thu Oct 22 07:31:15 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: aarch64_machdep.c,v 1.52 2020/10/22 07:23:24 skrll Exp $ */
+/* $NetBSD: aarch64_machdep.c,v 1.53 2020/10/22 07:31:15 skrll Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
*/
#include
-__KERNEL_RCSID(1, "$NetBSD: aarch64_machdep.c,v 1.52 2020/10/22 07:23:24 skrll Exp $");
+__KERNEL_RCSID(1, "$NetBSD: aarch64_machdep.c,v 1.53 2020/10/22 07:31:15 skrll Exp $");
#include "opt_arm_debug.h"
#include "opt_cpuoptions.h"
@@ -171,7 +171,7 @@ cpu_kernel_vm_init(uint64_t memory_start
/* Disable translation table walks using TTBR0 */
uint64_t tcr = reg_tcr_el1_read();
reg_tcr_el1_write(tcr | TCR_EPD0);
- __asm __volatile("isb" ::: "memory");
+ isb();
aarch64_tlbi_all();
Index: src/sys/arch/aarch64/aarch64/cpufunc.c
diff -u src/sys/arch/aarch64/aarch64/cpufunc.c:1.25 src/sys/arch/aarch64/aarch64/cpufunc.c:1.26
--- src/sys/arch/aarch64/aarch64/cpufunc.c:1.25 Thu Oct 22 07:23:24 2020
+++ src/sys/arch/aarch64/aarch64/cpufunc.c Thu Oct 22 07:31:15 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: cpufunc.c,v 1.25 2020/10/22 07:23:24 skrll Exp $ */
+/* $NetBSD: cpufunc.c,v 1.26 2020/10/22 07:31:15 skrll Exp $ */
/*
* Copyright (c) 2017 Ryo Shimizu
@@ -30,7 +30,7 @@
#include "opt_multiprocessor.h"
#include
-__KERNEL_RCSID(0, "$NetBSD: cpufunc.c,v 1.25 2020/10/22 07:23:24 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cpufunc.c,v 1.26 2020/10/22 07:31:15 skrll Exp $");
#include
#include
@@ -69,7 +69,7 @@ extract_cacheunit(int level, bool insn,
/* select and extract level N data cache */
reg_csselr_el1_write(__SHIFTIN(level, CSSELR_LEVEL) |
__SHIFTIN(insn ? 1 : 0, CSSELR_IND));
- __asm __volatile ("isb");
+ isb();
ccsidr = reg_ccsidr_el1_read();
mmfr2 = reg_id_aa64mmfr2_el1_read();
@@ -391,10 +391,10 @@ aarch64_dcache_wbinv_all(void)
if (cinfo[level].cacheable == CACHE_CACHEABLE_NONE)
break;
- __asm __volatile ("dsb ish");
+ dsb(ish);
ln_dcache_wbinv_all(level, [level].dcache);
}
- __asm __volatile ("dsb ish");
+ dsb(ish);
}
void
@@ -409,10 +409,10 @@ aarch64_dcache_inv_all(void)
if (cinfo[level].cacheable == CACHE_CACHEABLE_NONE)
break;
- __asm __volatile ("dsb ish");
+ dsb(ish);
ln_dcache_inv_all(level, [level].dcache);
}
- __asm __volatile ("dsb ish");
+ dsb(ish);
}
void
@@ -427,10 +427,10 @@ aarch64_dcache_wb_all(void)
if (cinfo[level].cacheable == CACHE_CACHEABLE_NONE)
break;
- __asm __volatile ("dsb ish");
+ dsb(ish);
ln_dcache_wb_all(level, [level].dcache);
}
- __asm __volatile ("dsb ish");
+ dsb(ish);
}
int
Index: src/sys/arch/aarch64/aarch64/db_machdep.c
diff -u src/sys/arch/aarch64/aarch64/db_machdep.c:1.27 src/sys/arch/aarch64/aarch64/db_machdep.c:1.28
--- src/sys/arch/aarch64/aarch64/db_machdep.c:1.27 Thu Oct 22 07:23:24 2020
+++ src/sys/arch/aarch64/aarch64/db_machdep.c Thu Oct 22 07:31:15 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: db_machdep.c,v 1.27 2020/10/22 07:23:24 skrll Exp $ */
+/* $NetBSD: db_machdep.c,v 1.28 2020/10/22 07:31:15 skrll Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: db_machdep.c,v 1.27 2020/10/22 07:23:24 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: db_machdep.c,v 1.28 2020/10/22 07:31:15 skrll Exp $");
#ifdef _KERNEL_OPT
#include "opt_compat_netbsd32.h"
@@ -444,13 +444,13 @@ db_md_pte_cmd(db_expr_t addr, bool have_
}
reg_s1e0r_write(addr);
- __asm __volatile ("isb");
+ isb();
par = reg_par_el1_read();
db_printf("Stage1 EL0 translation %016llx -> PAR_EL1 = ", addr);
db_par_print(par, addr);
reg_s1e1r_write(addr);
- __asm __volatile
CVS commit: src/sys/arch/aarch64/aarch64
Module Name:src
Committed By: ryo
Date: Thu Oct 22 07:16:06 UTC 2020
Modified Files:
src/sys/arch/aarch64/aarch64: locore.S
Log Message:
Don't trap EL0 accesses to the DCC registers.
VMWare use "mrs xzr, mdccsr_el0" for guest side backdoor.
To generate a diff of this commit:
cvs rdiff -u -r1.73 -r1.74 src/sys/arch/aarch64/aarch64/locore.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/aarch64/aarch64/locore.S
diff -u src/sys/arch/aarch64/aarch64/locore.S:1.73 src/sys/arch/aarch64/aarch64/locore.S:1.74
--- src/sys/arch/aarch64/aarch64/locore.S:1.73 Tue Sep 15 09:28:20 2020
+++ src/sys/arch/aarch64/aarch64/locore.S Thu Oct 22 07:16:06 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: locore.S,v 1.73 2020/09/15 09:28:20 ryo Exp $ */
+/* $NetBSD: locore.S,v 1.74 2020/10/22 07:16:06 ryo Exp $ */
/*
* Copyright (c) 2017 Ryo Shimizu
@@ -38,7 +38,7 @@
#include
#include "assym.h"
-RCSID("$NetBSD: locore.S,v 1.73 2020/09/15 09:28:20 ryo Exp $")
+RCSID("$NetBSD: locore.S,v 1.74 2020/10/22 07:16:06 ryo Exp $")
#ifdef AARCH64_DEVICE_MEM_STRONGLY_ORDERED
#define MAIR_DEVICE_MEM MAIR_DEVICE_nGnRnE
@@ -241,9 +241,8 @@ ASEND(clear_bss)
init_sysregs:
stp x0, lr, [sp, #-16]!
- /* init debug event */
- ldr x0, mdscr_setting
- msr mdscr_el1, x0
+ /* init debug registers */
+ msr mdscr_el1, xzr
msr oslar_el1, xzr
/* Clear context id register */
@@ -1041,11 +1040,6 @@ sctlr_pac:
SCTLR_EnDB |/* PACDB (APDBKey_EL1) instruction enable */ \
0)
-mdscr_setting:
- .quad ( \
- MDSCR_TDCC |/* Trap Debug Communications Channel access */ \
- 0)
-
.L_devmap_addr:
.quad VM_KERNEL_IO_ADDRESS
CVS commit: src/sys/arch/aarch64/aarch64
Module Name:src
Committed By: rin
Date: Thu Oct 15 23:15:36 UTC 2020
Modified Files:
src/sys/arch/aarch64/aarch64: trap.c
Log Message:
Byte-swapping instructions for arm and thumb on aarch64eb;
instructions are stored in little-endian byte-order for BE8,
an only valid binary format for ILP32BE executables.
XXX
Apply similar fixes to armv7{,hf}eb.
To generate a diff of this commit:
cvs rdiff -u -r1.37 -r1.38 src/sys/arch/aarch64/aarch64/trap.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/aarch64/aarch64/trap.c
diff -u src/sys/arch/aarch64/aarch64/trap.c:1.37 src/sys/arch/aarch64/aarch64/trap.c:1.38
--- src/sys/arch/aarch64/aarch64/trap.c:1.37 Mon Sep 14 10:53:02 2020
+++ src/sys/arch/aarch64/aarch64/trap.c Thu Oct 15 23:15:36 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: trap.c,v 1.37 2020/09/14 10:53:02 ryo Exp $ */
+/* $NetBSD: trap.c,v 1.38 2020/10/15 23:15:36 rin Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -31,7 +31,7 @@
#include
-__KERNEL_RCSID(1, "$NetBSD: trap.c,v 1.37 2020/09/14 10:53:02 ryo Exp $");
+__KERNEL_RCSID(1, "$NetBSD: trap.c,v 1.38 2020/10/15 23:15:36 rin Exp $");
#include "opt_arm_intr_impl.h"
#include "opt_compat_netbsd32.h"
@@ -532,6 +532,12 @@ int
fetch_arm_insn(uint64_t pc, uint64_t spsr, uint32_t *insn)
{
+ /*
+ * Instructions are stored in little endian for BE8,
+ * only a valid binary format for ILP32EB. Therefore,
+ * we need byte-swapping before decoding on aarch64eb.
+ */
+
/* THUMB? */
if (spsr & SPSR_A32_T) {
uint16_t *p = (uint16_t *)(pc & ~1UL); /* XXX */
@@ -539,6 +545,7 @@ fetch_arm_insn(uint64_t pc, uint64_t sps
if (ufetch_16(p, ))
return -1;
+ LE16TOH(hi);
if (!THUMB_32BIT(hi)) {
/* 16-bit Thumb instruction */
@@ -549,6 +556,7 @@ fetch_arm_insn(uint64_t pc, uint64_t sps
/* 32-bit Thumb instruction */
if (ufetch_16(p + 1, ))
return -1;
+ LE16TOH(lo);
*insn = ((uint32_t)hi << 16) | lo;
return 4;
@@ -556,6 +564,7 @@ fetch_arm_insn(uint64_t pc, uint64_t sps
if (ufetch_32((uint32_t *)pc, insn))
return -1;
+ LE32TOH(*insn);
return 4;
}
CVS commit: src/sys/arch/aarch64/aarch64
Module Name:src Committed By: rin Date: Thu Oct 15 23:10:06 UTC 2020 Modified Files: src/sys/arch/aarch64/aarch64: netbsd32_machdep.c Log Message: Call netbsd32_adjust_limits() in netbsd32_setregs() for sure, as done for amd64 and sparc64. To generate a diff of this commit: cvs rdiff -u -r1.15 -r1.16 src/sys/arch/aarch64/aarch64/netbsd32_machdep.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/aarch64/aarch64/netbsd32_machdep.c diff -u src/sys/arch/aarch64/aarch64/netbsd32_machdep.c:1.15 src/sys/arch/aarch64/aarch64/netbsd32_machdep.c:1.16 --- src/sys/arch/aarch64/aarch64/netbsd32_machdep.c:1.15 Thu Oct 15 22:41:02 2020 +++ src/sys/arch/aarch64/aarch64/netbsd32_machdep.c Thu Oct 15 23:10:06 2020 @@ -1,4 +1,4 @@ -/* $NetBSD: netbsd32_machdep.c,v 1.15 2020/10/15 22:41:02 rin Exp $ */ +/* $NetBSD: netbsd32_machdep.c,v 1.16 2020/10/15 23:10:06 rin Exp $ */ /* * Copyright (c) 2018 Ryo Shimizu @@ -27,7 +27,7 @@ */ #include -__KERNEL_RCSID(0, "$NetBSD: netbsd32_machdep.c,v 1.15 2020/10/15 22:41:02 rin Exp $"); +__KERNEL_RCSID(0, "$NetBSD: netbsd32_machdep.c,v 1.16 2020/10/15 23:10:06 rin Exp $"); #if defined(_KERNEL_OPT) #include "opt_compat_netbsd.h" @@ -64,6 +64,8 @@ netbsd32_setregs(struct lwp *l, struct e struct proc * const p = l->l_proc; struct trapframe * const tf = l->l_md.md_utf; + netbsd32_adjust_limits(p); + aarch64_setregs_ptrauth(l, false); p->p_flag |= PK_32;
CVS commit: src/sys/arch/aarch64/aarch64
Module Name:src
Committed By: rin
Date: Thu Oct 15 22:52:08 UTC 2020
Modified Files:
src/sys/arch/aarch64/aarch64: vm_machdep.c
Log Message:
Fix clone(2) for COMPAT_NETBSD32.
(1) Set r13 (sp for arm32 processes) appropriately when stack is
specified to fork1().
(2) For arm32 processes, align stack to 8-byte boundary, instead of
16-byte for native aarch64 processes, to match our 32-bit ABI:
https://nxr.netbsd.org/xref/src/sys/arch/arm/arm32/vm_machdep.c#150
Note that sp alignment checking is disabled in aarch32 mode, and
this works fine with AARCH64_EL0_STACK_ALIGNMENT_CHECK option.
OK ryo
To generate a diff of this commit:
cvs rdiff -u -r1.8 -r1.9 src/sys/arch/aarch64/aarch64/vm_machdep.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/aarch64/aarch64/vm_machdep.c
diff -u src/sys/arch/aarch64/aarch64/vm_machdep.c:1.8 src/sys/arch/aarch64/aarch64/vm_machdep.c:1.9
--- src/sys/arch/aarch64/aarch64/vm_machdep.c:1.8 Sat May 23 18:08:59 2020
+++ src/sys/arch/aarch64/aarch64/vm_machdep.c Thu Oct 15 22:52:08 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: vm_machdep.c,v 1.8 2020/05/23 18:08:59 ryo Exp $ */
+/* $NetBSD: vm_machdep.c,v 1.9 2020/10/15 22:52:08 rin Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -29,10 +29,11 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
+#include "opt_compat_netbsd32.h"
#include "opt_ddb.h"
#include
-__KERNEL_RCSID(0, "$NetBSD: vm_machdep.c,v 1.8 2020/05/23 18:08:59 ryo Exp $");
+__KERNEL_RCSID(0, "$NetBSD: vm_machdep.c,v 1.9 2020/10/15 22:52:08 rin Exp $");
#include
#include
@@ -143,11 +144,19 @@ cpu_lwp_fork(struct lwp *l1, struct lwp
*utf = *l1->l_md.md_utf;
/*
- * If specified, give the child a different stack
- * (make sure it's 16-byte aligned).
+ * If specified, give the child a different stack (make sure it's
+ * 16- or 8-byte aligned for 64- or 32-bit processes, respectively).
*/
- if (stack != NULL)
- utf->tf_sp = ((vaddr_t)(stack) + stacksize) & -16;
+ if (stack != NULL) {
+ utf->tf_sp = (vaddr_t)(stack) + stacksize;
+#ifdef COMPAT_NETBSD32
+ if (__predict_false(l2->l_proc->p_flag & PK_32)) {
+ utf->tf_sp &= -8;
+ utf->tf_reg[13] = utf->tf_sp;
+ } else
+#endif
+ utf->tf_sp &= -16;
+ }
/* build a new switchframe */
struct trapframe * const ktf = utf - 1;
CVS commit: src/sys/arch/aarch64/aarch64
Module Name:src Committed By: rin Date: Thu Oct 15 22:41:02 UTC 2020 Modified Files: src/sys/arch/aarch64/aarch64: netbsd32_machdep.c Log Message: For rev 1.14 and before, netbsd32_process_write_regs() returns EINVAL if non-modifiable bits are set in CPSR. Instead, mask out non-modifiable bits and make this function success regardless of value in CPSR. New behavior matches that of arm: https://nxr.netbsd.org/xref/src/sys/arch/arm/arm/process_machdep.c#187 This fixes lib/libc/sys/t_ptrace_wait*:access_regs6 tests, in which register contents retrieved by PT_GETREGS are set back by PT_SETREGS. No new regression is observed in full ATF run. OK ryo To generate a diff of this commit: cvs rdiff -u -r1.14 -r1.15 src/sys/arch/aarch64/aarch64/netbsd32_machdep.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/aarch64/aarch64/netbsd32_machdep.c diff -u src/sys/arch/aarch64/aarch64/netbsd32_machdep.c:1.14 src/sys/arch/aarch64/aarch64/netbsd32_machdep.c:1.15 --- src/sys/arch/aarch64/aarch64/netbsd32_machdep.c:1.14 Thu Jul 2 13:04:46 2020 +++ src/sys/arch/aarch64/aarch64/netbsd32_machdep.c Thu Oct 15 22:41:02 2020 @@ -1,4 +1,4 @@ -/* $NetBSD: netbsd32_machdep.c,v 1.14 2020/07/02 13:04:46 rin Exp $ */ +/* $NetBSD: netbsd32_machdep.c,v 1.15 2020/10/15 22:41:02 rin Exp $ */ /* * Copyright (c) 2018 Ryo Shimizu @@ -27,7 +27,7 @@ */ #include -__KERNEL_RCSID(0, "$NetBSD: netbsd32_machdep.c,v 1.14 2020/07/02 13:04:46 rin Exp $"); +__KERNEL_RCSID(0, "$NetBSD: netbsd32_machdep.c,v 1.15 2020/10/15 22:41:02 rin Exp $"); #if defined(_KERNEL_OPT) #include "opt_compat_netbsd.h" @@ -198,8 +198,7 @@ netbsd32_process_write_regs(struct lwp * if ((p->p_flag & PK_32) == 0) return EINVAL; - if ((regs->r_cpsr & ~(SPSR_NZCV | SPSR_A32_T)) != 0 || - regs->r_pc >= VM_MAXUSER_ADDRESS32 || + if (regs->r_pc >= VM_MAXUSER_ADDRESS32 || regs->r_sp >= VM_MAXUSER_ADDRESS32) return EINVAL; @@ -209,7 +208,7 @@ netbsd32_process_write_regs(struct lwp * tf->tf_reg[14] = regs->r_lr; /* r14 = lr */ tf->tf_pc = regs->r_pc; /* r15 = pc */ tf->tf_spsr &= ~(SPSR_NZCV | SPSR_A32_T); - tf->tf_spsr |= regs->r_cpsr; + tf->tf_spsr |= regs->r_cpsr & (SPSR_NZCV | SPSR_A32_T); /* THUMB CODE? */ if (regs->r_pc & 1)
CVS commit: src/sys/arch/aarch64/aarch64
Module Name:src
Committed By: rin
Date: Thu Oct 15 22:30:34 UTC 2020
Modified Files:
src/sys/arch/aarch64/aarch64: fault.c
Log Message:
For cpu_jump_onfault() in data_abort_handler(), stop returning
hard-coded EFAULT and use return value from uvm_fault() instead.
There are some paths that do not call uvm_fault():
(1) For fatalabort case, use EFAULT as before.
(2) When va range is invalid, use EFAULT instead of EINVAL.
These change fixes bytes_transfer_eof_* tests in
sys/lib/libc/sys/t_ptrace_wait*.
Note that without (2) above, some tests like
sys/lib/libc/sys/t_wait:write_error become newly failing.
I've confirmed that there's no new regression in full ATF run.
OK ryo
To generate a diff of this commit:
cvs rdiff -u -r1.19 -r1.20 src/sys/arch/aarch64/aarch64/fault.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/aarch64/aarch64/fault.c
diff -u src/sys/arch/aarch64/aarch64/fault.c:1.19 src/sys/arch/aarch64/aarch64/fault.c:1.20
--- src/sys/arch/aarch64/aarch64/fault.c:1.19 Sun Aug 9 07:26:20 2020
+++ src/sys/arch/aarch64/aarch64/fault.c Thu Oct 15 22:30:34 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: fault.c,v 1.19 2020/08/09 07:26:20 skrll Exp $ */
+/* $NetBSD: fault.c,v 1.20 2020/10/15 22:30:34 rin Exp $ */
/*
* Copyright (c) 2017 Ryo Shimizu
@@ -27,7 +27,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: fault.c,v 1.19 2020/08/09 07:26:20 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: fault.c,v 1.20 2020/10/15 22:30:34 rin Exp $");
#include "opt_compat_netbsd32.h"
#include "opt_ddb.h"
@@ -134,7 +134,7 @@ data_abort_handler(struct trapframe *tf,
vaddr_t va;
uint32_t esr, fsc, rw;
vm_prot_t ftype;
- int error = 0, len;
+ int error = EFAULT, len;
const bool user = IS_SPSR_USER(tf->tf_spsr) ? true : false;
bool is_pan_trap = false;
@@ -169,10 +169,8 @@ data_abort_handler(struct trapframe *tf,
map = >p_vmspace->vm_map;
UVMHIST_LOG(pmaphist, "use user vm_map %p (kernel_map=%p)",
map, kernel_map, 0, 0);
- } else {
- error = EINVAL;
+ } else
goto do_fault;
- }
if ((eclass == ESR_EC_INSN_ABT_EL0) || (eclass == ESR_EC_INSN_ABT_EL1))
ftype = VM_PROT_EXECUTE;
@@ -223,7 +221,7 @@ data_abort_handler(struct trapframe *tf,
if (curcpu()->ci_intr_depth == 0) {
fb = cpu_disable_onfault();
if (fb != NULL) {
- cpu_jump_onfault(tf, fb, EFAULT);
+ cpu_jump_onfault(tf, fb, error);
return;
}
}
CVS commit: src/sys/arch/aarch64/aarch64
Module Name:src
Committed By: jmcneill
Date: Thu Oct 15 21:14:15 UTC 2020
Modified Files:
src/sys/arch/aarch64/aarch64: bus_space.c
Log Message:
Reduce scope of memory barriers use in bus_space_barrier() implementation.
Instead of always "dsb sy", use "dsb ishld" for reads, "dsb ishst" for
writes, and "dsh ish" for reads and writes.
Ok skrll@
To generate a diff of this commit:
cvs rdiff -u -r1.10 -r1.11 src/sys/arch/aarch64/aarch64/bus_space.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/aarch64/aarch64/bus_space.c
diff -u src/sys/arch/aarch64/aarch64/bus_space.c:1.10 src/sys/arch/aarch64/aarch64/bus_space.c:1.11
--- src/sys/arch/aarch64/aarch64/bus_space.c:1.10 Sat Sep 5 16:44:54 2020
+++ src/sys/arch/aarch64/aarch64/bus_space.c Thu Oct 15 21:14:15 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: bus_space.c,v 1.10 2020/09/05 16:44:54 jakllsch Exp $ */
+/* $NetBSD: bus_space.c,v 1.11 2020/10/15 21:14:15 jmcneill Exp $ */
/*
* Copyright (c) 2017 Ryo Shimizu
@@ -27,7 +27,7 @@
*/
#include
-__KERNEL_RCSID(1, "$NetBSD: bus_space.c,v 1.10 2020/09/05 16:44:54 jakllsch Exp $");
+__KERNEL_RCSID(1, "$NetBSD: bus_space.c,v 1.11 2020/10/15 21:14:15 jmcneill Exp $");
#include
#include
@@ -38,6 +38,7 @@ __KERNEL_RCSID(1, "$NetBSD: bus_space.c,
#include
#include
+#include
/* Prototypes for all the bus_space structure functions */
bs_protos(generic)
@@ -612,8 +613,17 @@ generic_bs_barrier(void *t, bus_space_ha
{
flags &= BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE;
- if (flags != 0)
- __asm __volatile ("dmb sy" ::: "memory");
+ switch (flags) {
+ case BUS_SPACE_BARRIER_READ:
+ dmb(ishld);
+ break;
+ case BUS_SPACE_BARRIER_WRITE:
+ dmb(ishst);
+ break;
+ case BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE:
+ dmb(ish);
+ break;
+ }
}
void *
CVS commit: src/sys/arch/aarch64/aarch64
Module Name:src
Committed By: ryo
Date: Thu Oct 15 08:37:20 UTC 2020
Modified Files:
src/sys/arch/aarch64/aarch64: vectors.S
Log Message:
slightly optimized loop for trap_doast() calls
To generate a diff of this commit:
cvs rdiff -u -r1.20 -r1.21 src/sys/arch/aarch64/aarch64/vectors.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/aarch64/aarch64/vectors.S
diff -u src/sys/arch/aarch64/aarch64/vectors.S:1.20 src/sys/arch/aarch64/aarch64/vectors.S:1.21
--- src/sys/arch/aarch64/aarch64/vectors.S:1.20 Tue Oct 6 06:26:46 2020
+++ src/sys/arch/aarch64/aarch64/vectors.S Thu Oct 15 08:37:20 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: vectors.S,v 1.20 2020/10/06 06:26:46 skrll Exp $ */
+/* $NetBSD: vectors.S,v 1.21 2020/10/15 08:37:20 ryo Exp $ */
#include
#include
@@ -10,7 +10,7 @@
#include "opt_ddb.h"
#include "opt_dtrace.h"
-RCSID("$NetBSD: vectors.S,v 1.20 2020/10/06 06:26:46 skrll Exp $")
+RCSID("$NetBSD: vectors.S,v 1.21 2020/10/15 08:37:20 ryo Exp $")
ARMV8_DEFINE_OPTIONS
@@ -255,26 +255,26 @@ ENTRY_NP(el0_trap)
nop/* dummy for DDB backtrace (for lr-4) */
#endif
ENTRY_NP(el0_trap_exit)
- DISABLE_INTERRUPT /* make sure I|F marked */
+
+ adr lr, 1f /* return address from trap_doast */
1:
/* while (curlwp->l_md.md_astpending != 0) { */
- mrs x8, tpidr_el1
- ldr w9, [x8, #L_MD_ASTPENDING]
- cbz w9, 9f
+ DISABLE_INTERRUPT /* make sure I|F marked */
+ mrs x9, tpidr_el1
+ ldr w8, [x9, #L_MD_ASTPENDING]
+ cbz w8, 9f
/* curlwp->l_md.md_astpending = 0; */
- str xzr, [x8, #L_MD_ASTPENDING]
+ str xzr, [x9, #L_MD_ASTPENDING]
/* trap_doast(tf); */
ENABLE_INTERRUPT
mov x0, sp
- bl _C_LABEL(trap_doast)
- DISABLE_INTERRUPT
- b 1b
+ b _C_LABEL(trap_doast) /* tail call (return to 1b) */
/* } */
9:
- mrs x9, tpidr_el1
+ /* x9 is tpidr_el1 */
ldr x23, [x9, #L_MD_CPACR]
msr cpacr_el1, x23 /* FP unit EL0 handover */
isb/* necessary? */
CVS commit: src/sys/arch/aarch64/aarch64
Module Name:src
Committed By: skrll
Date: Tue Oct 13 21:27:18 UTC 2020
Modified Files:
src/sys/arch/aarch64/aarch64: lock_stubs.S
Log Message:
Use load-acquire exclusive and store-release exclusive (and remove the
barrier instructions) as suggested by riastradh a little while ago.
To generate a diff of this commit:
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/aarch64/aarch64/lock_stubs.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/aarch64/aarch64/lock_stubs.S
diff -u src/sys/arch/aarch64/aarch64/lock_stubs.S:1.2 src/sys/arch/aarch64/aarch64/lock_stubs.S:1.3
--- src/sys/arch/aarch64/aarch64/lock_stubs.S:1.2 Thu Aug 13 07:14:04 2020
+++ src/sys/arch/aarch64/aarch64/lock_stubs.S Tue Oct 13 21:27:18 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: lock_stubs.S,v 1.2 2020/08/13 07:14:04 skrll Exp $ */
+/* $NetBSD: lock_stubs.S,v 1.3 2020/10/13 21:27:18 skrll Exp $ */
/*-
* Copyright (c) 2014, 2020 The NetBSD Foundation, Inc.
@@ -35,7 +35,7 @@
#include "assym.h"
-RCSID("$NetBSD: lock_stubs.S,v 1.2 2020/08/13 07:14:04 skrll Exp $")
+RCSID("$NetBSD: lock_stubs.S,v 1.3 2020/10/13 21:27:18 skrll Exp $")
#ifndef LOCKDEBUG
/*
@@ -45,11 +45,10 @@ RCSID("$NetBSD: lock_stubs.S,v 1.2 2020/
ENTRY(mutex_enter)
mrs x1, tpidr_el1 /* x1 = curlwp */
1:
- ldxr x2, [x0] /* load old value */
+ ldaxr x2, [x0] /* load old value */
cbnz x2, 3f /* equals zero? */
stxr w3, x1, [x0] /* store curlwp as new value */
cbnz w3, 2f /* succeed? nope, try again. */
- dmb sy /* membar_enter() */
ret
2:
b 1b
@@ -64,13 +63,12 @@ END(mutex_enter)
* so just use ldxr+stxr to achieve the same.
*/
ENTRY(mutex_exit)
- dmb sy /* membar_exit() */
mrs x1, tpidr_el1 /* x1 = curlwp */
1:
ldxr x2, [x0] /* load old value */
cmp x1, x2 /* equals curlwp? */
b.ne 3f /* slow path if different */
- stxr w3, xzr, [x0] /* store zero as new value */
+ stlxr w3, xzr, [x0] /* store zero as new value */
cbnz w3, 2f /* succeed? nope, try again. */
ret
2:
CVS commit: src/sys/arch/aarch64/aarch64
Module Name:src
Committed By: skrll
Date: Tue Oct 13 21:24:22 UTC 2020
Modified Files:
src/sys/arch/aarch64/aarch64: cpuswitch.S
Log Message:
Use corrcet membar_exit barrier
To generate a diff of this commit:
cvs rdiff -u -r1.29 -r1.30 src/sys/arch/aarch64/aarch64/cpuswitch.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/aarch64/aarch64/cpuswitch.S
diff -u src/sys/arch/aarch64/aarch64/cpuswitch.S:1.29 src/sys/arch/aarch64/aarch64/cpuswitch.S:1.30
--- src/sys/arch/aarch64/aarch64/cpuswitch.S:1.29 Tue Oct 6 06:26:46 2020
+++ src/sys/arch/aarch64/aarch64/cpuswitch.S Tue Oct 13 21:24:22 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: cpuswitch.S,v 1.29 2020/10/06 06:26:46 skrll Exp $ */
+/* $NetBSD: cpuswitch.S,v 1.30 2020/10/13 21:24:22 skrll Exp $ */
/*-
* Copyright (c) 2014, 2020 The NetBSD Foundation, Inc.
@@ -38,7 +38,7 @@
#include "opt_ddb.h"
#include "opt_kasan.h"
-RCSID("$NetBSD: cpuswitch.S,v 1.29 2020/10/06 06:26:46 skrll Exp $")
+RCSID("$NetBSD: cpuswitch.S,v 1.30 2020/10/13 21:24:22 skrll Exp $")
ARMV8_DEFINE_OPTIONS
@@ -119,7 +119,7 @@ ENTRY_NP(cpu_switchto)
msr tpidr_el1, x1 /* switch curlwp to new lwp */
ldr x3, [x1, #L_CPU]
str x1, [x3, #CI_CURLWP] /* switch curlwp to new lwp */
- dmb st /* see comments in kern_mutex.c */
+ dmb ishst /* see comments in kern_mutex.c */
ENABLE_INTERRUPT
/*
CVS commit: src/sys/arch/aarch64/aarch64
Module Name:src Committed By: rin Date: Tue Oct 13 07:04:49 UTC 2020 Modified Files: src/sys/arch/aarch64/aarch64: exec_machdep.c Log Message: BE32 binaries are no longer supported for ARMv7 and later, and therefore for aarch64eb. Reject them with ENOEXEC, rather than causing illegal instruction exceptions due to unexpected binary format. To generate a diff of this commit: cvs rdiff -u -r1.7 -r1.8 src/sys/arch/aarch64/aarch64/exec_machdep.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/aarch64/aarch64/exec_machdep.c diff -u src/sys/arch/aarch64/aarch64/exec_machdep.c:1.7 src/sys/arch/aarch64/aarch64/exec_machdep.c:1.8 --- src/sys/arch/aarch64/aarch64/exec_machdep.c:1.7 Sat May 23 18:08:59 2020 +++ src/sys/arch/aarch64/aarch64/exec_machdep.c Tue Oct 13 07:04:49 2020 @@ -1,4 +1,4 @@ -/* $NetBSD: exec_machdep.c,v 1.7 2020/05/23 18:08:59 ryo Exp $ */ +/* $NetBSD: exec_machdep.c,v 1.8 2020/10/13 07:04:49 rin Exp $ */ /*- * Copyright (c) 2014 The NetBSD Foundation, Inc. @@ -31,7 +31,7 @@ #include -__KERNEL_RCSID(1, "$NetBSD: exec_machdep.c,v 1.7 2020/05/23 18:08:59 ryo Exp $"); +__KERNEL_RCSID(1, "$NetBSD: exec_machdep.c,v 1.8 2020/10/13 07:04:49 rin Exp $"); #include "opt_compat_netbsd.h" #include "opt_compat_netbsd32.h" @@ -77,6 +77,11 @@ aarch64_netbsd_elf32_probe(struct lwp *l /* OABI not support */ if (!elf_aapcs_p) return ENOEXEC; +#ifdef __AARCH64EB__ + /* BE32 not support */ + if ((eh->e_flags & EF_ARM_BE8) == 0) + return ENOEXEC; +#endif /* * require aarch32 feature.
CVS commit: src/sys/arch/aarch64/aarch64
Module Name:src
Committed By: jmcneill
Date: Sat Oct 10 08:22:57 UTC 2020
Modified Files:
src/sys/arch/aarch64/aarch64: cpu.c
Log Message:
Fix detection of FP and SIMD features on Armv8.2+.
To generate a diff of this commit:
cvs rdiff -u -r1.55 -r1.56 src/sys/arch/aarch64/aarch64/cpu.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/aarch64/aarch64/cpu.c
diff -u src/sys/arch/aarch64/aarch64/cpu.c:1.55 src/sys/arch/aarch64/aarch64/cpu.c:1.56
--- src/sys/arch/aarch64/aarch64/cpu.c:1.55 Wed Oct 7 16:03:10 2020
+++ src/sys/arch/aarch64/aarch64/cpu.c Sat Oct 10 08:22:57 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu.c,v 1.55 2020/10/07 16:03:10 jmcneill Exp $ */
+/* $NetBSD: cpu.c,v 1.56 2020/10/10 08:22:57 jmcneill Exp $ */
/*
* Copyright (c) 2017 Ryo Shimizu
@@ -27,7 +27,7 @@
*/
#include
-__KERNEL_RCSID(1, "$NetBSD: cpu.c,v 1.55 2020/10/07 16:03:10 jmcneill Exp $");
+__KERNEL_RCSID(1, "$NetBSD: cpu.c,v 1.56 2020/10/10 08:22:57 jmcneill Exp $");
#include "locators.h"
#include "opt_arm_debug.h"
@@ -378,7 +378,9 @@ cpu_identify2(device_t self, struct cpu_
break;
}
switch (__SHIFTOUT(id->ac_aa64pfr0, ID_AA64PFR0_EL1_FP)) {
- case ID_AA64PFR0_EL1_FP_IMPL:
+ case ID_AA64PFR0_EL1_FP_NONE:
+ break;
+ default:
aprint_verbose(", FP");
break;
}
@@ -422,7 +424,9 @@ cpu_identify2(device_t self, struct cpu_
/* PFR0:AdvSIMD */
switch (__SHIFTOUT(id->ac_aa64pfr0, ID_AA64PFR0_EL1_ADVSIMD)) {
- case ID_AA64PFR0_EL1_ADV_SIMD_IMPL:
+ case ID_AA64PFR0_EL1_ADV_SIMD_NONE:
+ break;
+ default:
aprint_verbose(", NEON");
break;
}
CVS commit: src/sys/arch/aarch64/aarch64
Module Name:src
Committed By: jmcneill
Date: Wed Oct 7 16:03:10 UTC 2020
Modified Files:
src/sys/arch/aarch64/aarch64: cpu.c
Log Message:
Only touch PMC registers if Performance Monitor Extensions are present.
To generate a diff of this commit:
cvs rdiff -u -r1.54 -r1.55 src/sys/arch/aarch64/aarch64/cpu.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/aarch64/aarch64/cpu.c
diff -u src/sys/arch/aarch64/aarch64/cpu.c:1.54 src/sys/arch/aarch64/aarch64/cpu.c:1.55
--- src/sys/arch/aarch64/aarch64/cpu.c:1.54 Sat Jul 25 22:51:57 2020
+++ src/sys/arch/aarch64/aarch64/cpu.c Wed Oct 7 16:03:10 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu.c,v 1.54 2020/07/25 22:51:57 riastradh Exp $ */
+/* $NetBSD: cpu.c,v 1.55 2020/10/07 16:03:10 jmcneill Exp $ */
/*
* Copyright (c) 2017 Ryo Shimizu
@@ -27,7 +27,7 @@
*/
#include
-__KERNEL_RCSID(1, "$NetBSD: cpu.c,v 1.54 2020/07/25 22:51:57 riastradh Exp $");
+__KERNEL_RCSID(1, "$NetBSD: cpu.c,v 1.55 2020/10/07 16:03:10 jmcneill Exp $");
#include "locators.h"
#include "opt_arm_debug.h"
@@ -472,6 +472,13 @@ cpu_identify2(device_t self, struct cpu_
static void
cpu_init_counter(struct cpu_info *ci)
{
+ const uint64_t dfr0 = reg_id_aa64dfr0_el1_read();
+ const u_int pmuver = __SHIFTOUT(dfr0, ID_AA64DFR0_EL1_PMUVER);
+ if (pmuver == ID_AA64DFR0_EL1_PMUVER_NONE) {
+ /* Performance Monitors Extension not implemented. */
+ return;
+ }
+
reg_pmcr_el0_write(PMCR_E | PMCR_C);
reg_pmcntenset_el0_write(PMCNTEN_C);
CVS commit: src/sys/arch/aarch64/aarch64
Module Name:src
Committed By: skrll
Date: Tue Oct 6 06:26:46 UTC 2020
Modified Files:
src/sys/arch/aarch64/aarch64: cpuswitch.S vectors.S
Log Message:
move #include "opt_compat_netbsd32.h" to where it's required
To generate a diff of this commit:
cvs rdiff -u -r1.28 -r1.29 src/sys/arch/aarch64/aarch64/cpuswitch.S
cvs rdiff -u -r1.19 -r1.20 src/sys/arch/aarch64/aarch64/vectors.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/aarch64/aarch64/cpuswitch.S
diff -u src/sys/arch/aarch64/aarch64/cpuswitch.S:1.28 src/sys/arch/aarch64/aarch64/cpuswitch.S:1.29
--- src/sys/arch/aarch64/aarch64/cpuswitch.S:1.28 Wed Sep 30 16:35:49 2020
+++ src/sys/arch/aarch64/aarch64/cpuswitch.S Tue Oct 6 06:26:46 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: cpuswitch.S,v 1.28 2020/09/30 16:35:49 skrll Exp $ */
+/* $NetBSD: cpuswitch.S,v 1.29 2020/10/06 06:26:46 skrll Exp $ */
/*-
* Copyright (c) 2014, 2020 The NetBSD Foundation, Inc.
@@ -34,12 +34,11 @@
#include "assym.h"
-#include "opt_compat_netbsd32.h"
#include "opt_cpuoptions.h"
#include "opt_ddb.h"
#include "opt_kasan.h"
-RCSID("$NetBSD: cpuswitch.S,v 1.28 2020/09/30 16:35:49 skrll Exp $")
+RCSID("$NetBSD: cpuswitch.S,v 1.29 2020/10/06 06:26:46 skrll Exp $")
ARMV8_DEFINE_OPTIONS
Index: src/sys/arch/aarch64/aarch64/vectors.S
diff -u src/sys/arch/aarch64/aarch64/vectors.S:1.19 src/sys/arch/aarch64/aarch64/vectors.S:1.20
--- src/sys/arch/aarch64/aarch64/vectors.S:1.19 Wed Sep 30 16:35:49 2020
+++ src/sys/arch/aarch64/aarch64/vectors.S Tue Oct 6 06:26:46 2020
@@ -1,15 +1,16 @@
-/* $NetBSD: vectors.S,v 1.19 2020/09/30 16:35:49 skrll Exp $ */
+/* $NetBSD: vectors.S,v 1.20 2020/10/06 06:26:46 skrll Exp $ */
#include
#include
#include "assym.h"
+#include "opt_compat_netbsd32.h"
#include "opt_cpuoptions.h"
#include "opt_ddb.h"
#include "opt_dtrace.h"
-RCSID("$NetBSD: vectors.S,v 1.19 2020/09/30 16:35:49 skrll Exp $")
+RCSID("$NetBSD: vectors.S,v 1.20 2020/10/06 06:26:46 skrll Exp $")
ARMV8_DEFINE_OPTIONS
CVS commit: src/sys/arch/aarch64/aarch64
Module Name:src Committed By: skrll Date: Sun Oct 4 08:09:12 UTC 2020 Modified Files: src/sys/arch/aarch64/aarch64: aarch64_machdep.c Log Message: KNF To generate a diff of this commit: cvs rdiff -u -r1.50 -r1.51 src/sys/arch/aarch64/aarch64/aarch64_machdep.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/aarch64/aarch64/aarch64_machdep.c diff -u src/sys/arch/aarch64/aarch64/aarch64_machdep.c:1.50 src/sys/arch/aarch64/aarch64/aarch64_machdep.c:1.51 --- src/sys/arch/aarch64/aarch64/aarch64_machdep.c:1.50 Sat Oct 3 05:56:26 2020 +++ src/sys/arch/aarch64/aarch64/aarch64_machdep.c Sun Oct 4 08:09:12 2020 @@ -1,4 +1,4 @@ -/* $NetBSD: aarch64_machdep.c,v 1.50 2020/10/03 05:56:26 skrll Exp $ */ +/* $NetBSD: aarch64_machdep.c,v 1.51 2020/10/04 08:09:12 skrll Exp $ */ /*- * Copyright (c) 2014 The NetBSD Foundation, Inc. @@ -30,14 +30,14 @@ */ #include -__KERNEL_RCSID(1, "$NetBSD: aarch64_machdep.c,v 1.50 2020/10/03 05:56:26 skrll Exp $"); +__KERNEL_RCSID(1, "$NetBSD: aarch64_machdep.c,v 1.51 2020/10/04 08:09:12 skrll Exp $"); #include "opt_arm_debug.h" #include "opt_cpuoptions.h" #include "opt_ddb.h" +#include "opt_fdt.h" #include "opt_kernhist.h" #include "opt_modular.h" -#include "opt_fdt.h" #include #include
CVS commit: src/sys/arch/aarch64/aarch64
Module Name:src
Committed By: skrll
Date: Sat Oct 3 05:56:26 UTC 2020
Modified Files:
src/sys/arch/aarch64/aarch64: aarch64_machdep.c
Log Message:
G/C
To generate a diff of this commit:
cvs rdiff -u -r1.49 -r1.50 src/sys/arch/aarch64/aarch64/aarch64_machdep.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/aarch64/aarch64/aarch64_machdep.c
diff -u src/sys/arch/aarch64/aarch64/aarch64_machdep.c:1.49 src/sys/arch/aarch64/aarch64/aarch64_machdep.c:1.50
--- src/sys/arch/aarch64/aarch64/aarch64_machdep.c:1.49 Wed Sep 30 16:47:55 2020
+++ src/sys/arch/aarch64/aarch64/aarch64_machdep.c Sat Oct 3 05:56:26 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: aarch64_machdep.c,v 1.49 2020/09/30 16:47:55 skrll Exp $ */
+/* $NetBSD: aarch64_machdep.c,v 1.50 2020/10/03 05:56:26 skrll Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
*/
#include
-__KERNEL_RCSID(1, "$NetBSD: aarch64_machdep.c,v 1.49 2020/09/30 16:47:55 skrll Exp $");
+__KERNEL_RCSID(1, "$NetBSD: aarch64_machdep.c,v 1.50 2020/10/03 05:56:26 skrll Exp $");
#include "opt_arm_debug.h"
#include "opt_cpuoptions.h"
@@ -366,7 +366,7 @@ initarm_common(vaddr_t kvm_base, vsize_t
* order.
*/
paddr_t segend = end;
- for (size_t j = 0; j < nbp; j++ /*, start = segend, segend = end */) {
+ for (size_t j = 0; j < nbp; j++) {
paddr_t bp_start = bp[j].bp_start;
paddr_t bp_end = bp_start + bp[j].bp_pages;
CVS commit: src/sys/arch/aarch64/aarch64
Module Name:src Committed By: skrll Date: Thu Oct 1 07:31:27 UTC 2020 Modified Files: src/sys/arch/aarch64/aarch64: procfs_machdep.c Log Message: KNF (and some newlines) To generate a diff of this commit: cvs rdiff -u -r1.3 -r1.4 src/sys/arch/aarch64/aarch64/procfs_machdep.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/aarch64/aarch64/procfs_machdep.c diff -u src/sys/arch/aarch64/aarch64/procfs_machdep.c:1.3 src/sys/arch/aarch64/aarch64/procfs_machdep.c:1.4 --- src/sys/arch/aarch64/aarch64/procfs_machdep.c:1.3 Thu Oct 1 06:40:16 2020 +++ src/sys/arch/aarch64/aarch64/procfs_machdep.c Thu Oct 1 07:31:27 2020 @@ -1,4 +1,4 @@ -/* $NetBSD: procfs_machdep.c,v 1.3 2020/10/01 06:40:16 ryo Exp $ */ +/* $NetBSD: procfs_machdep.c,v 1.4 2020/10/01 07:31:27 skrll Exp $ */ /*- * Copyright (c) 2020 Ryo Shimizu @@ -27,12 +27,14 @@ */ #include -__KERNEL_RCSID(0, "$NetBSD: procfs_machdep.c,v 1.3 2020/10/01 06:40:16 ryo Exp $"); +__KERNEL_RCSID(0, "$NetBSD: procfs_machdep.c,v 1.4 2020/10/01 07:31:27 skrll Exp $"); #include -#include #include +#include + #include + #include
CVS commit: src/sys/arch/aarch64/aarch64
Module Name:src Committed By: skrll Date: Wed Sep 30 16:47:55 UTC 2020 Modified Files: src/sys/arch/aarch64/aarch64: aarch64_machdep.c Log Message: Improve a comment To generate a diff of this commit: cvs rdiff -u -r1.48 -r1.49 src/sys/arch/aarch64/aarch64/aarch64_machdep.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/aarch64/aarch64/aarch64_machdep.c diff -u src/sys/arch/aarch64/aarch64/aarch64_machdep.c:1.48 src/sys/arch/aarch64/aarch64/aarch64_machdep.c:1.49 --- src/sys/arch/aarch64/aarch64/aarch64_machdep.c:1.48 Wed Sep 16 18:26:15 2020 +++ src/sys/arch/aarch64/aarch64/aarch64_machdep.c Wed Sep 30 16:47:55 2020 @@ -1,4 +1,4 @@ -/* $NetBSD: aarch64_machdep.c,v 1.48 2020/09/16 18:26:15 skrll Exp $ */ +/* $NetBSD: aarch64_machdep.c,v 1.49 2020/09/30 16:47:55 skrll Exp $ */ /*- * Copyright (c) 2014 The NetBSD Foundation, Inc. @@ -30,7 +30,7 @@ */ #include -__KERNEL_RCSID(1, "$NetBSD: aarch64_machdep.c,v 1.48 2020/09/16 18:26:15 skrll Exp $"); +__KERNEL_RCSID(1, "$NetBSD: aarch64_machdep.c,v 1.49 2020/09/30 16:47:55 skrll Exp $"); #include "opt_arm_debug.h" #include "opt_cpuoptions.h" @@ -251,11 +251,10 @@ initarm_common(vaddr_t kvm_base, vsize_t #ifdef MODULAR /* - * aarch64 compiler (gcc & llvm) uses R_AARCH_CALL26/R_AARCH_JUMP26 - * for function calling/jumping. - * (at this time, both compilers doesn't support -mlong-calls) - * therefore kernel modules should be loaded within maximum 26bit word, - * or +-128MB from kernel. + * The aarch64 compilers (gcc & llvm) use R_AARCH_CALL26/R_AARCH_JUMP26 + * for function calls (bl)/jumps(b). At this time, neither compiler + * supports -mlong-calls therefore the kernel modules should be loaded + * within the maximum range of +/-128MB from kernel text. */ #define MODULE_RESERVED_MAX (1024 * 1024 * 128) #define MODULE_RESERVED_SIZE (1024 * 1024 * 32) /* good enough? */
CVS commit: src/sys/arch/aarch64/aarch64
Module Name:src
Committed By: skrll
Date: Wed Sep 30 16:35:49 UTC 2020
Modified Files:
src/sys/arch/aarch64/aarch64: cpuswitch.S vectors.S
Log Message:
Move el[01]_trap_exit into vectors.S where the callers exist
To generate a diff of this commit:
cvs rdiff -u -r1.27 -r1.28 src/sys/arch/aarch64/aarch64/cpuswitch.S
cvs rdiff -u -r1.18 -r1.19 src/sys/arch/aarch64/aarch64/vectors.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/aarch64/aarch64/cpuswitch.S
diff -u src/sys/arch/aarch64/aarch64/cpuswitch.S:1.27 src/sys/arch/aarch64/aarch64/cpuswitch.S:1.28
--- src/sys/arch/aarch64/aarch64/cpuswitch.S:1.27 Sat Sep 26 06:09:33 2020
+++ src/sys/arch/aarch64/aarch64/cpuswitch.S Wed Sep 30 16:35:49 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: cpuswitch.S,v 1.27 2020/09/26 06:09:33 skrll Exp $ */
+/* $NetBSD: cpuswitch.S,v 1.28 2020/09/30 16:35:49 skrll Exp $ */
/*-
* Copyright (c) 2014, 2020 The NetBSD Foundation, Inc.
@@ -31,6 +31,7 @@
#include
#include
+
#include "assym.h"
#include "opt_compat_netbsd32.h"
@@ -38,7 +39,7 @@
#include "opt_ddb.h"
#include "opt_kasan.h"
-RCSID("$NetBSD: cpuswitch.S,v 1.27 2020/09/26 06:09:33 skrll Exp $")
+RCSID("$NetBSD: cpuswitch.S,v 1.28 2020/09/30 16:35:49 skrll Exp $")
ARMV8_DEFINE_OPTIONS
@@ -304,143 +305,6 @@ ENTRY_NP(lwp_trampoline)
br x16 /* call function with arg */
END(lwp_trampoline)
- .macro unwind_x0_x2
- ldp x0, x1, [sp, #TF_X0]
- ldr x2, [sp, #TF_X2]
- .endm
-
- .macro unwind_x3_x30
- ldp x3, x4, [sp, #TF_X3]
- ldp x5, x6, [sp, #TF_X5]
- ldp x7, x8, [sp, #TF_X7]
- ldp x9, x10, [sp, #TF_X9]
- ldp x11, x12, [sp, #TF_X11]
- ldp x13, x14, [sp, #TF_X13]
- ldp x15, x16, [sp, #TF_X15]
- ldp x17, x18, [sp, #TF_X17]
- ldp x19, x20, [sp, #TF_X19]
- ldp x21, x22, [sp, #TF_X21]
- ldp x23, x24, [sp, #TF_X23]
- ldp x25, x26, [sp, #TF_X25]
- ldp x27, x28, [sp, #TF_X27]
- ldp x29, x30, [sp, #TF_X29]
- .endm
-
-/*
- * EL1 exception return for trap and interrupt.
- */
-#ifdef DDB
-ENTRY_NP(el1_trap)
- nop/* dummy for DDB backtrace (for lr-4) */
-#endif
-ENTRY_NP(el1_trap_exit)
- DISABLE_INTERRUPT /* make sure I|F marked */
-
- unwind_x3_x30
-
-#if TF_PC + 8 == TF_SPSR
- ldp x0, x1, [sp, #TF_PC]
-#else
- ldr x0, [sp, #TF_PC]
- ldr x1, [sp, #TF_SPSR]
-#endif
- msr elr_el1, x0 /* exception pc */
- msr spsr_el1, x1 /* exception pstate */
-
- /*
- * cpu_jump_onfault() modify tf->tf_sp, therefore
- * we need to restore sp from trapframe,
- * and unwind x0-x2 without sp.
- */
- mov x0, sp
- ldr x1, [x0, #TF_SP]
- mov sp, x1
- ldp x1, x2, [x0, #TF_X1]
- ldr x0, [x0, #TF_X0]
-
- ERET
-END(el1_trap_exit)
-#ifdef DDB
-END(el1_trap)
-#endif
-
-/*
- * EL0 exception return for trap, interrupt and syscall with
- * possible AST processing.
- */
-#ifdef DDB
-ENTRY_NP(el0_trap)
- nop/* dummy for DDB backtrace (for lr-4) */
-#endif
-ENTRY_NP(el0_trap_exit)
- DISABLE_INTERRUPT /* make sure I|F marked */
-1:
- /* while (curlwp->l_md.md_astpending != 0) { */
- mrs x8, tpidr_el1
- ldr w9, [x8, #L_MD_ASTPENDING]
- cbz w9, 9f
-
- /* curlwp->l_md.md_astpending = 0; */
- str xzr, [x8, #L_MD_ASTPENDING]
-
- /* trap_doast(tf); */
- ENABLE_INTERRUPT
- mov x0, sp
- bl _C_LABEL(trap_doast)
- DISABLE_INTERRUPT
- b 1b
- /* } */
-9:
-
- mrs x9, tpidr_el1
- ldr x23, [x9, #L_MD_CPACR]
- msr cpacr_el1, x23 /* FP unit EL0 handover */
- isb/* necessary? */
-
- ldr x0, [x9, #L_PRIVATE] /* tpidr_el0 = curlwp->l_private */
- msr tpidr_el0, x0
-#ifdef COMPAT_NETBSD32
- msr tpidrro_el0, x0
-#endif
-
-#ifdef ARMV83_PAC
- /* Switch to the user PAC key. */
- adrl x4, _C_LABEL(aarch64_pac_enabled)
- ldr w4, [x4]
- cbz w4, 1f
- ldp x5, x6, [x9, #L_MD_IA_USER]
- msr APIAKeyLo_EL1, x5
- msr APIAKeyHi_EL1, x6
-1:
-#endif
-
- unwind_x3_x30
-
-#if TF_PC + 8 == TF_SPSR
- ldp x0, x1, [sp, #TF_PC]
-#else
- ldr x0, [sp, #TF_PC]
- ldr x1, [sp, #TF_SPSR]
-#endif
- ldr x2, [sp, #TF_SP]
- msr elr_el1, x0 /* exception pc */
- msr spsr_el1, x1 /* exception pstate */
- msr sp_el0, x2 /* restore EL0 stack */
-
- /* if the process is traced, enable MDSCR_EL1.SS */
- tbz x1, #SPSR_SS_SHIFT, 1f
- mrs x0, mdscr_el1
- orr x0, x0, #MDSCR_SS
- msr mdscr_el1, x0
-1:
- unwind_x0_x2
-
- /* leave sp at l_md.md_utf, return back to EL0 user process */
- ERET
-END(el0_trap_exit)
-#ifdef DDB
-END(el0_trap)
-#endif
#ifdef DDB
ENTRY_NP(cpu_Debugger)
Index: src/sys/arch/aarch64/aarch64/vectors.S
diff -u src/sys/arch/aarch64/aarch64/vectors.S:1.18 src/sys/arch/aarch64/aarch64/vectors.S:1.19
--- src/sys/arch/aarch64/aarch64/vectors.S:1.18 Wed Aug 12 13:19:35 2020
+++ src/sys/arch/aarch64/aarch64/vectors.S Wed Sep 30 16:35:49 2020
@@ -1,11 +1,16 @@
-/* $NetBSD: vectors.S,v 1.18 2020/08/12 13:19:35 skrll Exp $ */
+/* $NetBSD: vectors.S,v 1.19 2020/09/30 16:35:49 skrll Exp $ */
#include
+#include
+
#include "assym.h"
+
#include "opt_cpuoptions.h"
#include "opt_ddb.h"
#include
CVS commit: src/sys/arch/aarch64/aarch64
Module Name:src
Committed By: ryo
Date: Wed Sep 30 08:43:47 UTC 2020
Modified Files:
src/sys/arch/aarch64/aarch64: procfs_machdep.c
Log Message:
add linux compatible /proc/cpuinfo
To generate a diff of this commit:
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/aarch64/aarch64/procfs_machdep.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/aarch64/aarch64/procfs_machdep.c
diff -u src/sys/arch/aarch64/aarch64/procfs_machdep.c:1.1 src/sys/arch/aarch64/aarch64/procfs_machdep.c:1.2
--- src/sys/arch/aarch64/aarch64/procfs_machdep.c:1.1 Sun Aug 10 05:47:37 2014
+++ src/sys/arch/aarch64/aarch64/procfs_machdep.c Wed Sep 30 08:43:47 2020
@@ -1,12 +1,9 @@
-/* $NetBSD: procfs_machdep.c,v 1.1 2014/08/10 05:47:37 matt Exp $ */
+/* $NetBSD: procfs_machdep.c,v 1.2 2020/09/30 08:43:47 ryo Exp $ */
/*-
- * Copyright (c) 2014 The NetBSD Foundation, Inc.
+ * Copyright (c) 2020 Ryo Shimizu
* All rights reserved.
*
- * This code is derived from software contributed to The NetBSD Foundation
- * by Matt Thomas of 3am Software Foundry.
- *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
@@ -16,39 +13,202 @@
*notice, this list of conditions and the following disclaimer in the
*documentation and/or other materials provided with the distribution.
*
- * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
- * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
- * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
- * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: procfs_machdep.c,v 1.1 2014/08/10 05:47:37 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: procfs_machdep.c,v 1.2 2020/09/30 08:43:47 ryo Exp $");
#include
-#include
-#include
-#include
-#include
-#include
-
#include
+#include
+
+
+/* use variables named 'buf', 'left', 'total' */
+#define FORWARD_BUF(_len) \
+ do { \
+ total += _len; \
+ if (_len < left) {\
+ buf += _len;\
+ left -= _len;\
+ } else { \
+ buf += left;\
+ left = 0;\
+ } \
+ } while (0 /*CONSTCOND*/)
+
+#define OUTPUT_BUF(fmt, args...)\
+ do { \
+ size_t l = snprintf(buf, left, fmt, ## args); \
+ FORWARD_BUF(l); \
+ } while (0/*CONSTCOND*/)
+
+static int
+procfs_cpuinfo_features(struct cpu_info *ci, char *buf, int buflen)
+{
+ uint64_t isar0, isar1, mmfr2, pfr0, pfr1;
+ size_t left, total;
+
+ isar0 = ci->ci_id.ac_aa64isar0;
+ isar1 = ci->ci_id.ac_aa64isar1;
+ mmfr2 = ci->ci_id.ac_aa64mmfr2;
+ pfr0 = ci->ci_id.ac_aa64pfr0;
+ pfr1 = ci->ci_id.ac_aa64pfr1;
+
+ left = buflen;
+ total = 0;
+
+ /*
+ * I don't know if we need to mimic the order of HWCAP in linux
+ */
+ OUTPUT_BUF("Features\t:");
+#define SO_EQ(reg, mask, val) (__SHIFTOUT((reg), (mask)) == (val))
+ if (SO_EQ(pfr0, ID_AA64PFR0_EL1_FP, ID_AA64PFR0_EL1_FP_IMPL))
+ OUTPUT_BUF(" fp");
+ if (SO_EQ(pfr0, ID_AA64PFR0_EL1_ADVSIMD, ID_AA64PFR0_EL1_ADV_SIMD_IMPL))
+ OUTPUT_BUF(" asimd");
+ /* notyet: " evtstrm" */
+ if (SO_EQ(isar0, ID_AA64ISAR0_EL1_AES, ID_AA64ISAR0_EL1_AES_AES))
+ OUTPUT_BUF(" aes");
+ if (SO_EQ(isar0, ID_AA64ISAR0_EL1_AES, ID_AA64ISAR0_EL1_AES_PMUL))
+ OUTPUT_BUF(" pmull");
+ if (SO_EQ(isar0, ID_AA64ISAR0_EL1_SHA1,
+ ID_AA64ISAR0_EL1_SHA1_SHA1CPMHSU))
+ OUTPUT_BUF(" sha1");
+ if (SO_EQ(isar0, ID_AA64ISAR0_EL1_SHA2,
+ ID_AA64ISAR0_EL1_SHA2_SHA256HSU))
+ OUTPUT_BUF(" sha2");
+ if (SO_EQ(isar0, ID_AA64ISAR0_EL1_CRC32, ID_AA64ISAR0_EL1_CRC32_CRC32X))
+ OUTPUT_BUF(" crc32");
+ if
CVS commit: src/sys/arch/aarch64/aarch64
Module Name:src Committed By: skrll Date: Mon Sep 28 12:04:19 UTC 2020 Modified Files: src/sys/arch/aarch64/aarch64: pmap.c Log Message: Only set pmap_devmap_bootstrap_done if something gets mapped. Think acpi_platform_devmap To generate a diff of this commit: cvs rdiff -u -r1.90 -r1.91 src/sys/arch/aarch64/aarch64/pmap.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/aarch64/aarch64/pmap.c diff -u src/sys/arch/aarch64/aarch64/pmap.c:1.90 src/sys/arch/aarch64/aarch64/pmap.c:1.91 --- src/sys/arch/aarch64/aarch64/pmap.c:1.90 Sat Sep 19 13:33:08 2020 +++ src/sys/arch/aarch64/aarch64/pmap.c Mon Sep 28 12:04:19 2020 @@ -1,4 +1,4 @@ -/* $NetBSD: pmap.c,v 1.90 2020/09/19 13:33:08 skrll Exp $ */ +/* $NetBSD: pmap.c,v 1.91 2020/09/28 12:04:19 skrll Exp $ */ /* * Copyright (c) 2017 Ryo Shimizu @@ -27,7 +27,7 @@ */ #include -__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.90 2020/09/19 13:33:08 skrll Exp $"); +__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.91 2020/09/28 12:04:19 skrll Exp $"); #include "opt_arm_debug.h" #include "opt_ddb.h" @@ -373,9 +373,8 @@ pmap_devmap_bootstrap(vaddr_t l0pt, cons table[i].pd_size, table[i].pd_prot, table[i].pd_flags); + pmap_devmap_bootstrap_done = true; } - - pmap_devmap_bootstrap_done = true; } const struct pmap_devmap *
CVS commit: src/sys/arch/aarch64/aarch64
Module Name:src
Committed By: skrll
Date: Sat Sep 26 06:09:33 UTC 2020
Modified Files:
src/sys/arch/aarch64/aarch64: cpuswitch.S
Log Message:
Use 'lr' instead of 'x30' in an instruction for clarity
To generate a diff of this commit:
cvs rdiff -u -r1.26 -r1.27 src/sys/arch/aarch64/aarch64/cpuswitch.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/aarch64/aarch64/cpuswitch.S
diff -u src/sys/arch/aarch64/aarch64/cpuswitch.S:1.26 src/sys/arch/aarch64/aarch64/cpuswitch.S:1.27
--- src/sys/arch/aarch64/aarch64/cpuswitch.S:1.26 Sat Sep 26 06:08:41 2020
+++ src/sys/arch/aarch64/aarch64/cpuswitch.S Sat Sep 26 06:09:33 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: cpuswitch.S,v 1.26 2020/09/26 06:08:41 skrll Exp $ */
+/* $NetBSD: cpuswitch.S,v 1.27 2020/09/26 06:09:33 skrll Exp $ */
/*-
* Copyright (c) 2014, 2020 The NetBSD Foundation, Inc.
@@ -38,7 +38,7 @@
#include "opt_ddb.h"
#include "opt_kasan.h"
-RCSID("$NetBSD: cpuswitch.S,v 1.26 2020/09/26 06:08:41 skrll Exp $")
+RCSID("$NetBSD: cpuswitch.S,v 1.27 2020/09/26 06:09:33 skrll Exp $")
ARMV8_DEFINE_OPTIONS
@@ -298,7 +298,7 @@ ENTRY_NP(lwp_trampoline)
/*
* When the x27 function returns, it will jump to el0_trap_exit.
*/
- adr x30, el0_trap_exit /* tail call via lr */
+ adr lr, el0_trap_exit /* tail call via lr */
mov x0, x28 /* mov arg into place */
mov x16, x27 /* use x16 as jump register, for BTI */
br x16 /* call function with arg */
CVS commit: src/sys/arch/aarch64/aarch64
Module Name:src
Committed By: skrll
Date: Sat Sep 26 06:08:41 UTC 2020
Modified Files:
src/sys/arch/aarch64/aarch64: cpuswitch.S
Log Message:
Fix a comment
To generate a diff of this commit:
cvs rdiff -u -r1.25 -r1.26 src/sys/arch/aarch64/aarch64/cpuswitch.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/aarch64/aarch64/cpuswitch.S
diff -u src/sys/arch/aarch64/aarch64/cpuswitch.S:1.25 src/sys/arch/aarch64/aarch64/cpuswitch.S:1.26
--- src/sys/arch/aarch64/aarch64/cpuswitch.S:1.25 Wed Aug 12 13:19:35 2020
+++ src/sys/arch/aarch64/aarch64/cpuswitch.S Sat Sep 26 06:08:41 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: cpuswitch.S,v 1.25 2020/08/12 13:19:35 skrll Exp $ */
+/* $NetBSD: cpuswitch.S,v 1.26 2020/09/26 06:08:41 skrll Exp $ */
/*-
* Copyright (c) 2014, 2020 The NetBSD Foundation, Inc.
@@ -38,7 +38,7 @@
#include "opt_ddb.h"
#include "opt_kasan.h"
-RCSID("$NetBSD: cpuswitch.S,v 1.25 2020/08/12 13:19:35 skrll Exp $")
+RCSID("$NetBSD: cpuswitch.S,v 1.26 2020/09/26 06:08:41 skrll Exp $")
ARMV8_DEFINE_OPTIONS
@@ -161,7 +161,7 @@ ENTRY_NP(cpu_switchto_softint)
stp x23, x24, [sp, #TF_X23]
stp x25, x26, [sp, #TF_X25]
stp x27, x28, [sp, #TF_X27]
- stp x29, x2, [sp, #TF_X29] /* tf->lr = softint_cleanup; */
+ stp x29, x2, [sp, #TF_X29] /* tf->tf_lr = softint_cleanup; */
mrs x19, tpidr_el1 /* x19 := curlwp */
mov x4, sp
CVS commit: src/sys/arch/aarch64/aarch64
Module Name:src
Committed By: ryo
Date: Thu Sep 24 16:15:49 UTC 2020
Modified Files:
src/sys/arch/aarch64/aarch64: bus_space_asm_generic.S
Log Message:
fix *_bs_rm_4_swap(). it was only reading 2 bytes, not 4 bytes.
pointed out by skrll@ thanks.
To generate a diff of this commit:
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/aarch64/aarch64/bus_space_asm_generic.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/aarch64/aarch64/bus_space_asm_generic.S
diff -u src/sys/arch/aarch64/aarch64/bus_space_asm_generic.S:1.3 src/sys/arch/aarch64/aarch64/bus_space_asm_generic.S:1.4
--- src/sys/arch/aarch64/aarch64/bus_space_asm_generic.S:1.3 Thu Sep 24 09:04:38 2020
+++ src/sys/arch/aarch64/aarch64/bus_space_asm_generic.S Thu Sep 24 16:15:49 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: bus_space_asm_generic.S,v 1.3 2020/09/24 09:04:38 ryo Exp $ */
+/* $NetBSD: bus_space_asm_generic.S,v 1.4 2020/09/24 16:15:49 ryo Exp $ */
/*
* Copyright (c) 2017 Ryo Shimizu
@@ -29,7 +29,7 @@
#include
#include "assym.h"
-RCSID("$NetBSD: bus_space_asm_generic.S,v 1.3 2020/09/24 09:04:38 ryo Exp $")
+RCSID("$NetBSD: bus_space_asm_generic.S,v 1.4 2020/09/24 16:15:49 ryo Exp $")
.macro generate_bsfunc funcname, dsbop
/* uint8_t {funcname}_bs_r_1(x0:tag, x1:addr, x2:offset) */
@@ -225,7 +225,7 @@ ENTRY_NP(\funcname\()_bs_rm_4_swap)
ldr w8, [x0, #BS_STRIDE]
lsl x8, x2, x8 /* offset <<= tag->bs_stride */
1:
- ldrh w9, [x1, x8]
+ ldr w9, [x1, x8]
subs x4, x4, #1 /* count-- */
rev w9, w9
str w9, [x3], #4
CVS commit: src/sys/arch/aarch64/aarch64
Module Name:src
Committed By: ryo
Date: Thu Sep 24 09:04:38 UTC 2020
Modified Files:
src/sys/arch/aarch64/aarch64: bus_space_asm_generic.S
Log Message:
fix bugs in *_bs_rm_8_swap(). it was only reading 4 bytes, not 8 bytes.
To generate a diff of this commit:
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/aarch64/aarch64/bus_space_asm_generic.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/aarch64/aarch64/bus_space_asm_generic.S
diff -u src/sys/arch/aarch64/aarch64/bus_space_asm_generic.S:1.2 src/sys/arch/aarch64/aarch64/bus_space_asm_generic.S:1.3
--- src/sys/arch/aarch64/aarch64/bus_space_asm_generic.S:1.2 Mon Jan 13 17:23:07 2020
+++ src/sys/arch/aarch64/aarch64/bus_space_asm_generic.S Thu Sep 24 09:04:38 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: bus_space_asm_generic.S,v 1.2 2020/01/13 17:23:07 ryo Exp $ */
+/* $NetBSD: bus_space_asm_generic.S,v 1.3 2020/09/24 09:04:38 ryo Exp $ */
/*
* Copyright (c) 2017 Ryo Shimizu
@@ -29,7 +29,7 @@
#include
#include "assym.h"
-RCSID("$NetBSD: bus_space_asm_generic.S,v 1.2 2020/01/13 17:23:07 ryo Exp $")
+RCSID("$NetBSD: bus_space_asm_generic.S,v 1.3 2020/09/24 09:04:38 ryo Exp $")
.macro generate_bsfunc funcname, dsbop
/* uint8_t {funcname}_bs_r_1(x0:tag, x1:addr, x2:offset) */
@@ -248,7 +248,7 @@ ENTRY_NP(\funcname\()_bs_rm_8_swap)
ldr w8, [x0, #BS_STRIDE]
lsl x8, x2, x8 /* offset <<= tag->bs_stride */
1:
- ldrh w9, [x1, x8]
+ ldr x9, [x1, x8]
subs x4, x4, #1 /* count-- */
rev x9, x9
str x9, [x3], #8
CVS commit: src/sys/arch/aarch64/aarch64
Module Name:src Committed By: skrll Date: Wed Sep 16 18:24:58 UTC 2020 Modified Files: src/sys/arch/aarch64/aarch64: aarch64_machdep.c Log Message: Fix a comment To generate a diff of this commit: cvs rdiff -u -r1.46 -r1.47 src/sys/arch/aarch64/aarch64/aarch64_machdep.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/aarch64/aarch64/aarch64_machdep.c diff -u src/sys/arch/aarch64/aarch64/aarch64_machdep.c:1.46 src/sys/arch/aarch64/aarch64/aarch64_machdep.c:1.47 --- src/sys/arch/aarch64/aarch64/aarch64_machdep.c:1.46 Sun Aug 2 06:58:16 2020 +++ src/sys/arch/aarch64/aarch64/aarch64_machdep.c Wed Sep 16 18:24:57 2020 @@ -1,4 +1,4 @@ -/* $NetBSD: aarch64_machdep.c,v 1.46 2020/08/02 06:58:16 maxv Exp $ */ +/* $NetBSD: aarch64_machdep.c,v 1.47 2020/09/16 18:24:57 skrll Exp $ */ /*- * Copyright (c) 2014 The NetBSD Foundation, Inc. @@ -30,7 +30,7 @@ */ #include -__KERNEL_RCSID(1, "$NetBSD: aarch64_machdep.c,v 1.46 2020/08/02 06:58:16 maxv Exp $"); +__KERNEL_RCSID(1, "$NetBSD: aarch64_machdep.c,v 1.47 2020/09/16 18:24:57 skrll Exp $"); #include "opt_arm_debug.h" #include "opt_cpuoptions.h" @@ -205,15 +205,15 @@ cpu_kernel_vm_init(uint64_t memory_start * 0x__ffe0_ End of KVA * = VM_MAX_KERNEL_ADDRESS * - * 0x_ffc0_0???_ End of kernel + * 0x_c000_0???_ End of kernel * = _end[] - * 0x_ffc0_00??_ Start of kernel + * 0x_c000_00??_ Start of kernel * = __kernel_text[] * - * 0x_ffc0__ Kernel base address & start of KVA + * 0x_c000__ Kernel base address & start of KVA * = VM_MIN_KERNEL_ADDRESS * - * 0x_ffbf__ End of direct mapped + * 0x_bfff__ End of direct mapped * 0x___ Start of direct mapped * = AARCH64_KSEG_START * = AARCH64_KMEMORY_BASE
CVS commit: src/sys/arch/aarch64/aarch64
Module Name:src
Committed By: ryo
Date: Tue Sep 15 09:23:15 UTC 2020
Modified Files:
src/sys/arch/aarch64/aarch64: locore.S locore_el2.S start.S
Log Message:
fix aarch64eb MULTIPROCESSOR boot
- set endian of EL2,EL1 and EL0 at the beginning of start() and cpu_mpstart()
- drop_to_el1() keeps the endian setting
To generate a diff of this commit:
cvs rdiff -u -r1.71 -r1.72 src/sys/arch/aarch64/aarch64/locore.S
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/aarch64/aarch64/locore_el2.S
cvs rdiff -u -r1.9 -r1.10 src/sys/arch/aarch64/aarch64/start.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/aarch64/aarch64/locore.S
diff -u src/sys/arch/aarch64/aarch64/locore.S:1.71 src/sys/arch/aarch64/aarch64/locore.S:1.72
--- src/sys/arch/aarch64/aarch64/locore.S:1.71 Sun Aug 16 10:08:42 2020
+++ src/sys/arch/aarch64/aarch64/locore.S Tue Sep 15 09:23:15 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: locore.S,v 1.71 2020/08/16 10:08:42 skrll Exp $ */
+/* $NetBSD: locore.S,v 1.72 2020/09/15 09:23:15 ryo Exp $ */
/*
* Copyright (c) 2017 Ryo Shimizu
@@ -38,7 +38,7 @@
#include
#include "assym.h"
-RCSID("$NetBSD: locore.S,v 1.71 2020/08/16 10:08:42 skrll Exp $")
+RCSID("$NetBSD: locore.S,v 1.72 2020/09/15 09:23:15 ryo Exp $")
#ifdef AARCH64_DEVICE_MEM_STRONGLY_ORDERED
#define MAIR_DEVICE_MEM MAIR_DEVICE_nGnRnE
@@ -373,6 +373,30 @@ printcpu:
#endif /* DEBUG_LOCORE */
ENTRY_NP(cpu_mpstart)
+
+ mrs x8, CurrentEL
+ lsr x8, x8, #2
+ cmp x8, #0x2
+ b.lo 1f
+
+ mrs x8, sctlr_el2
+#ifdef __AARCH64EB__
+ orr x8, x8, #SCTLR_EE /* set: Big Endian */
+#else
+ bic x8, x8, #SCTLR_EE /* clear: Little Endian */
+#endif
+ msr sctlr_el2, x8
+ isb
+1:
+ mrs x8, sctlr_el1
+#ifdef __AARCH64EB__
+ orr x8, x8, #(SCTLR_EE | SCTLR_EOE) /* set: Big Endian */
+#else
+ bic x8, x8, #(SCTLR_EE | SCTLR_EOE) /* clear: Little Endian */
+#endif
+ msr sctlr_el1, x8
+ isb
+
mrs x3, mpidr_el1
ldr x0, =(MPIDR_AFF0 | MPIDR_AFF1 | MPIDR_AFF2 | MPIDR_AFF3)
and x3, x3, x0
@@ -925,12 +949,6 @@ mmu_enable:
ldr x1, sctlr_set
orr x0, x0, x1
- ldr x1, sctlr_ee
-#ifdef __AARCH64EB__
- orr x0, x0, x1 /* set: BigEndian */
-#else
- bic x0, x0, x1 /* clear: LittleEndian */
-#endif
msr sctlr_el1, x0 /* enabling MMU! */
isb
@@ -985,8 +1003,6 @@ tcr_setting:
#endif
-sctlr_ee:
- .quad (SCTLR_EE | SCTLR_EOE) /* Endianness of Exception and EL0 */
sctlr_set:
.quad ( \
SCTLR_LSMAOE | /* Load/Store Multiple Atomicity and Ordering */ \
Index: src/sys/arch/aarch64/aarch64/locore_el2.S
diff -u src/sys/arch/aarch64/aarch64/locore_el2.S:1.5 src/sys/arch/aarch64/aarch64/locore_el2.S:1.6
--- src/sys/arch/aarch64/aarch64/locore_el2.S:1.5 Sat Sep 5 17:49:26 2020
+++ src/sys/arch/aarch64/aarch64/locore_el2.S Tue Sep 15 09:23:15 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: locore_el2.S,v 1.5 2020/09/05 17:49:26 jakllsch Exp $ */
+/* $NetBSD: locore_el2.S,v 1.6 2020/09/15 09:23:15 ryo Exp $ */
/*-
* Copyright (c) 2012-2014 Andrew Turner
@@ -32,7 +32,7 @@
#include
#include "assym.h"
-RCSID("$NetBSD: locore_el2.S,v 1.5 2020/09/05 17:49:26 jakllsch Exp $")
+RCSID("$NetBSD: locore_el2.S,v 1.6 2020/09/15 09:23:15 ryo Exp $")
/*
* For use in #include "locore_el2.S".
@@ -75,9 +75,9 @@ in_el2:
/* Set the bits that need to be 1 in SCTLR_EL1. */
ldr x2, .Lsctlr_res1
-#ifdef __AARCH64EB__
- orr x2, x2, #SCTLR_EE
-#endif
+ mrs x1, sctlr_el1
+ and x1, x1, #(SCTLR_EE | SCTLR_EOE) /* keep SCTLR_EL1.{EE,E0E} */
+ orr x2, x2, x1
msr sctlr_el1, x2
/* Don't trap to EL2 on FP instructions. */
Index: src/sys/arch/aarch64/aarch64/start.S
diff -u src/sys/arch/aarch64/aarch64/start.S:1.9 src/sys/arch/aarch64/aarch64/start.S:1.10
--- src/sys/arch/aarch64/aarch64/start.S:1.9 Sat Sep 5 17:49:26 2020
+++ src/sys/arch/aarch64/aarch64/start.S Tue Sep 15 09:23:15 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: start.S,v 1.9 2020/09/05 17:49:26 jakllsch Exp $ */
+/* $NetBSD: start.S,v 1.10 2020/09/15 09:23:15 ryo Exp $ */
/*
* Copyright (c) 2017 Ryo Shimizu
@@ -33,7 +33,7 @@
#include
#include "assym.h"
-RCSID("$NetBSD: start.S,v 1.9 2020/09/05 17:49:26 jakllsch Exp $")
+RCSID("$NetBSD: start.S,v 1.10 2020/09/15 09:23:15 ryo Exp $")
/*
* Padding at start of kernel image to make room for 64-byte header
@@ -59,19 +59,18 @@ start:
#endif
msr sctlr_el2, x8
isb
- b 2f
1:
mrs x8, sctlr_el1
#ifdef __AARCH64EB__
- orr x8, x8, #SCTLR_EE /* set: Big Endian */
+ orr x8, x8, #(SCTLR_EE | SCTLR_EOE) /* set: Big Endian */
#else
- bic x8, x8, #SCTLR_EE /* clear: Little Endian */
+ bic x8, x8, #(SCTLR_EE | SCTLR_EOE) /* clear: Little Endian */
#endif
msr sctlr_el1, x8
isb
-2:
+
adr x9, start
ldr x10, =start
CVS commit: src/sys/arch/aarch64/aarch64
Module Name:src
Committed By: ryo
Date: Mon Sep 14 17:14:12 UTC 2020
Modified Files:
src/sys/arch/aarch64/aarch64: kobj_machdep.c
Log Message:
swap insns for aarch64eb
To generate a diff of this commit:
cvs rdiff -u -r1.4 -r1.5 src/sys/arch/aarch64/aarch64/kobj_machdep.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/aarch64/aarch64/kobj_machdep.c
diff -u src/sys/arch/aarch64/aarch64/kobj_machdep.c:1.4 src/sys/arch/aarch64/aarch64/kobj_machdep.c:1.5
--- src/sys/arch/aarch64/aarch64/kobj_machdep.c:1.4 Wed Jul 8 03:45:13 2020
+++ src/sys/arch/aarch64/aarch64/kobj_machdep.c Mon Sep 14 17:14:12 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: kobj_machdep.c,v 1.4 2020/07/08 03:45:13 ryo Exp $ */
+/* $NetBSD: kobj_machdep.c,v 1.5 2020/09/14 17:14:12 ryo Exp $ */
/*
* Copyright (c) 2018 Ryo Shimizu
@@ -27,7 +27,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: kobj_machdep.c,v 1.4 2020/07/08 03:45:13 ryo Exp $");
+__KERNEL_RCSID(0, "$NetBSD: kobj_machdep.c,v 1.5 2020/09/14 17:14:12 ryo Exp $");
#define ELFSIZE ARCH_ELFSIZE
@@ -184,7 +184,7 @@ kobj_reloc(kobj_t ko, uintptr_t relocbas
old = *where;
#ifdef DDB
snprintf(disasmbuf, sizeof(disasmbuf), "%08x %s",
- *insn, strdisasm((vaddr_t)insn), 0);
+ le32toh(*insn), strdisasm((vaddr_t)insn), 0);
#endif
#endif /* KOBJ_MACHDEP_DEBUG */
@@ -247,7 +247,8 @@ kobj_reloc(kobj_t ko, uintptr_t relocbas
}
val &= WIDTHMASK(12);
val >>= shift;
- *insn = (*insn & ~__BITS(21,10)) | (val << 10);
+ *insn = htole32(
+ (le32toh(*insn) & ~__BITS(21,10)) | (val << 10));
break;
case R_AARCH64_ADR_PREL_PG_HI21_NC:
@@ -268,8 +269,9 @@ kobj_reloc(kobj_t ko, uintptr_t relocbas
}
immlo = val & WIDTHMASK(2);
immhi = (val >> 2) & WIDTHMASK(19);
- *insn = (*insn & ~(__BITS(30,29) | __BITS(23,5))) |
- (immlo << 29) | (immhi << 5);
+ *insn = htole32((le32toh(*insn) &
+ ~(__BITS(30,29) | __BITS(23,5))) |
+ (immlo << 29) | (immhi << 5));
break;
case R_AARCH_JUMP26:
@@ -291,7 +293,7 @@ kobj_reloc(kobj_t ko, uintptr_t relocbas
break;
}
val &= WIDTHMASK(26);
- *insn = (*insn & ~__BITS(25,0)) | val;
+ *insn = htole32((le32toh(*insn) & ~__BITS(25,0)) | val);
break;
case R_AARCH64_PREL64:
@@ -348,7 +350,7 @@ kobj_reloc(kobj_t ko, uintptr_t relocbas
#ifdef DDB
printf("%s:insn %s\n", __func__, disasmbuf);
printf("%s: -> %08x %s\n", __func__,
- *insn, strdisasm((vaddr_t)insn, 0));
+ le32toh(*insn), strdisasm((vaddr_t)insn, 0));
#endif
printf("\n");
#endif /* KOBJ_MACHDEP_DEBUG */
CVS commit: src/sys/arch/aarch64/aarch64
Module Name:src
Committed By: jakllsch
Date: Sat Sep 5 17:49:26 UTC 2020
Modified Files:
src/sys/arch/aarch64/aarch64: locore_el2.S start.S
Log Message:
aarch64: switch CPU to the kernel's byte order during boot
To generate a diff of this commit:
cvs rdiff -u -r1.4 -r1.5 src/sys/arch/aarch64/aarch64/locore_el2.S
cvs rdiff -u -r1.8 -r1.9 src/sys/arch/aarch64/aarch64/start.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/aarch64/aarch64/locore_el2.S
diff -u src/sys/arch/aarch64/aarch64/locore_el2.S:1.4 src/sys/arch/aarch64/aarch64/locore_el2.S:1.5
--- src/sys/arch/aarch64/aarch64/locore_el2.S:1.4 Sat Aug 29 07:17:23 2020
+++ src/sys/arch/aarch64/aarch64/locore_el2.S Sat Sep 5 17:49:26 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: locore_el2.S,v 1.4 2020/08/29 07:17:23 maxv Exp $ */
+/* $NetBSD: locore_el2.S,v 1.5 2020/09/05 17:49:26 jakllsch Exp $ */
/*-
* Copyright (c) 2012-2014 Andrew Turner
@@ -32,7 +32,7 @@
#include
#include "assym.h"
-RCSID("$NetBSD: locore_el2.S,v 1.4 2020/08/29 07:17:23 maxv Exp $")
+RCSID("$NetBSD: locore_el2.S,v 1.5 2020/09/05 17:49:26 jakllsch Exp $")
/*
* For use in #include "locore_el2.S".
@@ -75,6 +75,9 @@ in_el2:
/* Set the bits that need to be 1 in SCTLR_EL1. */
ldr x2, .Lsctlr_res1
+#ifdef __AARCH64EB__
+ orr x2, x2, #SCTLR_EE
+#endif
msr sctlr_el1, x2
/* Don't trap to EL2 on FP instructions. */
Index: src/sys/arch/aarch64/aarch64/start.S
diff -u src/sys/arch/aarch64/aarch64/start.S:1.8 src/sys/arch/aarch64/aarch64/start.S:1.9
--- src/sys/arch/aarch64/aarch64/start.S:1.8 Thu Jul 16 11:36:35 2020
+++ src/sys/arch/aarch64/aarch64/start.S Sat Sep 5 17:49:26 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: start.S,v 1.8 2020/07/16 11:36:35 skrll Exp $ */
+/* $NetBSD: start.S,v 1.9 2020/09/05 17:49:26 jakllsch Exp $ */
/*
* Copyright (c) 2017 Ryo Shimizu
@@ -31,8 +31,9 @@
#include
#include
+#include "assym.h"
-RCSID("$NetBSD: start.S,v 1.8 2020/07/16 11:36:35 skrll Exp $")
+RCSID("$NetBSD: start.S,v 1.9 2020/09/05 17:49:26 jakllsch Exp $")
/*
* Padding at start of kernel image to make room for 64-byte header
@@ -45,6 +46,32 @@ RCSID("$NetBSD: start.S,v 1.8 2020/07/16
*/
.global start
start:
+ mrs x8, CurrentEL
+ lsr x8, x8, #2
+ cmp x8, #0x2
+ b.lo 1f
+
+ mrs x8, sctlr_el2
+#ifdef __AARCH64EB__
+ orr x8, x8, #SCTLR_EE /* set: Big Endian */
+#else
+ bic x8, x8, #SCTLR_EE /* clear: Little Endian */
+#endif
+ msr sctlr_el2, x8
+ isb
+ b 2f
+
+1:
+ mrs x8, sctlr_el1
+#ifdef __AARCH64EB__
+ orr x8, x8, #SCTLR_EE /* set: Big Endian */
+#else
+ bic x8, x8, #SCTLR_EE /* clear: Little Endian */
+#endif
+ msr sctlr_el1, x8
+ isb
+
+2:
adr x9, start
ldr x10, =start
CVS commit: src/sys/arch/aarch64/aarch64
Module Name:src
Committed By: jakllsch
Date: Sat Sep 5 16:44:54 UTC 2020
Modified Files:
src/sys/arch/aarch64/aarch64: bus_space.c
Log Message:
Adjust aarch64 bus_space tags to also work on aarch64eb
To generate a diff of this commit:
cvs rdiff -u -r1.9 -r1.10 src/sys/arch/aarch64/aarch64/bus_space.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/aarch64/aarch64/bus_space.c
diff -u src/sys/arch/aarch64/aarch64/bus_space.c:1.9 src/sys/arch/aarch64/aarch64/bus_space.c:1.10
--- src/sys/arch/aarch64/aarch64/bus_space.c:1.9 Sat Dec 28 17:19:43 2019
+++ src/sys/arch/aarch64/aarch64/bus_space.c Sat Sep 5 16:44:54 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: bus_space.c,v 1.9 2019/12/28 17:19:43 jmcneill Exp $ */
+/* $NetBSD: bus_space.c,v 1.10 2020/09/05 16:44:54 jakllsch Exp $ */
/*
* Copyright (c) 2017 Ryo Shimizu
@@ -27,7 +27,7 @@
*/
#include
-__KERNEL_RCSID(1, "$NetBSD: bus_space.c,v 1.9 2019/12/28 17:19:43 jmcneill Exp $");
+__KERNEL_RCSID(1, "$NetBSD: bus_space.c,v 1.10 2020/09/05 16:44:54 jakllsch Exp $");
#include
#include
@@ -43,6 +43,12 @@ __KERNEL_RCSID(1, "$NetBSD: bus_space.c,
bs_protos(generic)
bs_protos(generic_dsb)
+#if __AARCH64EB__
+#define NSWAP(n) n ## _swap
+#else
+#define NSWAP(n) n
+#endif
+
struct bus_space arm_generic_bs_tag = {
.bs_cookie = _generic_bs_tag,
@@ -60,27 +66,27 @@ struct bus_space arm_generic_bs_tag = {
/* read */
.bs_r_1 = generic_bs_r_1,
- .bs_r_2 = generic_bs_r_2,
- .bs_r_4 = generic_bs_r_4,
- .bs_r_8 = generic_bs_r_8,
+ .bs_r_2 = NSWAP(generic_bs_r_2),
+ .bs_r_4 = NSWAP(generic_bs_r_4),
+ .bs_r_8 = NSWAP(generic_bs_r_8),
/* write */
.bs_w_1 = generic_bs_w_1,
- .bs_w_2 = generic_bs_w_2,
- .bs_w_4 = generic_bs_w_4,
- .bs_w_8 = generic_bs_w_8,
+ .bs_w_2 = NSWAP(generic_bs_w_2),
+ .bs_w_4 = NSWAP(generic_bs_w_4),
+ .bs_w_8 = NSWAP(generic_bs_w_8),
/* read region */
.bs_rr_1 = generic_bs_rr_1,
- .bs_rr_2 = generic_bs_rr_2,
- .bs_rr_4 = generic_bs_rr_4,
- .bs_rr_8 = generic_bs_rr_8,
+ .bs_rr_2 = NSWAP(generic_bs_rr_2),
+ .bs_rr_4 = NSWAP(generic_bs_rr_4),
+ .bs_rr_8 = NSWAP(generic_bs_rr_8),
/* write region */
.bs_wr_1 = generic_bs_wr_1,
- .bs_wr_2 = generic_bs_wr_2,
- .bs_wr_4 = generic_bs_wr_4,
- .bs_wr_8 = generic_bs_wr_8,
+ .bs_wr_2 = NSWAP(generic_bs_wr_2),
+ .bs_wr_4 = NSWAP(generic_bs_wr_4),
+ .bs_wr_8 = NSWAP(generic_bs_wr_8),
/* copy region */
.bs_c_1 = generic_bs_c_1,
@@ -90,27 +96,27 @@ struct bus_space arm_generic_bs_tag = {
/* set region */
.bs_sr_1 = generic_bs_sr_1,
- .bs_sr_2 = generic_bs_sr_2,
- .bs_sr_4 = generic_bs_sr_4,
- .bs_sr_8 = generic_bs_sr_8,
+ .bs_sr_2 = NSWAP(generic_bs_sr_2),
+ .bs_sr_4 = NSWAP(generic_bs_sr_4),
+ .bs_sr_8 = NSWAP(generic_bs_sr_8),
/* read multi */
.bs_rm_1 = generic_bs_rm_1,
- .bs_rm_2 = generic_bs_rm_2,
- .bs_rm_4 = generic_bs_rm_4,
- .bs_rm_8 = generic_bs_rm_8,
+ .bs_rm_2 = NSWAP(generic_bs_rm_2),
+ .bs_rm_4 = NSWAP(generic_bs_rm_4),
+ .bs_rm_8 = NSWAP(generic_bs_rm_8),
/* write multi */
.bs_wm_1 = generic_bs_wm_1,
- .bs_wm_2 = generic_bs_wm_2,
- .bs_wm_4 = generic_bs_wm_4,
- .bs_wm_8 = generic_bs_wm_8,
+ .bs_wm_2 = NSWAP(generic_bs_wm_2),
+ .bs_wm_4 = NSWAP(generic_bs_wm_4),
+ .bs_wm_8 = NSWAP(generic_bs_wm_8),
/* set multi */
.bs_sm_1 = generic_bs_sm_1,
- .bs_sm_2 = generic_bs_sm_2,
- .bs_sm_4 = generic_bs_sm_4,
- .bs_sm_8 = generic_bs_sm_8,
+ .bs_sm_2 = NSWAP(generic_bs_sm_2),
+ .bs_sm_4 = NSWAP(generic_bs_sm_4),
+ .bs_sm_8 = NSWAP(generic_bs_sm_8),
#ifdef __BUS_SPACE_HAS_STREAM_METHODS
/* read stream */
@@ -182,27 +188,27 @@ struct bus_space aarch64_generic_dsb_bs_
/* read */
.bs_r_1 = generic_dsb_bs_r_1,
- .bs_r_2 = generic_dsb_bs_r_2,
- .bs_r_4 = generic_dsb_bs_r_4,
- .bs_r_8 = generic_dsb_bs_r_8,
+ .bs_r_2 = NSWAP(generic_dsb_bs_r_2),
+ .bs_r_4 = NSWAP(generic_dsb_bs_r_4),
+ .bs_r_8 = NSWAP(generic_dsb_bs_r_8),
/* write */
.bs_w_1 = generic_dsb_bs_w_1,
- .bs_w_2 = generic_dsb_bs_w_2,
- .bs_w_4 = generic_dsb_bs_w_4,
- .bs_w_8 = generic_dsb_bs_w_8,
+ .bs_w_2 = NSWAP(generic_dsb_bs_w_2),
+ .bs_w_4 = NSWAP(generic_dsb_bs_w_4),
+ .bs_w_8 = NSWAP(generic_dsb_bs_w_8),
/* read region */
.bs_rr_1 = generic_dsb_bs_rr_1,
- .bs_rr_2 = generic_dsb_bs_rr_2,
- .bs_rr_4 = generic_dsb_bs_rr_4,
- .bs_rr_8 = generic_dsb_bs_rr_8,
+ .bs_rr_2 = NSWAP(generic_dsb_bs_rr_2),
+ .bs_rr_4 = NSWAP(generic_dsb_bs_rr_4),
+ .bs_rr_8 = NSWAP(generic_dsb_bs_rr_8),
/* write region */
.bs_wr_1 = generic_dsb_bs_wr_1,
- .bs_wr_2 = generic_dsb_bs_wr_2,
- .bs_wr_4 = generic_dsb_bs_wr_4,
- .bs_wr_8 = generic_dsb_bs_wr_8,
+ .bs_wr_2 = NSWAP(generic_dsb_bs_wr_2),
+ .bs_wr_4 = NSWAP(generic_dsb_bs_wr_4),
+ .bs_wr_8 = NSWAP(generic_dsb_bs_wr_8),
/* copy region */
.bs_c_1 = generic_dsb_bs_c_1,
@@ -212,27 +218,27 @@ struct bus_space aarch64_generic_dsb_bs_
/* set region */
.bs_sr_1 = generic_dsb_bs_sr_1,
- .bs_sr_2 =
CVS commit: src/sys/arch/aarch64/aarch64
Module Name:src
Committed By: jakllsch
Date: Sat Sep 5 15:59:09 UTC 2020
Modified Files:
src/sys/arch/aarch64/aarch64: disasm.c
Log Message:
AArch64 instructions are always LE: swap if we're BE
To generate a diff of this commit:
cvs rdiff -u -r1.9 -r1.10 src/sys/arch/aarch64/aarch64/disasm.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/aarch64/aarch64/disasm.c
diff -u src/sys/arch/aarch64/aarch64/disasm.c:1.9 src/sys/arch/aarch64/aarch64/disasm.c:1.10
--- src/sys/arch/aarch64/aarch64/disasm.c:1.9 Mon Aug 3 19:16:56 2020
+++ src/sys/arch/aarch64/aarch64/disasm.c Sat Sep 5 15:59:09 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: disasm.c,v 1.9 2020/08/03 19:16:56 ryo Exp $ */
+/* $NetBSD: disasm.c,v 1.10 2020/09/05 15:59:09 jakllsch Exp $ */
/*
* Copyright (c) 2018 Ryo Shimizu
@@ -27,7 +27,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: disasm.c,v 1.9 2020/08/03 19:16:56 ryo Exp $");
+__KERNEL_RCSID(0, "$NetBSD: disasm.c,v 1.10 2020/09/05 15:59:09 jakllsch Exp $");
#include
#include
@@ -4044,7 +4044,7 @@ disasm(const disasm_interface_t *di, uin
{
uint32_t insn;
- insn = di->di_readword(loc);
+ insn = le32toh(di->di_readword(loc));
disasm_insn(di, loc, insn);
/* return next address */
CVS commit: src/sys/arch/aarch64/aarch64
Module Name:src
Committed By: skrll
Date: Sun Aug 16 10:08:42 UTC 2020
Modified Files:
src/sys/arch/aarch64/aarch64: locore.S
Log Message:
Improve comments
To generate a diff of this commit:
cvs rdiff -u -r1.70 -r1.71 src/sys/arch/aarch64/aarch64/locore.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/aarch64/aarch64/locore.S
diff -u src/sys/arch/aarch64/aarch64/locore.S:1.70 src/sys/arch/aarch64/aarch64/locore.S:1.71
--- src/sys/arch/aarch64/aarch64/locore.S:1.70 Wed Aug 12 13:19:35 2020
+++ src/sys/arch/aarch64/aarch64/locore.S Sun Aug 16 10:08:42 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: locore.S,v 1.70 2020/08/12 13:19:35 skrll Exp $ */
+/* $NetBSD: locore.S,v 1.71 2020/08/16 10:08:42 skrll Exp $ */
/*
* Copyright (c) 2017 Ryo Shimizu
@@ -38,7 +38,7 @@
#include
#include "assym.h"
-RCSID("$NetBSD: locore.S,v 1.70 2020/08/12 13:19:35 skrll Exp $")
+RCSID("$NetBSD: locore.S,v 1.71 2020/08/16 10:08:42 skrll Exp $")
#ifdef AARCH64_DEVICE_MEM_STRONGLY_ORDERED
#define MAIR_DEVICE_MEM MAIR_DEVICE_nGnRnE
@@ -454,13 +454,15 @@ mp_vstart:
msr tpidr_el0, xzr
msr tpidrro_el0, xzr
- /* set curcpu(), and fill curcpu()->ci_{midr,mpidr} */
mov x0, #CPU_INFO_SIZE
mul x0, x27, x0
adrl x1, _C_LABEL(cpu_info_store)
add x0, x0, x1 /* x0 = _info_store[cpuindex] */
+
+ /* temporarily set tpidr_el1 to curcpu until the idle lwp is setup */
msr tpidr_el1, x0 /* tpidr_el1 = curcpu = x0 */
+ /* fill curcpu()->ci_{midr,mpidr} */
mrs x1, midr_el1
str x1, [x0, #CI_MIDR] /* curcpu()->ci_cpuid = midr_el1 */
mrs x1, mpidr_el1
@@ -508,8 +510,11 @@ mp_vstart:
b 1b
9:
- /* fill my cpu_info */
- mrs x0, tpidr_el1 /* curcpu */
+ /*
+ * set curlwp (tpidr_el1 and curcpu()->ci_curlwp) now we know the
+ * idle lwp from curcpu()->ci_idlelwp
+ */
+ mrs x0, tpidr_el1 /* curcpu (temporarily) */
ldr x1, [x0, #CI_IDLELWP] /* x0 = curcpu()->ci_idlelwp */
msr tpidr_el1, x1 /* tpidr_el1 = curlwp = x1 */
str x1, [x0, #CI_CURLWP] /* curlwp is idlelwp */
CVS commit: src/sys/arch/aarch64/aarch64
Module Name:src
Committed By: skrll
Date: Fri Aug 14 08:19:26 UTC 2020
Modified Files:
src/sys/arch/aarch64/aarch64: pmap.c
Log Message:
Whitespace
To generate a diff of this commit:
cvs rdiff -u -r1.86 -r1.87 src/sys/arch/aarch64/aarch64/pmap.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/aarch64/aarch64/pmap.c
diff -u src/sys/arch/aarch64/aarch64/pmap.c:1.86 src/sys/arch/aarch64/aarch64/pmap.c:1.87
--- src/sys/arch/aarch64/aarch64/pmap.c:1.86 Wed Aug 12 13:36:36 2020
+++ src/sys/arch/aarch64/aarch64/pmap.c Fri Aug 14 08:19:26 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: pmap.c,v 1.86 2020/08/12 13:36:36 skrll Exp $ */
+/* $NetBSD: pmap.c,v 1.87 2020/08/14 08:19:26 skrll Exp $ */
/*
* Copyright (c) 2017 Ryo Shimizu
@@ -27,7 +27,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.86 2020/08/12 13:36:36 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.87 2020/08/14 08:19:26 skrll Exp $");
#include "opt_arm_debug.h"
#include "opt_ddb.h"
@@ -1998,7 +1998,7 @@ _pmap_enter(struct pmap *pm, vaddr_t va,
if (pps[0] != NULL)
pmap_pv_unlock(pps[0]);
fail0:
- if (!kenter) {
+ if (!kenter) {
pm_unlock(pm);
/* spare pv was not used. discard */
CVS commit: src/sys/arch/aarch64/aarch64
Module Name:src
Committed By: skrll
Date: Thu Aug 13 07:14:04 UTC 2020
Modified Files:
src/sys/arch/aarch64/aarch64: lock_stubs.S
Log Message:
Trailing whitespace
To generate a diff of this commit:
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/aarch64/aarch64/lock_stubs.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/aarch64/aarch64/lock_stubs.S
diff -u src/sys/arch/aarch64/aarch64/lock_stubs.S:1.1 src/sys/arch/aarch64/aarch64/lock_stubs.S:1.2
--- src/sys/arch/aarch64/aarch64/lock_stubs.S:1.1 Wed Aug 12 13:28:46 2020
+++ src/sys/arch/aarch64/aarch64/lock_stubs.S Thu Aug 13 07:14:04 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: lock_stubs.S,v 1.1 2020/08/12 13:28:46 skrll Exp $ */
+/* $NetBSD: lock_stubs.S,v 1.2 2020/08/13 07:14:04 skrll Exp $ */
/*-
* Copyright (c) 2014, 2020 The NetBSD Foundation, Inc.
@@ -35,7 +35,7 @@
#include "assym.h"
-RCSID("$NetBSD: lock_stubs.S,v 1.1 2020/08/12 13:28:46 skrll Exp $")
+RCSID("$NetBSD: lock_stubs.S,v 1.2 2020/08/13 07:14:04 skrll Exp $")
#ifndef LOCKDEBUG
/*
@@ -53,7 +53,7 @@ ENTRY(mutex_enter)
ret
2:
b 1b
-3:
+3:
b _C_LABEL(mutex_vector_enter)
END(mutex_enter)
@@ -75,7 +75,7 @@ ENTRY(mutex_exit)
ret
2:
b 1b
-3:
+3:
b _C_LABEL(mutex_vector_exit)
END(mutex_exit)
#endif /* !LOCKDEBUG */
CVS commit: src/sys/arch/aarch64/aarch64
Module Name:src Committed By: skrll Date: Tue Aug 11 19:46:56 UTC 2020 Modified Files: src/sys/arch/aarch64/aarch64: db_interface.c Log Message: Improve a comment To generate a diff of this commit: cvs rdiff -u -r1.8 -r1.9 src/sys/arch/aarch64/aarch64/db_interface.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/aarch64/aarch64/db_interface.c diff -u src/sys/arch/aarch64/aarch64/db_interface.c:1.8 src/sys/arch/aarch64/aarch64/db_interface.c:1.9 --- src/sys/arch/aarch64/aarch64/db_interface.c:1.8 Sun Aug 2 06:58:16 2020 +++ src/sys/arch/aarch64/aarch64/db_interface.c Tue Aug 11 19:46:56 2020 @@ -1,4 +1,4 @@ -/* $NetBSD: db_interface.c,v 1.8 2020/08/02 06:58:16 maxv Exp $ */ +/* $NetBSD: db_interface.c,v 1.9 2020/08/11 19:46:56 skrll Exp $ */ /* * Copyright (c) 2017 Ryo Shimizu @@ -27,7 +27,7 @@ */ #include -__KERNEL_RCSID(0, "$NetBSD: db_interface.c,v 1.8 2020/08/02 06:58:16 maxv Exp $"); +__KERNEL_RCSID(0, "$NetBSD: db_interface.c,v 1.9 2020/08/11 19:46:56 skrll Exp $"); #include #include @@ -121,10 +121,11 @@ db_write_text(vaddr_t addr, size_t size, pte = *ptep; /* - * change to writable. require to keep execute permission. - * because if the block/page to which the target address belongs and - * the block/page to which this function itself belongs are the same, - * if drop PROT_EXECUTE and TLB invalidate, the program stop... + * change to writable. it is required to keep execute permission. + * because if the block/page to which the target address belongs is + * the same as the block/page to which this function belongs, then + * if PROT_EXECUTE is dropped and TLB is invalidated, the program + * will stop... */ pmap_kvattr(addr, VM_PROT_EXECUTE|VM_PROT_READ|VM_PROT_WRITE); aarch64_tlbi_all();
CVS commit: src/sys/arch/aarch64/aarch64
Module Name:src
Committed By: skrll
Date: Sun Aug 9 09:11:41 UTC 2020
Modified Files:
src/sys/arch/aarch64/aarch64: pmap.c
Log Message:
Fix another UVMHIST so it doesn't use %s
To generate a diff of this commit:
cvs rdiff -u -r1.84 -r1.85 src/sys/arch/aarch64/aarch64/pmap.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/aarch64/aarch64/pmap.c
diff -u src/sys/arch/aarch64/aarch64/pmap.c:1.84 src/sys/arch/aarch64/aarch64/pmap.c:1.85
--- src/sys/arch/aarch64/aarch64/pmap.c:1.84 Thu Jul 16 11:36:35 2020
+++ src/sys/arch/aarch64/aarch64/pmap.c Sun Aug 9 09:11:41 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: pmap.c,v 1.84 2020/07/16 11:36:35 skrll Exp $ */
+/* $NetBSD: pmap.c,v 1.85 2020/08/09 09:11:41 skrll Exp $ */
/*
* Copyright (c) 2017 Ryo Shimizu
@@ -27,7 +27,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.84 2020/07/16 11:36:35 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.85 2020/08/09 09:11:41 skrll Exp $");
#include "opt_arm_debug.h"
#include "opt_ddb.h"
@@ -2236,7 +2236,6 @@ pmap_fault_fixup(struct pmap *pm, vaddr_
UVMHIST_LOG(pmaphist, "pm=%p, va=%016lx, accessprot=%08x",
pm, va, accessprot, 0);
-
#if 0
KASSERT_PM_ADDR(pm, va);
#else
@@ -2246,8 +2245,8 @@ pmap_fault_fixup(struct pmap *pm, vaddr_
!(IN_RANGE(va, VM_MIN_ADDRESS, VM_MAX_ADDRESS {
UVMHIST_LOG(pmaphist,
- "pmap space and va mismatch: pm=%s, va=%016lx",
- (pm == pmap_kernel()) ? "kernel" : "user", va, 0, 0);
+ "pmap space and va mismatch: kernel=%jd, va=%016lx",
+ pm == pmap_kernel(), va, 0, 0);
return false;
}
#endif
CVS commit: src/sys/arch/aarch64/aarch64
Module Name:src
Committed By: skrll
Date: Sun Aug 9 07:26:20 UTC 2020
Modified Files:
src/sys/arch/aarch64/aarch64: fault.c
Log Message:
Don't use %s in UVMHIST_PRINT. Remove an unnecessary #ifdef UVMHIST while
I'm here
To generate a diff of this commit:
cvs rdiff -u -r1.18 -r1.19 src/sys/arch/aarch64/aarch64/fault.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/aarch64/aarch64/fault.c
diff -u src/sys/arch/aarch64/aarch64/fault.c:1.18 src/sys/arch/aarch64/aarch64/fault.c:1.19
--- src/sys/arch/aarch64/aarch64/fault.c:1.18 Thu Aug 6 06:50:39 2020
+++ src/sys/arch/aarch64/aarch64/fault.c Sun Aug 9 07:26:20 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: fault.c,v 1.18 2020/08/06 06:50:39 ryo Exp $ */
+/* $NetBSD: fault.c,v 1.19 2020/08/09 07:26:20 skrll Exp $ */
/*
* Copyright (c) 2017 Ryo Shimizu
@@ -27,7 +27,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: fault.c,v 1.18 2020/08/06 06:50:39 ryo Exp $");
+__KERNEL_RCSID(0, "$NetBSD: fault.c,v 1.19 2020/08/09 07:26:20 skrll Exp $");
#include "opt_compat_netbsd32.h"
#include "opt_ddb.h"
@@ -181,16 +181,13 @@ data_abort_handler(struct trapframe *tf,
else
ftype = (rw == 0) ? VM_PROT_READ : VM_PROT_WRITE;
-#ifdef UVMHIST
if (ftype & VM_PROT_EXECUTE) {
- UVMHIST_LOG(pmaphist, "pagefault %016lx %016lx in %s EXEC",
- tf->tf_far, va, user ? "user" : "kernel", 0);
+ UVMHIST_LOG(pmaphist, "pagefault %016jx %016jx user=%jd EXEC",
+ tf->tf_far, va, user, 0);
} else {
- UVMHIST_LOG(pmaphist, "pagefault %016lx %016lx in %s %s",
- tf->tf_far, va, user ? "user" : "kernel",
- (rw == 0) ? "read" : "write");
+ UVMHIST_LOG(pmaphist, "pagefault %016lx %016lx user=%jd "
+ "write=%jd", tf->tf_far, va, user, rw);
}
-#endif
if (__predict_false(!user && (map != kernel_map) &&
(tf->tf_spsr & SPSR_PAN))) {
CVS commit: src/sys/arch/aarch64/aarch64
Module Name:src
Committed By: ryo
Date: Thu Aug 6 06:50:39 UTC 2020
Modified Files:
src/sys/arch/aarch64/aarch64: fault.c
Log Message:
No need to recover from fault from within a hardware interrupt handler.
To generate a diff of this commit:
cvs rdiff -u -r1.17 -r1.18 src/sys/arch/aarch64/aarch64/fault.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/aarch64/aarch64/fault.c
diff -u src/sys/arch/aarch64/aarch64/fault.c:1.17 src/sys/arch/aarch64/aarch64/fault.c:1.18
--- src/sys/arch/aarch64/aarch64/fault.c:1.17 Thu Aug 6 06:49:55 2020
+++ src/sys/arch/aarch64/aarch64/fault.c Thu Aug 6 06:50:39 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: fault.c,v 1.17 2020/08/06 06:49:55 ryo Exp $ */
+/* $NetBSD: fault.c,v 1.18 2020/08/06 06:50:39 ryo Exp $ */
/*
* Copyright (c) 2017 Ryo Shimizu
@@ -27,7 +27,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: fault.c,v 1.17 2020/08/06 06:49:55 ryo Exp $");
+__KERNEL_RCSID(0, "$NetBSD: fault.c,v 1.18 2020/08/06 06:50:39 ryo Exp $");
#include "opt_compat_netbsd32.h"
#include "opt_ddb.h"
@@ -223,10 +223,12 @@ data_abort_handler(struct trapframe *tf,
do_fault:
/* faultbail path? */
- fb = cpu_disable_onfault();
- if (fb != NULL) {
- cpu_jump_onfault(tf, fb, EFAULT);
- return;
+ if (curcpu()->ci_intr_depth == 0) {
+ fb = cpu_disable_onfault();
+ if (fb != NULL) {
+ cpu_jump_onfault(tf, fb, EFAULT);
+ return;
+ }
}
handle_fault:
CVS commit: src/sys/arch/aarch64/aarch64
Module Name:src
Committed By: ryo
Date: Mon Aug 3 19:16:56 UTC 2020
Modified Files:
src/sys/arch/aarch64/aarch64: disasm.c
Log Message:
make more ARMv8.x system registers are disassemblable
To generate a diff of this commit:
cvs rdiff -u -r1.8 -r1.9 src/sys/arch/aarch64/aarch64/disasm.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/aarch64/aarch64/disasm.c
diff -u src/sys/arch/aarch64/aarch64/disasm.c:1.8 src/sys/arch/aarch64/aarch64/disasm.c:1.9
--- src/sys/arch/aarch64/aarch64/disasm.c:1.8 Tue May 26 05:25:21 2020
+++ src/sys/arch/aarch64/aarch64/disasm.c Mon Aug 3 19:16:56 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: disasm.c,v 1.8 2020/05/26 05:25:21 ryo Exp $ */
+/* $NetBSD: disasm.c,v 1.9 2020/08/03 19:16:56 ryo Exp $ */
/*
* Copyright (c) 2018 Ryo Shimizu
@@ -27,7 +27,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: disasm.c,v 1.8 2020/05/26 05:25:21 ryo Exp $");
+__KERNEL_RCSID(0, "$NetBSD: disasm.c,v 1.9 2020/08/03 19:16:56 ryo Exp $");
#include
#include
@@ -342,11 +342,23 @@ const struct sysreg_table sysreg_table[]
{ SYSREG_ENC(3, 0, 2, 0, 0), "ttbr0_el1" },
{ SYSREG_ENC(3, 0, 2, 0, 1), "ttbr1_el1" },
{ SYSREG_ENC(3, 0, 2, 0, 2), "tcr_el1" },
+ { SYSREG_ENC(3, 0, 2, 1, 0), "apiakeylo_el1" },
+ { SYSREG_ENC(3, 0, 2, 1, 1), "apiakeyhi_el1" },
+ { SYSREG_ENC(3, 0, 2, 1, 2), "apibkeylo_el1" },
+ { SYSREG_ENC(3, 0, 2, 1, 3), "apibkeyhi_el1" },
+ { SYSREG_ENC(3, 0, 2, 2, 0), "apdakeylo_el1" },
+ { SYSREG_ENC(3, 0, 2, 2, 1), "apdakeyhi_el1" },
+ { SYSREG_ENC(3, 0, 2, 2, 2), "apdbkeylo_el1" },
+ { SYSREG_ENC(3, 0, 2, 2, 3), "apdbkeyhi_el1" },
+ { SYSREG_ENC(3, 0, 2, 3, 0), "apgakeylo_el1" },
+ { SYSREG_ENC(3, 0, 2, 3, 1), "apgakeyhi_el1" },
{ SYSREG_ENC(3, 0, 4, 0, 0), "spsr_el1" },
{ SYSREG_ENC(3, 0, 4, 0, 1), "elr_el1" },
{ SYSREG_ENC(3, 0, 4, 1, 0), "sp_el0" },
{ SYSREG_ENC(3, 0, 4, 2, 0), "spsel" },
{ SYSREG_ENC(3, 0, 4, 2, 2), "currentel" },
+ { SYSREG_ENC(3, 0, 4, 2, 3), "pan" },
+ { SYSREG_ENC(3, 0, 4, 2, 4), "uao" },
{ SYSREG_ENC(3, 0, 5, 1, 0), "afsr0_el1" },
{ SYSREG_ENC(3, 0, 5, 1, 1), "afsr1_el1" },
{ SYSREG_ENC(3, 0, 5, 2, 0), "esr_el1" },
@@ -369,8 +381,13 @@ const struct sysreg_table sysreg_table[]
{ SYSREG_ENC(3, 2, 0, 0, 0), "csselr_el1" },
{ SYSREG_ENC(3, 3, 0, 0, 1), "ctr_el0" },
{ SYSREG_ENC(3, 3, 0, 0, 7), "dczid_el0" },
+ { SYSREG_ENC(3, 3, 2, 4, 0), "rndr" },
+ { SYSREG_ENC(3, 3, 2, 4, 1), "rndrrs" },
{ SYSREG_ENC(3, 3, 4, 2, 0), "nzcv" },
{ SYSREG_ENC(3, 3, 4, 2, 1), "daif" },
+ { SYSREG_ENC(3, 3, 4, 2, 5), "dit" },
+ { SYSREG_ENC(3, 3, 4, 2, 6), "ssbs" },
+ { SYSREG_ENC(3, 3, 4, 2, 7), "tco" },
{ SYSREG_ENC(3, 3, 4, 4, 0), "fpcr" },
{ SYSREG_ENC(3, 3, 4, 4, 1), "fpsr" },
{ SYSREG_ENC(3, 3, 4, 5, 0), "dspsr_el0" },
@@ -1239,10 +1256,33 @@ static struct op_sys_table op_sys_table[
{ SYSREG_ENC(1, 3, 7, 11, 1), OPE_XT, "dc\tcvau" },
{ SYSREG_ENC(1, 3, 7, 14, 1), OPE_XT, "dc\tcivac" },
{ SYSREG_ENC(1, 3, 7, 4, 1), OPE_XT, "dc\tzva" },
+ { SYSREG_ENC(1, 0, 7, 6, 3), OPE_XT, "dc\tigvac" },
+ { SYSREG_ENC(1, 0, 7, 6, 4), OPE_XT, "dc\tigsw" },
+ { SYSREG_ENC(1, 0, 7, 6, 5), OPE_XT, "dc\tigdvac" },
+ { SYSREG_ENC(1, 0, 7, 6, 6), OPE_XT, "dc\tigdsw" },
+ { SYSREG_ENC(1, 0, 7, 10, 4), OPE_XT, "dc\tcgsw" },
+ { SYSREG_ENC(1, 0, 7, 10, 6), OPE_XT, "dc\tcgdsw" },
+ { SYSREG_ENC(1, 0, 7, 14, 4), OPE_XT, "dc\tcigsw" },
+ { SYSREG_ENC(1, 0, 7, 14, 6), OPE_XT, "dc\tcigdsw" },
+ { SYSREG_ENC(1, 3, 7, 4, 3), OPE_XT, "dc\tgva" },
+ { SYSREG_ENC(1, 3, 7, 4, 4), OPE_XT, "dc\tgzva" },
+ { SYSREG_ENC(1, 3, 7, 10, 3), OPE_XT, "dc\tcgvac" },
+ { SYSREG_ENC(1, 3, 7, 10, 5), OPE_XT, "dc\tcgdvac" },
+ { SYSREG_ENC(1, 3, 7, 12, 3), OPE_XT, "dc\tcgvap" },
+ { SYSREG_ENC(1, 3, 7, 12, 5), OPE_XT, "dc\tcgdvap" },
+ { SYSREG_ENC(1, 3, 7, 13, 3), OPE_XT, "dc\tcgvadp" },
+ { SYSREG_ENC(1, 3, 7, 13, 5), OPE_XT, "dc\tcgdvadp" },
+ { SYSREG_ENC(1, 3, 7, 14, 3), OPE_XT, "dc\tcigvac" },
+ { SYSREG_ENC(1, 3, 7, 14, 5), OPE_XT, "dc\tcigdvac" },
+ { SYSREG_ENC(1, 3, 7, 12, 1), OPE_XT, "dc\tcvap" },
+ { SYSREG_ENC(1, 3, 7, 13, 1), OPE_XT, "dc\tcvadp" },
+
{ SYSREG_ENC(1, 0, 7, 8, 0), OPE_XT, "at\ts1e1r" },
{ SYSREG_ENC(1, 0, 7, 8, 1), OPE_XT, "at\ts1e1w" },
{ SYSREG_ENC(1, 0, 7, 8, 2), OPE_XT, "at\ts1e0r" },
{ SYSREG_ENC(1, 0, 7, 8, 3), OPE_XT, "at\ts1e0w" },
+ { SYSREG_ENC(1, 0, 7, 9, 0), OPE_XT, "at\ts1e1rp" },
+ { SYSREG_ENC(1, 0, 7, 9, 1), OPE_XT, "at\ts1e1wp" },
{ SYSREG_ENC(1, 4, 7, 8, 0), OPE_XT, "at\ts1e2r" },
{ SYSREG_ENC(1, 4, 7, 8, 1), OPE_XT, "at\ts1e2w" },
{ SYSREG_ENC(1, 4, 7, 8, 4), OPE_XT, "at\ts12e1r" },
@@ -1251,6 +1291,11 @@ static struct op_sys_table op_sys_table[
{ SYSREG_ENC(1, 4, 7, 8, 7), OPE_XT, "at\ts12e0w" },
{ SYSREG_ENC(1, 6, 7,
CVS commit: src/sys/arch/aarch64/aarch64
Module Name:src
Committed By: riastradh
Date: Sat Aug 1 02:06:59 UTC 2020
Modified Files:
src/sys/arch/aarch64/aarch64: fpu.c trap.c
Log Message:
Add kthread_fpu_enter/exit support to aarch64.
To generate a diff of this commit:
cvs rdiff -u -r1.7 -r1.8 src/sys/arch/aarch64/aarch64/fpu.c
cvs rdiff -u -r1.34 -r1.35 src/sys/arch/aarch64/aarch64/trap.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/aarch64/aarch64/fpu.c
diff -u src/sys/arch/aarch64/aarch64/fpu.c:1.7 src/sys/arch/aarch64/aarch64/fpu.c:1.8
--- src/sys/arch/aarch64/aarch64/fpu.c:1.7 Mon Jul 13 16:54:03 2020
+++ src/sys/arch/aarch64/aarch64/fpu.c Sat Aug 1 02:06:59 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: fpu.c,v 1.7 2020/07/13 16:54:03 riastradh Exp $ */
+/* $NetBSD: fpu.c,v 1.8 2020/08/01 02:06:59 riastradh Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -31,10 +31,12 @@
#include
-__KERNEL_RCSID(1, "$NetBSD: fpu.c,v 1.7 2020/07/13 16:54:03 riastradh Exp $");
+__KERNEL_RCSID(1, "$NetBSD: fpu.c,v 1.8 2020/08/01 02:06:59 riastradh Exp $");
#include
#include
+#include
+#include
#include
#include
@@ -176,12 +178,30 @@ fpu_state_release(lwp_t *l)
__asm __volatile ("isb");
}
+static const struct fpreg zero_fpreg;
+
+/*
+ * True if this is a system thread with its own private FPU state.
+ */
+static inline bool
+lwp_system_fpu_p(struct lwp *l)
+{
+
+ return (l->l_flag & (LW_SYSTEM|LW_SYSTEM_FPU)) ==
+ (LW_SYSTEM|LW_SYSTEM_FPU);
+}
+
void
fpu_kern_enter(void)
{
struct cpu_info *ci;
int s;
+ if (lwp_system_fpu_p(curlwp) && !cpu_intr_p()) {
+ KASSERT(!cpu_softintr_p());
+ return;
+ }
+
/*
* Block interrupts up to IPL_VM. We must block preemption
* since -- if this is a user thread -- there is nowhere to
@@ -209,10 +229,16 @@ fpu_kern_enter(void)
void
fpu_kern_leave(void)
{
- static const struct fpreg zero_fpreg;
- struct cpu_info *ci = curcpu();
+ struct cpu_info *ci;
int s;
+ if (lwp_system_fpu_p(curlwp) && !cpu_intr_p()) {
+ KASSERT(!cpu_softintr_p());
+ return;
+ }
+
+ ci = curcpu();
+
KASSERT(ci->ci_cpl == IPL_VM);
KASSERT(ci->ci_kfpu_spl != -1);
@@ -234,3 +260,19 @@ fpu_kern_leave(void)
ci->ci_kfpu_spl = -1;
splx(s);
}
+
+void
+kthread_fpu_enter_md(void)
+{
+
+ fpu_load(curlwp);
+}
+
+void
+kthread_fpu_exit_md(void)
+{
+
+ /* XXX Should fpu_state_release zero the registers itself? */
+ load_fpregs(_fpreg);
+ fpu_discard(curlwp, 0);
+}
Index: src/sys/arch/aarch64/aarch64/trap.c
diff -u src/sys/arch/aarch64/aarch64/trap.c:1.34 src/sys/arch/aarch64/aarch64/trap.c:1.35
--- src/sys/arch/aarch64/aarch64/trap.c:1.34 Mon Jul 27 07:32:48 2020
+++ src/sys/arch/aarch64/aarch64/trap.c Sat Aug 1 02:06:59 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: trap.c,v 1.34 2020/07/27 07:32:48 ryo Exp $ */
+/* $NetBSD: trap.c,v 1.35 2020/08/01 02:06:59 riastradh Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -31,7 +31,7 @@
#include
-__KERNEL_RCSID(1, "$NetBSD: trap.c,v 1.34 2020/07/27 07:32:48 ryo Exp $");
+__KERNEL_RCSID(1, "$NetBSD: trap.c,v 1.35 2020/08/01 02:06:59 riastradh Exp $");
#include "opt_arm_intr_impl.h"
#include "opt_compat_netbsd32.h"
@@ -242,6 +242,12 @@ trap_el1h_sync(struct trapframe *tf)
break;
case ESR_EC_FP_ACCESS:
+ if ((curlwp->l_flag & (LW_SYSTEM|LW_SYSTEM_FPU)) ==
+ (LW_SYSTEM|LW_SYSTEM_FPU)) {
+ fpu_load(curlwp);
+ break;
+ }
+ /*FALLTHROUGH*/
case ESR_EC_FP_TRAP_A64:
case ESR_EC_PC_ALIGNMENT:
case ESR_EC_SP_ALIGNMENT:
CVS commit: src/sys/arch/aarch64/aarch64
Module Name:src
Committed By: ryo
Date: Mon Jul 27 07:32:48 UTC 2020
Modified Files:
src/sys/arch/aarch64/aarch64: trap.c
Log Message:
fix build error. need cast.
To generate a diff of this commit:
cvs rdiff -u -r1.33 -r1.34 src/sys/arch/aarch64/aarch64/trap.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/aarch64/aarch64/trap.c
diff -u src/sys/arch/aarch64/aarch64/trap.c:1.33 src/sys/arch/aarch64/aarch64/trap.c:1.34
--- src/sys/arch/aarch64/aarch64/trap.c:1.33 Sun Jul 26 07:26:52 2020
+++ src/sys/arch/aarch64/aarch64/trap.c Mon Jul 27 07:32:48 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: trap.c,v 1.33 2020/07/26 07:26:52 ryo Exp $ */
+/* $NetBSD: trap.c,v 1.34 2020/07/27 07:32:48 ryo Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -31,7 +31,7 @@
#include
-__KERNEL_RCSID(1, "$NetBSD: trap.c,v 1.33 2020/07/26 07:26:52 ryo Exp $");
+__KERNEL_RCSID(1, "$NetBSD: trap.c,v 1.34 2020/07/27 07:32:48 ryo Exp $");
#include "opt_arm_intr_impl.h"
#include "opt_compat_netbsd32.h"
@@ -615,10 +615,10 @@ emul_arm_swp(uint32_t insn, struct trapf
if ((error = cpu_set_onfault()) == 0) {
if (insn & 0x0040) {
/* swpb */
- val = atomic_swap_8(vaddr, val);
+ val = atomic_swap_8((uint8_t *)vaddr, val);
} else {
/* swp */
- val = atomic_swap_32(vaddr, val);
+ val = atomic_swap_32((uint32_t *)vaddr, val);
}
cpu_unset_onfault();
tf->tf_reg[Rd] = val;
CVS commit: src/sys/arch/aarch64/aarch64
Module Name:src
Committed By: ryo
Date: Sun Jul 26 07:26:52 UTC 2020
Modified Files:
src/sys/arch/aarch64/aarch64: trap.c
Log Message:
add support swp,swpb instruction emulation
To generate a diff of this commit:
cvs rdiff -u -r1.32 -r1.33 src/sys/arch/aarch64/aarch64/trap.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/aarch64/aarch64/trap.c
diff -u src/sys/arch/aarch64/aarch64/trap.c:1.32 src/sys/arch/aarch64/aarch64/trap.c:1.33
--- src/sys/arch/aarch64/aarch64/trap.c:1.32 Sun Jul 26 07:25:38 2020
+++ src/sys/arch/aarch64/aarch64/trap.c Sun Jul 26 07:26:52 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: trap.c,v 1.32 2020/07/26 07:25:38 ryo Exp $ */
+/* $NetBSD: trap.c,v 1.33 2020/07/26 07:26:52 ryo Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -31,7 +31,7 @@
#include
-__KERNEL_RCSID(1, "$NetBSD: trap.c,v 1.32 2020/07/26 07:25:38 ryo Exp $");
+__KERNEL_RCSID(1, "$NetBSD: trap.c,v 1.33 2020/07/26 07:26:52 ryo Exp $");
#include "opt_arm_intr_impl.h"
#include "opt_compat_netbsd32.h"
@@ -588,6 +588,46 @@ arm_cond_match(uint32_t insn, uint64_t s
return (!match != !invert);
}
+uint8_t atomic_swap_8(volatile uint8_t *, uint8_t);
+
+static int
+emul_arm_swp(uint32_t insn, struct trapframe *tf)
+{
+ struct faultbuf fb;
+ vaddr_t vaddr;
+ uint32_t val;
+ int Rn, Rd, Rm, error;
+
+ Rn = __SHIFTOUT(insn, 0x000f);
+ Rd = __SHIFTOUT(insn, 0xf000);
+ Rm = __SHIFTOUT(insn, 0x000f);
+
+ vaddr = tf->tf_reg[Rn] & 0x;
+ val = tf->tf_reg[Rm];
+
+ /* fault if insn is swp, and unaligned access */
+ if ((insn & 0x0040) == 0 && (vaddr & 3) != 0) {
+ tf->tf_far = vaddr;
+ return EFAULT;
+ }
+
+ /* vaddr will always point to userspace, since it has only 32bit */
+ if ((error = cpu_set_onfault()) == 0) {
+ if (insn & 0x0040) {
+ /* swpb */
+ val = atomic_swap_8(vaddr, val);
+ } else {
+ /* swp */
+ val = atomic_swap_32(vaddr, val);
+ }
+ cpu_unset_onfault();
+ tf->tf_reg[Rd] = val;
+ } else {
+ tf->tf_far = reg_far_el1_read();
+ }
+ return error;
+}
+
static enum emul_arm_result
emul_thumb_insn(struct trapframe *tf, uint32_t insn, int insn_size)
{
@@ -635,6 +675,15 @@ emul_arm_insn(struct trapframe *tf)
if ((insn & 0xf000) == 0xf000)
goto unknown_insn;
+ /* swp,swpb */
+ if ((insn & 0x0fb00ff0) == 0x0190) {
+ if (arm_cond_match(insn, tf->tf_spsr)) {
+ if (emul_arm_swp(insn, tf) != 0)
+return EMUL_ARM_FAULT;
+ }
+ goto emulated;
+ }
+
/*
* Emulate ARMv6 instructions with cache operations
* register (c7), that can be used in user mode.
CVS commit: src/sys/arch/aarch64/aarch64
Module Name:src
Committed By: ryo
Date: Sun Jul 26 07:25:38 UTC 2020
Modified Files:
src/sys/arch/aarch64/aarch64: trap.c
Log Message:
- add support conditionally execution for A32 instruction emulation
- separated the processing of ARM and THUMB emul clearly. do not confuse the
Thumb-32bit instruction with the ARM instruction.
- use far_el1 instead of tf_pc to return correct fault address when instruction
emulation
To generate a diff of this commit:
cvs rdiff -u -r1.31 -r1.32 src/sys/arch/aarch64/aarch64/trap.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/aarch64/aarch64/trap.c
diff -u src/sys/arch/aarch64/aarch64/trap.c:1.31 src/sys/arch/aarch64/aarch64/trap.c:1.32
--- src/sys/arch/aarch64/aarch64/trap.c:1.31 Wed Jul 8 03:45:13 2020
+++ src/sys/arch/aarch64/aarch64/trap.c Sun Jul 26 07:25:38 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: trap.c,v 1.31 2020/07/08 03:45:13 ryo Exp $ */
+/* $NetBSD: trap.c,v 1.32 2020/07/26 07:25:38 ryo Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -31,7 +31,7 @@
#include
-__KERNEL_RCSID(1, "$NetBSD: trap.c,v 1.31 2020/07/08 03:45:13 ryo Exp $");
+__KERNEL_RCSID(1, "$NetBSD: trap.c,v 1.32 2020/07/26 07:25:38 ryo Exp $");
#include "opt_arm_intr_impl.h"
#include "opt_compat_netbsd32.h"
@@ -374,8 +374,10 @@ emul_aarch64_insn(struct trapframe *tf)
{
uint32_t insn;
- if (ufetch_32((uint32_t *)tf->tf_pc, ))
+ if (ufetch_32((uint32_t *)tf->tf_pc, )) {
+ tf->tf_far = reg_far_el1_read();
return EMUL_ARM_FAULT;
+ }
if ((insn & 0xffe0) == 0xd53b0020) {
/* mrs x?,ctr_el0 */
@@ -457,7 +459,7 @@ trap_el0_sync(struct trapframe *tf)
goto unknown;
case EMUL_ARM_FAULT:
do_trapsignal(l, SIGSEGV, SEGV_MAPERR,
- (void *)tf->tf_pc, esr);
+ (void *)tf->tf_far, esr);
break;
}
userret(l);
@@ -550,74 +552,126 @@ fetch_arm_insn(uint64_t pc, uint64_t sps
return 4;
}
+static bool
+arm_cond_match(uint32_t insn, uint64_t spsr)
+{
+ bool invert = (insn >> 28) & 1;
+ bool match;
+
+ switch (insn >> 29) {
+ case 0: /* EQ or NE */
+ match = spsr & SPSR_Z;
+ break;
+ case 1: /* CS/HI or CC/LO */
+ match = spsr & SPSR_C;
+ break;
+ case 2: /* MI or PL */
+ match = spsr & SPSR_N;
+ break;
+ case 3: /* VS or VC */
+ match = spsr & SPSR_V;
+ break;
+ case 4: /* HI or LS */
+ match = ((spsr & (SPSR_C | SPSR_Z)) == SPSR_C);
+ break;
+ case 5: /* GE or LT */
+ match = (!(spsr & SPSR_N) == !(spsr & SPSR_V));
+ break;
+ case 6: /* GT or LE */
+ match = !(spsr & SPSR_Z) &&
+ (!(spsr & SPSR_N) == !(spsr & SPSR_V));
+ break;
+ case 7: /* AL */
+ match = true;
+ break;
+ }
+ return (!match != !invert);
+}
+
+static enum emul_arm_result
+emul_thumb_insn(struct trapframe *tf, uint32_t insn, int insn_size)
+{
+ /* T32-16bit or 32bit instructions */
+ switch (insn_size) {
+ case 2:
+ /* Breakpoint used by GDB */
+ if (insn == 0xdefe) {
+ do_trapsignal(curlwp, SIGTRAP, TRAP_BRKPT,
+ (void *)tf->tf_pc, 0);
+ return EMUL_ARM_SUCCESS;
+ }
+ /* XXX: some T32 IT instruction deprecated should be emulated */
+ break;
+ case 4:
+ break;
+ default:
+ return EMUL_ARM_FAULT;
+ }
+ return EMUL_ARM_UNKNOWN;
+}
+
static enum emul_arm_result
emul_arm_insn(struct trapframe *tf)
{
- struct lwp * const l = curlwp;
uint32_t insn;
int insn_size;
insn_size = fetch_arm_insn(tf->tf_pc, tf->tf_spsr, );
+ tf->tf_far = reg_far_el1_read();
- switch (insn_size) {
- case 2:
- /* T32-16bit instruction */
+ if (tf->tf_spsr & SPSR_A32_T)
+ return emul_thumb_insn(tf, insn, insn_size);
+ if (insn_size != 4)
+ return EMUL_ARM_FAULT;
- /*
- * Breakpoint used by GDB.
- */
- if (insn == 0xdefe)
- goto trap;
+ /* Breakpoint used by GDB */
+ if (insn == 0xe611 || insn == 0xe7ffdefe) {
+ do_trapsignal(curlwp, SIGTRAP, TRAP_BRKPT,
+ (void *)tf->tf_pc, 0);
+ return EMUL_ARM_SUCCESS;
+ }
- /* XXX: some T32 IT instruction deprecated should be emulated */
- break;
- case 4:
- /* T32-32bit instruction, or A32 instruction */
+ /* Unconditional instruction extension space? */
+ if ((insn & 0xf000) == 0xf000)
+ goto unknown_insn;
- /*
- * Breakpoint used by GDB.
- */
- if (insn == 0xe611 || insn == 0xe7ffdefe) {
- trap:
- do_trapsignal(l, SIGTRAP, TRAP_BRKPT,
- (void *)tf->tf_pc, 0);
- return 0;
- }
-
- /*
- * Emulate ARMv6 instructions with cache operations
- * register (c7), that can be used in user mode.
- */
- switch (insn & 0x0fff0fff) {
- case 0x0e070f95:
+ /*
+ * Emulate ARMv6 instructions with cache operations
+ * register (c7), that can be used in user mode.
+ */
+ switch (insn & 0x0fff0fff) {
+ case 0x0e070f95:
+ if (arm_cond_match(insn, tf->tf_spsr)) {
/*
* mcr p15, 0, , c7, c5, 4
* (flush prefetch buffer)
*/
__asm __volatile("isb sy" ::: "memory");
- goto emulated;
- case 0x0e070f9a:
+ }
+ goto
CVS commit: src/sys/arch/aarch64/aarch64
Module Name:src
Committed By: skrll
Date: Thu Jul 23 13:12:54 UTC 2020
Modified Files:
src/sys/arch/aarch64/aarch64: cpuswitch.S
Log Message:
Reduce the window of having interrupts disabled in cpu_switchto{,_softint}
and ensure astpending is checked with interrupts disabled.
To generate a diff of this commit:
cvs rdiff -u -r1.21 -r1.22 src/sys/arch/aarch64/aarch64/cpuswitch.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/aarch64/aarch64/cpuswitch.S
diff -u src/sys/arch/aarch64/aarch64/cpuswitch.S:1.21 src/sys/arch/aarch64/aarch64/cpuswitch.S:1.22
--- src/sys/arch/aarch64/aarch64/cpuswitch.S:1.21 Sat May 23 18:08:59 2020
+++ src/sys/arch/aarch64/aarch64/cpuswitch.S Thu Jul 23 13:12:54 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: cpuswitch.S,v 1.21 2020/05/23 18:08:59 ryo Exp $ */
+/* $NetBSD: cpuswitch.S,v 1.22 2020/07/23 13:12:54 skrll Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -38,7 +38,7 @@
#include "opt_ddb.h"
#include "opt_kasan.h"
-RCSID("$NetBSD: cpuswitch.S,v 1.21 2020/05/23 18:08:59 ryo Exp $")
+RCSID("$NetBSD: cpuswitch.S,v 1.22 2020/07/23 13:12:54 skrll Exp $")
ARMV8_DEFINE_OPTIONS
@@ -76,16 +76,18 @@ ENTRY_NP(cpu_switchto)
str x4, [x6, #PCB_TF]
/* We are done with the old lwp */
-
- DISABLE_INTERRUPT
ldr x6, [x1, #L_PCB] /* x6 = lwp_getpcb(newlwp) */
ldr x4, [x6, #PCB_TF] /* get trapframe ptr (aka SP) */
#ifdef DDB
str xzr, [x6, #PCB_TF] /* clear l->l_addr->pcb_tf */
#endif
ldr x5, [x1, #L_MD_CPACR] /* get cpacr_el1 */
+
+ mrs x3, tpidr_el1
+ DISABLE_INTERRUPT
mov sp, x4 /* restore stack pointer */
msr cpacr_el1, x5 /* restore cpacr_el1 */
+ str x1, [x3, #CI_CURLWP] /* switch curlwp to new lwp */
#ifdef ARMV83_PAC
/* Switch the PAC key. */
@@ -116,8 +118,6 @@ ENTRY_NP(cpu_switchto)
1:
#endif
- mrs x3, tpidr_el1
- str x1, [x3, #CI_CURLWP] /* switch curlwp to new lwp */
ENABLE_INTERRUPT
/*
@@ -161,26 +161,14 @@ ENTRY_NP(cpu_switchto_softint)
stp x27, x28, [sp, #TF_X27]
stp x29, x2, [sp, #TF_X29] /* tf->lr = softint_cleanup; */
- mrs x3, tpidr_el1 /* x3 := curcpu() */
- DISABLE_INTERRUPT
- ldr x19, [x3, #CI_CURLWP] /* x19 := curcpu()->ci_curlwp */
+ mrs x20, tpidr_el1 /* x20 := curcpu() */
+ ldr x19, [x20, #CI_CURLWP] /* x19 := curcpu()->ci_curlwp */
mov x4, sp
+
mrs x5, cpacr_el1
ldr x6, [x19, #L_PCB] /* x6 = lwp_getpcb(curlwp) */
str x4, [x6, #PCB_TF]
str x5, [x19, #L_MD_CPACR]
- str x0, [x3, #CI_CURLWP] /* curcpu()->ci_curlwp = softlwp; */
-
-#ifdef ARMV83_PAC
- /* Switch the PAC key. */
- adrl x4, _C_LABEL(aarch64_pac_enabled)
- ldr w4, [x4]
- cbz w4, 1f
- ldp x5, x6, [x0, #L_MD_IA_KERN]
- msr APIAKeyLo_EL1, x5
- msr APIAKeyHi_EL1, x6
-1:
-#endif
#ifdef KASAN
/* clear the new stack */
@@ -189,26 +177,42 @@ ENTRY_NP(cpu_switchto_softint)
ldp x0, x1, [sp], #16
#endif
- /* onto new stack */
ldr x4, [x0, #L_MD_UTF]
+
+ DISABLE_INTERRUPT
+ /* onto new stack */
sub sp, x4, #TF_SIZE /* new sp := softlwp->l_md_utf - 1 */
+ str x0, [x20, #CI_CURLWP] /* curcpu()->ci_curlwp = softlwp; */
+
mov x5, #CPACR_FPEN_NONE
msr cpacr_el1, x5 /* cpacr_el1 = CPACR_FPEN_NONE */
+
+#ifdef ARMV83_PAC
+ /* Switch the PAC key. */
+ adrl x4, _C_LABEL(aarch64_pac_enabled)
+ ldr w4, [x4]
+ cbz w4, 1f
+ ldp x5, x6, [x0, #L_MD_IA_KERN]
+ msr APIAKeyLo_EL1, x5
+ msr APIAKeyHi_EL1, x6
+1:
+#endif
ENABLE_INTERRUPT
/* softint_dispatch(pinned_lwp, ipl) */
mov x0, x19 /* x0 := pinned_lwp */
bl _C_LABEL(softint_dispatch)
- mrs x3, tpidr_el1
- DISABLE_INTERRUPT
- str x19, [x3, #CI_CURLWP] /* curcpu()->ci_curlwp := x19 */
+ mrs x20, tpidr_el1
ldr x6, [x19, #L_PCB] /* x6 = lwp_getpcb(curlwp) */
ldr x4, [x6, #PCB_TF] /* x4 := pinned_lwp->l_addr->pcb_tf */
#ifdef DDB
str xzr, [x6, #PCB_TF] /* clear l->l_addr->pcb_tf */
#endif
ldr x5, [x19, #L_MD_CPACR] /* x5 := pinned_lwp->l_md_cpacr */
+
+ DISABLE_INTERRUPT
+ str x19, [x20, #CI_CURLWP] /* curcpu()->ci_curlwp := x19 */
mov sp, x4 /* restore pinned_lwp sp */
msr cpacr_el1, x5 /* restore pinned_lwp cpacr */
@@ -245,10 +249,10 @@ END(cpu_switchto_softint)
ENTRY_NP(softint_cleanup)
mov lr, x20 /* restore original lr */
- mrs x3, tpidr_el1 /* curcpu() */
- ldr w2, [x3, #CI_MTX_COUNT] /* ->ci_mtx_count */
+ mrs x20, tpidr_el1 /* curcpu() */
+ ldr w2, [x20, #CI_MTX_COUNT]/* ->ci_mtx_count */
add w2, w2, #1
- str w2, [x3, #CI_MTX_COUNT]
+ str w2, [x20, #CI_MTX_COUNT]
msr daif, x19 /* restore interrupt mask */
ldp x19, x20, [sp], #16 /* restore */
@@ -360,6 +364,7 @@ ENTRY_NP(el0_trap)
nop/* dummy for DDB backtrace (for lr-4) */
#endif
ENTRY_NP(el0_trap_exit)
+ DISABLE_INTERRUPT /* make sure I|F marked */
1:
/* while (curcpu()->ci_astpending & __BIT(0)) { */
mrs x8, tpidr_el1
@@ -379,8 +384,6 @@ ENTRY_NP(el0_trap_exit)
b 1b
/* } */
9:
- DISABLE_INTERRUPT /* make sure I|F marked */
-
mrs x8,
CVS commit: src/sys/arch/aarch64/aarch64
Module Name:src Committed By: ryo Date: Sun Jul 19 07:18:07 UTC 2020 Modified Files: src/sys/arch/aarch64/aarch64: cpufunc_asm_armv8.S Log Message: fix build error with LLVM. To generate a diff of this commit: cvs rdiff -u -r1.6 -r1.7 src/sys/arch/aarch64/aarch64/cpufunc_asm_armv8.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/aarch64/aarch64/cpufunc_asm_armv8.S diff -u src/sys/arch/aarch64/aarch64/cpufunc_asm_armv8.S:1.6 src/sys/arch/aarch64/aarch64/cpufunc_asm_armv8.S:1.7 --- src/sys/arch/aarch64/aarch64/cpufunc_asm_armv8.S:1.6 Wed Jul 1 07:59:16 2020 +++ src/sys/arch/aarch64/aarch64/cpufunc_asm_armv8.S Sun Jul 19 07:18:07 2020 @@ -1,4 +1,4 @@ -/* $NetBSD: cpufunc_asm_armv8.S,v 1.6 2020/07/01 07:59:16 ryo Exp $ */ +/* $NetBSD: cpufunc_asm_armv8.S,v 1.7 2020/07/19 07:18:07 ryo Exp $ */ /*- * Copyright (c) 2014 Robin Randhawa @@ -43,18 +43,18 @@ * Macro to handle the cache. This takes the start address in x0, length * in x1. It will corrupt x2-x5. */ -.macro cache_handle_range dcop = 0, icop = 0 +.macro cache_handle_range dcop = "", icop = "" mrs x3, ctr_el0 mov x4, #4 /* size of word */ -.if \dcop != 0 +.ifnb \dcop ubfx x2, x3, #16, #4 /* x2 = D cache shift */ lsl x2, x4, x2 /* x2 = D cache line size */ .endif -.if \icop != 0 +.ifnb \icop and x3, x3, #15 /* x3 = I cache shift */ lsl x3, x4, x3 /* x3 = I cache line size */ .endif -.if \dcop != 0 +.ifnb \dcop sub x4, x2, #1 /* Get the address mask */ and x4, x0, x4 /* Get the low bits of the address */ add x5, x1, x4 /* Add these to the size */ @@ -66,7 +66,7 @@ b.hi 1b /* Check if we are done */ dsb ish .endif -.if \icop != 0 +.ifnb \icop sub x4, x3, #1 /* Get the address mask */ and x4, x0, x4 /* Get the low bits of the address */ add x5, x1, x4 /* Add these to the size */
CVS commit: src/sys/arch/aarch64/aarch64
Module Name:src
Committed By: ryo
Date: Fri Jul 17 07:21:44 UTC 2020
Modified Files:
src/sys/arch/aarch64/aarch64: pmapboot.c
Log Message:
KNF. 80 cols, use tab.
To generate a diff of this commit:
cvs rdiff -u -r1.9 -r1.10 src/sys/arch/aarch64/aarch64/pmapboot.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/aarch64/aarch64/pmapboot.c
diff -u src/sys/arch/aarch64/aarch64/pmapboot.c:1.9 src/sys/arch/aarch64/aarch64/pmapboot.c:1.10
--- src/sys/arch/aarch64/aarch64/pmapboot.c:1.9 Fri Jul 17 07:16:10 2020
+++ src/sys/arch/aarch64/aarch64/pmapboot.c Fri Jul 17 07:21:44 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: pmapboot.c,v 1.9 2020/07/17 07:16:10 ryo Exp $ */
+/* $NetBSD: pmapboot.c,v 1.10 2020/07/17 07:21:44 ryo Exp $ */
/*
* Copyright (c) 2018 Ryo Shimizu
@@ -27,7 +27,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: pmapboot.c,v 1.9 2020/07/17 07:16:10 ryo Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pmapboot.c,v 1.10 2020/07/17 07:21:44 ryo Exp $");
#include "opt_arm_debug.h"
#include "opt_ddb.h"
@@ -264,7 +264,8 @@ pmapboot_enter(vaddr_t va, paddr_t pa, p
if (l0[idx0] == 0) {
l1 = pmapboot_pagealloc();
if (l1 == NULL) {
-VPRINTF("pmapboot_enter: cannot allocate L1 page\n");
+VPRINTF("pmapboot_enter: "
+"cannot allocate L1 page\n");
return -1;
}
@@ -308,7 +309,8 @@ pmapboot_enter(vaddr_t va, paddr_t pa, p
if (!l1pde_valid(l1[idx1])) {
l2 = pmapboot_pagealloc();
if (l2 == NULL) {
-VPRINTF("pmapboot_enter: cannot allocate L2 page\n");
+VPRINTF("pmapboot_enter: "
+"cannot allocate L2 page\n");
return -1;
}
@@ -351,7 +353,8 @@ pmapboot_enter(vaddr_t va, paddr_t pa, p
if (!l2pde_valid(l2[idx2])) {
l3 = pmapboot_pagealloc();
if (l3 == NULL) {
-VPRINTF("pmapboot_enter: cannot allocate L3 page\n");
+VPRINTF("pmapboot_enter: "
+"cannot allocate L3 page\n");
return -1;
}
@@ -403,7 +406,8 @@ pmapboot_enter(vaddr_t va, paddr_t pa, p
}
if (va == va_end && (llidx & 15) != 15) {
/* clear CONTIG flag after this pte entry */
-for (i = (llidx + 1); i < ((llidx + 16) & ~15); i++) {
+for (i = (llidx + 1); i < ((llidx + 16) & ~15);
+i++) {
ll[i] &= ~LX_BLKPAG_CONTIG;
}
}
@@ -445,7 +449,7 @@ pmapboot_pagealloc(void)
char *e = s + PAGE_SIZE;
while (s < e)
- *s++ = 0;
+ *s++ = 0;
return (pd_entry_t *)pa;
}
