Hi York,
On Tue, Dec 20, 2016 at 6:14 AM, york sun wrote:
> On 12/18/2016 11:26 PM, Chris Packham wrote:
>> When setting the compatible property for the L2 cache ensure that we
>> follow the documented binding by setting both
>> "-l2-cache-controller" and "cache" as values.
>>
Currently, mdelay() and udelay() are declared in include/common.h,
while ndelay() in include/linux/compat.h. It would be nice to
collect them into include/linux/delay.h like Linux.
While we are here, fix the ndelay() implementation; I used the
DIV_ROUND_UP() instead of (x)/1000 because we must
On 16.12.2016 18:28, Moritz Fischer wrote:
> Hi Michal,
>
> On Fri, Dec 16, 2016 at 5:38 AM, Michal Simek wrote:
>> spi-max-frequency for spi bus depends on devices which are
>> connected to it. Remove this parameter from dtsi file.
>>
>> Signed-off-by: Michal Simek
Masahiro Yamada (5):
delay: collect {m,n,u}delay declarations to include/linux/delay.h
time: move timer APIs to include/time.h
typecheck: import include/linux/typecheck.h from Linux 4.9
time: import time_after, time_before and friends from Linux
iopoll: import include/linux/iopoll.h
The include/common.h is a collection of unrelated declarations,
macros, etc.
It is horrible to include such a cluttered header just for some
timer functions. Split out timer functions into include/timer.h.
Signed-off-by: Masahiro Yamada
---
include/common.h |
It is not safe to compare timer values directly.
On 32-bit systems, for example, timer_get_us() wraps around every
72 min. (2 ^ 32 / 100 =~ 4295 sec =~ 72 min). Depending on
the get_ticks() implementation, it may wrap more frequently.
The 72 min might be possible on the use of U-Boot.
Let's
This was imported from Linux 4.9 and adjusted for U-Boot.
- Replace the license block with SPDX
- Drop all *_atomic variants, which make no sense for U-Boot
- Remove the sleep_us argument, which makes no sense for U-Boot
Signed-off-by: Masahiro Yamada
---
Copied from Linux 4.9.
Signed-off-by: Masahiro Yamada
---
include/linux/typecheck.h | 24
1 file changed, 24 insertions(+)
create mode 100644 include/linux/typecheck.h
diff --git a/include/linux/typecheck.h b/include/linux/typecheck.h
On 18.12.2016 15:03, Nathan Rossi wrote:
> The dram_init and dram_init_banksize functions were using a board
> specific implementation for decoding the memory banks from the fdt. This
> board specific implementation uses a static variable 'tmp' which makes
> these functions unsafe for execution
Hi Tom.
2016-12-07 22:10 GMT+09:00 Masahiro Yamada :
>
> I wrote a new SDHCI driver for my new SoCs, but before posting it,
> I just want to make a clean base for my driver entry.
>
> Of course, I could enable some needed options in my header file
> (for options in
Hello Tom,
please pull from u-boot-i2c.git master
The following changes since commit 0b4bc1b3ab1850fccbade3e6103f2036f6bdb364:
Merge branch 'master' of git://git.denx.de/u-boot-spi (2016-12-16 18:32:43
-0500)
are available in the git repository at:
git://git.denx.de/u-boot-i2c.git
Hi Igor, Simon,
On 12/15/2016 11:08 AM, Igor Grinberg wrote:
> Hi Tomas,
>
> On 12/14/16 16:23, Tomas Melin wrote:
>> Hi Simon, Igor,
>>
>> On 12/14/2016 02:53 PM, Igor Grinberg wrote:
>>> On 12/13/16 22:29, Simon Glass wrote:
>>>
>>> I think two above debug() are very legitimate - no
2016-12-20 6:59 GMT+09:00 Tom Rini :
> On Mon, Dec 19, 2016 at 07:31:02PM +0900, Masahiro Yamada wrote:
>> Commit be72591bcd64 ("Kconfig: Move USE_ARCH_MEMCPY/MEMSET to
>> Kconfig") is misconversion.
>>
>> The original logic in include/configs/uniphier.h was as follows:
>>
>>
Hi Tom.
2016-12-20 7:02 GMT+09:00 Tom Rini :
> On Mon, Dec 19, 2016 at 07:31:03PM +0900, Masahiro Yamada wrote:
>
>> CONFIG_USE_ARCH_MEMSET controls nothing about SPL. (it is effective
>> only on U-Boot proper building of ARM).
>
> That's not true. We have these functions
On Sun, Nov 20, 2016 at 4:25 AM, Simon Glass wrote:
> Update the Makefile so that some 32-bit init can be built into SPL rather
> than U-Boot proper.
>
> Signed-off-by: Simon Glass
> ---
>
> Changes in v2: None
>
> arch/x86/cpu/ivybridge/Makefile | 4 ++--
>
On Sun, Nov 20, 2016 at 4:25 AM, Simon Glass wrote:
> Use this new option to control the location of 32-bit init. This will allow
> us to place this in SPL if needed.
>
> Signed-off-by: Simon Glass
> ---
>
> Changes in v2: None
>
>
On Sun, Nov 20, 2016 at 4:25 AM, Simon Glass wrote:
> Use this new option to control the location of 16-bit init. This will allow
> us to place this in SPL if needed.
>
> Signed-off-by: Simon Glass
> ---
>
> Changes in v2: None
>
> Makefile|
Hi Simon,
On Sun, Nov 20, 2016 at 4:25 AM, Simon Glass wrote:
> At present all 16/32-bit init is controlled by CONFIG_X86_RESET_VECTOR. If
> this is enabled, then U-Boot is the 'first' boot loader and handles execution
> from the reset vector through to U-Boot's command
Hi Simon,
On Sun, Nov 20, 2016 at 4:25 AM, Simon Glass wrote:
> Add a new CONFIG_X86_64 option which will eventually cause U-Boot to be
> built as a 64-bit application, with SPL doing the 16/32-bit init.
>
> Signed-off-by: Simon Glass
> ---
>
> Changes in
On Sun, Nov 20, 2016 at 4:25 AM, Simon Glass wrote:
> Fix a cast in get_next_hob() that causes warnings on 64-bit machines.
>
> Signed-off-by: Simon Glass
> ---
>
> Changes in v2:
> - Fix cast in get_guid_hob_data() also
>
>
On Sun, Nov 20, 2016 at 4:25 AM, Simon Glass wrote:
> We almost always need the serial port before relocation, so mark it as such.
> This will ensure that it appears in the device tree for SPL, if used.
>
> Signed-off-by: Simon Glass
> ---
>
> Changes in v2:
On Sun, Nov 20, 2016 at 4:24 AM, Simon Glass wrote:
> We should use unsigned long rather than u32 for addresses. Update this so
> that the table-generation code builds correctly on 64-bit machines.
>
> Signed-off-by: Simon Glass
> ---
>
> Changes in v2:
> -
Hi Tom
On Mon, 2016-12-19 at 20:14 +, Tom Warren wrote:
> Marcel,
>
> > -Original Message-
> > From: Marcel Ziswiler [mailto:mar...@ziswiler.com]
> > Sent: Monday, December 19, 2016 7:36 AM
> > To: u-boot@lists.denx.de
> > Cc: Max Krummenacher ; Stefan
On 12/18/2016 09:11 PM, Priyanka Jain wrote:
> Firmware of Management Complex (MC) should be loaded
> at 512MB aligned privately allocated memory at DRAM end.
> And this memory should be reduced from total memory
> available for general purposes.
It is already reserved at the alignment of
Hi Tom,
On Mon, Dec 19, 2016 at 8:09 PM, Tom Rini wrote:
> I feel like this is correct. I also feel like it's too close to release
> to do this, so I'll be applying this shortly after release, thanks!
Yes, agreed this is material for the next release.
> I also found it
On Thu, Dec 15, 2016 at 04:00:13PM -0200, Fabio Estevam wrote:
> Simplify the 'cp' command implementation by using the memcpy() function,
> which brings the additional benefit of performance gain for those who have
> CONFIG_USE_ARCH_MEMCPY selected.
>
> Tested on a mx6qsabreauto board where a 5x
On Mon, Dec 19, 2016 at 07:31:03PM +0900, Masahiro Yamada wrote:
> CONFIG_USE_ARCH_MEMSET controls nothing about SPL. (it is effective
> only on U-Boot proper building of ARM).
That's not true. We have these functions available to SPL and use them
there by default now (as it's a speed win and
Previously values greater than 255 were implicitly truncated. Add some
stricter checking to reject addresses with components >255.
With the input "1234192.168.1.1" the old behaviour would truncate the
address to 192.168.1.1. New behaviour rejects the string outright and
returns 0.0.0.0, which for
On Mon, Dec 19, 2016 at 07:31:04PM +0900, Masahiro Yamada wrote:
> These options are now described in the Kconfig help. We do not want
> to maintain duplicated documentation.
>
> Signed-off-by: Masahiro Yamada
Reviewed-by: Tom Rini
--
Tom
On Mon, Dec 19, 2016 at 07:31:02PM +0900, Masahiro Yamada wrote:
> Commit be72591bcd64 ("Kconfig: Move USE_ARCH_MEMCPY/MEMSET to
> Kconfig") is misconversion.
>
> The original logic in include/configs/uniphier.h was as follows:
>
> #if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_ARM64)
>
Hi all,
I'm working on a Zynq-7000 system that currently performs a "legacy" boot - the
kernel, device tree and initramfs are loaded independently into RAM, and then
they're all loaded by passing their addresses into 'bootm'. I'd like to update
this to a "moderm" boot, where the system loads a
Hey all,
It's release day and v2017.01-rc2 is out. I've tried to clean up my
queue a bit and I think it's looking OK. I also know that there's a few
things others have outstanding that I'm inclined to let come in such as
binman. If anyone thinks that's a bad idea, please shout. I think
things
On Mon, Dec 19, 2016 at 03:27:50PM +0100, Marek Vasut wrote:
> The EVP_MD_CTX and EVP_CIPHER_CTX are made opaque since 1.1.x , so instead
> of embedding them directly into struct sb_image_ctx and initializing them
> using EVP_*_CTX_init(), we use pointers and allocate the crypto contexts
> using
On Thu, Dec 15, 2016 at 04:48:55PM +0100, Marek Vasut wrote:
> Shuffle the macros around a little to remove the following warning
> when building for i.MX28:
>
> arch/arm/cpu/arm926ejs/mxs/spl_boot.c:44:26: warning: ‘iomux_boot’ defined
> but not used [-Wunused-const-variable=]
> static const
On Thu, Dec 01, 2016 at 02:06:31AM +0100, Marek Vasut wrote:
> Add compatibility string for the Ingenic JZ4780 SoC, the necessary
> UART enable bit into FCR and register shift. Neither are encoded
> in the DTS coming from Linux, so we need to support it this way.
>
> Signed-off-by: Marek Vasut
On Thu, Dec 01, 2016 at 02:06:30AM +0100, Marek Vasut wrote:
> Add driver data to each compatible string to identify the type of
> the port. Since all the ports in the driver are entirely compatible
> with 16550 for now, all are marked with PORT_NS16550. But, there
> are ports which have specific
On Thu, Dec 01, 2016 at 02:06:29AM +0100, Marek Vasut wrote:
> Add function which allows fetching the default FCR register setting
> from platform data for DM , while retaining old behavior for non-DM
> by returning UART_FCRVAL.
>
> Signed-off-by: Marek Vasut
> Cc: Tom Rini
On Sun, Dec 18, 2016 at 06:48:17PM +0100, Stefano Babic wrote:
> Hi Tom,
>
> please pull from u-boot-imx, thanks !
>
> The following changes since commit 53e8ca22538c2cec691fe74098684a359302688c:
>
> MAINTAINERS: DFU: Change e-mail address for DFU maintainer (2016-12-12
> 13:03:15 -0500)
>
Marcel,
> -Original Message-
> From: Marcel Ziswiler [mailto:mar...@ziswiler.com]
> Sent: Monday, December 19, 2016 7:36 AM
> To: u-boot@lists.denx.de
> Cc: Max Krummenacher ; Stefan Agner
> ; Marcel Ziswiler
>
On Sat, Dec 17, 2016 at 2:46 PM, Simon Glass wrote:
> Hi Maxim,
>
> On 16 December 2016 at 17:18, Maxim Sloyko wrote:
>> Greetings,
>>
>> I'm working on adding new platform to U-Boot and right now I'm trying
>> to clean up the directory structure, but
On 12/18/2016 11:26 PM, Chris Packham wrote:
> When setting the compatible property for the L2 cache ensure that we
> follow the documented binding by setting both
> "-l2-cache-controller" and "cache" as values.
>
> Signed-off-by: Chris Packham
> ---
>
> Changes in v2:
>
On Mon, Dec 19, 2016 at 5:23 PM, Icenowy Zheng wrote:
>
>
> 16.12.2016, 22:52, "Jagan Teki" :
>> On Fri, Dec 16, 2016 at 3:35 PM, Icenowy Zheng wrote:
>>> Add a proper device tree file for Orange Pi Zero boards from Xunlong,
>>> which
16.12.2016, 22:52, "Jagan Teki" :
> On Fri, Dec 16, 2016 at 3:35 PM, Icenowy Zheng wrote:
>> Add a proper device tree file for Orange Pi Zero boards from Xunlong,
>> which come with a Allwinner H2+ SoC (similar to H3).
>>
>> Signed-off-by: Icenowy Zheng
Hi,
On 19-12-16 17:25, Icenowy Zheng wrote:
20.12.2016, 00:17, "Hans de Goede" :
Hi,
On 19-12-16 17:06, Icenowy Zheng wrote:
19.12.2016, 23:30, "Hans de Goede" :
Hi,
On 19-12-16 16:22, Icenowy Zheng wrote:
Hi everyone,
Today, I and
20.12.2016, 00:17, "Hans de Goede" :
> Hi,
>
> On 19-12-16 17:06, Icenowy Zheng wrote:
>> 19.12.2016, 23:30, "Hans de Goede" :
>>> Hi,
>>>
>>> On 19-12-16 16:22, Icenowy Zheng wrote:
Hi everyone,
Today, I and KotCzarny on IRC of
Hi,
I observe a behavior with the QSPI functionality on newer uboot versions; e.g.
2016.11 rc1 and also latest from DENX mainline.
I was wondering whether anyone else has experienced similar issue(s) and can
perhaps give hints as to what can cause this.
I will try to narrow down the issue
From: Marcel Ziswiler
This patch adds board support for the Toradex Apalis TK1 a computer on
module which can be used on different carrier boards.
The module consists of a Tegra TK1 SoC, a PMIC solution, 2 GB of DDR3L
RAM, a bunch of level shifters, an eMMC, a
On Sel, 2016-12-06 at 16:10 +0800, Chee Tien Fong wrote:
> From: Tien Fong Chee
>
> The drivers is restructured such common functions, gen5 functions,
> and arria10 functions are moved to clock_manager.c, cock_manager_gen5
> and clock_manager_arria10 respectively.
>
>
Hi,
On 19-12-16 17:06, Icenowy Zheng wrote:
19.12.2016, 23:30, "Hans de Goede" :
Hi,
On 19-12-16 16:22, Icenowy Zheng wrote:
Hi everyone,
Today, I and KotCzarny on IRC of linux-sunxi found a problem in the SID
controller of H3 (incl. H2+).
See
I am working on a new Allwiner A13 and accesory chipset board, whose
name is Wakame, after the seafood.
After working several months on this project, now i think that the idea
of building a prototype starts to come a feasible thing.Obviously it is
my very first development ever since i
19.12.2016, 23:30, "Hans de Goede" :
> Hi,
>
> On 19-12-16 16:22, Icenowy Zheng wrote:
>> Hi everyone,
>>
>> Today, I and KotCzarny on IRC of linux-sunxi found a problem in the SID
>> controller of H3 (incl. H2+).
>>
>> See
Hi,
On 19-12-16 16:22, Icenowy Zheng wrote:
Hi everyone,
Today, I and KotCzarny on IRC of linux-sunxi found a problem in the SID
controller of H3 (incl. H2+).
See https://irclog.whitequark.org/linux-sunxi/2016-12-19 .
Two read method of the H3 eFUSE is used in the BSP: by register accessing,
From: Konstantin Porotchkin
Add default configuration for MACHHIATOBin community board
based on Aramda-8040 SoC.
Change-Id: I60efcca5b31060340ad0a948561f082646f6556c
Signed-off-by: Konstantin Porotchkin
Cc: Stefan Roese
Cc: Nadav Haklai
From: Konstantin Porotchkin
Add support for "marvell,vbus-gpio" property to mvebu XHCI
board init function.
This option is valid when CONFIG_DM_GPIO=y
Change-Id: I930b3ebe001e50ae8d5abe1f3c774bcdb1739e64
Signed-off-by: Konstantin Porotchkin
Cc: Stefan
From: Konstantin Porotchkin
Add i2c-1 pin mappings to CP0(master) DTSI file
Change-Id: I0c6e6de8a557393f518f7df8e6daa6dfce1788b0
Signed-off-by: Konstantin Porotchkin
Cc: Stefan Roese
Cc: Nadav Haklai
Cc: Neta Zur
From: Konstantin Porotchkin
Add GPIO nodes to AP-806 and CP-110-master DTSI files.
Change-Id: I05958698d460cb721b7d8683d34f74a5ea32532c
Signed-off-by: Konstantin Porotchkin
Cc: Stefan Roese
Cc: Nadav Haklai
Cc: Neta
From: Konstantin Porotchkin
Add board init hook to mvebu DW PCIe device driver.
Add support for "marvell,reset-gpio" property to A8K
board init function.
This option is valid when CONFIG_DM_GPIO=y
Change-Id: Ic17c500449050c2fbb700731f1a9ca8b83298986
Signed-off-by: Konstantin
From: Rabeeh Khoury
Added A8040 dts file for community board MACCHIATIBin.
The patch includes the following features:
AP - eMMC, Serial console (connected to onboard FTDI usb to serial)
CP0 - PCIe x4, SATA, I2C and 10G KR
(connected to Marvell 3310 10G copper / SFP+
From: Konstantin Porotchkin
Update the MMC block device access code in bubt command
implementation according to the latest MMC driver changes
Change-Id: Ie852ceefa0b040ffe1362bdb7815fcea9b2d923b
Signed-off-by: Konstantin Porotchkin
Cc: Stefan Roese
From: Konstantin Porotchkin
This patch series adds initil support for A8K community board
MACCHIATOBin manufactured by SolidRun.
It should be applied on top of Stefan Roese patches adding support
for SD/eMMC devices on Marvell A37x0/A80x0/A70x0 SoCs.
The top level patch is
From: Konstantin Porotchkin
Fix the MMU mapping for A8K device family:
- Separate A7K and A8K memory mappings
- Fix memory regions by including IO mapping for all
3 PCIe interfaces existing on each connected CP110 controller
Add A8K memory mapping documentation with all
From: Marcel Ziswiler
Fix 'driver model' rather than 'driver mode' in description.
Signed-off-by: Marcel Ziswiler
---
drivers/pci/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pci/Kconfig
From: Marcel Ziswiler
Add a comment about the disabled PCIe port nodes.
Signed-off-by: Marcel Ziswiler
---
arch/arm/dts/tegra30-apalis.dts | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/dts/tegra30-apalis.dts
From: Marcel Ziswiler
This series contains two spelling fixes, some added comments as well as
the Toradex Colibri T20 ULPI reset polarity fix.
The whole series is also available here:
http://git.toradex.com/cgit/u-boot-toradex.git/log/?h=for-next
Marcel Ziswiler
From: Marcel Ziswiler
Fix ULPI reset polarity which caused a hard hang on Colibri T20 upon
attempting to start the USB subsystem:
This fixes my late commit d5a24d8b53d350364bd429b7104ec369b817e4b8
(colibri_t20: fix usb operation and controller order) inadvertently
From: Marcel Ziswiler
Introduce CONFIG_TEGRA124_MMC_DISABLE_EXT_LOOPBACK to disable the external clock
loopback and use the internal one on SDMMC3 as per the SDMMC_VENDOR_MISC_CNTRL_0
register's SDMMC_SPARE1 bits being set to 0xfffd according to the TRM.
From: Marcel Ziswiler
This series adds support for the Toradex Apalis TK1 as well as moves
the CONFIG_TEGRA_MMC to Kconfig and introduces a new option to disable
the external clock loopback on SDMMC3.
The whole series is also available here:
From: Marcel Ziswiler
Get rid of spurious 'are' in the comment.
Signed-off-by: Marcel Ziswiler
---
drivers/video/tegra124/display.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/video/tegra124/display.c
From: Marcel Ziswiler
Basically running the following script:
tools/moveconfig.py CONFIG_TEGRA_MMC
Note that I left the SPL specific handling in
include/configs/tegra-common-post.h unchanged.
Signed-off-by: Marcel Ziswiler
From: Marcel Ziswiler
Signed-off-by: Marcel Ziswiler
Reviewed-by: Simon Glass
---
Changes in v2:
- Added Simon's reviewed-by.
drivers/mmc/Kconfig | 6 ++
1 file changed, 6 insertions(+)
diff --git
From: Marcel Ziswiler
Actually make use of that shiny new CONFIG_TEGRA124_MMC_DISABLE_EXT_LOOPBACK.
Signed-off-by: Marcel Ziswiler
---
Changes in v2: None
configs/apalis-tk1_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git
On 19.12.2016 11:33, Andre Przywara wrote:
> Hi,
>
> On 19/12/16 10:01, Maxime Ripard wrote:
>> On Mon, Dec 19, 2016 at 01:50:09AM +, Andre Przywara wrote:
>>> According to Jens disabling the on-die-termination should set bit 5,
>>> not bit 1 in the respective register. Fix this.
>>>
>>>
The EVP_MD_CTX and EVP_CIPHER_CTX are made opaque since 1.1.x , so instead
of embedding them directly into struct sb_image_ctx and initializing them
using EVP_*_CTX_init(), we use pointers and allocate the crypto contexts
using EVP_*_CTX_new().
Signed-off-by: Marek Vasut
Cc: Tom
Hi Tom,
On Fri, 2016-12-09 at 17:18 +0300, Vlad Zakharov wrote:
> Earlier timer driver needed a clock-frequency property in compatible
> device-tree nodes. Another way is to reference a clock via a phandle.
>
> So now timer_pre_probe tries to get clock by reference through device
> tree. In case
Hi,
On Wed, Dec 14, 2016 at 11:11:19PM +0100, Jernej Škrabec wrote:
> > > While I took Rockchip HDMI code for reference, it can't be easily reused.
> > > First of, it uses DT nodes. I guess I could write DT binding or modify
> > > existing driver to work without it.
> >
> > Like we discussed in
On 12/19/2016 11:31 AM, Chee, Tien Fong wrote:
> On Isn, 2016-12-19 at 11:04 +0100, Marek Vasut wrote:
>> On 12/19/2016 09:54 AM, Chee, Tien Fong wrote:
>>>
>>> On Isn, 2016-12-19 at 09:43 +0100, Marek Vasut wrote:
On 12/19/2016 09:40 AM, Chee, Tien Fong wrote:
>
>
> On Isn,
On Sat, Dec 17, 2016 at 04:56:49PM -0800, Stefan Agner wrote:
> > Do you have a base DT and an overlay showing up the error you're
> > trying to fix? Either way, that should be discussed with upstream's
> > libfdt ml and maintainer, not (only) on U-Boot.
>
> Yeah my problem was that my base DT
On 12/19/2016 11:34 AM, Chee, Tien Fong wrote:
> On Isn, 2016-12-19 at 09:44 +0100, Marek Vasut wrote:
>> On 12/19/2016 09:41 AM, Chee, Tien Fong wrote:
>>>
>>> On Isn, 2016-12-19 at 08:56 +0100, Marek Vasut wrote:
On 12/19/2016 05:04 AM, Chee, Tien Fong wrote:
>
>
> On Jum,
On Mon, Dec 19, 2016 at 8:31 AM, Masahiro Yamada
wrote:
> These options are now described in the Kconfig help. We do not want
> to maintain duplicated documentation.
>
> Signed-off-by: Masahiro Yamada
Reviewed-by: Fabio Estevam
On Mon, Dec 19, 2016 at 8:31 AM, Masahiro Yamada
wrote:
> Commit be72591bcd64 ("Kconfig: Move USE_ARCH_MEMCPY/MEMSET to
> Kconfig") is misconversion.
>
> The original logic in include/configs/uniphier.h was as follows:
>
> #if !defined(CONFIG_SPL_BUILD) &&
On Mon, Dec 19, 2016 at 8:31 AM, Masahiro Yamada
wrote:
> CONFIG_USE_ARCH_MEMSET controls nothing about SPL. (it is effective
> only on U-Boot proper building of ARM).
>
> Signed-off-by: Masahiro Yamada
Reviewed-by: Fabio Estevam
Hi,
On 19/12/16 09:57, Maxime Ripard wrote:
> On Mon, Dec 19, 2016 at 01:50:06AM +, Andre Przywara wrote:
>> From: Jens Kuske
>>
>> So far the DRAM driver for the H3 SoC (and apparently boot0/libdram as
>> well) only applied coarse delay line settings, with one delay
On Isn, 2016-12-19 at 09:44 +0100, Marek Vasut wrote:
> On 12/19/2016 09:41 AM, Chee, Tien Fong wrote:
> >
> > On Isn, 2016-12-19 at 08:56 +0100, Marek Vasut wrote:
> > >
> > > On 12/19/2016 05:04 AM, Chee, Tien Fong wrote:
> > > >
> > > >
> > > > On Jum, 2016-12-09 at 14:02 +0100, Marek Vasut
These options are now described in the Kconfig help. We do not want
to maintain duplicated documentation.
Signed-off-by: Masahiro Yamada
---
README | 6 --
1 file changed, 6 deletions(-)
diff --git a/README b/README
index 25cad2f..0bd6e6c 100644
---
Hi,
On 19/12/16 10:01, Maxime Ripard wrote:
> On Mon, Dec 19, 2016 at 01:50:09AM +, Andre Przywara wrote:
>> According to Jens disabling the on-die-termination should set bit 5,
>> not bit 1 in the respective register. Fix this.
>>
>> Reported-by: Jens Kuske
>>
Masahiro Yamada (3):
ARM: revive CONFIG_USE_ARCH_MEMCPY/MEMSET for UniPhier and Tegra
common/init: remove meaningless defined(CONFIG_USE_ARCH_MEMSET)
README: remove description about CONFIG_USE_ARCH_MEMCPY/SET
README| 6 --
arch/arm/Kconfig | 4
Commit be72591bcd64 ("Kconfig: Move USE_ARCH_MEMCPY/MEMSET to
Kconfig") is misconversion.
The original logic in include/configs/uniphier.h was as follows:
#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_ARM64)
#define CONFIG_USE_ARCH_MEMSET
#define CONFIG_USE_ARCH_MEMCPY
#endif
This
CONFIG_USE_ARCH_MEMSET controls nothing about SPL. (it is effective
only on U-Boot proper building of ARM).
Signed-off-by: Masahiro Yamada
---
common/init/board_init.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git
On Isn, 2016-12-19 at 11:04 +0100, Marek Vasut wrote:
> On 12/19/2016 09:54 AM, Chee, Tien Fong wrote:
> >
> > On Isn, 2016-12-19 at 09:43 +0100, Marek Vasut wrote:
> > >
> > > On 12/19/2016 09:40 AM, Chee, Tien Fong wrote:
> > > >
> > > >
> > > > On Isn, 2016-12-19 at 08:55 +0100, Marek Vasut
Salut Maxime,
On 19/12/16 08:20, Maxime Ripard wrote:
> On Sat, Dec 17, 2016 at 02:44:46PM +, André Przywara wrote:
>>> Instead, can you do something similar to tegra, which uses ARMv4t for
>>> SPL and ARMv7 for U-Boot proper?
>>
>> You will need two different (cross-)compilers, so just
On 12/19/2016 09:54 AM, Chee, Tien Fong wrote:
> On Isn, 2016-12-19 at 09:43 +0100, Marek Vasut wrote:
>> On 12/19/2016 09:40 AM, Chee, Tien Fong wrote:
>>>
>>> On Isn, 2016-12-19 at 08:55 +0100, Marek Vasut wrote:
On 12/19/2016 05:10 AM, Chee, Tien Fong wrote:
>
>
> On Rab,
On 12/19/2016 10:30 AM, Chee, Tien Fong wrote:
> On Isn, 2016-12-19 at 08:47 +0100, Marek Vasut wrote:
>> On 12/19/2016 07:53 AM, Chee, Tien Fong wrote:
>>>
>>> On Jum, 2016-12-09 at 13:51 +0100, Marek Vasut wrote:
On 12/09/2016 11:04 AM, Chee, Tien Fong wrote:
>
>
> On Rab,
On Mon, Dec 19, 2016 at 01:50:16AM +, Andre Przywara wrote:
> When compiling the SPL for the Allwinner A64 in AArch64 mode, we can't
> use the more compact Thumb2 encoding, which only exists for AArch32
> code. This makes the SPL rather big, up to a point where any code
> additions or even a
On Mon, Dec 19, 2016 at 01:50:15AM +, Andre Przywara wrote:
> The ARMv8 capable Allwinner A64 SoC comes out of reset in AArch32 mode.
> To run AArch64 code, we have to trigger a warm reset via the RMR register,
> which proceeds with code execution at the address stored in the RVBAR
> register.
On Mon, Dec 19, 2016 at 01:50:11AM +, Andre Przywara wrote:
> Now that the SPL is ready to be compiled in AArch64 and the DRAM
> init code is ready, enable SPL support for the A64 SoC and in the
> Pine64 defconfig.
> For now we keep the boot0 header in the U-Boot proper, as this allows
> to
On Mon, Dec 19, 2016 at 01:50:10AM +, Andre Przywara wrote:
> Fix the output of the DRAM size on AArch64 SPLs.
>
> Signed-off-by: Andre Przywara
> Reviewed-by: Alexander Graf
> Reviewed-by: Simon Glass
Acked-by: Maxime Ripard
On Mon, Dec 19, 2016 at 01:50:09AM +, Andre Przywara wrote:
> According to Jens disabling the on-die-termination should set bit 5,
> not bit 1 in the respective register. Fix this.
>
> Reported-by: Jens Kuske
> Signed-off-by: Andre Przywara
> ---
On Mon, Dec 19, 2016 at 01:50:08AM +, Andre Przywara wrote:
> From: Jens Kuske
>
> The A64 DRAM controller is very similar to the H3 one,
> so the code can be reused with some small changes.
> This refactoring does not change the code size for the existing H3 part.
>
>
On Mon, Dec 19, 2016 at 01:50:06AM +, Andre Przywara wrote:
> From: Jens Kuske
>
> So far the DRAM driver for the H3 SoC (and apparently boot0/libdram as
> well) only applied coarse delay line settings, with one delay value for
> all the data lines in each byte lane and
On Mon, Dec 19, 2016 at 01:50:07AM +, Andre Przywara wrote:
> From: Philipp Tomsich
>
> Signed-off-by: Philipp Tomsich
> Signed-off-by: Andre Przywara
Acked-by: Maxime Ripard
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