Fix a bug of 'commit 8104deb2d6b7 ("armv8: layerscape: Adjust memory
mapping for Flash/SD card on LS1046A")' as NAND block size is
256KB on LS1046AQDS.
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
include/configs/ls1046a_common.h | 2 +-
include/configs/ls1046aqds.h
Tested on ls1046ardb with automatically boot Ubuntu from SD card or
USB disk, if it fails to detect external storage disk, fall back to
qspi boot.
Signed-off-by: Shengzhou Liu <shengzhou@nxp.com>
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
v2:
- No chang
Move the macro to defconfig to take effect globally.
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
v2:
- Reordered the macro.
configs/ls1046aqds_SECURE_BOOT_defconfig| 1 +
configs/ls1046aqds_defconfig| 1 +
configs/ls1046aqds_lpuart_defconfig
Update the default core frequency to 1800MHZ for best performance under
SD boot and eMMC boot.
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
board/freescale/ls1046ardb/ls1046ardb_rcw_emmc.cfg | 2 +-
board/freescale/ls1046ardb/ls1046ardb_rcw_sd.cfg | 2 +-
2 files changed, 2 inse
Tested on ls1046ardb with automatically boot Ubuntu from SD card or
USB disk, if it fails to detect external storage disk, fall back to
qspi boot.
Signed-off-by: Shengzhou Liu <shengzhou@nxp.com>
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
configs/ls1046ardb_qspi_defc
Move the macro to defconfig to take effect globally.
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
configs/ls1046aqds_SECURE_BOOT_defconfig| 1 +
configs/ls1046aqds_defconfig| 1 +
configs/ls1046aqds_lpuart_defconfig | 1 +
c
UART: supports two UARTs up to 115200 bps for console
Signed-off-by: Mingkai Hu <mingkai...@nxp.com>
Signed-off-by: Shaohui Xie <shaohui@nxp.com>
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
v6:
- Move CONFIG_FSL_QSPI to defconfig and select DM_SPI_FLASH in Kconfig.
v
The SPL images are growing much bigger especially when DEBUG is ON.
So need to fix the values for them.
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
include/configs/ls1043a_common.h | 25 -
1 file changed, 16 insertions(+), 9 deletions(-)
diff --git a/i
UART: supports two UARTs up to 115200 bps for console
Signed-off-by: Mingkai Hu <mingkai...@nxp.com>
Signed-off-by: Shaohui Xie <shaohui@nxp.com>
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
v6:
- Move CONFIG_FSL_QSPI to defconfig and select DM_SPI_FLASH in Kconfig.
v
m>
Signed-off-by: Mingkai Hu <mingkai...@nxp.com>
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
v6:
- Remove lpuart support.
- Move CONFIG_FSL_QSPI to defconfig and select DM_SPI_FLASH in Kconfig.
v5:
- Fix SPL_PAD_TO size to block aligned value.
- Adjust the SPL BSS and MA
From: Shengzhou Liu <shengzhou@nxp.com>
Enable ERRATUM_A008511, ERRATUM_A009801, ERRATUM_A009803,
ERRATUM_A009942, ERRATUM_A010165
Signed-off-by: Shengzhou Liu <shengzhou@nxp.com>
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
v3-v6:
- No change.
v2:
- Add ERRAT
From: Shaohui Xie <shaohui@nxp.com>
This is a workaround to fix SATA CRC error. Once the root cause
is found the ECC disabling will be removed.
Signed-off-by: Shaohui Xie <shaohui@nxp.com>
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
v3-v6:
- No change.
As per the top level U-Boot README "Board Initialisation Flow"
section, board_init_f() should return without calling board_init_r()
directly.
Clearing BSS and calling board_init_r() will be done in crt0_64.S.
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
v6:
- No change.
ed-off-by: Mingkai Hu <mingkai...@nxp.com>
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
v3-v6:
- No change.
v2:
- Revise commit message.
arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 15 +++
1 file changed, 15 insertions(+)
diff --git a/arch/arm/cpu/armv8/fsl-lay
From: Shaohui Xie <shaohui@nxp.com>
The CONFIG_STANDALONE_LOAD_ADDR is set to 0x8030 by default.
Signed-off-by: Shaohui Xie <shaohui@nxp.com>
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
v2-v6:
- No change.
arch/arm/include/asm/arch-fsl-layerscape/confi
From: Shaohui Xie <shaohui@nxp.com>
The 'commit 95279315076c ("board/ls2085rdb: Export functions for
standalone AQ FW load apps")' mentioned memset was exported but
it was not, this patch exports the memset.
Signed-off-by: Shaohui Xie <shaohui@nxp.com>
Sign
ove unused flash r/w functions.
- Remove DDR3 defines.
- Revise some commit messages.
Gong Qianyu (1):
armv8: fsl-layerscape: spl: remove BSS clearing and board_init_r
Mingkai Hu (2):
armv8: fsl-layerscape: Increase L2 Data RAM latency and L2 Tag RAM
latency
armv8: ls1046ardb: Add LS1046A
From: Shaohui Xie <shaohui@nxp.com>
When CONFIG_SYS_FSL_ERRATUM_A009801 is defined but
CONFIG_SYS_FSL_ERRATUM_A008511 not defined, there is compile error that
temp32 undeclared, this patch fixes it.
Signed-off-by: Shaohui Xie <shaohui@nxp.com>
Signed-off-by: Gong Qian
From: Shaohui Xie <shaohui@nxp.com>
The 'commit 95279315076c ("board/ls2085rdb: Export functions for
standalone AQ FW load apps")' mentioned memset was exported but
it was not, this patch exports the memset.
Signed-off-by: Shaohui Xie <shaohui@nxp.com>
Sign
From: Shengzhou Liu <shengzhou@nxp.com>
Enable ERRATUM_A008511, ERRATUM_A009801, ERRATUM_A009803,
ERRATUM_A009942, ERRATUM_A010165
Signed-off-by: Shengzhou Liu <shengzhou@nxp.com>
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
v3-v5:
- No change.
v2:
- Add ERRAT
From: Shaohui Xie <shaohui@nxp.com>
When CONFIG_SYS_FSL_ERRATUM_A009801 is defined but
CONFIG_SYS_FSL_ERRATUM_A008511 not defined, there is compile error that
temp32 undeclared, this patch fixes it.
Signed-off-by: Shaohui Xie <shaohui@nxp.com>
Signed-off-by: Gong Qian
m>
Signed-off-by: Mingkai Hu <mingkai...@nxp.com>
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
v5:
- Fix SPL_PAD_TO size to block aligned value.
- Adjust the SPL BSS and MALLOC address.
v4:
- New Patch.
arch/arm/Kconfig | 12
UART: supports two UARTs up to 115200 bps for console
Signed-off-by: Mingkai Hu <mingkai...@nxp.com>
Signed-off-by: Shaohui Xie <shaohui@nxp.com>
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
v5:
- Adjust the SPL BSS and MALLOC address.
v4:
- Extend SPL max size and pad
From: Shaohui Xie <shaohui@nxp.com>
This is a workaround to fix SATA CRC error. Once the root cause
is found the ECC disabling will be removed.
Signed-off-by: Shaohui Xie <shaohui@nxp.com>
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
v3-v5:
- No change.
From: Shaohui Xie <shaohui@nxp.com>
The CONFIG_STANDALONE_LOAD_ADDR is set to 0x8030 by default.
Signed-off-by: Shaohui Xie <shaohui@nxp.com>
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
v2-v5:
- No change.
arch/arm/include/asm/arch-fsl-layerscape/confi
ed-off-by: Mingkai Hu <mingkai...@nxp.com>
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
v3-v5:
- No change.
v2:
- Revise commit message.
arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 15 +++
1 file changed, 15 insertions(+)
diff --git a/arch/arm/cpu/armv8/fsl-lay
As per the top level U-Boot README "Board Initialisation Flow"
section, board_init_f() should return without calling board_init_r()
directly.
Clearing BSS and calling board_init_r() will be done in crt0_64.S.
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
v5:
- New Patch
ERRATUM_A008511.
- Use values directly instead of macros for SATA ECC.
- Add >60 characters' paragraph for the board help.
- Fix the memory map in readme.
- Remove unused flash r/w functions.
- Remove DDR3 defines.
- Revise some commit messages.
Gong Qianyu (1):
armv8: fsl-layerscape: spl: rem
From: Shaohui Xie <shaohui@nxp.com>
This is a workaround to fix SATA CRC error. Once the root cause
is found the ECC disabling will be removed.
Signed-off-by: Shaohui Xie <shaohui@nxp.com>
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
v3-v4:
- No change.
From: Shaohui Xie <shaohui@nxp.com>
The 'commit 95279315076c ("board/ls2085rdb: Export functions for
standalone AQ FW load apps")' mentioned memset was exported but
it was not, this patch exports the memset.
Signed-off-by: Shaohui Xie <shaohui@nxp.com>
Sign
UART: supports two UARTs up to 115200 bps for console
Signed-off-by: Mingkai Hu <mingkai...@nxp.com>
Signed-off-by: Shaohui Xie <shaohui@nxp.com>
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
v4:
- Extend SPL max size and pad_to size for SD boot.
v3:
- Remove red
ed-off-by: Mingkai Hu <mingkai...@nxp.com>
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
v3-v4:
- No change.
v2:
- Revise commit message.
arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 15 +++
1 file changed, 15 insertions(+)
diff --git a/arch/arm/cpu/armv8/fsl-lay
m>
Signed-off-by: Mingkai Hu <mingkai...@nxp.com>
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
v4:
- New Patch.
arch/arm/Kconfig | 12 +
arch/arm/dts/Makefile | 2 +
arch/arm/dts/fsl-ls1046a-qds-duart.dts
Hi all,
This is version 4 patchset mainly to add support for both LS1046ARDB board.
It should be based on two DDR patches to work well on LS1046ARDB or LS1046AQDS.
The two patches are:
http://patchwork.ozlabs.org/patch/663534/
http://patchwork.ozlabs.org/patch/663535/
PCIe and USB are not
From: Shaohui Xie <shaohui@nxp.com>
The CONFIG_STANDALONE_LOAD_ADDR is set to 0x8030 by default.
Signed-off-by: Shaohui Xie <shaohui@nxp.com>
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
v2-v4:
- No change.
arch/arm/include/asm/arch-fsl-layerscape/confi
From: Shaohui Xie <shaohui@nxp.com>
When CONFIG_SYS_FSL_ERRATUM_A009801 is defined but
CONFIG_SYS_FSL_ERRATUM_A008511 not defined, there is compile error that
temp32 undeclared, this patch fixes it.
Signed-off-by: Shaohui Xie <shaohui@nxp.com>
Signed-off-by: Gong Qian
From: Shengzhou Liu <shengzhou@nxp.com>
Enable ERRATUM_A008511, ERRATUM_A009801, ERRATUM_A009803,
ERRATUM_A009942, ERRATUM_A010165
Signed-off-by: Shengzhou Liu <shengzhou@nxp.com>
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
v3-v4:
- No change.
v2:
- Add ERRAT
The current code would always use the speed and mode set by
CONFIG_ENV_SPI_MAX_HZ and CONFIG_ENV_SPI_MODE. But if using
SPI driver model it should get the values from DT.
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
Reviewed-by: Jagan Teki <jt...@openedev.com>
Reviewed-by: Joe
From: Shengzhou Liu <shengzhou@nxp.com>
Enable ERRATUM_A008511, ERRATUM_A009801, ERRATUM_A009803,
ERRATUM_A009942, ERRATUM_A010165
Signed-off-by: Shengzhou Liu <shengzhou@nxp.com>
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
v3:
- No change.
v2:
- Add ERRAT
UART: supports two UARTs up to 115200 bps for console
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
Signed-off-by: Mingkai Hu <mingkai...@nxp.com>
---
v3:
- Remove redundant sd rcw .cfg files.
- Adjust the format of memory map.
- Add emmc boot support.
v2:
- Add >60 characters' pa
From: Shaohui Xie <shaohui@nxp.com>
This is a workaround to fix SATA CRC error. Once the root cause
is found the ECC disabling will be removed.
Signed-off-by: Shaohui Xie <shaohui@nxp.com>
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
v3:
- No change.
v2:
- U
ed-off-by: Mingkai Hu <mingkai...@nxp.com>
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
v3:
- No change.
v2:
- Revise commit message.
arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 15 +++
1 file changed, 15 insertions(+)
diff --git a/arch/arm/cpu/armv8/fsl-layers
From: Shaohui Xie <shaohui@nxp.com>
The CONFIG_STANDALONE_LOAD_ADDR is set to 0x8030 by default.
Signed-off-by: Shaohui Xie <shaohui@nxp.com>
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
v2-v3:
- No change.
arch/arm/include/asm/arch-fsl-layerscape/confi
From: Shaohui Xie <shaohui@nxp.com>
The 'commit 95279315076c ("board/ls2085rdb: Export functions for
standalone AQ FW load apps")' mentioned memset was exported but
it was not, this patch exports the memset.
Signed-off-by: Shaohui Xie <shaohui@nxp.com>
Sign
Hi all,
This is version 3 patchset mainly to add support for LS1046ARDB board.
It should be based on two DDR patches to work well on LS1046ARDB.
The two patches are:
http://patchwork.ozlabs.org/patch/663534/
http://patchwork.ozlabs.org/patch/663535/
PCIe and USB are not supported yet due to lack
From: Shaohui Xie <shaohui@nxp.com>
When CONFIG_SYS_FSL_ERRATUM_A009801 is defined but
CONFIG_SYS_FSL_ERRATUM_A008511 not defined, there is compile error that
temp32 undeclared, this patch fixes it.
Signed-off-by: Shaohui Xie <shaohui@nxp.com>
Signed-off-by: Gong Qian
From: Shaohui Xie <shaohui@nxp.com>
This is a workaround to fix SATA CRC error. Once the root cause
is found the ECC disabling will be removed.
Signed-off-by: Shaohui Xie <shaohui@nxp.com>
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
v2:
- Use values directly
From: Shengzhou Liu <shengzhou@nxp.com>
Enable ERRATUM_A008511, ERRATUM_A009801, ERRATUM_A009803,
ERRATUM_A009942, ERRATUM_A010165
Signed-off-by: Shengzhou Liu <shengzhou@nxp.com>
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
v2:
- Add ERRATUM_A008511.
arch/ar
ed-off-by: Mingkai Hu <mingkai...@nxp.com>
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
v2:
- Revise commit message.
arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 15 +++
1 file changed, 15 insertions(+)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel
From: Shaohui Xie <shaohui@nxp.com>
When CONFIG_SYS_FSL_ERRATUM_A009801 is defined but
CONFIG_SYS_FSL_ERRATUM_A008511 not defined, there is compile error that
temp32 undeclared, this patch fixes it.
Signed-off-by: Shaohui Xie <shaohui@nxp.com>
Signed-off-by: Gong Qian
UART: supports two UARTs up to 115200 bps for console
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
Signed-off-by: Mingkai Hu <mingkai...@nxp.com>
---
v2:
- Add >60 characters' paragraph for the board help.
- Fix the memory map in readme.
- Remove unused flash r/w functions.
From: Shaohui Xie <shaohui@nxp.com>
The 'commit 95279315076c ("board/ls2085rdb: Export functions for
standalone AQ FW load apps")' mentioned memset was exported but
it was not, this patch exports the memset.
Signed-off-by: Shaohui Xie <shaohui@nxp.com>
Sign
From: Shaohui Xie <shaohui@nxp.com>
The CONFIG_STANDALONE_LOAD_ADDR is set to 0x8030 by default.
Signed-off-by: Shaohui Xie <shaohui@nxp.com>
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
v2:
- No change.
arch/arm/include/asm/arch-fsl-layerscape/confi
Hi all,
This is version 2 patchset mainly to add support for LS1046ARDB board.
It should be based on two DDR patches to work well on LS1046ARDB.
The two patches are:
http://patchwork.ozlabs.org/patch/663534/
http://patchwork.ozlabs.org/patch/663535/
PCIe and USB are not supported yet due to lack
Hi all,
This patchset mainly adds support for LS1046ARDB board. Tested on
LS1046ARDB board.
PCIe and USB are not supported yet due to lack of some driver patches
and I'll add them once they're ready for upstream.
Please help to review. Thanks!
Mingkai Hu (3):
drivers/ddr/fsl: add DEBUG_38
From: Shaohui Xie <shaohui@nxp.com>
When CONFIG_SYS_FSL_ERRATUM_A009801 is defined but
CONFIG_SYS_FSL_ERRATUM_A008511 not defined, there is compile error that
temp32 undeclared, this patch fixes it.
Signed-off-by: Shaohui Xie <shaohui@nxp.com>
Signed-off-by: Gong Qian
From: Mingkai Hu <mingkai...@nxp.com>
Use 3 cycles.
Signed-off-by: Mingkai Hu <mingkai...@nxp.com>
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 15 +++
1 file changed, 15 insertions(+)
diff --git a/arch
UART: supports two UARTs up to 115200 bps for console
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
Signed-off-by: Mingkai Hu <mingkai...@nxp.com>
---
arch/arm/Kconfig | 9 +
arch/arm/dts/Makefile | 1 +
arch/arm/dts/f
From: Mingkai Hu <mingkai...@nxp.com>
DEBUG_38 is needed for rev2 DDR controller.
Signed-off-by: Mingkai Hu <mingkai...@nxp.com>
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
drivers/ddr/fsl/ctrl_regs.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/ddr
From: Shengzhou Liu <shengzhou@nxp.com>
Enable ERRATUM_A009801, ERRATUM_A009803, ERRATUM_A009942, ERRATUM_A010165
Signed-off-by: Shengzhou Liu <shengzhou@nxp.com>
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
arch/arm/include/asm/arch-fsl-layerscape/config.h
From: Shaohui Xie <shaohui@nxp.com>
commit 952793150 'board/ls2085rdb: Export functions for standalone
AQ FW load apps' mentioned memset was exported but it was not,
this patch exports the memset.
Signed-off-by: Shaohui Xie <shaohui@nxp.com>
Signed-off-by: Gong Qian
From: Shaohui Xie <shaohui@nxp.com>
So to fix SATA CRC error.
Signed-off-by: Shaohui Xie <shaohui@nxp.com>
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
arch/arm/cpu/armv8/fsl-layerscape/soc.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch
From: Shaohui Xie <shaohui@nxp.com>
The CONFIG_STANDALONE_LOAD_ADDR is set to 0x8030 by default.
Signed-off-by: Shaohui Xie <shaohui@nxp.com>
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
arch/arm/include/asm/arch-fsl-layerscape/config.h | 2 ++
1 file cha
The current code would always use the speed and mode set by
CONFIG_ENV_SPI_MAX_HZ and CONFIG_ENV_SPI_MODE. But if using
SPI driver model it should get the values from DT.
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
Reviewed-by: Jagan Teki <jt...@openedev.com>
---
v2:
- Revised
QSPI and IFC are pin-multiplexed on LS1043AQDS board. If QSPI is
enabled, IFC would not be initialized correctly. So disable the IFC
node for Linux.
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
v3:
- Moved the fixup to board file.
- Detected the muxing through QIXIS at r
When using SPI driver model, it will get the values from DT. So
there is no need to set CONFIG_ENV_SPI_MAX_HZ and
CONFIG_ENV_SPI_MODE any more.
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
include/configs/ls1012a_common.h | 2 --
include/configs/ls1043a_common.h | 2 --
2 files c
The current code would always use the speed and mode set by
CONFIG_ENV_SPI_MAX_HZ and CONFIG_ENV_SPI_MODE. But if using
SPI driver model it should get the values from DT.
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
drivers/net/fm/fm.c | 10 ++
1 file changed, 10 inse
;
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
Reviewed-by: Masahiro Yamada <yamada.masah...@socionext.com>
---
v2:
- Revise commit message, add for A57/A72 part.
- Add comments above the code.
arch/arm/cpu/armv8/start.S | 8
1 file changed, 8 insertions(+)
diff --git a/ar
detection
Gong Qianyu (2):
armv8: fsl-layerscape: Consolidate the LSCH2 common defines
armv8: fsl_lsch2: Add SerDes 2 support
Mingkai Hu (2):
armv8: fsl_lsch2: Add LS1046A SoC support
drivers: net/fm: Add Fman support for LS1046A
arch/arm/cpu/armv8/fsl-layerscape/Makefile | 4
com>
Signed-off-by: Mingkai Hu <mingkai...@nxp.com>
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
v3:
- No change.
v2:
- Move serdes 2 support to a new patch.
- Fix SVR and add LS1026A SVR.
- Add SoC descriptions in README.soc.
- Remove ls1046a errata.
arch/arm/cpu/armv8/fsl-la
New SoC LS1046A belongs to Freescale Chassis Generation 2 and
has two SerDes so we need to add this support in fsl_lsch2.
The SoC related SerDes 2 support will be added in SoC patch.
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
v3:
- Revise commit message.
v2:
- New Patch.
ar
From: Alison Wang <b18...@freescale.com>
Add support to detect Cortex-A72 core for printing it out.
The Initiator Version of A72 core should be 0x4.
Signed-off-by: Alison Wang <alison.w...@nxp.com>
Signed-off-by: Mingkai Hu <mingkai...@nxp.com>
Signed-off-by: Gong Qianyu &l
Both LS1012A and LS1043A belong to FSL_LSCH2 and share some common
configurations. So put the common define under FSL_LSCH2 to increase
readability.
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
v3:
- New Patch.
arch/arm/include/asm/arch-fsl-layerscape/config.
From: Mingkai Hu <mingkai...@nxp.com>
The Fman module on LS1046A is similiar with that on LS1043A but
LS1046A has one more XFI (10GbE) interface.
Signed-off-by: Shaohui Xie <shaohui@nxp.com>
Signed-off-by: Mingkai Hu <mingkai...@nxp.com>
Signed-off-by: Gong Qianyu &l
This patch adds serdes 2 support for FSL_LSCH2.
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
v2:
- New patch.
arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c | 19 +++
arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h | 1 +
.../arm/include/asm/ar
From: Alison Wang <b18...@freescale.com>
Add support to detect Cortex-A72 core for printing it out.
Signed-off-by: Alison Wang <alison.w...@nxp.com>
Signed-off-by: Mingkai Hu <mingkai...@nxp.com>
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
v2:
- Added commit
From: Mingkai Hu <mingkai...@nxp.com>
This patch adds support for aquantia AQR106/107 PHY.
Signed-off-by: Mingkai Hu <mingkai...@nxp.com>
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
drivers/net/phy/aquantia.c | 28
1 file changed, 28 i
com>
Signed-off-by: Mingkai Hu <mingkai...@nxp.com>
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
v2:
- Move serdes 2 support to a new patch.
- Fix SVR and add LS1026A SVR.
- Add SoC descriptions in README.soc.
- Remove ls1046a errata.
arch/arm/cpu/armv8/fsl-layerscape/Makefile
The LS1046A processor is built on the QorIQ LS series architecture
combining four ARM A72 processor cores with DPAA 1.0 support.
Change history:
[Patch v2 1/4] armv8: fsl-layerscape: Add A72 core detection
v2:
- Add commit messages.
[Patch v2 2/4] armv8/fsl_lsch2: Add LS1046A SoC support
v2:
From: Mingkai Hu <mingkai...@nxp.com>
This patch adds Fman support for LS1046A SoC.
Signed-off-by: Shaohui Xie <shaohui@nxp.com>
Signed-off-by: Mingkai Hu <mingkai...@nxp.com>
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
v2:
- Add commit messages.
drive
com>
Signed-off-by: Mingkai Hu <mingkai...@nxp.com>
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile
b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
index eb2cbc3..4df467d 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile
+++ b/arc
From: Alison Wang <b18...@freescale.com>
Signed-off-by: Alison Wang <alison.w...@nxp.com>
Signed-off-by: Mingkai Hu <mingkai...@nxp.com>
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
b/arch/arm/cpu/armv8/fsl-layers
From: Mingkai Hu <mingkai...@nxp.com>
Signed-off-by: Shaohui Xie <shaohui@freescale.com>
Signed-off-by: Mingkai Hu <mingkai...@nxp.com>
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
diff --git a/drivers/net/fm/Makefile b/drivers/net/fm/Makefile
index 493cdc6..344f
The LS1046A processor is built on the QorIQ LS series architecture
combining four ARM A72 processor cores with DPAA 1.0 support.
[PATCH 1/3] armv8: fsl-layerscape: Add A72 core detection
[PATCH 2/3] armv8/fsl_lsch2: Add LS1046A SoC support
[PATCH 3/3] armv8/ls1046a: Add Fman support
Regards,
t;mingkai...@nxp.com>
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S
index 670e323..735dd67 100644
--- a/arch/arm/cpu/armv8/start.S
+++ b/arch/arm/cpu/armv8/start.S
@@ -81,6 +81,11 @@ reset:
msr
From: Mingkai Hu <mingkai...@nxp.com>
Set the flash to Uniform Sector Architecture in the non-volatile
register. After the power cycle, it's also Uniform Sector Architecture.
Signed-off-by: Mingkai Hu <mingkai...@nxp.com>
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
diff -
From: Mingkai Hu <mingkai...@nxp.com>
Signed-off-by: Mingkai Hu <mingkai...@nxp.com>
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
diff --git a/drivers/net/phy/aquantia.c b/drivers/net/phy/aquantia.c
index f90c2ae..ad12f6d 100644
--- a/drivers/net/phy/aquantia.c
+++
Now I2C is initialized early enough to access FPGA so it supports to
show board info as early as other boot methods.
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
include/configs/ls1043aqds.h | 4
1 file changed, 4 deletions(-)
diff --git a/include/configs/ls1043aqds.h b/i
Get the clocks from FPGA through IFC or I2C. So it needs I2C early init
if booting with IFC disabled.
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
board/freescale/ls1043aqds/ls1043aqds.c | 4
include/configs/ls1043aqds.h| 5 +++--
2 files changed, 7 insertions
The LBMAP switches on the board will tell which boot device is used.
Only QSPI boot is supported if the boot device is IFCCard.
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
board/freescale/ls1043aqds/ls1043aqds.c | 8 +++-
1 file changed, 3 insertions(+), 5 deletions(-)
diff
IFC is considered as a required component in Layerscape platforms' Linux.
But if IFC is not enabled in U-Boot on some boards, accessing IFC memory
space would cause kernel call trace. So disable IFC node in such cases.
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
V2:
- Revised the
There is no MODE_FAT but MODE_FS. Fix it.
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
arch/arm/cpu/armv7/ls102xa/spl.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv7/ls102xa/spl.c b/arch/arm/cpu/armv7/ls102xa/spl.c
index 1dfbf54..0289058
There is no MODE_FAT but MODE_FS. Fix it.
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
arch/arm/cpu/armv8/fsl-layerscape/spl.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/spl.c
b/arch/arm/cpu/armv8/fsl-layerscape/spl.c
init_early_memctl_regs() will also be called in board_early_init_f().
So remove the duplicate call in spl code.
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
arch/arm/cpu/armv8/fsl-layerscape/spl.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/arch/arm/cpu/armv8/fsl-laye
gd->env_addr will be initialized in env_init() in
common/env_nowhere.c if CONFIG_ENV_IS_NOWHERE is defined.
So no need to do it again.
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
board/freescale/ls1043aqds/ls1043aqds.c | 4
board/freescale/ls1043ardb/ls1043ardb.c | 5 -
Using u16 for cfg_rcw_src and u8 for sd1refclk_sel is enough.
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
board/freescale/ls1043ardb/ls1043ardb.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/board/freescale/ls1043ardb/ls1043ardb.c
b/board/fre
The current 'cpld reset' will just write global_rst register
but couldn't switch to NOR boot if the board's switches are
for NAND/SD boot. So need to write rcw source registers for
NOR boot as well.
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
board/freescale/ls1043ardb/cpld.
IFC won't be initialized in U-Boot if QSPI is enabled on LS1043AQDS.
So this patch could fix 'sync abort' caused by autoboot that tries to
access IFC address.
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
include/configs/ls1043a_common.h | 5 +
1 file changed, 5 insertions(+)
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
include/configs/ls1043a_common.h | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h
index 2432531..e900c50 100644
--- a/include/c
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
include/configs/ls1043a_common.h | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h
index fd243b1..2432531 100644
--- a/include/configs/ls1043a_co
1 - 100 of 360 matches
Mail list logo
