Marek Vasut schrieb am Fr., 8. Nov. 2019, 16:46:
> On 11/8/19 3:47 PM, Patrick Delaunay wrote:
> >
> > In this serie I update the DWC2 host driver to use the device tree
> > information and the associated PHY and CLOCK drivers when they are
> > available.
>
> I'm kinda on the fence whether to add
Westergreen
Cc: Dinh Nguyen
Cc: Jagan Teki
Cc: Ley Foon Tan
Cc: Philipp Tomisch
Cc: Simon Goldschmidt
Cc: Tien Fong Chee
---
V2: - Support both DM and non-DM probing
- Fix watchdog stop handling by setting CR bit
---
configs/socfpga_stratix10_defconfig | 2 +
configs
: Chin Liang See
Cc: Dalon Westergreen
Cc: Dinh Nguyen
Cc: Jagan Teki
Cc: Ley Foon Tan
Cc: Philipp Tomisch
Cc: Simon Goldschmidt
Cc: Tien Fong Chee
Reviewed-by: Simon Goldschmidt
---
V2: Use non-DM watchdog in SPL on S10
---
configs/socfpga_stratix10_defconfig | 1 +
configs
On Thu, Nov 7, 2019 at 9:40 AM Marek Vasut wrote:
>
> On 11/7/19 9:36 AM, Simon Goldschmidt wrote:
> > On Thu, Nov 7, 2019 at 9:33 AM Marek Vasut wrote:
> >>
> >> On 11/7/19 4:31 AM, Ley Foon Tan wrote:
> >>> On Thu, Nov 7, 2019 at 10:49 AM Marek Vasut wr
On Thu, Nov 7, 2019 at 9:33 AM Marek Vasut wrote:
>
> On 11/7/19 4:31 AM, Ley Foon Tan wrote:
> > On Thu, Nov 7, 2019 at 10:49 AM Marek Vasut wrote:
> >>
> >> On 11/7/19 3:10 AM, Ley Foon Tan wrote:
> >> [...]
> >>> diff --git a/arch/arm/dts/socfpga-common-u-boot.dtsi
> >>> b/arch/arm/dts/socfpga
Hi Vignesh,
On Thu, Oct 17, 2019 at 2:31 PM Vignesh Raghavendra wrote:
>
> Hi Simon,
>
> On 17/10/19 4:50 PM, Simon Goldschmidt wrote:
> > On Mon, Oct 14, 2019 at 3:27 PM Vignesh Raghavendra wrote:
> >>
> >> Current Cadence QSPI driver has few limitations. It
Am 05.11.2019 um 17:33 schrieb Simon Glass:
Hi Jean-Jacques,
On Mon, 4 Nov 2019 at 08:41, Jean-Jacques Hiblot wrote:
On 30/10/2019 02:48, Simon Glass wrote:
On Mon, 30 Sep 2019 at 10:15, Jean-Jacques Hiblot wrote:
Add managed functions to get a reset_ctl from the device-tree, based on a
n
d GCC 9.2 shows this. I don't know why other
versions don't issue this warning.
This new commit message might still concentrate too much on the GCC version,
but I think it's ok. I just wanted to prevent someone reading this in the
future and taking it as a hint that the attr
Tom Rini schrieb am Mo., 4. Nov. 2019, 22:15:
> On Mon, Nov 04, 2019 at 09:28:51PM +0100, Simon Goldschmidt wrote:
> > Am 04.11.2019 um 20:34 schrieb Heinrich Schuchardt:
> > > struct ip_udp_hdr is naturally packed. There is no point in adding a
> > > __packed attrib
Am 30.10.2019 um 21:34 schrieb richard.g...@linux.intel.com:
From: Richard Gong
This is 2nd submission of Intel Remote System Update patches.
Ok, so what has changed since v1? You'd normally add a changelog
(ideally to both this cover-letter and to each patch). Have a look at
patman in tool
Am 04.11.2019 um 20:34 schrieb Heinrich Schuchardt:
struct ip_udp_hdr is naturally packed. There is no point in adding a
__packed attribute. With the attribute the network stack does not compile
using GCC 9.2.1:
Is this commit message correct? In lwIP, we *do* need to pack all these
network he
On Wed, Oct 30, 2019 at 10:48 AM Ley Foon Tan wrote:
>
> On Tue, Oct 29, 2019 at 6:31 PM Simon Goldschmidt
> wrote:
> >
> >
> >
> > Ley Foon Tan schrieb am Di., 29. Okt. 2019, 11:16:
> >>
> >> On Fri, Oct 25, 2019 at 5:37 PM Simon Goldschmidt
Ley Foon Tan schrieb am Di., 29. Okt. 2019, 11:16:
> On Fri, Oct 25, 2019 at 5:37 PM Simon Goldschmidt
> wrote:
> >
> > On Fri, Oct 25, 2019 at 11:17 AM Ley Foon Tan
> wrote:
> > >
> > > On Wed, Oct 23, 2019 at 2:11 AM Simon Goldschmidt
> > >
Richard Gong schrieb am Mo., 28. Okt. 2019,
14:58:
> Hi Simon,
>
> Thanks for your comment.
>
> I will move files to driver/firmware.
>
Would moving to uclass mailbox fit for these kind of things?
Regards,
Simon
>
> Regards,
> Richard
>
> On 10/24/19 10:00 AM
not be set to
zero, resulting in bogus behaviour.
To fix this, use 'memset' instead of 'MALLOC_ZERO' to zero out memory
that compes from simple malloc.
Signed-off-by: Simon Goldschmidt
---
common/dlmalloc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --gi
As SPL_SPI_FLASH_SUPPORT cannot work without SPL_SPI_SUPPORT, fix
dependencies to prevent enabling SPI flash support without basic SPI
support.
Signed-off-by: Simon Goldschmidt
---
Changes in v2:
- move SYS_SPI_U_BOOT_OFFS out of the SPL_SPI_FLASH_SUPPORT guard
since that broke sunxi SPL
On Fri, Oct 25, 2019 at 11:17 AM Ley Foon Tan wrote:
>
> On Wed, Oct 23, 2019 at 2:11 AM Simon Goldschmidt
> wrote:
> >
> > Am 10.10.2019 um 09:37 schrieb Ley Foon Tan:
> > > Convert reset manager for Gen5, Arria 10 and Stratix 10 from struct
> > > to d
Am 24.10.2019 um 20:23 schrieb Simon Goldschmidt:
From: Simon Goldschmidt
Support loading clk speed via DM instead of requiring ad-hoc code.
Signed-off-by: Simon Goldschmidt
Signed-off-by: Simon Goldschmidt
That gmx adress somehow slipped in after cloning u-boot-spi. Can you
remove it
From: Simon Goldschmidt
Support loading clk speed via DM instead of requiring ad-hoc code.
Signed-off-by: Simon Goldschmidt
Signed-off-by: Simon Goldschmidt
---
Changes in v2:
- check return value of clk_get_rate for error
drivers/spi/cadence_qspi.c | 22 --
1 file
Am 24.10.2019 um 19:29 schrieb Dalon L Westergreen:
On Thu, 2019-10-24 at 16:29 +0200, Simon Goldschmidt wrote:
On Thu, Oct 24, 2019 at 4:25 PM Dalon L Westergreen
<
dalon.westergr...@linux.intel.com
<mailto:dalon.westergr...@linux.intel.com>
> wrote:
On Wed, 2019-10-23 at
On Thu, Oct 24, 2019 at 4:35 PM wrote:
>
> From: Richard Gong
>
> The Intel Remote System Update (RSU) provides a way for users to update
> the QSPI configuration bitstream of a Intel Stratix10 SoC device with
> significantly reduced risk of corrupting the bitstream storage and
> bricking the sys
On Thu, Oct 24, 2019 at 4:25 PM Dalon L Westergreen
wrote:
>
>
>
> On Wed, 2019-10-23 at 21:22 +0200, Simon Goldschmidt wrote:
>
> Am 23.10.2019 um 18:03 schrieb Dalon L Westergreen:
>
>
>
> On Tue, 2019-10-22 at 19:13 +0200, Simon Goldschmidt wrot
Jagan Teki schrieb am Do., 24. Okt. 2019,
09:22:
> On Thu, Oct 24, 2019 at 12:50 PM Simon Goldschmidt
> wrote:
> >
> > On Thu, Oct 24, 2019 at 4:54 AM Ley Foon Tan
> wrote:
> > >
> > > On Wed, 2019-10-23 at 22:27 +0200, Simon Goldschmidt wrote:
> >
On Thu, Oct 24, 2019 at 4:54 AM Ley Foon Tan wrote:
>
> On Wed, 2019-10-23 at 22:27 +0200, Simon Goldschmidt wrote:
> > Support loading clk speed via DM instead of requiring ad-hoc code.
> >
> > Signed-off-by: Simon Goldschmidt
> > ---
> >
Am 15.10.2019 um 22:10 schrieb Simon Goldschmidt:
This is an RFC series with the target to move SPL code from arch to
DM drivers.
I've sent a few patches of this series now as non-RFC, as I don't know
if I will make it this merge window: I still have trouble getting the
existing
The file arch/arm/mach-socfpga/include/mach/misc.h used the same include
guard as the global include/misc.h.
Fix this by giving the arch file an arch prefix.
Signed-off-by: Simon Goldschmidt
---
arch/arm/mach-socfpga/include/mach/misc.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions
Support loading clk speed via DM instead of requiring ad-hoc code.
Signed-off-by: Simon Goldschmidt
---
drivers/spi/cadence_qspi.c | 20 ++--
1 file changed, 18 insertions(+), 2 deletions(-)
diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c
index e2e54cd277
To use this DM timer on socfpga as system tick, it needs to take itself
out of reset.
Signed-off-by: Simon Goldschmidt
---
drivers/timer/dw-apb-timer.c | 18 +-
1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/drivers/timer/dw-apb-timer.c b/drivers/timer/dw-apb
Make the function pointer struct const, as it does not need to be
writable. This doesn't really change anything other than moving this
variable to a different section. No functional change.
Signed-off-by: Simon Goldschmidt
---
drivers/ddr/altera/sdram_gen5.c | 2 +-
1 file changed, 1 inse
Am 23.10.2019 um 21:39 schrieb Tom Rini:
When we have an excess size growth, fix the "limit" printf call to pass
in just the limit variable rather than the string bytes to the format
character.
Signed-off-by: Tom Rini
Reviewed-by: Simon Goldschmidt
---
Makefile | 2 +-
1 fi
Am 23.10.2019 um 18:03 schrieb Dalon L Westergreen:
On Tue, 2019-10-22 at 19:13 +0200, Simon Goldschmidt wrote:
Dalon L Westergreen <mailto:dalon.westergr...@linux.intel.com>> schrieb am Di., 22. Okt.
2019, 19:10:
I mentioned this before, it would be great to not rely on the
On Wed, Oct 23, 2019 at 12:00 PM Vignesh Raghavendra wrote:
>
>
>
> On 18/10/19 6:12 PM, Simon Goldschmidt wrote:
> > On Fri, Oct 18, 2019 at 2:40 PM Vignesh Raghavendra wrote:
> >>
> >> Hi,
> >>
> >> On 18/10/19 2:34 PM, Simon Goldschm
As SPL_SPI_FLASH_SUPPORT cannot work without SPL_SPI_SUPPORT, fix
dependencies to prevent enabling SPI flash support without basic SPI
support.
Also SYS_SPI_U_BOOT_OFFS does not make sense without
SPL_SPI_FLASH_SUPPORT enabled, so move it into its 'if' section.
Signed-off-by: Simon G
for valid pointers (e.g. 0xff00 is a valid heap pointer
in socfpga SPL). For such platforms, this value provides an upper range
of those error pointer values - up to 'MAX_ERRNO' bytes below this value
must be unused/invalid addresses.
Signed-off-by: Simon Goldschmidt
---
Kc
This patch changes ERR_PTR/PTR_ERR to use CONFIG_ERR_PTR_OFFSET to map
errno values into a pointer region that cannot contain valid pointers.
IS_ERR and IS_ERR_OR_NULL have to be converted to use PTR_ERR, too,
for this to work.
Signed-off-by: Simon Goldschmidt
---
include/linux/err.h | 8
errno values into the range
of the Boot ROM, which should not be used for valid pointers.
Signed-off-by: Simon Goldschmidt
---
arch/arm/mach-socfpga/Kconfig | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index fc0a54214f..3770e
for valid pointers (e.g. 0xff00 is a valid heap pointer
in socfpga SPL). For such platforms, this value provides an upper range
of those error pointer values - up to 'MAX_ERRNO' bytes below this value
must be unused/invalid addresses.
Simon Goldschmidt (3):
Kconfig add config ERR_
Am 11.10.2019 um 11:52 schrieb Ley Foon Tan:
Add build support for Agilex SoC.
Signed-off-by: Ley Foon Tan
Reviewed-by: Simon Goldschmidt
This does not apply any more, you'll need to rebase it (Marek has
changed mach-socfpga/Kconfig by renaming a board).
Regards,
Simon
-
Am 11.10.2019 um 11:52 schrieb Ley Foon Tan:
Restructure Stratix 10 SDRAM driver. Move common code to separate
file, in preparation to support SDRAM driver for Agilex.
Signed-off-by: Ley Foon Tan
---
v3:
- Change sdram_common.* to sdram_soc64.*
---
drivers/ddr/altera/Makefile
Am 11.10.2019 um 11:52 schrieb Ley Foon Tan:
Enable cache driver build in SPL.
Signed-off-by: Ley Foon Tan
---
drivers/Makefile | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/Makefile b/drivers/Makefile
index a4bb5e4975..0d231cddbb 100644
--- a/drivers/Makefile
+++ b/drivers/Mak
Am 11.10.2019 um 11:52 schrieb Ley Foon Tan:
Add Cache Coherency Unit (CCU) driver.
CCU is to ensures consistency of shared data between multi masters
in the system.
Driver initializes CCU's directories and coherency agent
interfaces in CCU IP.
Signed-off-by: Ley Foon Tan
Reviewed-by:
Am 11.10.2019 um 11:52 schrieb Ley Foon Tan:
CLKMGR_INTOSC_HZ should be 400MHz, instead of 460MHz.
Having this in a separate patch is clearly better.
Signed-off-by: Ley Foon Tan
---
arch/arm/mach-socfpga/include/mach/clock_manager_soc64.h | 2 +-
1 file changed, 1 insertion(+), 1 deletio
Am 11.10.2019 um 11:52 schrieb Ley Foon Tan:
Move Stratix10 and Agilex clock manager common code to new header file.
Signed-off-by: Ley Foon Tan
---
v5:
- Revert CLKMGR_INTOSC_HZ to 460MHz.
---
.../include/mach/clock_manager_s10.h | 16 +++--
.../include/mach/clock_manager_
Am 11.10.2019 um 11:52 schrieb Ley Foon Tan:
Add reset manager support for Agilex.
Signed-off-by: Ley Foon Tan
Reviewed-by: Simon Goldschmidt
---
v5:
- Remove reset_reset_manager_agilex.h and use reset_manager_soc64.h.
v3:
- Add reset_manager_soc64.h
- Convert to use defines instead of
Am 11.10.2019 um 11:52 schrieb Ley Foon Tan:
Add system manager support for Agilex.
Signed-off-by: Ley Foon Tan
Reviewed-by: Simon Goldschmidt
---
v5:
- Remove system_manager_agilex.h and use system_manager_soc64.h directly.
v3:
- Change include filename to system_manager_soc64.h
Am 10.10.2019 um 09:37 schrieb Ley Foon Tan:
Convert clock manager for Gen5, Arria 10 and Stratix 10 from struct
to defines.
Change to get clock manager base address from DT node instead of using
#define.
Signed-off-by: Ley Foon Tan
---
v4:
- Update commit message about get base address from
Am 10.10.2019 um 09:37 schrieb Ley Foon Tan:
Convert system manager for Gen5, Arria 10 and Stratix 10 from struct
to defines.
Change to get system manager base address from DT node instead of
using #define.
Signed-off-by: Ley Foon Tan
---
v4:
- Update commit message about get base address fro
Am 10.10.2019 um 09:37 schrieb Ley Foon Tan:
Convert reset manager for Gen5, Arria 10 and Stratix 10 from struct
to defines.
Change to get reset manager base address from DT node instead of using
#define.
Signed-off-by: Ley Foon Tan
---
v4:
- Update commit message about get base address from
.
Plus this tool is required to convert existing boards where we don't have
the quartus project files at hand.
Regards,
Simon
> --dalon
>
> On Tue, 2019-10-15 at 22:10 +0200, Simon Goldschmidt wrote:
>
> This new tool converts handoff information from quartus to "*_handoff.dtsi&
On Fri, Oct 11, 2019 at 11:53 AM Ley Foon Tan wrote:
>
> Add build support for Agilex SoC.
>
> Signed-off-by: Ley Foon Tan
> Reviewed-by: Simon Goldschmidt
>
> ---
> v5:
> - Enable NCORE_CACHE
>
> v3:
> - Disable CONFIG_USE_TINY_PRINTF
>
> v2:
> -
On Fri, Oct 18, 2019 at 2:40 PM Vignesh Raghavendra wrote:
>
> Hi,
>
> On 18/10/19 2:34 PM, Simon Goldschmidt wrote:
> > On Thu, Oct 17, 2019 at 2:55 PM Simon Goldschmidt
> > wrote:
> >>
> >> On Thu, Oct 17, 2019 at 2:44 PM Vignesh Raghavendra
> &
On Thu, Oct 17, 2019 at 2:55 PM Simon Goldschmidt
wrote:
>
> On Thu, Oct 17, 2019 at 2:44 PM Vignesh Raghavendra wrote:
> >
> > Hi,
> >
> > On 17/10/19 5:09 PM, Simon Goldschmidt wrote:
> > > On Mon, Oct 14, 2019 at 3:27 PM Vignesh Raghavendra
> >
On Thu, Oct 17, 2019 at 2:44 PM Vignesh Raghavendra wrote:
>
> Hi,
>
> On 17/10/19 5:09 PM, Simon Goldschmidt wrote:
> > On Mon, Oct 14, 2019 at 3:27 PM Vignesh Raghavendra wrote:
> >>
> >> Add support for Direct Access Controller mode of Cadence QSPI. Thi
On Mon, Oct 14, 2019 at 3:27 PM Vignesh Raghavendra wrote:
>
> Add support for Direct Access Controller mode of Cadence QSPI. This
> allows MMIO access to SPI NOR flash providing better read performance.
>
> Signed-off-by: Vignesh R
> Signed-off-by: Vignesh Raghavendra
I've tested this on my so
On Mon, Oct 14, 2019 at 3:27 PM Vignesh Raghavendra wrote:
>
> Current Cadence QSPI driver has few limitations. It assumes all read
> operations to be in Quad mode and thus does not support SFDP parsing.
> Also, adding support for new mode such as Octal mode would not be
> possible with current co
On Thu, Oct 17, 2019 at 8:44 AM Patrick Wildt wrote:
>
> On Thu, Oct 17, 2019 at 10:55:11AM +0800, Bin Meng wrote:
> > Hi Patrick,
> >
> > On Wed, Oct 16, 2019 at 11:35 PM Patrick Wildt wrote:
> > >
> > > On Wed, Oct 16, 2019 at 06:11:23PM +0800, Bin Meng wrote:
> > > > On Mon, Oct 14, 2019 at 7:
To use this timer on socfpga as system tick, it needs to take itself out
of reset.
Signed-off-by: Simon Goldschmidt
---
Changes in v2: None
drivers/timer/dw-apb-timer.c | 18 +-
1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/drivers/timer/dw-apb-timer.c b
'qts' files is also supported.
Signed-off-by: Simon Goldschmidt
---
Changes in v2: None
arch/arm/mach-socfpga/create_handoff_gen5.c | 660
arch/arm/mach-socfpga/qts-to-handoff.sh | 83 +++
2 files changed, 743 insertions(+)
create mode 100644 arch/arm/mach-socfpga
In preparation of moving SDRAM config from 'qts' files to devicetree,
make the config structs compatible to devicetree by keeping all struct
members of the same type (u8 or u32). That way, these structs can be
stored to devicetree as simple array.
Signed-off-by: Simon Goldschmidt
---
Instead of using ad-hoc code in arch/arm, load clock config from devicetree.
Signed-off-by: Simon Goldschmidt
---
Changes in v2: None
drivers/clk/altera/clk-gen5.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/altera/clk-gen5.c b/drivers/clk/altera/clk
Support loading clk speed via DM instead of requiring ad-hoc code.
Signed-off-by: Simon Goldschmidt
---
Changes in v2: None
drivers/spi/cadence_qspi.c | 20 ++--
1 file changed, 18 insertions(+), 2 deletions(-)
diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi
Remove the need for ad-hoc code for qspi speed.
Signed-off-by: Simon Goldschmidt
---
Changes in v2: None
include/configs/socfpga_common.h | 5 -
1 file changed, 5 deletions(-)
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index d1034ac280..e4a5dfc5ef
- removed wrapper files for sdram & pll
- fix freeze_controller to not depend on OSC1 speed
- remove unused function definitions
- add autogenerated handoff dtsi for socfpga_socrates
Signed-off-by: Simon Goldschmidt
---
Changes in v2: None
.../dts/socfpga_cyclone5_socrates-u-boot.dtsi |
In preparation to move handoff data from 'qts' files to devicetree, fetch
SDRAM config in 'of_to_platdata' DM callback. That way, this callback
can be changed to fetch the data from devicetree.
Signed-off-by: Simon Goldschmidt
---
Changes in v2: None
drivers/ddr/alte
Instead of reading SDRAM handoff data from 'qts' files, read it from
devicetree.
Signed-off-by: Simon Goldschmidt
---
Changes in v2: None
drivers/ddr/altera/sdram_gen5.c | 61 -
1 file changed, 53 insertions(+), 8 deletions(-)
diff --git a/drivers/
The socfpga gen5 clock driver will need some of the clock nodes to be
preserved in the SPL devicetree. Mark them appropriately.
Signed-off-by: Simon Goldschmidt
---
Changes in v2:
- split this patch from v1 5/6
arch/arm/dts/socfpga-common-u-boot.dtsi | 70 +
1 file
This moves setting initial clock values (as defined by Quartus handoff
files) from ad-hoc code in arch to CM_CLK driver.
TODO: CONFIG_CLOCKS and cmd 'clocks' must be fixed for dts access.
Signed-off-by: Simon Goldschmidt
---
Changes in v2: None
arch/arm/mach-socfpg
to be
left at 0 (L4WD0).
Signed-off-by: Simon Goldschmidt
---
Changes in v2:
- add dts based reset handling (messed up in v1)
arch/arm/dts/socfpga-common-u-boot.dtsi| 1 +
arch/arm/mach-socfpga/reset_manager_gen5.c | 13
arch/arm/mach-socfpga/spl_gen5.c | 21
Enable CLK and SPL_CLK so that the new readonly clock driver is used.
Signed-off-by: Simon Goldschmidt
---
Changes in v2: None
arch/arm/mach-socfpga/Kconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index 9efdcd6f10
For some clocks, the socfpga gen5 clock driver in preparation needs a
source register, which is used to select the parent clock.
Add these to the socfpga gen5 base device tree.
Signed-off-by: Simon Goldschmidt
---
Changes in v2:
- split this patch from v1 5/6
arch/arm/dts/socfpga.dtsi | 5
In preparation for moving socfpga gen5 clock handoff data to devicetree,
add a label to the base devicetree so that dts files including this base
tree can reference clkmgr by label.
Signed-off-by: Simon Goldschmidt
---
Changes in v2: None
arch/arm/dts/socfpga.dtsi | 2 +-
1 file changed, 1
This adds clk-gen5 as a readonly DM_CLK driver that can return clocks for
the peripherals.
Signed-off-by: Simon Goldschmidt
---
Changes in v2: None
MAINTAINERS | 1 +
drivers/clk/altera/Makefile | 1 +
drivers/clk/altera/clk-gen5.c | 338
In preparation to adding more DM based drivers, increase the SPL
pre-relocation heap just enough to allow those new drivers to run.
Signed-off-by: Simon Goldschmidt
---
Changes in v2: None
arch/arm/mach-socfpga/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch
Make the function pointer struct const, as it does not need to be
writable. This doesn't really change anything other than moving this
variable to a different section. No functional change.
Signed-off-by: Simon Goldschmidt
---
Changes in v2: None
drivers/ddr/altera/sdram_gen5.c | 2 +-
1
.
Changes in v2:
- add dts based reset handling (messed up in v1)
- split this patch from v1 5/6
- split this patch from v1 5/6
Simon Goldschmidt (18):
ddr: socfpga: gen5: constify altera_gen5_sdram_ops
dts: arm: socfpga: add label for clkmgr
arm: socfpga: gen5: increase SPL_SYS_MALLOC_F_LEN
Am 14.10.2019 um 22:02 schrieb Simon Glass:
Hi Simon,
On Mon, 14 Oct 2019 at 13:13, Simon Goldschmidt
wrote:
Am 12.10.2019 um 00:11 schrieb Simon Glass:
Hi Simon,
On Fri, 11 Oct 2019 at 12:31, Simon Goldschmidt
wrote:
Simon Glass schrieb am Fr., 11. Okt. 2019, 20:27:
Hi Simon,
On
Am 12.10.2019 um 00:11 schrieb Simon Glass:
Hi Simon,
On Fri, 11 Oct 2019 at 12:31, Simon Goldschmidt
wrote:
Simon Glass schrieb am Fr., 11. Okt. 2019, 20:27:
Hi Simon,
On Tue, 8 Oct 2019 at 14:34, Simon Goldschmidt
wrote:
In a series I'm currently preparing, I've stumbl
Simon Glass schrieb am Fr., 11. Okt. 2019, 20:27:
> Hi Simon,
>
> On Tue, 8 Oct 2019 at 14:34, Simon Goldschmidt
> wrote:
> >
> > In a series I'm currently preparing, I've stumbled accross the fact that
> > IS_ERR_VALUE() doesn't reliably work on
Stephen Warren schrieb am Do., 10. Okt. 2019, 17:56:
> On 10/10/19 5:44 AM, Michal Simek wrote:
> > Extend test suite to cover also automatic octal/hex converstions which
> > haven't been implemented in past.
>
> Acked-by: Stephen Warren
>
R
On Thu, Oct 10, 2019 at 12:46 PM Michal Simek wrote:
>
> On 09. 10. 19 19:28, Simon Goldschmidt wrote:
> > Am 09.10.2019 um 18:26 schrieb Tom Rini:
> >> On Tue, Oct 08, 2019 at 10:48:39AM +0200, Michal Simek wrote:
> >>> Hi Tom,
> >>>
> >>&
On Thu, Oct 10, 2019 at 11:29 AM Anatolij Gustschin wrote:
>
> On Thu, 10 Oct 2019 10:43:46 +0200
> Simon Goldschmidt simon.k.r.goldschm...@gmail.com wrote:
> ...
> > > Why is this required? In the past we have rejected all new code adding
> > > defines instead of
On Thu, Oct 10, 2019 at 10:09 AM Anatolij Gustschin wrote:
>
> On Thu, 10 Oct 2019 09:16:14 +0200
> Simon Goldschmidt simon.k.r.goldschm...@gmail.com wrote:
>
> > On Thu, Oct 10, 2019 at 8:20 AM Ley Foon Tan wrote:
> > >
> > > Convert system manager for Gen5,
On Thu, Oct 10, 2019 at 8:20 AM Ley Foon Tan wrote:
>
> Convert clock manager for Gen5, Arria 10 and Stratix 10 from struct
> to defines.
Same as 2/4: please add a description about the "read address from dts" thing.
Regards,
Simon
>
> Signed-off-by: Ley Foon Tan
>
> ---
> v3:
> - Remove "No f
On Thu, Oct 10, 2019 at 8:20 AM Ley Foon Tan wrote:
>
> Convert system manager for Gen5, Arria 10 and Stratix 10 from struct
> to defines.
Same as 2/4: please add a description about the "read address from dts" thing.
Regards,
Simon
>
> Signed-off-by: Ley Foon Tan
>
> ---
> v3:
> - Remove "No
On Thu, Oct 10, 2019 at 8:20 AM Ley Foon Tan wrote:
>
> Convert reset manager for Gen5, Arria 10 and Stratix 10 from struct
> to defines.
A commit message should describe what the commit does. By leaving out the fact
that you're now loading the base address from DTS, you're not describing all
cha
Marek Vasut schrieb am Mi., 9. Okt. 2019, 23:01:
> On 10/9/19 8:06 PM, Simon Goldschmidt wrote:
> [...]
> >>>>>>> Based on my understand through this register
> >>>>>>> fpga_mgr_fpgamgrdata
> >>>>>>> address map
Am 02.10.2019 um 11:23 schrieb Simon Goldschmidt:
On Wed, Oct 2, 2019 at 10:13 AM Ley Foon Tan wrote:
On Wed, Sep 18, 2019 at 12:23 PM Simon Goldschmidt
wrote:
Ley Foon Tan schrieb am Mi., 18. Sep. 2019, 04:32:
On Wed, Sep 18, 2019 at 6:33 AM Dinh Nguyen wrote:
On 9/10/19 3:37 AM
Am 24.05.2019 um 14:16 schrieb Chee, Tien Fong:
On Fri, 2019-05-24 at 14:00 +0200, Simon Goldschmidt wrote:
On Fri, May 24, 2019 at 1:57 PM Chee, Tien Fong
wrote:
On Fri, 2019-05-24 at 13:53 +0200, Simon Goldschmidt wrote:
On Fri, May 24, 2019 at 1:44 PM Marek Vasut
wrote:
On 5/24/19
Marek,
Am 27.06.2019 um 00:19 schrieb Marek Vasut:
The company Samtec was merged into Softing, migrate the board over to
the new name and update copyright headers.
What happened to this series?
Regards,
Simon
Signed-off-by: Marek Vasut
Cc: Silvio Fricke
Cc: Simon Goldschmidt
---
arch
Am 02.08.2019 um 16:41 schrieb Simon Glass:
Hi SImon,
On Thu, 1 Aug 2019 at 23:53, Simon Goldschmidt
wrote:
On Fri, Aug 2, 2019 at 12:45 AM Simon Glass wrote:
Hi Simon,
On Mon, 29 Jul 2019 at 04:47, Simon Goldschmidt
wrote:
Simon,
On Wed, Jul 10, 2019 at 8:50 PM Simon Goldschmidt
:
On Tue, 2019-05-07 at 21:44 +0200, Marek Vasut wrote:
On 5/7/19 9:43 PM, Simon Goldschmidt wrote:
On 07.05.19 21:41, Marek Vasut wrote:
On 5/7/19 9:36 PM, Simon Goldschmidt wrote:
On 07.05.19 21:19, Marek Vasut wrote:
According to SoCFPGA Cyclone V datasheet
rev.2018.01.26
Am 09.10.2019 um 18:26 schrieb Tom Rini:
On Tue, Oct 08, 2019 at 10:48:39AM +0200, Michal Simek wrote:
Hi Tom,
On 19. 09. 19 15:28, Michal Simek wrote:
On 13. 09. 19 17:09, Tom Rini wrote:
On Wed, Sep 11, 2019 at 03:39:53PM +0200, Michal Simek wrote:
From: T Karthik Reddy
This patch uses
On Wed, Oct 9, 2019 at 2:57 PM Dalon L Westergreen
wrote:
>
> On Sat, 2019-10-05 at 21:40 +0200, Simon Goldschmidt wrote:
>
> Am 27.09.2019 um 20:27 schrieb Dalon Westergreen:
>
> From: Dalon Westergreen <
>
> dalon.westergr...@intel.com
>
> >
>
>
> S
On Wed, Oct 9, 2019 at 2:56 PM Dalon L Westergreen
wrote:
>
> On Sat, 2019-10-05 at 21:41 +0200, Simon Goldschmidt wrote:
>
> Am 27.09.2019 um 20:27 schrieb Dalon Westergreen:
>
> From: Dalon Westergreen <
>
> dalon.westergr...@intel.com
>
> >
>
>
Hi Vignesh,
On Wed, Oct 9, 2019 at 12:58 PM Vignesh Raghavendra wrote:
>
> Hi Simon,
>
> On 01/10/19 11:58 AM, Simon Goldschmidt wrote:
> > On Tue, Oct 1, 2019 at 6:58 AM wrote:
> >>
> >>
> >>
> >> On 09/27/2019 07:43 AM, Vignesh Raghavendr
In a series I'm currently preparing, I've stumbled accross the fact that
IS_ERR_VALUE() doesn't reliably work on socfpga SPL as the onchip SRAM
begins at 0x and the heap is at the end of the 32 bit range.
Being like that, the current test for error (value >= -4095) which
equals 'value
On Tue, Oct 8, 2019 at 2:54 PM Tom Rini wrote:
>
> On Tue, Oct 08, 2019 at 08:50:17AM -0400, Tom Rini wrote:
> > On Tue, Oct 08, 2019 at 08:42:58PM +0800, Bin Meng wrote:
> > > On Tue, Oct 8, 2019 at 8:36 PM Tom Rini wrote:
> > > >
> > > > On Tue, Oct 08, 2019 at 02:20:40PM +0200, Michal Simek wr
On Fri, Sep 27, 2019 at 6:43 AM Vignesh Raghavendra wrote:
>
> Newer variants of mt25q* flashes support 4 Byte addressing opcodes. Add
> entries for the same. These flashes have bit 6 set in 5th byte of READ ID
> response.
>
> Signed-off-by: Vignesh Raghavendra
Tested-by: Si
On Fri, Sep 27, 2019 at 6:43 AM Vignesh Raghavendra wrote:
>
> Older variants of n25q256* and n25q512* do not support 4 Byte stateless
> addressing opcodes. Therefore drop SPI_NOR_4B_OPCODES flag from these
> entries.
>
> Signed-off-by: Vignesh Raghavendra
Tested-by: Simon Gol
There's something wrong with your mailer: indentation of replies doesn't seem
to work. It gets kind of hard to read who wrote what...
On Mon, Oct 7, 2019 at 4:34 PM Dalon L Westergreen
wrote:
>
> On Sun, 2019-10-06 at 20:05 +0200, Simon Goldschmidt wrote:
>
> Am 06.10.2019
201 - 300 of 1666 matches
Mail list logo
