Re: [U-Boot] [PATCH v10 4/4] common: Generic firmware loader for file system

[Chee, Tien Fong]

On Tue, 2018-03-06 at 10:51 -0700, Simon Glass wrote:
> Hi,
> 
> On 5 March 2018 at 02:43,   wrote:
> > 
> > From: Tien Fong Chee 
> > 
> > This is file system generic loader which can be used to load
> > the file image from the storage into target such as memory.
> > The consumer driver would then use this loader to program whatever,
> > ie. the FPGA device.
> > 
> > Signed-off-by: Tien Fong Chee 
> > Reviewed-by: Lothar Waßmann 
> > ---
> >  common/Kconfig |  10 ++
> >  common/Makefile|   1 +
> >  common/fs_loader.c | 353
> > +
> >  doc/README.firmware_loader |  86 +++
> >  include/fs_loader.h|  28 
> >  5 files changed, 478 insertions(+)
> >  create mode 100644 common/fs_loader.c
> >  create mode 100644 doc/README.firmware_loader
> >  create mode 100644 include/fs_loader.h
> This looks fine as a concept but I am not keen on the implementation.
> 
This patchset has been going through many rounds and a lot of time
spending in review, and it is already working and being tested. I still
have a lot subsequent patches pending on this patchset. I would suggest
to accept this patchset, then we can enhance it to driver model in
later.

> 1. It should use driver model (only) in U-Boot proper. If there is
> some SPL problem then add a specific function or feature for SPL.
We can doing this in later since it is require sometime to figure out
and testing.

> 2. It should not be necessary ti manually init subsystems - driver
> model does this for you
This is for initializing storage driver in very early SPL, where
loading from storage to configure some critical HW need to done first.

> 3. You can use the uclass name to find things
Yeah, once it is converted to driver model, we can use the uclass for
searching HW info in DTS.
> 
> Please let me know if you need more info.
> 
> Regards,
> Simon
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[U-Boot] [PATCH v8 3/3] Adding wget

[DH]

From: Duncan Hare 

>
Adding wget



Signed-off-by: Duncan Hare 
---
All the code is new, and not copied from any source.

Adding
net/wget.c
include/net/wget.h

Chages to
cmd/net.c
cmd/Kconfig


Changes in v8: None

 cmd/Kconfig|  93 ++--
 cmd/net.c  |  13 ++
 include/net/wget.h |  17 +++
 net/Makefile   |   1 +
 net/wget.c | 420 +
 5 files changed, 467 insertions(+), 77 deletions(-)
 create mode 100644 include/net/wget.h
 create mode 100644 net/wget.c

diff --git a/cmd/Kconfig b/cmd/Kconfig
index 136836d146..46b489a966 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -23,29 +23,6 @@ config HUSH_PARSER
  If disabled, you get the old, much simpler behaviour with a somewhat
  smaller memory footprint.
 
-config CMDLINE_EDITING
-   bool "Enable command line editing"
-   depends on CMDLINE
-   default y
-   help
- Enable editing and History functions for interactive command line
- input operations
-
-config AUTO_COMPLETE
-   bool "Enable auto complete using TAB"
-   depends on CMDLINE
-   default y
-   help
- Enable auto completion of commands using TAB.
-
-config SYS_LONGHELP
-   bool "Enable long help messages"
-   depends on CMDLINE
-   default y if CMDLINE
-   help
- Defined when you want long help messages included
- Do not set this option when short of memory.
-
 config SYS_PROMPT
string "Shell prompt"
default "=> "
@@ -331,12 +308,6 @@ config CMD_SPL_WRITE_SIZE
  flash used by Falcon-mode boot. See the documentation until CMD_SPL
  for detail.
 
-config CMD_FITUPD
-   bool "fitImage update command"
-   help
- Implements the 'fitupd' command, which allows to automatically
- store software updates present on a TFTP server in NOR Flash
-
 config CMD_THOR_DOWNLOAD
bool "thor - TIZEN 'thor' download"
help
@@ -426,7 +397,6 @@ menu "Memory commands"
 config CMD_CRC32
bool "crc32"
select HASH
-   default n if ARCH_SUNXI
default y
help
  Compute CRC32.
@@ -568,7 +538,6 @@ config CMD_LZMADEC
 
 config CMD_UNZIP
bool "unzip"
-   default n if ARCH_SUNXI
default y if CMD_BOOTI
help
  Uncompress a zip-compressed memory region.
@@ -611,7 +580,7 @@ config CMD_DEMO
 
 config CMD_DFU
bool "dfu"
-   select DFU
+   select USB_FUNCTION_DFU
help
  Enables the command "dfu" which is used to have U-Boot create a DFU
  class device via USB. This command requires that the "dfu_alt_info"
@@ -645,7 +614,6 @@ config CMD_FLASH
 
 config CMD_FPGA
bool "fpga"
-   depends on FPGA
default y
help
  FPGA support.
@@ -701,7 +669,6 @@ config CMD_GPT
bool "GPT (GUID Partition Table) command"
select PARTITION_UUIDS
select EFI_PARTITION
-   select HAVE_BLOCK_DEVICE
imply RANDOM_UUID
help
  Enable the 'gpt' command to ready and write GPT style partition
@@ -709,7 +676,6 @@ config CMD_GPT
 
 config RANDOM_UUID
bool "GPT Random UUID generation"
-   select LIB_UUID
help
  Enable the generation of partitions with random UUIDs if none
  are provided.
@@ -780,14 +746,12 @@ config CMD_I2C
 
 config CMD_LOADB
bool "loadb"
-   default n if ARCH_SUNXI
default y
help
  Load a binary file over serial line.
 
 config CMD_LOADS
bool "loads"
-   default n if ARCH_SUNXI
default y
help
  Load an S-Record file over serial line
@@ -849,7 +813,6 @@ config CMD_ONENAND
 config CMD_PART
bool "part"
select PARTITION_UUIDS
-   select HAVE_BLOCK_DEVICE
help
  Read and display information about the partition table on
  various media.
@@ -900,15 +863,6 @@ config CMD_SAVES
  Provides a way to save a binary file using the Motorola S-Record
  format over the serial line.
 
-config CMD_SCSI
-   bool "scsi - Access to SCSI devices"
-   default y if SCSI
-   help
- This provides a 'scsi' command which provides access to SCSI (Small
- Computer System Interface) devices. The command provides a way to
- scan the bus, reset the bus, read and write data and get information
- about devices.
-
 config CMD_SDRAM
bool "sdram - Print SDRAM configuration information"
help
@@ -951,7 +905,6 @@ config CMD_UNIVERSE
 
 config CMD_USB
bool "usb"
-   select HAVE_BLOCK_DEVICE
help
  USB support.
 
@@ -961,18 +914,9 @@ config CMD_USB_SDP
help
  Enables the command "sdp" which is used to have U-Boot emulating the
  Serial Download Protocol (SDP) via USB.
-config CMD_ROCKUSB
-   bool "rockusb"
-   depends on 

[U-Boot] [PATCH v8 2/3] Adding TCP

[DH]

From: Duncan Hare 

All the code is new, and not copied from any source.

>


Signed-off-by: Duncan Hare 
---

Routine tcp_print_buffer() is used to print portions of
non zero terminated buffers. If there is an existing routine
please let me know. I'm from the world of length fields
not zero terminated strings (zOS).

Added
include/net.h
net/tcp.c

added CONFIG_TCP Kconfig parameter in networking to
Kconfig
Makefile
include/net.h
net/net.c

In net.c added procedure
int net_send_tcp_packet

Modified procedures
net_init - set tcp initial state
net_send_ip_packet -  debug messages
net_send_ip_packet - for tcp packet header creation
net_process_received_packet - rxhand_tcp_f


Changes in v8:
Adding TCP

 include/net.h |   8 +-
 include/net/tcp.h | 218 
 net/Kconfig   |  35 +--
 net/Makefile  |   2 +-
 net/net.c |  51 +++-
 net/tcp.c | 749 ++
 6 files changed, 1024 insertions(+), 39 deletions(-)
 create mode 100644 include/net/tcp.h
 create mode 100644 net/tcp.c

diff --git a/include/net.h b/include/net.h
index 7e5f5a6a5b..e29d804a23 100644
--- a/include/net.h
+++ b/include/net.h
@@ -548,7 +548,7 @@ extern int  net_restart_wrap;   /* Tried all 
network devices */
 
 enum proto_t {
BOOTP, RARP, ARP, TFTPGET, DHCP, PING, DNS, NFS, CDP, NETCONS, SNTP,
-   TFTPSRV, TFTPPUT, LINKLOCAL
+   TFTPSRV, TFTPPUT, LINKLOCAL, WGET
 };
 
 extern charnet_boot_file_name[1024];/* Boot File name */
@@ -681,11 +681,15 @@ static inline void net_send_packet(uchar *pkt, int len)
  * @param payload_len Length of data after the UDP header
  */
 int net_send_ip_packet(uchar *ether, struct in_addr dest, int dport, int sport,
-  int payload_len, int proto);
+  int payload_len, int proto, u8 action, u32 tcp_seq_num,
+  u32 tcp_ack_num);
 
 int net_send_udp_packet(uchar *ether, struct in_addr dest, int dport,
int sport, int payload_len);
 
+int net_send_tcp_packet(int payload_len, int dport, int sport, u8 action,
+   u32 tcp_seq_num, u32 tcp_ack_num);
+
 /* Processes a received packet */
 void net_process_received_packet(uchar *in_packet, int len);
 
diff --git a/include/net/tcp.h b/include/net/tcp.h
new file mode 100644
index 00..81f263351e
--- /dev/null
+++ b/include/net/tcp.h
@@ -0,0 +1,218 @@
+/*
+ * TCP Support for file transfer.
+ *
+ * Copyright 2017 Duncan Hare, All rights reserved.
+ *
+ *  SPDX-License-Identifier:GPL-2.0
+ */
+
+#define TCP_ACTIVITY 127   /* Activity on downloading  */
+
+struct ip_tcp_hdr {
+   u8  ip_hl_v;/* header length and version*/
+   u8  ip_tos; /* type of service  */
+   u16 ip_len; /* total length */
+   u16 ip_id;  /* identification   */
+   u16 ip_off; /* fragment offset field*/
+   u8  ip_ttl; /* time to live */
+   u8  ip_p;   /* protocol */
+   u16 ip_sum; /* checksum */
+   struct in_addr  ip_src; /* Source IP address*/
+   struct in_addr  ip_dst; /* Destination IP address   */
+   u16 tcp_src;/* TCP source port  */
+   u16 tcp_dst;/* TCP destination port */
+   u32 tcp_seq;/* TCP sequence number  */
+   u32 tcp_ack;/* TCP Acknowledgment number*/
+   u8  tcp_hlen;   /* 4 bits TCP header Length/4   */
+   /* 4 bits Reserved  */
+   /* 2 more bits reserved */
+   u8  tcp_flags;  /* see defines  */
+   u16 tcp_win;/* TCP windows size */
+   u16 tcp_xsum;   /* Checksum */
+   u16 tcp_ugr;/* Pointer to urgent data   */
+} __packed;
+
+#define IP_TCP_HDR_SIZE(sizeof(struct ip_tcp_hdr))
+#define TCP_HDR_SIZE   (IP_TCP_HDR_SIZE  - IP_HDR_SIZE)
+
+#define TCP_DATA   0x00/* Data Packet - internal use only  */
+#define TCP_FIN0x01/* Finish flag  
*/
+#define TCP_SYN0x02/* Synch (start) flag   
*/
+#define TCP_RST0x04/* reset flag   
*/
+#define TCP_PUSH   0x08/* Push - Notify app*/
+#define TCP_ACK0x10/* Acknowledgment of data received  

[U-Boot] [PATCH v8 1/3] Adding TCP and wget into u-boot

[DH]

From: Duncan Hare 

>


cover-letter:
Why netboot:
Central management, including logs and change control,
coupled with with enhanced security and unauthorized
change detection and remediation by exposing a
small attack surface.

Why TCP:

Currently file transfer are done using tftp or NFS both
over udp. This requires a request to be sent from client
(u-boot) to the boot server.

For a 4 Mbyte kernel, with a 1k block size this requires
4,000 request for a block.

Using a large block size, one greater than the Ethernet
maximum frame size limitation, would require fragmentation,
which u-boot supports. However missing fragment recovery
requires timeout detection and re-transmission requests
for missing fragments.

UDP is ideally suited to fast single packet exchanges,
inquiry/response, for example dns, becuse of the lack of
connection overhead.

UDP as a file transport mechanism is slow, even in low
latency networks, because file transfer with udp requires
poll/response mechanism to provide transfer integrity.

In networks with large latency, for example: the internet,
UDP is even slower. What is a 30 second transfer on a local
boot server and LAN increase to over 3 minutes, because of
all the requests/response traffic.

This was anticipated in the evolution of the IP protocols
and TCP was developed and then enhanced for high latency high
bandwidth networks.

The current standard is TCP with selective acknowledgment.

In our testing we have reduce kernel transmission time to
around 0.4 seconds for a 4Mbyte kernel, with a 100 Mbps
downlink.

Why http and wget:

HTTP is the most efficient file retrieval protocol in common
use. The client send a single request, after TCP connection,
to receive a file of any length.

WGET is the application which implements http file transfer
outside browsers as a file transfer protocol. Versions of
wget exists on many operating systems.
END

Signed-off-by: Duncan Hare 
---

Changed in this patch:
include/net.h
net/net.c

Added a protocol parameter to ip packet sending in net.c
Added UDP protocol for current applications to minimize
code changes to existing net apps.

All the code is new, and not copied from any source.


Changes in v8:
Initial changes for adding TCP

 include/net.h | 25 +++--
 net/net.c | 52 ++--
 net/ping.c|  9 ++---
 3 files changed, 55 insertions(+), 31 deletions(-)

diff --git a/include/net.h b/include/net.h
index 455b48f6c7..7e5f5a6a5b 100644
--- a/include/net.h
+++ b/include/net.h
@@ -15,17 +15,26 @@
 #include 
 #include  /* for nton* / ntoh* stuff */
 
-#define DEBUG_LL_STATE 0   /* Link local state machine changes */
-#define DEBUG_DEV_PKT 0/* Packets or info directed to the 
device */
-#define DEBUG_NET_PKT 0/* Packets on info on the network at 
large */
+#define DEBUG_LL_STATE  0  /* Link local state machine changes */
+#define DEBUG_DEV_PKT   0  /* Packets or info directed to the device */
+#define DEBUG_NET_PKT   0  /* Packets on info on the network at large */
 #define DEBUG_INT_STATE 0  /* Internal network state changes */
 
 /*
  * The number of receive packet buffers, and the required packet buffer
  * alignment in memory.
  *
+ * The number of buffers for TCP is used to calculate a static TCP window
+ * size, becuse TCP window size is a promise to the sending TCP to be able
+ * to buffer up to the window size of data.
+ * When the sending TCP has a window size of outstanding unacknowledged
+ * data, the sending TCP will stop sending.
  */
 
+#if defined(CONFIG_TCP)
+#define CONFIG_SYS_RX_ETH_BUFFER 12/* For TCP */
+#endif
+
 #ifdef CONFIG_SYS_RX_ETH_BUFFER
 # define PKTBUFSRX CONFIG_SYS_RX_ETH_BUFFER
 #else
@@ -354,6 +363,7 @@ struct vlan_ethernet_hdr {
 
 #define IPPROTO_ICMP1  /* Internet Control Message Protocol*/
 #define IPPROTO_UDP17  /* User Datagram Protocol   */
+#define IPPROTO_TCP 6  /* Transmission Control Protocol*/
 
 /*
  * Internet Protocol (IP) header.
@@ -596,10 +606,10 @@ int net_set_ether(uchar *xet, const uchar *dest_ethaddr, 
uint prot);
 int net_update_ether(struct ethernet_hdr *et, uchar *addr, uint prot);
 
 /* Set IP header */
-void net_set_ip_header(uchar *pkt, struct in_addr dest, struct in_addr source);
+void net_set_ip_header(uchar *pkt, struct in_addr dest, struct in_addr source,
+  u16  pkt_len, u8 prot);
 void net_set_udp_header(uchar *pkt, struct in_addr dest, int dport,
-   int sport, int len);
-
+   int sport, int len);
 /**
  * compute_ip_checksum() - Compute IP checksum
  *
@@ -670,6 +680,9 @@ static inline void net_send_packet(uchar *pkt, int len)
  * @param sport Source UDP port
  * @param payload_len Length of data after the UDP header
  */
+int net_send_ip_packet(uchar 

[U-Boot] [PATCH] imx: syscounter: make sure asm is volatile

[Yasushi SHOJI]

Without the volatile attribute, compilers are entitled to optimize out
the same asm().  In the case of __udelay() in syscounter.c, it calls
`get_ticks()` twice, one for the starting time and the second in the
loop to check the current time.  When compilers inline `get_ticks()`
they see the same `mrrc` instructions and optimize out the second one.
This leads to infinite loop since we don't get updated value from the
system counter.

Here is a portion of the disassembly of __udelay:

  88:   428bcmp r3, r1
  8a:   f8ce 20a4   str.w   r2, [lr, #164]  ; 0xa4
  8e:   bf08it  eq
  90:   4282cmpeq   r2, r0
  92:   f8ce 30a0   str.w   r3, [lr, #160]  ; 0xa0
  96:   d3f7bcc.n   88 <__udelay+0x88>
  98:   e8bd 8cf0   ldmia.w sp!, {r4, r5, r6, r7, sl, fp, pc}

Note that final jump / loop at 96 to 88, we don't have any `mrrc`.

With a volatile attribute, the above changes to this:

  8a:   ec53 2f0e   mrrc15, 0, r2, r3, cr14
  8e:   42abcmp r3, r5
  90:   f8c1 20a4   str.w   r2, [r1, #164]  ; 0xa4
  94:   bf08it  eq
  96:   42a2cmpeq   r2, r4
  98:   f8c1 30a0   str.w   r3, [r1, #160]  ; 0xa0
  9c:   d3f5bcc.n   8a <__udelay+0x8a>
  9e:   e8bd 8cf0   ldmia.w sp!, {r4, r5, r6, r7, sl, fp, pc}
  a2:   bf00nop

I'm advised[1] to put volatile on all asm(), so this commit also adds it
to the asm() in timer_init().

[1]: https://lists.denx.de/pipermail/u-boot/2018-March/322062.html

Signed-off-by: Yasushi SHOJI 
Reviewed-by: Fabio Estevam 
---
 arch/arm/mach-imx/syscounter.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-imx/syscounter.c b/arch/arm/mach-imx/syscounter.c
index 9290918dca..1d4ebfe343 100644
--- a/arch/arm/mach-imx/syscounter.c
+++ b/arch/arm/mach-imx/syscounter.c
@@ -62,7 +62,7 @@ int timer_init(void)
unsigned long val, freq;
 
freq = CONFIG_SC_TIMER_CLK;
-   asm("mcr p15, 0, %0, c14, c0, 0" : : "r" (freq));
+   asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (freq));
 
writel(freq, >cntfid0);
 
@@ -82,7 +82,7 @@ unsigned long long get_ticks(void)
 {
unsigned long long now;
 
-   asm("mrrc p15, 0, %Q0, %R0, c14" : "=r" (now));
+   asm volatile("mrrc p15, 0, %Q0, %R0, c14" : "=r" (now));
 
gd->arch.tbl = (unsigned long)(now & 0x);
gd->arch.tbu = (unsigned long)(now >> 32);
-- 
2.16.2

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Re: [U-Boot] [PATCH v2 3/3] ubs: xhci-dwc3: Enable USB3 PHY when available

[Bin Meng]

On Wed, Mar 7, 2018 at 5:20 PM, Vignesh R  wrote:
> DWC3 USB3 controllers will need USB3 PHY to be enabled, in addition to
> USB2 PHY, to be functional. Therefore enable USB3 PHY when available.
>
> Signed-off-by: Vignesh R 
> ---
>  drivers/usb/host/xhci-dwc3.c | 11 +++
>  1 file changed, 11 insertions(+)
>

Reviewed-by: Bin Meng 
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Re: [U-Boot] [PATCH v2 2/3] usb: xhci-dwc3: Refractor PHY operations into separate function

[Bin Meng]

On Wed, Mar 7, 2018 at 5:20 PM, Vignesh R  wrote:
> Refractor PHY get/init/poweron and PHY poweroff/exit operations into
> separate function so that its easy to support multiple PHYs.
>
> Signed-off-by: Vignesh R 
> ---
>  drivers/usb/host/xhci-dwc3.c | 75 
> 
>  1 file changed, 48 insertions(+), 27 deletions(-)
>

Reviewed-by: Bin Meng 
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Re: [U-Boot] [PATCH] dm: mmc: socfpga: call dwmci_probe()

[Jaehoon Chung]

On 03/08/2018 12:12 PM, Marek Vasut wrote:
> On 03/08/2018 03:17 AM, Jaehoon Chung wrote:
>> On 03/06/2018 05:07 PM, linux-kernel-...@beckhoff.com wrote:
>>> From: Patrick Bruenn 
>>>
>>> On a socfpga_cyclone5 based board the SD card, was never powered up. For
>>> other dw_mmc based SoCs dwmci_probe() is called in the platform specific
>>> probe(). It seems this call is missing for socfpga_dw_mmc.
>>>
>>> With this change DWMCI_PWREN is set by dmwci_init().
>>>
>>> Signed-off-by: Patrick Bruenn 
>>
>> Reviewed-by: Jaehoon Chung 
>>
>> Will apply this patch before releasing v2018.03.
>> (I have a problem about accessing git.denx.de. After fixing my problem, will 
>> resend email about applying.)
> 
> DWMMC works on SoCFPGA for me (tested on rc4), so I don't understand what 
> this patch is trying to fix. I'd prefer if you did not hastily apply this.

It's my misunderstanding. When i checked more. I think that Marek is right.
Thanks Marek for pointing out.

Best Regards,
Jaehoon Chung

> 
> 
> 

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Re: [U-Boot] [PATCH] dm: mmc: socfpga: call dwmci_probe()

[Marek Vasut]

On 03/08/2018 03:17 AM, Jaehoon Chung wrote:

On 03/06/2018 05:07 PM, linux-kernel-...@beckhoff.com wrote:

From: Patrick Bruenn 

On a socfpga_cyclone5 based board the SD card, was never powered up. For
other dw_mmc based SoCs dwmci_probe() is called in the platform specific
probe(). It seems this call is missing for socfpga_dw_mmc.

With this change DWMCI_PWREN is set by dmwci_init().

Signed-off-by: Patrick Bruenn 


Reviewed-by: Jaehoon Chung 

Will apply this patch before releasing v2018.03.
(I have a problem about accessing git.denx.de. After fixing my problem, will 
resend email about applying.)


DWMMC works on SoCFPGA for me (tested on rc4), so I don't understand 
what this patch is trying to fix. I'd prefer if you did not hastily 
apply this.

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Re: [U-Boot] [PATCH] dm: mmc: socfpga: call dwmci_probe()

[Jaehoon Chung]

On 03/06/2018 05:07 PM, linux-kernel-...@beckhoff.com wrote:
> From: Patrick Bruenn 
> 
> On a socfpga_cyclone5 based board the SD card, was never powered up. For
> other dw_mmc based SoCs dwmci_probe() is called in the platform specific
> probe(). It seems this call is missing for socfpga_dw_mmc.
> 
> With this change DWMCI_PWREN is set by dmwci_init().
> 
> Signed-off-by: Patrick Bruenn 

Reviewed-by: Jaehoon Chung 

Will apply this patch before releasing v2018.03.
(I have a problem about accessing git.denx.de. After fixing my problem, will 
resend email about applying.)

Thanks.

Best Regards,
Jaehoon Chung

> ---
> 
>  drivers/mmc/socfpga_dw_mmc.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/mmc/socfpga_dw_mmc.c b/drivers/mmc/socfpga_dw_mmc.c
> index 759686ccd6..c5fce8f09d 100644
> --- a/drivers/mmc/socfpga_dw_mmc.c
> +++ b/drivers/mmc/socfpga_dw_mmc.c
> @@ -124,7 +124,7 @@ static int socfpga_dwmmc_probe(struct udevice *dev)
>   upriv->mmc = host->mmc;
>   host->mmc->dev = dev;
>  
> - return 0;
> + return dwmci_probe(dev);
>  }
>  
>  static int socfpga_dwmmc_bind(struct udevice *dev)
> 

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Re: [U-Boot] [PATCH] mmc: fix return value check condition

[Jaehoon Chung]

Hi Peng,

On 03/05/2018 05:20 PM, Peng Fan wrote:
> sd_read_ssr returns 0, means no error.
> Fixes: 5b2e72f32721484("mmc: read ssr only if MMC write support is enabled")
> 
> Signed-off-by: Peng Fan 
> Cc: Jaehoon Chung 
> Cc: Jean-Jacques Hiblot 

Will apply your patch. I have a problem about firewall exception for 
git.denx.de.
After fixing my problem, re-send the email about applying a patch.

Best Regards,
Jaehoon Chung

> ---
>  drivers/mmc/mmc.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
> index c930893300..92ea78b8af 100644
> --- a/drivers/mmc/mmc.c
> +++ b/drivers/mmc/mmc.c
> @@ -1689,7 +1689,7 @@ static int sd_select_mode_and_width(struct mmc *mmc, 
> uint card_caps)
>  
>  #if CONFIG_IS_ENABLED(MMC_WRITE)
>   err = sd_read_ssr(mmc);
> - if (!err)
> + if (err)
>   pr_warn("unable to read ssr\n");
>  #endif
>   if (!err)
> 

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Re: [U-Boot] [PATCH] spi: atcspi200: Full dm conversion

[陳建志]

2018-03-07 19:02 GMT+08:00 Jagan Teki :
>
>
> On 07-Mar-2018 1:12 PM, "陳建志"  wrote:
>
> 2018-03-07 15:20 GMT+08:00 Jagan Teki :
>> On Wed, Mar 7, 2018 at 12:34 PM, Andes  wrote:
>>> From: Rick Chen 
>>>
>>> atcspi200_spi now support dt along with platform data.
>>>
>>> Signed-off-by: Rick Chen 
>>> Signed-off-by: Rick Chen 
>>> Signed-off-by: Greentime Hu 
>>> ---
>>>  drivers/spi/atcspi200_spi.c  |  134
>>> ++
>>>  include/dm/platform_data/spi_atcspi200.h |   15 
>>
>> I have seen only two boards using this driver (adp-ae3xx_defconfig,
>> nx25-ae250_defconfig) and both are enabled DM_SPI with OF_CONTROL why
>> we need to have platdata for this? here [1] is non-dm code drop.
>>
>> [1] https://patchwork.ozlabs.org/patch/882404/
>
> Hi Tagan Teki
>
> I just refer to [PATCH][Boards Need to Switch DM] spi: davinci: Full
> dm conversion
> And have this modification.
>
> So it is not necessary to add platdata for atcspi200_spi, just drop
> non-dm code, right ?
>
>
> There are two boards using this driver adp-ae3xx_defconfig and
> nx25-ae250_defconfig, both of them use DM_SPL with dr. With this reason it
> is not require to add pdata here?

Thanks for your explanations.

Rick
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Re: [U-Boot] [PATCH v2] common: add a prototype for mach_cpu_init()

[Masahiro Yamada]

2018-03-07 23:45 GMT+09:00 Tom Rini :
> On Wed, Mar 07, 2018 at 03:28:20PM +0100, Patrick Delaunay wrote:
>
>> avoid warning: no previous prototype for ‘mach_cpu_init’
>>
>> Signed-off-by: Patrick Delaunay 
>
> Reviewed-by: Tom Rini 
>
> --


People tend to put all sort of misc thingy into common.h
but this is one of the ugliest parts in U-Boot.

Most of files parse  that contains
unrelated / unnecessary defines.
Please realize this madness.

I have tried to slim it down several times,
but people have added more and more.  So this task never ends.

How about splitting out platform init hooks?
( or anything suitable is OK.)

Also, I'd like to ban new additions to 
like we do for config_whitelist.txt
(for example, record the number of lines of 
then build fails if somebody increases it.)




-- 
Best Regards
Masahiro Yamada
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[U-Boot] [PATCH] fs: ext4: Do not print mount fail message when not ext4 filesystem

[Marek Behún]

Other filesystem drivers don't do this.

Signed-off-by: Marek Behun 
---
 fs/ext4/ext4_common.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/fs/ext4/ext4_common.c b/fs/ext4/ext4_common.c
index dac9545365..e3cc30a1e0 100644
--- a/fs/ext4/ext4_common.c
+++ b/fs/ext4/ext4_common.c
@@ -2343,7 +2343,7 @@ int ext4fs_mount(unsigned part_length)
 
/* Make sure this is an ext2 filesystem. */
if (le16_to_cpu(data->sblock.magic) != EXT2_MAGIC)
-   goto fail;
+   goto fail_noerr;
 
 
if (le32_to_cpu(data->sblock.revision_level) == 0) {
@@ -2379,6 +2379,7 @@ int ext4fs_mount(unsigned part_length)
return 1;
 fail:
printf("Failed to mount ext2 filesystem...\n");
+fail_noerr:
free(data);
ext4fs_root = NULL;
 
-- 
2.16.1

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[U-Boot] [PATCH v1 15/19] spi: mvebu_a3700_spi: Use Armada 37xx clk driver for SPI clock frequency

[Marek Behún]

Since now we have driver for clocks on Armada 37xx, use it to determine
SQF clock frequency for the SPI driver.

Also change the default config files for Armada 37xx devices so that
the clock driver is enabled by default, otherwise the SPI driver cannot
be enabled.

Signed-off-by: Marek Behun 
---
 arch/arm/dts/armada-37xx.dtsi   |  4 +--
 configs/mvebu_db-88f3720_defconfig  |  3 ++
 configs/mvebu_espressobin-88f3720_defconfig |  3 ++
 drivers/spi/Kconfig |  1 +
 drivers/spi/mvebu_a3700_spi.c   | 52 -
 5 files changed, 37 insertions(+), 26 deletions(-)

diff --git a/arch/arm/dts/armada-37xx.dtsi b/arch/arm/dts/armada-37xx.dtsi
index e848812fca..c254c0aded 100644
--- a/arch/arm/dts/armada-37xx.dtsi
+++ b/arch/arm/dts/armada-37xx.dtsi
@@ -281,8 +281,8 @@
#address-cells = <1>;
#size-cells = <0>;
#clock-cells = <0>;
-   clock-frequency = <16>;
-   spi-max-frequency = <4>;
+   spi-max-frequency = <5000>;
+   clocks = <_periph_clk 7>;
status = "disabled";
};
 
diff --git a/configs/mvebu_db-88f3720_defconfig 
b/configs/mvebu_db-88f3720_defconfig
index 338d764d84..c8ca06e428 100644
--- a/configs/mvebu_db-88f3720_defconfig
+++ b/configs/mvebu_db-88f3720_defconfig
@@ -33,6 +33,9 @@ CONFIG_DM_GPIO=y
 # CONFIG_MVEBU_GPIO is not set
 CONFIG_DM_I2C=y
 CONFIG_MISC=y
+CONFIG_CLK=y
+CONFIG_CLK_MVEBU=y
+CONFIG_CLK_ARMADA_3720=y
 CONFIG_DM_MMC=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_SDMA=y
diff --git a/configs/mvebu_espressobin-88f3720_defconfig 
b/configs/mvebu_espressobin-88f3720_defconfig
index 28005e6131..5f449d34ea 100644
--- a/configs/mvebu_espressobin-88f3720_defconfig
+++ b/configs/mvebu_espressobin-88f3720_defconfig
@@ -30,6 +30,9 @@ CONFIG_SCSI_AHCI=y
 CONFIG_BLOCK_CACHE=y
 CONFIG_DM_I2C=y
 CONFIG_MISC=y
+CONFIG_CLK=y
+CONFIG_CLK_MVEBU=y
+CONFIG_CLK_ARMADA_3720=y
 CONFIG_DM_MMC=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_SDMA=y
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 235a8c7d73..4ea94a5f35 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -94,6 +94,7 @@ config ICH_SPI
 
 config MVEBU_A3700_SPI
bool "Marvell Armada 3700 SPI driver"
+   depends on CLK_ARMADA_3720
help
  Enable the Marvell Armada 3700 SPI driver. This driver can be
  used to access the SPI NOR flash on platforms embedding this
diff --git a/drivers/spi/mvebu_a3700_spi.c b/drivers/spi/mvebu_a3700_spi.c
index d1708a8d56..19e854945b 100644
--- a/drivers/spi/mvebu_a3700_spi.c
+++ b/drivers/spi/mvebu_a3700_spi.c
@@ -10,6 +10,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 
@@ -22,9 +23,8 @@ DECLARE_GLOBAL_DATA_PTR;
 #define MVEBU_SPI_A3700_CLK_POLBIT(7)
 #define MVEBU_SPI_A3700_FIFO_ENBIT(17)
 #define MVEBU_SPI_A3700_SPI_EN_0   BIT(16)
-#define MVEBU_SPI_A3700_CLK_PRESCALE_BIT   0
-#define MVEBU_SPI_A3700_CLK_PRESCALE_MASK  \
-   (0x1f << MVEBU_SPI_A3700_CLK_PRESCALE_BIT)
+#define MVEBU_SPI_A3700_CLK_PRESCALE_MASK  0x1f
+
 
 /* SPI registers */
 struct spi_reg {
@@ -36,8 +36,7 @@ struct spi_reg {
 
 struct mvebu_spi_platdata {
struct spi_reg *spireg;
-   unsigned int frequency;
-   unsigned int clock;
+   struct clk clk;
 };
 
 static void spi_cs_activate(struct spi_reg *reg, int cs)
@@ -178,17 +177,18 @@ static int mvebu_spi_set_speed(struct udevice *bus, uint 
hz)
 {
struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
struct spi_reg *reg = plat->spireg;
-   u32 data;
+   u32 data, prescale;
 
data = readl(>cfg);
 
-   /* Set Prescaler */
-   data &= ~MVEBU_SPI_A3700_CLK_PRESCALE_MASK;
+   prescale = DIV_ROUND_UP(clk_get_rate(>clk), hz);
+   if (prescale > 31)
+   prescale = 0x1f;
+   else if (prescale > 15)
+   prescale = 0x10 + (prescale + 1)/2;
 
-   /* Calculate Prescaler = (spi_input_freq / spi_max_freq) */
-   if (hz > plat->frequency)
-   hz = plat->frequency;
-   data |= plat->clock / hz;
+   data &= ~MVEBU_SPI_A3700_CLK_PRESCALE_MASK;
+   data |= prescale & MVEBU_SPI_A3700_CLK_PRESCALE_MASK;
 
writel(data, >cfg);
 
@@ -252,21 +252,24 @@ static int mvebu_spi_probe(struct udevice *bus)
 static int mvebu_spi_ofdata_to_platdata(struct udevice *bus)
 {
struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
+   int ret;
 
plat->spireg = (struct spi_reg *)devfdt_get_addr(bus);
 
-   /*
-* FIXME
-* Right now, mvebu does not have a clock infrastructure in U-Boot
-* which should be used to query the input clock to the SPI
-* 

[U-Boot] [PATCH v1 11/19] phy: marvell: a3700: Use comphy_mux on Armada 37xx.

[Marek Behún]

Lane 0 supports SGMII1 and USB3.
Lane 1 supports SGMII0 and PEX0.
Lane 2 supports SATA0 and USB3.

This is needed for Armada 37xx.

Signed-off-by: Marek Behun 
---
 arch/arm/dts/armada-37xx.dtsi  |  5 +++--
 drivers/phy/marvell/comphy_a3700.c | 36 
 2 files changed, 39 insertions(+), 2 deletions(-)

diff --git a/arch/arm/dts/armada-37xx.dtsi b/arch/arm/dts/armada-37xx.dtsi
index 690234234b..d0529637f4 100644
--- a/arch/arm/dts/armada-37xx.dtsi
+++ b/arch/arm/dts/armada-37xx.dtsi
@@ -284,8 +284,9 @@
compatible = "marvell,mvebu-comphy", 
"marvell,comphy-armada-3700";
reg = <0x18300 0x28>,
  <0x1f300 0x3d000>;
-   mux-bitcount = <1>;
-   max-lanes = <2>;
+   mux-bitcount = <4>;
+   mux-lane-order = <1 0 2>;
+   max-lanes = <3>;
};
};
};
diff --git a/drivers/phy/marvell/comphy_a3700.c 
b/drivers/phy/marvell/comphy_a3700.c
index 1182842609..c665d6fde8 100644
--- a/drivers/phy/marvell/comphy_a3700.c
+++ b/drivers/phy/marvell/comphy_a3700.c
@@ -14,6 +14,38 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+struct comphy_mux_data a3700_comphy_mux_data[] = {
+/* Lane 0 */
+   {
+   4,
+   {
+   { PHY_TYPE_UNCONNECTED, 0x0 },
+   { PHY_TYPE_SGMII1,  0x0 },
+   { PHY_TYPE_USB3_HOST0,  0x1 },
+   { PHY_TYPE_USB3_DEVICE, 0x1 }
+   }
+   },
+/* Lane 1 */
+   {
+   3,
+   {
+   { PHY_TYPE_UNCONNECTED, 0x0},
+   { PHY_TYPE_SGMII0,  0x0},
+   { PHY_TYPE_PEX0,0x1}
+   }
+   },
+/* Lane 2 */
+   {
+   4,
+   {
+   { PHY_TYPE_UNCONNECTED, 0x0},
+   { PHY_TYPE_SATA0,   0x0},
+   { PHY_TYPE_USB3_HOST0,  0x1},
+   { PHY_TYPE_USB3_DEVICE, 0x1}
+   }
+   },
+};
+
 struct sgmii_phy_init_data_fix {
u16 addr;
u16 value;
@@ -943,6 +975,10 @@ int comphy_a3700_init(struct chip_serdes_phy_config 
*chip_cfg,
 
debug_enter();
 
+   /* Initialize PHY mux */
+   chip_cfg->mux_data = a3700_comphy_mux_data;
+   comphy_mux_init(chip_cfg, serdes_map, COMPHY_SEL_ADDR);
+
for (lane = 0, comphy_map = serdes_map; lane < comphy_max_count;
 lane++, comphy_map++) {
debug("Initialize serdes number %d\n", lane);
-- 
2.16.1

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[U-Boot] [PATCH v1 14/19] driver: clk: Add support for clocks on Armada 37xx

[Marek Behún]

The drivers are based on Linux driver by Gregory Clement.

The TBG clocks support only the .get_rate method.
  - since setting rate is not supported, the driver computes the rates
when probing and so subsequent calls to the .get_rate method do not
read the corresponding registers again

The peripheral clocks support methods .get_rate, .enable and .disable.

  - the .set_parent method theoretically could be supported on some clocks
(the parent would have to be one of the TBG clocks)

  - the .set_rate method would have to try all the divider values to find
the best approximation of a given rate, and it doesn't seem like
this should be needed in U-Boot, therefore not implemented

Signed-off-by: Marek Behun 
---
 arch/arm/dts/armada-37xx.dtsi  |  20 ++
 drivers/clk/Kconfig|   1 +
 drivers/clk/Makefile   |   1 +
 drivers/clk/mvebu/Kconfig  |  11 +
 drivers/clk/mvebu/Makefile |   1 +
 drivers/clk/mvebu/armada-37xx-periph.c | 464 +
 drivers/clk/mvebu/armada-37xx-tbg.c| 153 +++
 7 files changed, 651 insertions(+)

diff --git a/arch/arm/dts/armada-37xx.dtsi b/arch/arm/dts/armada-37xx.dtsi
index d0529637f4..e848812fca 100644
--- a/arch/arm/dts/armada-37xx.dtsi
+++ b/arch/arm/dts/armada-37xx.dtsi
@@ -106,6 +106,26 @@
status = "disabled";
};
 
+   nb_periph_clk: nb-periph-clk@13000 {
+   compatible = 
"marvell,armada-3700-periph-clock-nb";
+   reg = <0x13000 0x100>;
+   clocks = < 0>, < 1>, < 2>, < 3>;
+   #clock-cells = <1>;
+   };
+
+   sb_periph_clk: sb-periph-clk@18000 {
+   compatible = 
"marvell,armada-3700-periph-clock-sb";
+   reg = <0x18000 0x100>;
+   clocks = < 0>, < 1>, < 2>, < 3>;
+   #clock-cells = <1>;
+   };
+
+   tbg: tbg@13200 {
+   compatible = "marvell,armada-3700-tbg-clock";
+   reg = <0x13200 0x100>;
+   #clock-cells = <1>;
+   };
+
pinctrl_nb: pinctrl-nb@13800 {
compatible = "marvell,armada3710-nb-pinctrl",
"syscon", "simple-mfd";
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index cdfa052c16..a40c8e5c8f 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -80,5 +80,6 @@ source "drivers/clk/uniphier/Kconfig"
 source "drivers/clk/exynos/Kconfig"
 source "drivers/clk/at91/Kconfig"
 source "drivers/clk/renesas/Kconfig"
+source "drivers/clk/mvebu/Kconfig"
 
 endmenu
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index dab106ab7f..094bcf5847 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -11,6 +11,7 @@ obj-y += tegra/
 obj-$(CONFIG_ARCH_ASPEED) += aspeed/
 obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
 obj-$(CONFIG_CLK_AT91) += at91/
+obj-$(CONFIG_CLK_MVEBU) += mvebu/
 obj-$(CONFIG_CLK_BCM6345) += clk_bcm6345.o
 obj-$(CONFIG_CLK_BOSTON) += clk_boston.o
 obj-$(CONFIG_CLK_EXYNOS) += exynos/
diff --git a/drivers/clk/mvebu/Kconfig b/drivers/clk/mvebu/Kconfig
new file mode 100644
index 00..e776a15e7b
--- /dev/null
+++ b/drivers/clk/mvebu/Kconfig
@@ -0,0 +1,11 @@
+config CLK_MVEBU
+   bool "MVEBU clock drivers"
+   depends on CLK && ARCH_MVEBU
+   help
+ Enable support for clock present on Marvell MVEBU SoCs.
+
+config CLK_ARMADA_3720
+   bool "Marvell Armada 3720 clock driver"
+   depends on CLK_MVEBU && ARM64
+   help
+ Enable this to support the clocks on Marvell Armada 3720 SoC.
diff --git a/drivers/clk/mvebu/Makefile b/drivers/clk/mvebu/Makefile
new file mode 100644
index 00..7f80313203
--- /dev/null
+++ b/drivers/clk/mvebu/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_CLK_ARMADA_3720) += armada-37xx-periph.o armada-37xx-tbg.o
diff --git a/drivers/clk/mvebu/armada-37xx-periph.c 
b/drivers/clk/mvebu/armada-37xx-periph.c
new file mode 100644
index 00..94eabe5f19
--- /dev/null
+++ b/drivers/clk/mvebu/armada-37xx-periph.c
@@ -0,0 +1,464 @@
+/*
+ * Marvell Armada 37xx SoC Peripheral clocks
+ *
+ * Marek Behun 
+ *
+ * Based on Linux driver by:
+ *   Gregory CLEMENT 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define TBG_SEL0x0
+#define DIV_SEL0   0x4
+#define DIV_SEL1   0x8
+#define DIV_SEL2   0xC
+#define CLK_SEL0x10
+#define CLK_DIS0x14
+
+enum a37xx_periph_parent {
+   TBG_A_P = 0,
+   

[U-Boot] [PATCH v1 18/19] phy: marvell: core: Cosmetic fixes

[Marek Behún]

Move the reg_set* functions into comphy.h as static inline functions.
Change return type of get_*_string to const char *.

Signed-off-by: Marek Behun 
---
 drivers/phy/marvell/comphy.h  | 41 ++---
 drivers/phy/marvell/comphy_core.c | 64 +--
 2 files changed, 52 insertions(+), 53 deletions(-)

diff --git a/drivers/phy/marvell/comphy.h b/drivers/phy/marvell/comphy.h
index 32e0a1e652..176bc89cac 100644
--- a/drivers/phy/marvell/comphy.h
+++ b/drivers/phy/marvell/comphy.h
@@ -102,10 +102,43 @@ struct chip_serdes_phy_config {
 };
 
 /* Register helper functions */
-void reg_set(void __iomem *addr, u32 data, u32 mask);
-void reg_set_silent(void __iomem *addr, u32 data, u32 mask);
-void reg_set16(void __iomem *addr, u16 data, u16 mask);
-void reg_set_silent16(void __iomem *addr, u16 data, u16 mask);
+static inline void reg_set_silent(void __iomem *addr, u32 data, u32 mask)
+{
+   u32 reg_data;
+
+   reg_data = readl(addr);
+   reg_data &= ~mask;
+   reg_data |= data;
+   writel(reg_data, addr);
+}
+
+static inline void reg_set(void __iomem *addr, u32 data, u32 mask)
+{
+   debug("Write to address = %#010lx, data = %#010x (mask = %#010x) - ",
+ (unsigned long)addr, data, mask);
+   debug("old value = %#010x ==> ", readl(addr));
+   reg_set_silent(addr, data, mask);
+   debug("new value %#010x\n", readl(addr));
+}
+
+static inline void reg_set_silent16(void __iomem *addr, u16 data, u16 mask)
+{
+   u16 reg_data;
+
+   reg_data = readw(addr);
+   reg_data &= ~mask;
+   reg_data |= data;
+   writew(reg_data, addr);
+}
+
+static inline void reg_set16(void __iomem *addr, u16 data, u16 mask)
+{
+   debug("Write to address = %#010lx, data = %#06x (mask = %#06x) - ",
+ (unsigned long)addr, data, mask);
+   debug("old value = %#06x ==> ", readw(addr));
+   reg_set_silent16(addr, data, mask);
+   debug("new value %#06x\n", readw(addr));
+}
 
 /* SoC specific init functions */
 #ifdef CONFIG_ARMADA_3700
diff --git a/drivers/phy/marvell/comphy_core.c 
b/drivers/phy/marvell/comphy_core.c
index 1e5664c435..b2fe9fca0a 100644
--- a/drivers/phy/marvell/comphy_core.c
+++ b/drivers/phy/marvell/comphy_core.c
@@ -18,11 +18,13 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static char *get_speed_string(u32 speed)
+static const char *get_speed_string(u32 speed)
 {
-   char *speed_strings[] = {"1.25 Gbps", "1.5 Gbps", "2.5 Gbps",
-"3.0 Gbps", "3.125 Gbps", "5 Gbps", "6 Gbps",
-"6.25 Gbps", "10.31 Gbps" };
+   const char *speed_strings[] = {
+   "1.25 Gbps", "1.5 Gbps", "2.5 Gbps",
+   "3.0 Gbps", "3.125 Gbps", "5 Gbps", "6 Gbps",
+   "6.25 Gbps", "10.31 Gbps"
+   };
 
if (speed < 0 || speed > PHY_SPEED_MAX)
return "invalid";
@@ -30,14 +32,16 @@ static char *get_speed_string(u32 speed)
return speed_strings[speed];
 }
 
-static char *get_type_string(u32 type)
+static const char *get_type_string(u32 type)
 {
-   char *type_strings[] = {"UNCONNECTED", "PEX0", "PEX1", "PEX2", "PEX3",
-   "SATA0", "SATA1", "SATA2", "SATA3", "SGMII0",
-   "SGMII1", "SGMII2", "SGMII3", "QSGMII",
-   "USB3_HOST0", "USB3_HOST1", "USB3_DEVICE",
-   "XAUI0", "XAUI1", "XAUI2", "XAUI3",
-   "RXAUI0", "RXAUI1", "SFI", "IGNORE"};
+   const char *type_strings[] = {
+   "UNCONNECTED", "PEX0", "PEX1", "PEX2", "PEX3",
+   "SATA0", "SATA1", "SATA2", "SATA3", "SGMII0",
+   "SGMII1", "SGMII2", "SGMII3", "QSGMII",
+   "USB3_HOST0", "USB3_HOST1", "USB3_DEVICE",
+   "XAUI0", "XAUI1", "XAUI2", "XAUI3",
+   "RXAUI0", "RXAUI1", "SFI", "IGNORE"
+   };
 
if (type < 0 || type > PHY_TYPE_MAX)
return "invalid";
@@ -45,44 +49,6 @@ static char *get_type_string(u32 type)
return type_strings[type];
 }
 
-void reg_set(void __iomem *addr, u32 data, u32 mask)
-{
-   debug("Write to address = %#010lx, data = %#010x (mask = %#010x) - ",
- (unsigned long)addr, data, mask);
-   debug("old value = %#010x ==> ", readl(addr));
-   reg_set_silent(addr, data, mask);
-   debug("new value %#010x\n", readl(addr));
-}
-
-void reg_set_silent(void __iomem *addr, u32 data, u32 mask)
-{
-   u32 reg_data;
-
-   reg_data = readl(addr);
-   reg_data &= ~mask;
-   reg_data |= data;
-   writel(reg_data, addr);
-}
-
-void reg_set16(void __iomem *addr, u16 data, u16 mask)
-{
-   debug("Write to address = %#010lx, data = %#06x (mask = %#06x) - ",
- (unsigned long)addr, data, mask);
-   debug("old value = %#06x ==> ", readw(addr));
-   reg_set_silent16(addr, data, mask);
-   debug("new value 

[U-Boot] [PATCH v1 13/19] arm64: mvebu_armada_37xx: Use Armada 37xx pinctrl driver by default

[Marek Behún]

The driver is already in the tree and functional. Enable it by default
and also remove the board_early_init_f which was a temporary fix for
not having the pinctrl driver.

Signed-off-by: Marek Behun 
---
 board/Marvell/mvebu_armada-37xx/board.c | 32 -
 configs/mvebu_db-88f3720_defconfig  |  5 -
 configs/mvebu_espressobin-88f3720_defconfig |  5 -
 3 files changed, 8 insertions(+), 34 deletions(-)

diff --git a/board/Marvell/mvebu_armada-37xx/board.c 
b/board/Marvell/mvebu_armada-37xx/board.c
index ac3e3a392f..fdd42788d2 100644
--- a/board/Marvell/mvebu_armada-37xx/board.c
+++ b/board/Marvell/mvebu_armada-37xx/board.c
@@ -21,10 +21,6 @@ DECLARE_GLOBAL_DATA_PTR;
 #define I2C_IO_REG_0_SATA_OFF  2
 #define I2C_IO_REG_0_USB_H_OFF 1
 
-/* The pin control values are the same for DB and Espressobin */
-#define PINCTRL_NB_REG_VALUE   0x000173fa
-#define PINCTRL_SB_REG_VALUE   0x7a23
-
 /* Ethernet switch registers */
 /* SMI addresses for multi-chip mode */
 #define MVEBU_PORT_CTRL_SMI_ADDR(p)(16 + (p))
@@ -48,34 +44,6 @@ DECLARE_GLOBAL_DATA_PTR;
 #define MVEBU_G2_SMI_PHY_CMD_REG   (24)
 #define MVEBU_G2_SMI_PHY_DATA_REG  (25)
 
-int board_early_init_f(void)
-{
-   const void *blob = gd->fdt_blob;
-   const char *bank_name;
-   const char *compat = "marvell,armada-3700-pinctl";
-   int off, len;
-   void __iomem *addr;
-
-   /* FIXME
-* Temporary WA for setting correct pin control values
-* until the real pin control driver is awailable.
-*/
-   off = fdt_node_offset_by_compatible(blob, -1, compat);
-   while (off != -FDT_ERR_NOTFOUND) {
-   bank_name = fdt_getprop(blob, off, "bank-name", );
-   addr = (void __iomem *)fdtdec_get_addr_size_auto_noparent(
-   blob, off, "reg", 0, NULL, true);
-   if (!strncmp(bank_name, "armada-3700-nb", len))
-   writel(PINCTRL_NB_REG_VALUE, addr);
-   else if (!strncmp(bank_name, "armada-3700-sb", len))
-   writel(PINCTRL_SB_REG_VALUE, addr);
-
-   off = fdt_node_offset_by_compatible(blob, off, compat);
-   }
-
-   return 0;
-}
-
 int board_init(void)
 {
/* adress of boot parameters */
diff --git a/configs/mvebu_db-88f3720_defconfig 
b/configs/mvebu_db-88f3720_defconfig
index 1d6233a6ff..338d764d84 100644
--- a/configs/mvebu_db-88f3720_defconfig
+++ b/configs/mvebu_db-88f3720_defconfig
@@ -12,7 +12,6 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y
 # CONFIG_DISPLAY_CPUINFO is not set
 # CONFIG_DISPLAY_BOARDINFO is not set
 CONFIG_ARCH_EARLY_INIT_R=y
-CONFIG_BOARD_EARLY_INIT_F=y
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_I2C=y
@@ -38,6 +37,10 @@ CONFIG_DM_MMC=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_SDMA=y
 CONFIG_MMC_SDHCI_XENON=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_GENERIC=y
+CONFIG_PINMUX=y
+CONFIG_PINCTRL_ARMADA_37XX=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/mvebu_espressobin-88f3720_defconfig 
b/configs/mvebu_espressobin-88f3720_defconfig
index 314d405ea3..28005e6131 100644
--- a/configs/mvebu_espressobin-88f3720_defconfig
+++ b/configs/mvebu_espressobin-88f3720_defconfig
@@ -12,7 +12,6 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y
 # CONFIG_DISPLAY_CPUINFO is not set
 # CONFIG_DISPLAY_BOARDINFO is not set
 CONFIG_ARCH_EARLY_INIT_R=y
-CONFIG_BOARD_EARLY_INIT_F=y
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
@@ -35,6 +34,10 @@ CONFIG_DM_MMC=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_SDMA=y
 CONFIG_MMC_SDHCI_XENON=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_GENERIC=y
+CONFIG_PINMUX=y
+CONFIG_PINCTRL_ARMADA_37XX=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_SPANSION=y
-- 
2.16.1

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[U-Boot] [PATCH v1 08/19] phy: marvell: a3700: Set USB3 RX wait depending on ref clock

[Marek Behún]

According to specification, CFG_PM_RXDLOZ_WAIT should be set to 0x7
when reference clock is at 25 MHz. The specification (at least the
version I have) does not mentoin the setting for 40 MHz reference
clock, but Marvell's U-Boot sets 0xC in that case.

Signed-off-by: Marek Behun 
---
 drivers/phy/marvell/comphy_a3700.c | 8 +++-
 1 file changed, 3 insertions(+), 5 deletions(-)

diff --git a/drivers/phy/marvell/comphy_a3700.c 
b/drivers/phy/marvell/comphy_a3700.c
index b5f2013bbb..78caa96014 100644
--- a/drivers/phy/marvell/comphy_a3700.c
+++ b/drivers/phy/marvell/comphy_a3700.c
@@ -394,20 +394,18 @@ static int comphy_usb3_power_up(u32 lane, u32 type, u32 
speed, u32 invert)
/*
 * 3. Check crystal jumper setting and program the Power and PLL
 * Control accordingly
+* 4. Change RX wait
 */
if (get_ref_clk() == 40) {
/* 40 MHz */
usb3_reg_set16(PWR_PLL_CTRL, 0xFCA3, 0x);
+   usb3_reg_set16(PWR_MGM_TIM1, 0x10C, 0x);
} else {
/* 25 MHz */
usb3_reg_set16(PWR_PLL_CTRL, 0xFCA2, 0x);
+   usb3_reg_set16(PWR_MGM_TIM1, 0x107, 0x);
}
 
-   /*
-* 4. Change RX wait
-*/
-   usb3_reg_set16(PWR_MGM_TIM1, 0x10C, 0x);
-
/*
 * 5. Enable idle sync
 */
-- 
2.16.1

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[U-Boot] [PATCH v1 03/19] phy: marvell: a3700: Don't create functional macro for each register

[Marek Behún]

Currently there is for each register special functional macro, ie:
  LANE_CFG1_ADDR(u)
  GLOB_CLK_SRC_LO_ADDR(u)
  ...
where can be either PCIE or USB3.

Change this to one function PHY_ADDR(unit, addr). The code becomes:
  PHY_ADDR(PCIE, LANE_CFG1)
  PHY_ADDR(PCIE, GLOB_CLK_SRC_LO)
  ...

Signed-off-by: Marek Behun 
---
 drivers/phy/marvell/comphy_a3700.c | 105 ++---
 drivers/phy/marvell/comphy_a3700.h |  92 +---
 2 files changed, 89 insertions(+), 108 deletions(-)

diff --git a/drivers/phy/marvell/comphy_a3700.c 
b/drivers/phy/marvell/comphy_a3700.c
index 505e0933a3..6506c134e2 100644
--- a/drivers/phy/marvell/comphy_a3700.c
+++ b/drivers/phy/marvell/comphy_a3700.c
@@ -141,72 +141,70 @@ static int comphy_pcie_power_up(u32 speed, u32 invert)
/*
 * 1. Enable max PLL.
 */
-   reg_set16(LANE_CFG1_ADDR(PCIE), bf_use_max_pll_rate, 0);
+   reg_set16(PHY_ADDR(PCIE, LANE_CFG1), bf_use_max_pll_rate, 0);
 
/*
 * 2. Select 20 bit SERDES interface.
 */
-   reg_set16(GLOB_CLK_SRC_LO_ADDR(PCIE), bf_cfg_sel_20b, 0);
+   reg_set16(PHY_ADDR(PCIE, GLOB_CLK_SRC_LO), bf_cfg_sel_20b, 0);
 
/*
 * 3. Force to use reg setting for PCIe mode
 */
-   reg_set16(MISC_REG1_ADDR(PCIE), bf_sel_bits_pcie_force, 0);
+   reg_set16(PHY_ADDR(PCIE, MISC_REG1), bf_sel_bits_pcie_force, 0);
 
/*
 * 4. Change RX wait
 */
-   reg_set16(PWR_MGM_TIM1_ADDR(PCIE), 0x10C, 0x);
+   reg_set16(PHY_ADDR(PCIE, PWR_MGM_TIM1), 0x10C, 0x);
 
/*
 * 5. Enable idle sync
 */
-   reg_set16(UNIT_CTRL_ADDR(PCIE), 0x60 | rb_idle_sync_en, 0x);
+   reg_set16(PHY_ADDR(PCIE, UNIT_CTRL), 0x60 | rb_idle_sync_en, 0x);
 
/*
 * 6. Enable the output of 100M/125M/500M clock
 */
-   reg_set16(MISC_REG0_ADDR(PCIE),
+   reg_set16(PHY_ADDR(PCIE, MISC_REG0),
  0xA00D | rb_clk500m_en | rb_clk100m_125m_en, 0x);
 
/*
 * 7. Enable TX
 */
-   reg_set(PHY_REF_CLK_ADDR, 0x1342, 0x);
+   reg_set(PCIE_REF_CLK_ADDR, 0x1342, 0x);
 
/*
 * 8. Check crystal jumper setting and program the Power and PLL
 *Control accordingly
 */
if (get_ref_clk() == 40) {
-   reg_set16(PWR_PLL_CTRL_ADDR(PCIE),
- 0xFC63, 0x); /* 40 MHz */
+   /* 40 MHz */
+   reg_set16(PHY_ADDR(PCIE, PWR_PLL_CTRL), 0xFC63, 0x);
} else {
-   reg_set16(PWR_PLL_CTRL_ADDR(PCIE),
- 0xFC62, 0x); /* 25 MHz */
+   /* 25 MHz */
+   reg_set16(PHY_ADDR(PCIE, PWR_PLL_CTRL), 0xFC62, 0x);
}
 
/*
 * 9. Override Speed_PLL value and use MAC PLL
 */
-   reg_set16(KVCO_CAL_CTRL_ADDR(PCIE), 0x0040 | rb_use_max_pll_rate,
+   reg_set16(PHY_ADDR(PCIE, KVCO_CAL_CTRL), 0x0040 | rb_use_max_pll_rate,
  0x);
 
/*
 * 10. Check the Polarity invert bit
 */
-   if (invert & PHY_POLARITY_TXD_INVERT) {
-   reg_set16(SYNC_PATTERN_ADDR(PCIE), phy_txd_inv, 0);
-   }
+   if (invert & PHY_POLARITY_TXD_INVERT)
+   reg_set16(PHY_ADDR(PCIE, SYNC_PATTERN), phy_txd_inv, 0);
 
-   if (invert & PHY_POLARITY_RXD_INVERT) {
-   reg_set16(SYNC_PATTERN_ADDR(PCIE), phy_rxd_inv, 0);
-   }
+   if (invert & PHY_POLARITY_RXD_INVERT)
+   reg_set16(PHY_ADDR(PCIE, SYNC_PATTERN), phy_rxd_inv, 0);
 
/*
 * 11. Release SW reset
 */
-   reg_set16(GLOB_PHY_CTRL0_ADDR(PCIE),
+   reg_set16(PHY_ADDR(PCIE, GLOB_PHY_CTRL0),
  rb_mode_core_clk_freq_sel | rb_mode_pipe_width_32,
  bf_soft_rst | bf_mode_refdiv);
 
@@ -214,11 +212,11 @@ static int comphy_pcie_power_up(u32 speed, u32 invert)
udelay(PLL_SET_DELAY_US);
 
/* Assert PCLK enabled */
-   ret = comphy_poll_reg(LANE_STAT1_ADDR(PCIE),/* address */
- rb_txdclk_pclk_en,/* value */
- rb_txdclk_pclk_en,/* mask */
- PLL_LOCK_TIMEOUT, /* timeout */
- POLL_16B_REG);/* 16bit */
+   ret = comphy_poll_reg(PHY_ADDR(PCIE, LANE_STAT1),   /* address */
+ rb_txdclk_pclk_en,/* value */
+ rb_txdclk_pclk_en,/* mask */
+ PLL_LOCK_TIMEOUT, /* timeout */
+ POLL_16B_REG);/* 16bit */
if (ret == 0)
printf("Failed to lock PCIe PLL\n");
 
@@ -322,7 +320,7 @@ static int comphy_usb3_power_up(u32 type, u32 speed, u32 
invert)
 
/* 0xd005c300 = 

[U-Boot] [PATCH v1 19/19] net: mvneta: Fix fault when wrong device tree

[Marek Behún]

The driver does not check id phy_connect failed (for example on wrong
property name in device tree). In such a case a fault occurs and the
CPU is restarted.

Signed-off-by: Marek Behun 
---
 drivers/net/mvneta.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/drivers/net/mvneta.c b/drivers/net/mvneta.c
index 83e3153768..7403ccbd3c 100644
--- a/drivers/net/mvneta.c
+++ b/drivers/net/mvneta.c
@@ -1554,6 +1554,10 @@ static int mvneta_start(struct udevice *dev)
 
phydev = phy_connect(pp->bus, pp->phyaddr, dev,
 pp->phy_interface);
+   if (!phydev) {
+   printf("phy_connect failed\n");
+   return -1;
+   }
 
pp->phydev = phydev;
phy_config(phydev);
-- 
2.16.1

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[U-Boot] [PATCH v1 17/19] pinctrl: armada-37xx: Fix SB pinctrl groups according to new revision

[Marek Behún]

The groups pcie1, ptp and mii changed in new revision (from 2016).
Also smi was added to support enabling the MDIO pins.

Signed-off-by: Marek Behun 
---
 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c | 7 ---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c 
b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
index 2bf853eba1..8913e25c55 100644
--- a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
+++ b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
@@ -174,11 +174,12 @@ static struct armada_37xx_pin_group 
armada_37xx_sb_groups[] = {
PIN_GRP_GPIO("usb2_drvvbus1", 1, 1, BIT(1), "drvbus"),
PIN_GRP_GPIO("sdio_sb", 24, 5, BIT(2), "sdio"),
PIN_GRP_EXTRA("rgmii", 6, 14, BIT(3), 0, BIT(3), 23, 1, "mii", "gpio"),
-   PIN_GRP_GPIO("pcie1", 3, 2, BIT(4), "pcie"),
-   PIN_GRP_GPIO("ptp", 20, 3, BIT(5), "ptp"),
+   PIN_GRP_GPIO("smi", 18, 2, BIT(4), "smi"),
+   PIN_GRP_GPIO("pcie1", 3, 3, BIT(5) | BIT(9) | BIT(10), "pcie"),
+   PIN_GRP_GPIO("ptp", 20, 3, BIT(11) | BIT(12) | BIT(13), "ptp"),
PIN_GRP("ptp_clk", 21, 1, BIT(6), "ptp", "mii"),
PIN_GRP("ptp_trig", 22, 1, BIT(7), "ptp", "mii"),
-   PIN_GRP("mii_col", 23, 1, BIT(8), "mii", "mii_err"),
+   PIN_GRP("mii_col", 23, 1, BIT(8) | BIT(14), "mii", "mii_err"),
 };
 
 const struct armada_37xx_pin_data armada_37xx_pin_nb = {
-- 
2.16.1

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[U-Boot] [PATCH v1 10/19] phy: marvell: mux: Support nontrivial node order in selector register

[Marek Behún]

Currently comphy_mux supports only trivial order of nodes in pin
selector register, that is lane N on position N*bitcount.

Add support for nontrivial order, with map stored in device tree
property mux-lane-order.

This is needed for Armada 37xx.

Signed-off-by: Marek Behun 
---
 drivers/phy/marvell/comphy.h  |  1 +
 drivers/phy/marvell/comphy_core.c |  4 
 drivers/phy/marvell/comphy_mux.c  | 15 ---
 3 files changed, 17 insertions(+), 3 deletions(-)

diff --git a/drivers/phy/marvell/comphy.h b/drivers/phy/marvell/comphy.h
index c9b94a4c5e..32e0a1e652 100644
--- a/drivers/phy/marvell/comphy.h
+++ b/drivers/phy/marvell/comphy.h
@@ -97,6 +97,7 @@ struct chip_serdes_phy_config {
void __iomem *hpipe3_base_addr;
u32 comphy_lanes_count;
u32 comphy_mux_bitcount;
+   const fdt32_t *comphy_mux_lane_order;
u32 cp_index;
 };
 
diff --git a/drivers/phy/marvell/comphy_core.c 
b/drivers/phy/marvell/comphy_core.c
index 426db30f73..1e5664c435 100644
--- a/drivers/phy/marvell/comphy_core.c
+++ b/drivers/phy/marvell/comphy_core.c
@@ -135,6 +135,10 @@ static int comphy_probe(struct udevice *dev)
return -EINVAL;
}
 
+   chip_cfg->comphy_mux_lane_order =
+   fdtdec_locate_array(blob, node, "mux-lane-order",
+   chip_cfg->comphy_lanes_count);
+
if (device_is_compatible(dev, "marvell,comphy-armada-3700"))
chip_cfg->ptr_comphy_chip_init = comphy_a3700_init;
 
diff --git a/drivers/phy/marvell/comphy_mux.c b/drivers/phy/marvell/comphy_mux.c
index b036fb13b9..a8b07fdc98 100644
--- a/drivers/phy/marvell/comphy_mux.c
+++ b/drivers/phy/marvell/comphy_mux.c
@@ -79,7 +79,8 @@ static u32 comphy_mux_get_mux_value(struct comphy_mux_data 
*mux_data,
 static void comphy_mux_reg_write(struct comphy_mux_data *mux_data,
 struct comphy_map *comphy_map_data,
 int comphy_max_lanes,
-void __iomem *selector_base, u32 bitcount)
+void __iomem *selector_base,
+const fdt32_t *mux_lane_order, u32 bitcount)
 {
u32 lane, value, offset, mask;
 
@@ -90,7 +91,13 @@ static void comphy_mux_reg_write(struct comphy_mux_data 
*mux_data,
if (comphy_map_data->type == PHY_TYPE_IGNORE)
continue;
 
-   offset = lane * bitcount;
+   /* if the order of nodes in selector base register is
+  nontrivial, use mapping from mux_lane_order */
+   if (mux_lane_order)
+   offset = fdt32_to_cpu(mux_lane_order[lane]) * bitcount;
+   else
+   offset = lane * bitcount;
+
mask = (((1 << bitcount) - 1) << offset);
value = (comphy_mux_get_mux_value(mux_data,
  comphy_map_data->type,
@@ -106,6 +113,7 @@ void comphy_mux_init(struct chip_serdes_phy_config 
*chip_cfg,
 void __iomem *selector_base)
 {
struct comphy_mux_data *mux_data;
+   const fdt32_t *mux_lane_order;
u32 mux_bitcount;
u32 comphy_max_lanes;
 
@@ -113,13 +121,14 @@ void comphy_mux_init(struct chip_serdes_phy_config 
*chip_cfg,
 
comphy_max_lanes = chip_cfg->comphy_lanes_count;
mux_data = chip_cfg->mux_data;
+   mux_lane_order = chip_cfg->comphy_mux_lane_order;
mux_bitcount = chip_cfg->comphy_mux_bitcount;
 
/* check if the configuration is valid */
comphy_mux_check_config(mux_data, comphy_map_data, comphy_max_lanes);
/* Init COMPHY selectors */
comphy_mux_reg_write(mux_data, comphy_map_data, comphy_max_lanes,
-selector_base, mux_bitcount);
+selector_base, mux_lane_order, mux_bitcount);
 
debug_exit();
 }
-- 
2.16.1

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[U-Boot] [PATCH v1 16/19] clk: armada-37xx: Support soc_clk_dump

[Marek Behún]

Add support for the clk dump command on Armada 37xx.

Signed-off-by: Marek Behun 
---
 drivers/clk/mvebu/armada-37xx-periph.c | 36 +-
 drivers/clk/mvebu/armada-37xx-tbg.c|  2 ++
 2 files changed, 37 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/mvebu/armada-37xx-periph.c 
b/drivers/clk/mvebu/armada-37xx-periph.c
index 94eabe5f19..b53521bb9f 100644
--- a/drivers/clk/mvebu/armada-37xx-periph.c
+++ b/drivers/clk/mvebu/armada-37xx-periph.c
@@ -336,7 +336,8 @@ static int armada_37xx_periph_clk_disable(struct clk *clk)
return periph_clk_enable(clk, 0);
 }
 
-int armada_37xx_periph_clk_dump(struct udevice *dev)
+#if defined(CONFIG_CMD_CLK) && defined(CONFIG_CLK_ARMADA_3720)
+static int armada_37xx_periph_clk_dump(struct udevice *dev)
 {
struct a37xx_periphclk *priv = dev_get_priv(dev);
const struct clk_periph *clks;
@@ -355,6 +356,39 @@ int armada_37xx_periph_clk_dump(struct udevice *dev)
return 0;
 }
 
+static int clk_dump(const char *name, int (*func)(struct udevice *))
+{
+   struct udevice *dev;
+
+   if (uclass_get_device_by_name(UCLASS_CLK, name, )) {
+   printf("Cannot find device %s\n", name);
+   return -ENODEV;
+   }
+
+   return func(dev);
+}
+
+int armada_37xx_tbg_clk_dump(struct udevice *);
+
+int soc_clk_dump(void)
+{
+   printf("  xtal at %u00 Hz\n\n", get_ref_clk());
+
+   if (clk_dump("tbg@13200", armada_37xx_tbg_clk_dump))
+   return 1;
+
+   if (clk_dump("nb-periph-clk@13000",
+armada_37xx_periph_clk_dump))
+   return 1;
+
+   if (clk_dump("sb-periph-clk@18000",
+armada_37xx_periph_clk_dump))
+   return 1;
+
+   return 0;
+}
+#endif
+
 static int armada_37xx_periph_clk_probe(struct udevice *dev)
 {
struct a37xx_periphclk *priv = dev_get_priv(dev);
diff --git a/drivers/clk/mvebu/armada-37xx-tbg.c 
b/drivers/clk/mvebu/armada-37xx-tbg.c
index e8c654f1a6..3107d94494 100644
--- a/drivers/clk/mvebu/armada-37xx-tbg.c
+++ b/drivers/clk/mvebu/armada-37xx-tbg.c
@@ -94,6 +94,7 @@ static ulong armada_37xx_tbg_clk_get_rate(struct clk *clk)
return priv->rates[clk->id];
 }
 
+#if defined(CONFIG_CMD_CLK) && defined(CONFIG_CLK_ARMADA_3720)
 int armada_37xx_tbg_clk_dump(struct udevice *dev)
 {
struct a37xx_tbgclk *priv = dev_get_priv(dev);
@@ -106,6 +107,7 @@ int armada_37xx_tbg_clk_dump(struct udevice *dev)
 
return 0;
 }
+#endif
 
 static int armada_37xx_tbg_clk_probe(struct udevice *dev)
 {
-- 
2.16.1

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[U-Boot] [PATCH v1 04/19] phy: marvell: a3700: Use same timeout for all register polling

[Marek Behún]

The timeout is set to PLL_LOCK_TIMEOUT in every call to
comphy_poll_reg. Remove this parameter from the function.

Signed-off-by: Marek Behun 
---
 drivers/phy/marvell/comphy_a3700.c | 16 +++-
 1 file changed, 3 insertions(+), 13 deletions(-)

diff --git a/drivers/phy/marvell/comphy_a3700.c 
b/drivers/phy/marvell/comphy_a3700.c
index 6506c134e2..d283604e1a 100644
--- a/drivers/phy/marvell/comphy_a3700.c
+++ b/drivers/phy/marvell/comphy_a3700.c
@@ -106,12 +106,11 @@ static u16 sgmii_phy_init[512] = {
  *
  * return: 1 on success, 0 on timeout
  */
-static u32 comphy_poll_reg(void *addr, u32 val, u32 mask, u32 timeout,
-  u8 op_type)
+static u32 comphy_poll_reg(void *addr, u32 val, u32 mask, u8 op_type)
 {
-   u32 rval = 0xDEAD;
+   u32 rval = 0xDEAD, timeout;
 
-   for (; timeout > 0; timeout--) {
+   for (timeout = PLL_LOCK_TIMEOUT; timeout > 0; timeout--) {
if (op_type == POLL_16B_REG)
rval = readw(addr); /* 16 bit */
else
@@ -215,7 +214,6 @@ static int comphy_pcie_power_up(u32 speed, u32 invert)
ret = comphy_poll_reg(PHY_ADDR(PCIE, LANE_STAT1),   /* address */
  rb_txdclk_pclk_en,/* value */
  rb_txdclk_pclk_en,/* mask */
- PLL_LOCK_TIMEOUT, /* timeout */
  POLL_16B_REG);/* 16bit */
if (ret == 0)
printf("Failed to lock PCIe PLL\n");
@@ -285,7 +283,6 @@ static int comphy_sata_power_up(void)
ret = comphy_poll_reg(rh_vsreg_data,/* address */
  bs_pll_ready_tx,  /* value */
  bs_pll_ready_tx,  /* mask */
- PLL_LOCK_TIMEOUT, /* timeout */
  POLL_32B_REG);/* 32bit */
if (ret == 0)
printf("Failed to lock SATA PLL\n");
@@ -414,7 +411,6 @@ static int comphy_usb3_power_up(u32 type, u32 speed, u32 
invert)
ret = comphy_poll_reg(PHY_ADDR(USB3, LANE_STAT1),   /* address */
  rb_txdclk_pclk_en,/* value */
  rb_txdclk_pclk_en,/* mask */
- PLL_LOCK_TIMEOUT, /* timeout */
  POLL_16B_REG);/* 16bit */
if (ret == 0)
printf("Failed to lock USB3 PLL\n");
@@ -495,7 +491,6 @@ static int comphy_usb2_power_up(u8 usb32)
ret = comphy_poll_reg(USB2_PHY_CAL_CTRL_ADDR(usb32),
  rb_usb2phy_pllcal_done,   /* value */
  rb_usb2phy_pllcal_done,   /* mask */
- PLL_LOCK_TIMEOUT, /* timeout */
  POLL_32B_REG);/* 32bit */
if (ret == 0)
printf("Failed to end USB2 PLL calibration\n");
@@ -504,7 +499,6 @@ static int comphy_usb2_power_up(u8 usb32)
ret = comphy_poll_reg(USB2_PHY_CAL_CTRL_ADDR(usb32),
  rb_usb2phy_impcal_done,   /* value */
  rb_usb2phy_impcal_done,   /* mask */
- PLL_LOCK_TIMEOUT, /* timeout */
  POLL_32B_REG);/* 32bit */
if (ret == 0)
printf("Failed to end USB2 impedance calibration\n");
@@ -513,7 +507,6 @@ static int comphy_usb2_power_up(u8 usb32)
ret = comphy_poll_reg(USB2_PHY_RX_CHAN_CTRL1_ADDR(usb32),
  rb_usb2phy_sqcal_done,/* value */
  rb_usb2phy_sqcal_done,/* mask */
- PLL_LOCK_TIMEOUT, /* timeout */
  POLL_32B_REG);/* 32bit */
if (ret == 0)
printf("Failed to end USB2 unknown calibration\n");
@@ -522,7 +515,6 @@ static int comphy_usb2_power_up(u8 usb32)
ret = comphy_poll_reg(USB2_PHY_PLL_CTRL0_ADDR(usb32),
  rb_usb2phy_pll_ready, /* value */
  rb_usb2phy_pll_ready, /* mask */
- PLL_LOCK_TIMEOUT, /* timeout */
  POLL_32B_REG);/* 32bit */
 
if (ret == 0)
@@ -772,7 +764,6 @@ static int comphy_sgmii_power_up(u32 lane, u32 speed, u32 
invert)
ret = comphy_poll_reg(COMPHY_PHY_STAT1_ADDR(lane),  /* address */
  rb_pll_ready_tx | rb_pll_ready_rx, /* value */
  rb_pll_ready_tx | rb_pll_ready_rx, /* mask */
- PLL_LOCK_TIMEOUT, /* timeout */
  POLL_32B_REG);/* 32bit */
if (ret == 0)
printf("Failed to lock PLL for SGMII 

[U-Boot] [PATCH v1 09/19] phy: marvell: a3700: revise the USB3 comphy setting during power on

[Marek Behún]

This commit is based on commit d9899826 by
  zachary 
from u-boot-marvell, see
github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/d9899826

- According to design specification, the transmitter should be set to high
  impedence mode during electrical idle. Thus transmitter should detect RX
  at high impedence mode also, and delay is needed to accommodate high
  impedence off latency. Otherwise the USB3 will have detection issue that
  most of the time the USB3 device can not be detected at all, or be
  detected as USB2 device sometimes.
  Modified registers: RD005C302h (R181h) (0051h) Lane Configuration 1
  Bit 6: set to 1 to let Tx detect Rx at HiZ mode
  Bit [3:4]: set to 2 to be delayed by 2 clock cycles
  Bit 0: set to 1 to set transmitter to high impedance mode during idle.
- USB3 De-emphasize level of -3.5dB is mandatory, but USB3 MAC selects 0x2
  (emphasize disabled) in the MAC_PHY_TXDEEMPH [1:0], while it is supposed
  to select 0x1(3.5dB emphasize). Thus need to override what comes from
  the MAC(by setting register 0x1c2 bit2 to 0x1) and to configure the
  overridded values of MAC_PHY_TXDEEMPH [1:0] to 0x1(bit15 of register
  0x181 and bit0 of register 0x180).
- According to USB3 application note, need to update below comphy
  registers:
  Set max speed generation to USB3.0 5Gbps(set RD005C04Ah bit[11:10] to 1)
  Set capacitor value to 0xF(set RF005C224 bit[3:0] to 0xF)

Signed-off-by: Marek Behun 
---
 drivers/phy/marvell/comphy_a3700.c | 31 +++
 drivers/phy/marvell/comphy_a3700.h |  5 +
 2 files changed, 28 insertions(+), 8 deletions(-)

diff --git a/drivers/phy/marvell/comphy_a3700.c 
b/drivers/phy/marvell/comphy_a3700.c
index 78caa96014..1182842609 100644
--- a/drivers/phy/marvell/comphy_a3700.c
+++ b/drivers/phy/marvell/comphy_a3700.c
@@ -361,13 +361,18 @@ static int comphy_usb3_power_up(u32 lane, u32 type, u32 
speed, u32 invert)
usb3_reg_set16(LANE_CFG0, 0x1, 0xFF);
 
/*
-* unset BIT0: set Tx Electrical Idle Mode: Transmitter is in
-* low impedance mode during electrical idle
-* unset BIT4: set G2 Tx Datapath with no Delayed Latency
-* unset BIT6: set Tx Detect Rx Mode at LoZ mode
-*/
-   usb3_reg_set16(LANE_CFG1, 0x0, 0x);
-
+* Set BIT0: enable transmitter in high impedance mode
+* Set BIT[3:4]: delay 2 clock cycles for HiZ off latency
+* Set BIT6: Tx detect Rx at HiZ mode
+* Unset BIT15: set to 0 to set USB3 De-emphasize level to -3.5db
+*  together with bit 0 of COMPHY_REG_LANE_CFG0_ADDR
+*  register
+*/
+   usb3_reg_set16(LANE_CFG1,
+  tx_det_rx_mode | gen2_tx_data_dly_deft
+  | tx_elec_idle_mode_en,
+  prd_txdeemph1_mask | tx_det_rx_mode
+  | gen2_tx_data_dly_mask | tx_elec_idle_mode_en);
 
/* 0xd005c310 = 0x93: set Spread Spectrum Clock Enabled */
usb3_reg_set16(LANE_CFG4, bf_spread_spectrum_clock_en, 0x80);
@@ -436,7 +441,17 @@ static int comphy_usb3_power_up(u32 lane, u32 type, u32 
speed, u32 invert)
usb3_reg_set16(SYNC_PATTERN, phy_rxd_inv, 0);
 
/*
-* 10. Release SW reset
+* 10. Set max speed generation to USB3.0 5Gbps
+*/
+   usb3_reg_set16(SYNC_MASK_GEN, 0x0400, 0x0C00);
+
+   /*
+* 11. Set capacitor value for FFE gain peaking to 0xF
+*/
+   usb3_reg_set16(GEN3_SETTINGS_3, 0xF, 0xF);
+
+   /*
+* 12. Release SW reset
 */
usb3_reg_set16(GLOB_PHY_CTRL0,
   rb_mode_core_clk_freq_sel | rb_mode_pipe_width_32
diff --git a/drivers/phy/marvell/comphy_a3700.h 
b/drivers/phy/marvell/comphy_a3700.h
index 772e86515a..ef55f719b9 100644
--- a/drivers/phy/marvell/comphy_a3700.h
+++ b/drivers/phy/marvell/comphy_a3700.h
@@ -142,6 +142,11 @@ static inline void __iomem *PHY_ADDR(enum phy_unit unit, 
u32 addr)
 
 #define LANE_CFG1  0x181
 #define bf_use_max_pll_rateBIT(9)
+#define prd_txdeemph1_mask BIT(15)
+#define tx_det_rx_mode BIT(6)
+#define gen2_tx_data_dly_deft  (2 << 3)
+#define gen2_tx_data_dly_mask  (BIT(3) | BIT(4))
+#define tx_elec_idle_mode_en   BIT(0)
 
 #define LANE_CFG4  0x188
 #define bf_spread_spectrum_clock_enBIT(7)
-- 
2.16.1

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[U-Boot] [PATCH v1 12/19] phy: marvell: a3700: Save/restore selector reg in SGMII init

[Marek Behún]

In SGMII initialization PIN_PIPE_SEL has to be zero when resetting
the PHY. Since comphy_mux already set the selector register to
correct values, we have to store it's value before setting it to 0
and restore it after SGMII init.

Signed-off-by: Marek Behun 
---
 drivers/phy/marvell/comphy_a3700.c | 9 -
 drivers/phy/marvell/comphy_a3700.h | 1 -
 2 files changed, 8 insertions(+), 2 deletions(-)

diff --git a/drivers/phy/marvell/comphy_a3700.c 
b/drivers/phy/marvell/comphy_a3700.c
index c665d6fde8..71245b766f 100644
--- a/drivers/phy/marvell/comphy_a3700.c
+++ b/drivers/phy/marvell/comphy_a3700.c
@@ -708,13 +708,15 @@ static void comphy_sgmii_phy_init(u32 lane, u32 speed)
 static int comphy_sgmii_power_up(u32 lane, u32 speed, u32 invert)
 {
int ret;
+   u32 saved_selector;
 
debug_enter();
 
/*
 * 1. Configure PHY to SATA/SAS mode by setting pin PIN_PIPE_SEL=0
 */
-   reg_set(COMPHY_SEL_ADDR, 0, rf_compy_select(lane));
+   saved_selector = readl(COMPHY_SEL_ADDR);
+   reg_set(COMPHY_SEL_ADDR, 0, 0x);
 
/*
 * 2. Reset PHY by setting PHY input port PIN_RESET=1.
@@ -885,6 +887,11 @@ static int comphy_sgmii_power_up(u32 lane, u32 speed, u32 
invert)
if (!ret)
printf("Failed to init RX of SGMII PHY %d\n", lane);
 
+   /*
+* Restore saved selector.
+*/
+   reg_set(COMPHY_SEL_ADDR, saved_selector, 0x);
+
debug_exit();
 
return ret;
diff --git a/drivers/phy/marvell/comphy_a3700.h 
b/drivers/phy/marvell/comphy_a3700.h
index ef55f719b9..b674ef9064 100644
--- a/drivers/phy/marvell/comphy_a3700.h
+++ b/drivers/phy/marvell/comphy_a3700.h
@@ -23,7 +23,6 @@
  * COMPHY SB definitions
  */
 #define COMPHY_SEL_ADDRMVEBU_REG(0x0183FC)
-#define rf_compy_select(lane)  (0x1 << (((lane) == 1) ? 4 : 0))
 
 #define COMPHY_PHY_CFG1_ADDR(lane) MVEBU_REG(0x018300 + (lane) * 0x28)
 #define rb_pin_pu_iveref   BIT(1)
-- 
2.16.1

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[U-Boot] [PATCH v1 05/19] phy: marvell: a3700: Use (!ret) instead of (ret == 0)

[Marek Behún]

Signed-off-by: Marek Behun 
---
 drivers/phy/marvell/comphy_a3700.c | 26 +-
 1 file changed, 13 insertions(+), 13 deletions(-)

diff --git a/drivers/phy/marvell/comphy_a3700.c 
b/drivers/phy/marvell/comphy_a3700.c
index d283604e1a..734d4e55b1 100644
--- a/drivers/phy/marvell/comphy_a3700.c
+++ b/drivers/phy/marvell/comphy_a3700.c
@@ -215,7 +215,7 @@ static int comphy_pcie_power_up(u32 speed, u32 invert)
  rb_txdclk_pclk_en,/* value */
  rb_txdclk_pclk_en,/* mask */
  POLL_16B_REG);/* 16bit */
-   if (ret == 0)
+   if (!ret)
printf("Failed to lock PCIe PLL\n");
 
debug_exit();
@@ -284,7 +284,7 @@ static int comphy_sata_power_up(void)
  bs_pll_ready_tx,  /* value */
  bs_pll_ready_tx,  /* mask */
  POLL_32B_REG);/* 32bit */
-   if (ret == 0)
+   if (!ret)
printf("Failed to lock SATA PLL\n");
 
debug_exit();
@@ -412,7 +412,7 @@ static int comphy_usb3_power_up(u32 type, u32 speed, u32 
invert)
  rb_txdclk_pclk_en,/* value */
  rb_txdclk_pclk_en,/* mask */
  POLL_16B_REG);/* 16bit */
-   if (ret == 0)
+   if (!ret)
printf("Failed to lock USB3 PLL\n");
 
/*
@@ -492,7 +492,7 @@ static int comphy_usb2_power_up(u8 usb32)
  rb_usb2phy_pllcal_done,   /* value */
  rb_usb2phy_pllcal_done,   /* mask */
  POLL_32B_REG);/* 32bit */
-   if (ret == 0)
+   if (!ret)
printf("Failed to end USB2 PLL calibration\n");
 
/* Assert impedance calibration done */
@@ -500,7 +500,7 @@ static int comphy_usb2_power_up(u8 usb32)
  rb_usb2phy_impcal_done,   /* value */
  rb_usb2phy_impcal_done,   /* mask */
  POLL_32B_REG);/* 32bit */
-   if (ret == 0)
+   if (!ret)
printf("Failed to end USB2 impedance calibration\n");
 
/* Assert squetch calibration done */
@@ -508,7 +508,7 @@ static int comphy_usb2_power_up(u8 usb32)
  rb_usb2phy_sqcal_done,/* value */
  rb_usb2phy_sqcal_done,/* mask */
  POLL_32B_REG);/* 32bit */
-   if (ret == 0)
+   if (!ret)
printf("Failed to end USB2 unknown calibration\n");
 
/* Assert PLL is ready */
@@ -517,7 +517,7 @@ static int comphy_usb2_power_up(u8 usb32)
  rb_usb2phy_pll_ready, /* mask */
  POLL_32B_REG);/* 32bit */
 
-   if (ret == 0)
+   if (!ret)
printf("Failed to lock USB2 PLL\n");
 
debug_exit();
@@ -765,7 +765,7 @@ static int comphy_sgmii_power_up(u32 lane, u32 speed, u32 
invert)
  rb_pll_ready_tx | rb_pll_ready_rx, /* value */
  rb_pll_ready_tx | rb_pll_ready_rx, /* mask */
  POLL_32B_REG);/* 32bit */
-   if (ret == 0)
+   if (!ret)
printf("Failed to lock PLL for SGMII PHY %d\n", lane);
 
/*
@@ -787,7 +787,7 @@ static int comphy_sgmii_power_up(u32 lane, u32 speed, u32 
invert)
  rb_rx_init_done,  /* value */
  rb_rx_init_done,  /* mask */
  POLL_32B_REG);/* 32bit */
-   if (ret == 0)
+   if (!ret)
printf("Failed to init RX of SGMII PHY %d\n", lane);
 
debug_exit();
@@ -818,7 +818,7 @@ void comphy_dedicated_phys_init(void)
if (node > 0) {
if (fdtdec_get_is_enabled(blob, node)) {
ret = comphy_usb2_power_up(usb32);
-   if (ret == 0)
+   if (!ret)
printf("Failed to initialize UTMI 
PHY\n");
else
debug("UTMI PHY init succeed\n");
@@ -836,7 +836,7 @@ void comphy_dedicated_phys_init(void)
if (node > 0) {
if (fdtdec_get_is_enabled(blob, node)) {
ret = comphy_sata_power_up();
-   if (ret == 0)
+   if (!ret)
printf("Failed to initialize SATA PHY\n");
else
debug("SATA PHY init succeed\n");
@@ -857,7 +857,7 @@ void 

[U-Boot] [PATCH v1 07/19] phy: marvell: a3700: Access USB3 register indirectly on lane 2

[Marek Behún]

When USB3 is on comphy lane 2 on the Armada 37xx, the registers
have to be accessed indirectly via SATA indirect access.

Signed-off-by: Marek Behun 
---
 drivers/phy/marvell/comphy_a3700.c | 111 +
 drivers/phy/marvell/comphy_a3700.h |   1 +
 2 files changed, 78 insertions(+), 34 deletions(-)

diff --git a/drivers/phy/marvell/comphy_a3700.c 
b/drivers/phy/marvell/comphy_a3700.c
index 81d24a5b61..b5f2013bbb 100644
--- a/drivers/phy/marvell/comphy_a3700.c
+++ b/drivers/phy/marvell/comphy_a3700.c
@@ -133,7 +133,7 @@ static u32 comphy_poll_reg(void *addr, u32 val, u32 mask, 
u8 op_type)
  */
 static int comphy_pcie_power_up(u32 speed, u32 invert)
 {
-   int ret;
+   int ret;
 
debug_enter();
 
@@ -300,17 +300,50 @@ static int comphy_sata_power_up(void)
return ret;
 }
 
+/*
+ * usb3_reg_set16_indirect
+ *
+ * return: void
+ */
+static void usb3_reg_set16_indirect(u32 reg, u16 data, u16 mask)
+{
+   reg_set_indirect(USB3PHY_LANE2_REG_BASE_OFFSET + reg, data, mask);
+}
+
+/*
+ * usb3_reg_set16_direct
+ *
+ * return: void
+ */
+static void usb3_reg_set16_direct(u32 reg, u16 data, u16 mask)
+{
+   reg_set16(PHY_ADDR(USB3, reg), data, mask);
+}
+
 /*
  * comphy_usb3_power_up
  *
  * return: 1 if PLL locked (OK), 0 otherwise (FAIL)
  */
-static int comphy_usb3_power_up(u32 type, u32 speed, u32 invert)
+static int comphy_usb3_power_up(u32 lane, u32 type, u32 speed, u32 invert)
 {
-   int ret;
+   int ret;
+   void (*usb3_reg_set16)(u32, u16, u16);
 
debug_enter();
 
+   /*
+* When Lane 2 PHY is for USB3, access the PHY registers
+* through indirect Address and Data registers INDIR_ACC_PHY_ADDR
+* (RD00E0178h [31:0]) and INDIR_ACC_PHY_DATA (RD00E017Ch [31:0])
+* within the SATA Host Controller registers, Lane 2 base register
+* offset is 0x200
+*/
+   if (lane == 2)
+   usb3_reg_set16 = usb3_reg_set16_indirect;
+   else
+   usb3_reg_set16 = usb3_reg_set16_direct;
+
/*
 * 1. Power up OTG module
 */
@@ -325,38 +358,38 @@ static int comphy_usb3_power_up(u32 type, u32 speed, u32 
invert)
 
/* 0xd005c300 = 0x1001 */
/* set PRD_TXDEEMPH (3.5db de-emph) */
-   reg_set16(PHY_ADDR(USB3, LANE_CFG0), 0x1, 0xFF);
+   usb3_reg_set16(LANE_CFG0, 0x1, 0xFF);
 
/*
 * unset BIT0: set Tx Electrical Idle Mode: Transmitter is in
-* low impedance mode during electrical idle
+* low impedance mode during electrical idle
+* unset BIT4: set G2 Tx Datapath with no Delayed Latency
+* unset BIT6: set Tx Detect Rx Mode at LoZ mode
 */
-   /* unset BIT4: set G2 Tx Datapath with no Delayed Latency */
-   /* unset BIT6: set Tx Detect Rx Mode at LoZ mode */
-   reg_set16(PHY_ADDR(USB3, LANE_CFG1), 0x0, 0x);
+   usb3_reg_set16(LANE_CFG1, 0x0, 0x);
 
 
-   /* 0xd005c310 = 0x93: set Spread Spectrum Clock Enabled  */
-   reg_set16(PHY_ADDR(USB3, LANE_CFG4), bf_spread_spectrum_clock_en, 0x80);
+   /* 0xd005c310 = 0x93: set Spread Spectrum Clock Enabled */
+   usb3_reg_set16(LANE_CFG4, bf_spread_spectrum_clock_en, 0x80);
 
/*
 * set Override Margining Controls From the MAC: Use margining signals
 * from lane configuration
 */
-   reg_set16(PHY_ADDR(USB3, TEST_MODE_CTRL), rb_mode_margin_override, 
0x);
+   usb3_reg_set16(TEST_MODE_CTRL, rb_mode_margin_override, 0x);
 
/* set Lane-to-Lane Bundle Clock Sampling Period = per PCLK cycles */
/* set Mode Clock Source = PCLK is generated from REFCLK */
-   reg_set16(PHY_ADDR(USB3, GLOB_CLK_SRC_LO), 0x0, 0xFF);
+   usb3_reg_set16(GLOB_CLK_SRC_LO, 0x0, 0xFF);
 
/* set G2 Spread Spectrum Clock Amplitude at 4K */
-   reg_set16(PHY_ADDR(USB3, GEN2_SETTINGS_2), g2_tx_ssc_amp, 0xF000);
+   usb3_reg_set16(GEN2_SETTINGS_2, g2_tx_ssc_amp, 0xF000);
 
/*
 * unset G3 Spread Spectrum Clock Amplitude & set G3 TX and RX Register
 * Master Current Select
 */
-   reg_set16(PHY_ADDR(USB3, GEN2_SETTINGS_3), 0x0, 0x);
+   usb3_reg_set16(GEN2_SETTINGS_3, 0x0, 0x);
 
/*
 * 3. Check crystal jumper setting and program the Power and PLL
@@ -364,62 +397,71 @@ static int comphy_usb3_power_up(u32 type, u32 speed, u32 
invert)
 */
if (get_ref_clk() == 40) {
/* 40 MHz */
-   reg_set16(PHY_ADDR(USB3, PWR_PLL_CTRL), 0xFCA3, 0x);
+   usb3_reg_set16(PWR_PLL_CTRL, 0xFCA3, 0x);
} else {
/* 25 MHz */
-   reg_set16(PHY_ADDR(USB3, PWR_PLL_CTRL), 0xFCA2, 0x);
+   usb3_reg_set16(PWR_PLL_CTRL, 0xFCA2, 0x);
}
 
/*
 * 4. Change RX wait
 */
-   reg_set16(PHY_ADDR(USB3, PWR_MGM_TIM1), 0x10C, 0x);
+   

[U-Boot] [PATCH v1 02/19] phy: marvell: a3700: Use reg_set16 instead of phy_write16

[Marek Behún]

The macro phy_write16 is not used by the rest of the code,
phy_read16 is not used at all.
We also change the macro SGMIIPHY_ADDR to a static inline function.

Signed-off-by: Marek Behun 
---
 drivers/phy/marvell/comphy_a3700.c | 22 +++---
 drivers/phy/marvell/comphy_a3700.h | 15 ---
 2 files changed, 19 insertions(+), 18 deletions(-)

diff --git a/drivers/phy/marvell/comphy_a3700.c 
b/drivers/phy/marvell/comphy_a3700.c
index 8285b8b107..505e0933a3 100644
--- a/drivers/phy/marvell/comphy_a3700.c
+++ b/drivers/phy/marvell/comphy_a3700.c
@@ -610,7 +610,7 @@ static void comphy_sgmii_phy_init(u32 lane, u32 speed)
val = sgmii_phy_init[addr];
}
 
-   phy_write16(lane, addr, val, 0x);
+   reg_set16(SGMIIPHY_ADDR(lane, addr), val, 0x);
}
 }
 
@@ -673,26 +673,26 @@ static int comphy_sgmii_power_up(u32 lane, u32 speed, u32 
invert)
mdelay(10);
 
/* 9. Program COMPHY register PHY_MODE */
-   phy_write16(lane, PHY_PWR_PLL_CTRL_ADDR,
-   PHY_MODE_SGMII << rf_phy_mode_shift, rf_phy_mode_mask);
+   reg_set16(SGMIIPHY_ADDR(lane, PHY_PWR_PLL_CTRL_ADDR),
+ PHY_MODE_SGMII << rf_phy_mode_shift, rf_phy_mode_mask);
 
/*
 * 10. Set COMPHY register REFCLK_SEL to select the correct REFCLK
 * source
 */
-   phy_write16(lane, PHY_MISC_REG0_ADDR, 0, rb_ref_clk_sel);
+   reg_set16(SGMIIPHY_ADDR(lane, PHY_MISC_REG0_ADDR), 0, rb_ref_clk_sel);
 
/*
 * 11. Set correct reference clock frequency in COMPHY register
 * REF_FREF_SEL.
 */
if (get_ref_clk() == 40) {
-   phy_write16(lane, PHY_PWR_PLL_CTRL_ADDR,
-   0x4 << rf_ref_freq_sel_shift, rf_ref_freq_sel_mask);
+   reg_set16(SGMIIPHY_ADDR(lane, PHY_PWR_PLL_CTRL_ADDR),
+ 0x4 << rf_ref_freq_sel_shift, rf_ref_freq_sel_mask);
} else {
/* 25MHz */
-   phy_write16(lane, PHY_PWR_PLL_CTRL_ADDR,
-   0x1 << rf_ref_freq_sel_shift, rf_ref_freq_sel_mask);
+   reg_set16(SGMIIPHY_ADDR(lane, PHY_PWR_PLL_CTRL_ADDR),
+ 0x1 << rf_ref_freq_sel_shift, rf_ref_freq_sel_mask);
}
 
/* 12. Program COMPHY register PHY_GEN_MAX[1:0] */
@@ -708,7 +708,7 @@ static int comphy_sgmii_power_up(u32 lane, u32 speed, u32 
invert)
 * bus width
 */
/* 10bit */
-   phy_write16(lane, PHY_DIG_LB_EN_ADDR, 0, rf_data_width_mask);
+   reg_set16(SGMIIPHY_ADDR(lane, PHY_DIG_LB_EN_ADDR), 0, 
rf_data_width_mask);
 
/*
 * 14. As long as DFE function needs to be enabled in any mode,
@@ -751,10 +751,10 @@ static int comphy_sgmii_power_up(u32 lane, u32 speed, u32 
invert)
 * 18. Check the PHY Polarity invert bit
 */
if (invert & PHY_POLARITY_TXD_INVERT)
-   phy_write16(lane, PHY_SYNC_PATTERN_ADDR, phy_txd_inv, 0);
+   reg_set16(SGMIIPHY_ADDR(lane, PHY_SYNC_PATTERN_ADDR), 
phy_txd_inv, 0);
 
if (invert & PHY_POLARITY_RXD_INVERT)
-   phy_write16(lane, PHY_SYNC_PATTERN_ADDR, phy_rxd_inv, 0);
+   reg_set16(SGMIIPHY_ADDR(lane, PHY_SYNC_PATTERN_ADDR), 
phy_rxd_inv, 0);
 
/*
 * 19. Set PHY input ports PIN_PU_PLL, PIN_PU_TX and PIN_PU_RX to 1
diff --git a/drivers/phy/marvell/comphy_a3700.h 
b/drivers/phy/marvell/comphy_a3700.h
index f993ad9c84..a315bf2647 100644
--- a/drivers/phy/marvell/comphy_a3700.h
+++ b/drivers/phy/marvell/comphy_a3700.h
@@ -61,13 +61,14 @@
 #define USB32_CTRL_BASEMVEBU_REG(0x05D800)
 #define USB3PHY_SHFT   2
 
-#define SGMIIPHY_BASE(l)   (l == 1 ? USB3PHY_BASE : PCIEPHY_BASE)
-#define SGMIIPHY_ADDR(l, a)\
-   ((void __iomem *) (((a & 0x7FF) * 2) + SGMIIPHY_BASE(l)))
-
-#define phy_read16(l, a)   read16((void __iomem *)SGMIIPHY_ADDR(l, a))
-#define phy_write16(l, a, data, mask)  \
-   reg_set16(SGMIIPHY_ADDR(l, a), data, mask)
+static inline void __iomem *SGMIIPHY_ADDR(u32 lane, u32 addr)
+{
+   addr = (addr & 0x7FF) * 2;
+   if (lane == 1)
+   return USB3PHY_BASE + addr;
+   else
+   return PCIEPHY_BASE + addr;
+}
 
 /* units */
 #define PCIE   1
-- 
2.16.1

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[U-Boot] [PATCH v1 06/19] phy: marvell: a3700: Use reg_set_indirect istead of 2 reg_sets

[Marek Behún]

Create a special function for indirect register setting,
reg_set_indirect, and use it instead of the two calls to reg_set.

Signed-off-by: Marek Behun 
---
 drivers/phy/marvell/comphy_a3700.c | 32 
 1 file changed, 20 insertions(+), 12 deletions(-)

diff --git a/drivers/phy/marvell/comphy_a3700.c 
b/drivers/phy/marvell/comphy_a3700.c
index 734d4e55b1..81d24a5b61 100644
--- a/drivers/phy/marvell/comphy_a3700.c
+++ b/drivers/phy/marvell/comphy_a3700.c
@@ -224,6 +224,17 @@ static int comphy_pcie_power_up(u32 speed, u32 invert)
return ret;
 }
 
+/*
+ * reg_set_indirect
+ *
+ * return: void
+ */
+static inline void reg_set_indirect(u32 reg, u16 data, u16 mask)
+{
+   reg_set(rh_vsreg_addr, reg, 0x);
+   reg_set(rh_vsreg_data, data, mask);
+}
+
 /*
  * comphy_sata_power_up
  *
@@ -231,43 +242,40 @@ static int comphy_pcie_power_up(u32 speed, u32 invert)
  */
 static int comphy_sata_power_up(void)
 {
-   int ret;
+   int ret;
 
debug_enter();
 
/*
 * 0. Swap SATA TX lines
 */
-   reg_set(rh_vsreg_addr, vphy_sync_pattern_reg, 0x);
-   reg_set(rh_vsreg_data, bs_txd_inv, bs_txd_inv);
+   reg_set_indirect(vphy_sync_pattern_reg, bs_txd_inv, bs_txd_inv);
 
/*
 * 1. Select 40-bit data width width
 */
-   reg_set(rh_vsreg_addr, vphy_loopback_reg0, 0x);
-   reg_set(rh_vsreg_data, 0x800, bs_phyintf_40bit);
+   reg_set_indirect(vphy_loopback_reg0, 0x800, bs_phyintf_40bit);
 
/*
 * 2. Select reference clock and PHY mode (SATA)
 */
-   reg_set(rh_vsreg_addr, vphy_power_reg0, 0x);
if (get_ref_clk() == 40) {
-   reg_set(rh_vsreg_data, 0x3, 0x00FF); /* 40 MHz */
+   /* 40 MHz */
+   reg_set_indirect(vphy_power_reg0, 0x3, 0x00FF);
} else {
-   reg_set(rh_vsreg_data, 0x1, 0x00FF); /* 25 MHz */
+   /* 20 MHz */
+   reg_set_indirect(vphy_power_reg0, 0x1, 0x00FF);
}
 
/*
 * 3. Use maximum PLL rate (no power save)
 */
-   reg_set(rh_vsreg_addr, vphy_calctl_reg, 0x);
-   reg_set(rh_vsreg_data, bs_max_pll_rate, bs_max_pll_rate);
+   reg_set_indirect(vphy_calctl_reg, bs_max_pll_rate, bs_max_pll_rate);
 
/*
 * 4. Reset reserved bit (??)
 */
-   reg_set(rh_vsreg_addr, vphy_reserve_reg, 0x);
-   reg_set(rh_vsreg_data, 0, bs_phyctrl_frm_pin);
+   reg_set_indirect(vphy_reserve_reg, 0, bs_phyctrl_frm_pin);
 
/*
 * 5. Set vendor-specific configuration (??)
-- 
2.16.1

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[U-Boot] [PATCH v1 01/19] phy: marvell: a3700: Change return type of macro MVEBU_REG

[Marek Behún]

All the calls to reg_set and friends have to cast the first argument
to void __iomem *. Lets change the return type of the MVEBU_REG macro
instead.

Signed-off-by: Marek Behun 
---
 drivers/phy/marvell/comphy_a3700.c | 205 -
 drivers/phy/marvell/comphy_a3700.h |   8 +-
 2 files changed, 95 insertions(+), 118 deletions(-)

diff --git a/drivers/phy/marvell/comphy_a3700.c 
b/drivers/phy/marvell/comphy_a3700.c
index 5afd23c052..8285b8b107 100644
--- a/drivers/phy/marvell/comphy_a3700.c
+++ b/drivers/phy/marvell/comphy_a3700.c
@@ -141,78 +141,72 @@ static int comphy_pcie_power_up(u32 speed, u32 invert)
/*
 * 1. Enable max PLL.
 */
-   reg_set16((void __iomem *)LANE_CFG1_ADDR(PCIE),
- bf_use_max_pll_rate, 0);
+   reg_set16(LANE_CFG1_ADDR(PCIE), bf_use_max_pll_rate, 0);
 
/*
 * 2. Select 20 bit SERDES interface.
 */
-   reg_set16((void __iomem *)GLOB_CLK_SRC_LO_ADDR(PCIE),
- bf_cfg_sel_20b, 0);
+   reg_set16(GLOB_CLK_SRC_LO_ADDR(PCIE), bf_cfg_sel_20b, 0);
 
/*
 * 3. Force to use reg setting for PCIe mode
 */
-   reg_set16((void __iomem *)MISC_REG1_ADDR(PCIE),
- bf_sel_bits_pcie_force, 0);
+   reg_set16(MISC_REG1_ADDR(PCIE), bf_sel_bits_pcie_force, 0);
 
/*
 * 4. Change RX wait
 */
-   reg_set16((void __iomem *)PWR_MGM_TIM1_ADDR(PCIE), 0x10C, 0x);
+   reg_set16(PWR_MGM_TIM1_ADDR(PCIE), 0x10C, 0x);
 
/*
 * 5. Enable idle sync
 */
-   reg_set16((void __iomem *)UNIT_CTRL_ADDR(PCIE),
- 0x60 | rb_idle_sync_en, 0x);
+   reg_set16(UNIT_CTRL_ADDR(PCIE), 0x60 | rb_idle_sync_en, 0x);
 
/*
 * 6. Enable the output of 100M/125M/500M clock
 */
-   reg_set16((void __iomem *)MISC_REG0_ADDR(PCIE),
+   reg_set16(MISC_REG0_ADDR(PCIE),
  0xA00D | rb_clk500m_en | rb_clk100m_125m_en, 0x);
 
/*
 * 7. Enable TX
 */
-   reg_set((void __iomem *)PHY_REF_CLK_ADDR, 0x1342, 0x);
+   reg_set(PHY_REF_CLK_ADDR, 0x1342, 0x);
 
/*
 * 8. Check crystal jumper setting and program the Power and PLL
 *Control accordingly
 */
if (get_ref_clk() == 40) {
-   reg_set16((void __iomem *)PWR_PLL_CTRL_ADDR(PCIE),
+   reg_set16(PWR_PLL_CTRL_ADDR(PCIE),
  0xFC63, 0x); /* 40 MHz */
} else {
-   reg_set16((void __iomem *)PWR_PLL_CTRL_ADDR(PCIE),
+   reg_set16(PWR_PLL_CTRL_ADDR(PCIE),
  0xFC62, 0x); /* 25 MHz */
}
 
/*
 * 9. Override Speed_PLL value and use MAC PLL
 */
-   reg_set16((void __iomem *)KVCO_CAL_CTRL_ADDR(PCIE),
- 0x0040 | rb_use_max_pll_rate, 0x);
+   reg_set16(KVCO_CAL_CTRL_ADDR(PCIE), 0x0040 | rb_use_max_pll_rate,
+ 0x);
 
/*
 * 10. Check the Polarity invert bit
 */
if (invert & PHY_POLARITY_TXD_INVERT) {
-   reg_set16((void __iomem *)SYNC_PATTERN_ADDR(PCIE),
- phy_txd_inv, 0);
+   reg_set16(SYNC_PATTERN_ADDR(PCIE), phy_txd_inv, 0);
}
 
if (invert & PHY_POLARITY_RXD_INVERT) {
-   reg_set16((void __iomem *)SYNC_PATTERN_ADDR(PCIE),
- phy_rxd_inv, 0);
+   reg_set16(SYNC_PATTERN_ADDR(PCIE), phy_rxd_inv, 0);
}
 
/*
 * 11. Release SW reset
 */
-   reg_set16((void __iomem *)GLOB_PHY_CTRL0_ADDR(PCIE),
+   reg_set16(GLOB_PHY_CTRL0_ADDR(PCIE),
  rb_mode_core_clk_freq_sel | rb_mode_pipe_width_32,
  bf_soft_rst | bf_mode_refdiv);
 
@@ -220,11 +214,11 @@ static int comphy_pcie_power_up(u32 speed, u32 invert)
udelay(PLL_SET_DELAY_US);
 
/* Assert PCLK enabled */
-   ret = comphy_poll_reg((void *)LANE_STAT1_ADDR(PCIE),/* address */
- rb_txdclk_pclk_en,/* value */
- rb_txdclk_pclk_en,/* mask */
- PLL_LOCK_TIMEOUT, /* timeout */
- POLL_16B_REG);/* 16bit */
+   ret = comphy_poll_reg(LANE_STAT1_ADDR(PCIE),/* address */
+ rb_txdclk_pclk_en,/* value */
+ rb_txdclk_pclk_en,/* mask */
+ PLL_LOCK_TIMEOUT, /* timeout */
+ POLL_16B_REG);/* 16bit */
if (ret == 0)
printf("Failed to lock PCIe PLL\n");
 
@@ -248,57 +242,53 @@ static int comphy_sata_power_up(void)
/*
 * 0. Swap SATA TX lines
 */
-   reg_set((void __iomem *)rh_vsreg_addr,
-   

[U-Boot] [PATCH v1 00/19] More support for Armada 37xx boards

[Marek Behún]

This is a series of patches to update the support of Armada 37xx devices.

Summary:
  - patches 1-6 are cosmetic patches for the Armada 37xx comphy driver
  - the 7th patch adds support for USB3 on comphy lane 2, which needs indirect
register access
  - patches 8-9 change USB3 phy initialization according to u-boot-marvell
changes
  - the 10th patch adds support for nontrivial order of nodes in the pin
selector register in comphy_mux (on Armada 37xx the first two lanes
are switched in the selector register)
  - the 11th patch adds the mux support for Armada 37xx comphy driver
  - the 12th patch is a workaround for SGMII initialization, which needs to
change the pin selector register temporarily (while resetting the phy)
  - the 13th patch changes defconfigs to enable Armada 37xx pinctrl driver
by default and removes the board_early_init_f for those board, which
contained a temporary solution to not having the pinctrl driver
  - the 14th patch add support for TBG and peripheral clocks on Armada 37xx
  - the 15th patch changes the Armada 37xx SPI driver to use the clock driver
  - the 16th patch adds support for clk dump command
  - the 17th patch fixed the pinctrl driver according to new revision of the
specification
  - the 18th patch contains some more cosmetic fixes, this time for comphy_core
  - the 19th patch fixes a bug in the mvneta driver which can occur on invalid
property name in device tree

Signed-off-by: Marek Behun 

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Re: [U-Boot] [PATCH v5 08/15] net: add support for bcm6348-enet

[Joe Hershberger]

On Mon, Mar 5, 2018 at 2:05 PM, Álvaro Fernández Rojas
 wrote:
> Signed-off-by: Álvaro Fernández Rojas 
> ---
>  v5: Receive as much packets as possible from bcm6348-eth and cache them in
>  net_rx_packets. This is needed in order to fix flow control issues.
>  v4: Fix issues reported by Grygorii Strashko and other fixes:
>   - Copy received dma buffer to net_rx_packets in order to avoid possible
>   dma overwrites.
>   - Reset dma rx channel when sending a new packet to prevent flow control
>   issues.
>   - Fix packet casting on bcm6348_eth_recv/send.
>  v3: no changes
>  v2: select DMA_CHANNELS.
>
>  drivers/net/Kconfig|  10 +
>  drivers/net/Makefile   |   1 +
>  drivers/net/bcm6348-eth.c  | 575 
> +
>  include/configs/bmips_common.h |   5 +-
>  4 files changed, 590 insertions(+), 1 deletion(-)
>  create mode 100644 drivers/net/bcm6348-eth.c
>
> diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
> index de1947ccc1..e532332d78 100644
> --- a/drivers/net/Kconfig
> +++ b/drivers/net/Kconfig
> @@ -71,6 +71,16 @@ config BCM_SF2_ETH_GMAC
>   by the BCM_SF2_ETH driver.
>   Say Y to any bcmcygnus based platforms.
>
> +config BCM6348_ETH
> +   bool "BCM6348 EMAC support"
> +   depends on DM_ETH && ARCH_BMIPS
> +   select DMA
> +   select DMA_CHANNELS
> +   select MII
> +   select PHYLIB
> +   help
> + This driver supports the BCM6348 Ethernet MAC.
> +
>  config DWC_ETH_QOS
> bool "Synopsys DWC Ethernet QOS device support"
> depends on DM_ETH
> diff --git a/drivers/net/Makefile b/drivers/net/Makefile
> index ac5443c752..282adbc775 100644
> --- a/drivers/net/Makefile
> +++ b/drivers/net/Makefile
> @@ -8,6 +8,7 @@
>  obj-$(CONFIG_ALTERA_TSE) += altera_tse.o
>  obj-$(CONFIG_AG7XXX) += ag7xxx.o
>  obj-$(CONFIG_ARMADA100_FEC) += armada100_fec.o
> +obj-$(CONFIG_BCM6348_ETH) += bcm6348-eth.o
>  obj-$(CONFIG_DRIVER_AT91EMAC) += at91_emac.o
>  obj-$(CONFIG_DRIVER_AX88180) += ax88180.o
>  obj-$(CONFIG_BCM_SF2_ETH) += bcm-sf2-eth.o
> diff --git a/drivers/net/bcm6348-eth.c b/drivers/net/bcm6348-eth.c
> new file mode 100644
> index 00..43518f7b2d
> --- /dev/null
> +++ b/drivers/net/bcm6348-eth.c
> @@ -0,0 +1,575 @@
> +/*
> + * Copyright (C) 2018 Álvaro Fernández Rojas 
> + *
> + * Derived from linux/drivers/net/ethernet/broadcom/bcm63xx_enet.c:
> + * Copyright (C) 2008 Maxime Bizon 
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +#define ETH_RX_DESCPKTBUFSRX
> +#define ETH_MAX_MTU_SIZE   1518
> +#define ETH_TIMEOUT100
> +#define ETH_TX_WATERMARK   32
> +
> +/* ETH Receiver Configuration register */
> +#define ETH_RXCFG_REG  0x00
> +#define ETH_RXCFG_ENFLOW_SHIFT 5
> +#define ETH_RXCFG_ENFLOW_MASK  (1 << ETH_RXCFG_ENFLOW_SHIFT)
> +
> +/* ETH Receive Maximum Length register */
> +#define ETH_RXMAXLEN_REG   0x04
> +#define ETH_RXMAXLEN_SHIFT 0
> +#define ETH_RXMAXLEN_MASK  (0x7ff << ETH_RXMAXLEN_SHIFT)
> +
> +/* ETH Transmit Maximum Length register */
> +#define ETH_TXMAXLEN_REG   0x08
> +#define ETH_TXMAXLEN_SHIFT 0
> +#define ETH_TXMAXLEN_MASK  (0x7ff << ETH_TXMAXLEN_SHIFT)
> +
> +/* MII Status/Control register */
> +#define MII_SC_REG 0x10
> +#define MII_SC_MDCFREQDIV_SHIFT0
> +#define MII_SC_MDCFREQDIV_MASK (0x7f << MII_SC_MDCFREQDIV_SHIFT)
> +#define MII_SC_PREAMBLE_EN_SHIFT   7
> +#define MII_SC_PREAMBLE_EN_MASK(1 << 
> MII_SC_PREAMBLE_EN_SHIFT)
> +
> +/* MII Data register */
> +#define MII_DAT_REG0x14
> +#define MII_DAT_DATA_SHIFT 0
> +#define MII_DAT_DATA_MASK  (0x << MII_DAT_DATA_SHIFT)
> +#define MII_DAT_TA_SHIFT   16
> +#define MII_DAT_TA_MASK(0x3 << MII_DAT_TA_SHIFT)
> +#define MII_DAT_REG_SHIFT  18
> +#define MII_DAT_REG_MASK   (0x1f << MII_DAT_REG_SHIFT)
> +#define MII_DAT_PHY_SHIFT  23
> +#define MII_DAT_PHY_MASK   (0x1f << MII_DAT_PHY_SHIFT)
> +#define MII_DAT_OP_SHIFT   28
> +#define MII_DAT_OP_WRITE   (0x5 << MII_DAT_OP_SHIFT)
> +#define MII_DAT_OP_READ(0x6 << MII_DAT_OP_SHIFT)
> +
> +/* ETH Interrupts Mask register */
> +#define ETH_IRMASK_REG 0x18
> +
> +/* ETH Interrupts register */
> +#define ETH_IR_REG 0x1c
> +#define ETH_IR_MII_SHIFT   0
> +#define ETH_IR_MII_MASK(1 << ETH_IR_MII_SHIFT)
> +
> +/* ETH Control register */
> +#define ETH_CTL_REG0x2c

Re: [U-Boot] [PATCH v5 02/15] dma: add channels support

[Joe Hershberger]

On Mon, Mar 5, 2018 at 2:05 PM, Álvaro Fernández Rojas
 wrote:
> This adds channels support for dma controllers that have multiple channels
> which can transfer data to/from different devices (enet, usb...).
>
> Signed-off-by: Álvaro Fernández Rojas 
> Reviewed-by: Simon Glass 
> ---
>  v5: remove unneeded dma.h include
>  v4: no changes
>  v3: Introduce changes reported by Simon Glass:
>   - Improve dma-uclass.h documentation.
>   - Switch to live tree API.
>
>  drivers/dma/Kconfig  |   7 ++
>  drivers/dma/dma-uclass.c | 188 
> +--
>  include/dma-uclass.h |  78 
>  include/dma.h| 174 ++-
>  4 files changed, 439 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
> index 1b92c7789d..21b2c0dcaa 100644
> --- a/drivers/dma/Kconfig
> +++ b/drivers/dma/Kconfig
> @@ -12,6 +12,13 @@ config DMA
>   buses that is used to transfer data to and from memory.
>   The uclass interface is defined in include/dma.h.
>
> +config DMA_CHANNELS
> +   bool "Enable DMA channels support"
> +   depends on DMA
> +   help
> + Enable channels support for DMA. Some DMA controllers have multiple
> + channels which can either transfer data to/from different devices.
> +
>  config TI_EDMA3
> bool "TI EDMA3 driver"
> help
> diff --git a/drivers/dma/dma-uclass.c b/drivers/dma/dma-uclass.c
> index faa27a3a56..b5109aafc9 100644
> --- a/drivers/dma/dma-uclass.c
> +++ b/drivers/dma/dma-uclass.c
> @@ -1,23 +1,199 @@
>  /*
>   * Direct Memory Access U-Class driver
>   *
> - * (C) Copyright 2015
> - * Texas Instruments Incorporated, 
> - *
> - * Author: Mugunthan V N 
> + * Copyright (C) 2018 Álvaro Fernández Rojas 
> + * Copyright (C) 2015 Texas Instruments Incorporated 
> + * Written by Mugunthan V N 
>   *
>   * SPDX-License-Identifier: GPL-2.0+
>   */
>
>  #include 
>  #include 
> -#include 
> -#include 
> +#include 
>  #include 
> +#include 
>  #include 
>
>  DECLARE_GLOBAL_DATA_PTR;
>
> +#ifdef CONFIG_DMA_CHANNELS
> +static inline struct dma_ops *dma_dev_ops(struct udevice *dev)
> +{
> +   return (struct dma_ops *)dev->driver->ops;
> +}
> +
> +# if CONFIG_IS_ENABLED(OF_CONTROL)
> +#  if CONFIG_IS_ENABLED(OF_PLATDATA)
> +int dma_get_by_index_platdata(struct udevice *dev, int index,
> + struct phandle_1_arg *cells, struct dma *dma)
> +{
> +   int ret;
> +
> +   if (index != 0)
> +   return -ENOSYS;
> +   ret = uclass_get_device(UCLASS_DMA, 0, >dev);
> +   if (ret)
> +   return ret;
> +   dma->id = cells[0].id;
> +
> +   return 0;
> +}
> +#  else
> +static int dma_of_xlate_default(struct dma *dma,
> +   struct ofnode_phandle_args *args)
> +{
> +   debug("%s(dma=%p)\n", __func__, dma);
> +
> +   if (args->args_count > 1) {
> +   pr_err("Invaild args_count: %d\n", args->args_count);
> +   return -EINVAL;
> +   }
> +
> +   if (args->args_count)
> +   dma->id = args->args[0];
> +   else
> +   dma->id = 0;
> +
> +   return 0;
> +}
> +
> +int dma_get_by_index(struct udevice *dev, int index, struct dma *dma)
> +{
> +   int ret;
> +   struct ofnode_phandle_args args;
> +   struct udevice *dev_dma;
> +   const struct dma_ops *ops;
> +
> +   debug("%s(dev=%p, index=%d, dma=%p)\n", __func__, dev, index, dma);
> +
> +   assert(dma);
> +   dma->dev = NULL;
> +
> +   ret = dev_read_phandle_with_args(dev, "dmas", "#dma-cells", 0, index,
> +);
> +   if (ret) {
> +   pr_err("%s: dev_read_phandle_with_args failed: err=%d\n",
> +  __func__, ret);
> +   return ret;
> +   }
> +
> +   ret = uclass_get_device_by_ofnode(UCLASS_DMA, args.node, _dma);
> +   if (ret) {
> +   pr_err("%s: uclass_get_device_by_ofnode failed: err=%d\n",
> +  __func__, ret);
> +   return ret;
> +   }
> +
> +   dma->dev = dev_dma;
> +
> +   ops = dma_dev_ops(dev_dma);
> +
> +   if (ops->of_xlate)
> +   ret = ops->of_xlate(dma, );
> +   else
> +   ret = dma_of_xlate_default(dma, );
> +   if (ret) {
> +   pr_err("of_xlate() failed: %d\n", ret);
> +   return ret;
> +   }
> +
> +   return dma_request(dev_dma, dma);
> +}
> +#  endif /* OF_PLATDATA */
> +
> +int dma_get_by_name(struct udevice *dev, const char *name, struct dma *dma)
> +{
> +   int index;
> +
> +   debug("%s(dev=%p, name=%s, dma=%p)\n", __func__, dev, name, dma);
> +   dma->dev = NULL;
> +
> +   index = dev_read_stringlist_search(dev, "dma-names", 

[U-Boot] [PATCH v2 0/2] [for 2018.03] RPi: Drain RX queue on setbrg

[Alexander Graf]

We had a few reports coming in from people that had their autoboot chain
aborted after pinmuxing support was added for the RPi.

The culprit is easy: The UARTs may have been enabled before, but muxed
to an incorrect pin. That pin may have pulled the RX line down which again
lead to lots of zero bytes gathered in the RX buffer.

The easy fix for that is to drain the RX queue every time we set the baud
rate.

This patch set is the minimally intrusive fix for the RPi. We may want to
do that generically for all serial devices later.

v1 -> v2:

  - fix pl011 draining

Alexander Graf (2):
  serial_bcm283x_mu: Flush RX queue after setting baud rate
  bcm283x_pl011: Flush RX queue after setting baud rate

 drivers/serial/serial_bcm283x_mu.c |  8 +++-
 drivers/serial/serial_bcm283x_pl011.c  | 25 -
 drivers/serial/serial_pl01x.c  | 10 +-
 drivers/serial/serial_pl01x_internal.h |  7 ++-
 4 files changed, 42 insertions(+), 8 deletions(-)

-- 
2.12.3

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[U-Boot] [PATCH v2 2/2] bcm283x_pl011: Flush RX queue after setting baud rate

[Alexander Graf]

After the UART was initialized, we may still have bogus data in the
RX queue if it was enabled with incorrect pin muxing before.

So let's flush the RX queue whenever we initialize baud rates.

This fixes a regression with the dynamic pinmuxing code when enable_uart=1
is not set in config.txt on Raspberry Pis that use pl011 for serial.

Fixes: caf2233b28 ("bcm283x: Add pinctrl driver")
Reported-by: Göran Lundberg 
Reported-by: Peter Robinson 
Signed-off-by: Alexander Graf 

---

v1 -> v2:

  - correctly drain the queue
---
 drivers/serial/serial_bcm283x_pl011.c  | 25 -
 drivers/serial/serial_pl01x.c  | 10 +-
 drivers/serial/serial_pl01x_internal.h |  7 ++-
 3 files changed, 35 insertions(+), 7 deletions(-)

diff --git a/drivers/serial/serial_bcm283x_pl011.c 
b/drivers/serial/serial_bcm283x_pl011.c
index bfd39f84f3..dad7236895 100644
--- a/drivers/serial/serial_bcm283x_pl011.c
+++ b/drivers/serial/serial_bcm283x_pl011.c
@@ -9,6 +9,7 @@
 #include 
 #include 
 #include 
+#include 
 #include "serial_pl01x_internal.h"
 
 /*
@@ -55,6 +56,28 @@ static int bcm283x_pl011_serial_ofdata_to_platdata(struct 
udevice *dev)
return 0;
 }
 
+static int bcm283x_pl011_serial_setbrg(struct udevice *dev, int baudrate)
+{
+   int r;
+
+   r = pl01x_serial_setbrg(dev, baudrate);
+
+   /*
+* We may have been muxed to a bogus line before. Drain the RX
+* queue so we start at a clean slate.
+*/
+   while (pl01x_serial_getc(dev) != -EAGAIN) ;
+
+   return r;
+}
+
+static const struct dm_serial_ops bcm283x_pl011_serial_ops = {
+   .putc = pl01x_serial_putc,
+   .pending = pl01x_serial_pending,
+   .getc = pl01x_serial_getc,
+   .setbrg = bcm283x_pl011_serial_setbrg,
+};
+
 static const struct udevice_id bcm283x_pl011_serial_id[] = {
{.compatible = "brcm,bcm2835-pl011", .data = TYPE_PL011},
{}
@@ -67,7 +90,7 @@ U_BOOT_DRIVER(bcm283x_pl011_uart) = {
.ofdata_to_platdata = 
of_match_ptr(bcm283x_pl011_serial_ofdata_to_platdata),
.platdata_auto_alloc_size = sizeof(struct pl01x_serial_platdata),
.probe  = pl01x_serial_probe,
-   .ops= _serial_ops,
+   .ops= _pl011_serial_ops,
.flags  = DM_FLAG_PRE_RELOC,
.priv_auto_alloc_size = sizeof(struct pl01x_priv),
 };
diff --git a/drivers/serial/serial_pl01x.c b/drivers/serial/serial_pl01x.c
index 23d9d839cb..45f1282770 100644
--- a/drivers/serial/serial_pl01x.c
+++ b/drivers/serial/serial_pl01x.c
@@ -273,7 +273,7 @@ __weak struct serial_device *default_serial_console(void)
 
 #ifdef CONFIG_DM_SERIAL
 
-static int pl01x_serial_setbrg(struct udevice *dev, int baudrate)
+int pl01x_serial_setbrg(struct udevice *dev, int baudrate)
 {
struct pl01x_serial_platdata *plat = dev_get_platdata(dev);
struct pl01x_priv *priv = dev_get_priv(dev);
@@ -299,21 +299,21 @@ int pl01x_serial_probe(struct udevice *dev)
return 0;
 }
 
-static int pl01x_serial_getc(struct udevice *dev)
+int pl01x_serial_getc(struct udevice *dev)
 {
struct pl01x_priv *priv = dev_get_priv(dev);
 
return pl01x_getc(priv->regs);
 }
 
-static int pl01x_serial_putc(struct udevice *dev, const char ch)
+int pl01x_serial_putc(struct udevice *dev, const char ch)
 {
struct pl01x_priv *priv = dev_get_priv(dev);
 
return pl01x_putc(priv->regs, ch);
 }
 
-static int pl01x_serial_pending(struct udevice *dev, bool input)
+int pl01x_serial_pending(struct udevice *dev, bool input)
 {
struct pl01x_priv *priv = dev_get_priv(dev);
unsigned int fr = readl(>regs->fr);
@@ -324,7 +324,7 @@ static int pl01x_serial_pending(struct udevice *dev, bool 
input)
return fr & UART_PL01x_FR_TXFF ? 0 : 1;
 }
 
-const struct dm_serial_ops pl01x_serial_ops = {
+static const struct dm_serial_ops pl01x_serial_ops = {
.putc = pl01x_serial_putc,
.pending = pl01x_serial_pending,
.getc = pl01x_serial_getc,
diff --git a/drivers/serial/serial_pl01x_internal.h 
b/drivers/serial/serial_pl01x_internal.h
index c56dd54c7b..d4605f24a3 100644
--- a/drivers/serial/serial_pl01x_internal.h
+++ b/drivers/serial/serial_pl01x_internal.h
@@ -43,7 +43,12 @@ struct pl01x_regs {
 
 int pl01x_serial_ofdata_to_platdata(struct udevice *dev);
 int pl01x_serial_probe(struct udevice *dev);
-extern const struct dm_serial_ops pl01x_serial_ops;
+
+/* Needed for external pl01x_serial_ops drivers */
+int pl01x_serial_putc(struct udevice *dev, const char ch);
+int pl01x_serial_pending(struct udevice *dev, bool input);
+int pl01x_serial_getc(struct udevice *dev);
+int pl01x_serial_setbrg(struct udevice *dev, int baudrate);
 
 struct pl01x_priv {
struct pl01x_regs *regs;
-- 
2.12.3

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[U-Boot] [PATCH v2 1/2] serial_bcm283x_mu: Flush RX queue after setting baud rate

[Alexander Graf]

After the UART was initialized, we may still have bogus data in the
RX queue if it was enabled with incorrect pin muxing before.

So let's flush the RX queue whenever we initialize baud rates.

This fixes a regression with the dynamic pinmuxing code when enable_uart=1
is not set in config.txt.

Fixes: caf2233b28 ("bcm283x: Add pinctrl driver")
Reported-by: Göran Lundberg 
Reported-by: Peter Robinson 
Signed-off-by: Alexander Graf 
---
 drivers/serial/serial_bcm283x_mu.c | 8 +++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/serial/serial_bcm283x_mu.c 
b/drivers/serial/serial_bcm283x_mu.c
index 40029fadbc..d87b44e902 100644
--- a/drivers/serial/serial_bcm283x_mu.c
+++ b/drivers/serial/serial_bcm283x_mu.c
@@ -51,6 +51,8 @@ struct bcm283x_mu_priv {
struct bcm283x_mu_regs *regs;
 };
 
+static int bcm283x_mu_serial_getc(struct udevice *dev);
+
 static int bcm283x_mu_serial_setbrg(struct udevice *dev, int baudrate)
 {
struct bcm283x_mu_serial_platdata *plat = dev_get_platdata(dev);
@@ -59,13 +61,17 @@ static int bcm283x_mu_serial_setbrg(struct udevice *dev, 
int baudrate)
u32 divider;
 
if (plat->skip_init)
-   return 0;
+   goto out;
 
divider = plat->clock / (baudrate * 8);
 
writel(BCM283X_MU_LCR_DATA_SIZE_8, >lcr);
writel(divider - 1, >baud);
 
+out:
+   /* Flush the RX queue - all data in there is bogus */
+   while (bcm283x_mu_serial_getc(dev) != -EAGAIN) ;
+
return 0;
 }
 
-- 
2.12.3

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Re: [U-Boot] [PATCH 2/2] bcm283x_pl011: Flush RX queue after setting baud rate

[Alexander Graf]

On 07.03.18 13:59, Peter Robinson wrote:
> On Tue, Mar 6, 2018 at 1:13 PM, Alexander Graf  wrote:
>> After the UART was initialized, we may still have bogus data in the
>> RX queue if it was enabled with incorrect pin muxing before.
>>
>> So let's flush the RX queue whenever we initialize baud rates.
>>
>> This fixes a regression with the dynamic pinmuxing code when enable_uart=1
>> is not set in config.txt on Raspberry Pis that use pl011 for serial.
> 
> This causes my RPi2 devices not to actually boot. When I connected a
> HDMI monitor to one of them I get the rainbow square.

Ok, I was able to reproduce this on the RPi3 CM. See below ...

> 
> Peter
> 
> 
>> Fixes: caf2233b28 ("bcm283x: Add pinctrl driver")
>> Reported-by: Göran Lundberg 
>> Reported-by: Peter Robinson 
>> Signed-off-by: Alexander Graf 
>> ---
>>  drivers/serial/serial_bcm283x_pl011.c  | 25 -
>>  drivers/serial/serial_pl01x.c  | 10 +-
>>  drivers/serial/serial_pl01x_internal.h |  7 ++-
>>  3 files changed, 35 insertions(+), 7 deletions(-)
>>
>> diff --git a/drivers/serial/serial_bcm283x_pl011.c 
>> b/drivers/serial/serial_bcm283x_pl011.c
>> index bfd39f84f3..2c6fb267ff 100644
>> --- a/drivers/serial/serial_bcm283x_pl011.c
>> +++ b/drivers/serial/serial_bcm283x_pl011.c
>> @@ -9,6 +9,7 @@
>>  #include 
>>  #include 
>>  #include 
>> +#include 
>>  #include "serial_pl01x_internal.h"
>>
>>  /*
>> @@ -55,6 +56,28 @@ static int bcm283x_pl011_serial_ofdata_to_platdata(struct 
>> udevice *dev)
>> return 0;
>>  }
>>
>> +static int bcm283x_pl011_serial_setbrg(struct udevice *dev, int baudrate)
>> +{
>> +   int r;
>> +
>> +   r = pl01x_serial_setbrg(dev, baudrate);
>> +
>> +   /*
>> +* We may have been muxed to a bogus line before. Drain the RX
>> +* queue so we start at a clean slate.
>> +*/
>> +   while (pl01x_serial_getc(dev) == -EAGAIN) ;

... this is obviously wrong. It doesn't drain the queue but instead
loops as long as the queue is empty. Bleks.

I'll send a v2. Please retest then. Sorry for the mess :).


Alex
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Re: [U-Boot] [PATCH v5 07/15] phy: add support for internal phys

[Joe Hershberger]

On Mon, Mar 5, 2018 at 2:05 PM, Álvaro Fernández Rojas
 wrote:
> Signed-off-by: Álvaro Fernández Rojas 
> ---
>  v5: no changes
>  v4: no changes
>  v3: no changes
>  v2: no changes
>
>  include/phy.h | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/include/phy.h b/include/phy.h
> index 0543ec10c2..8f3e53db01 100644
> --- a/include/phy.h
> +++ b/include/phy.h
> @@ -50,6 +50,7 @@
>
>
>  typedef enum {
> +   PHY_INTERFACE_MODE_INTERNAL,

In Linux this is handled as a flag instead of a different mode. It
seems we should do it the same way.

> PHY_INTERFACE_MODE_MII,
> PHY_INTERFACE_MODE_GMII,
> PHY_INTERFACE_MODE_SGMII,
> @@ -72,6 +73,7 @@ typedef enum {
>  } phy_interface_t;
>
>  static const char *phy_interface_strings[] = {
> +   [PHY_INTERFACE_MODE_INTERNAL]   = "internal",
> [PHY_INTERFACE_MODE_MII]= "mii",
> [PHY_INTERFACE_MODE_GMII]   = "gmii",
> [PHY_INTERFACE_MODE_SGMII]  = "sgmii",
> --
> 2.11.0
>
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[U-Boot] Status of Altera Aria 10 in upstream

[Jan Kiszka]

Hi all,

just a quick check because I received reports internally that things are
not working: Is latest U-boot able to drive Aria 10 SoC FGPA boards
completely, or are there still some features missing that downstream
SDKs only contain?

We need upstream U-boot features for a target but are currently stuck
with a 2014-based downstream branch that looks too different to compare
quickly at feature level.

Thanks in advance!
Jan

-- 
Siemens AG, Corporate Technology, CT RDA IOT SES-DE
Corporate Competence Center Embedded Linux
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Re: [U-Boot] [PATCH v7 2/4] Integrating TCP and wget into u-boot v7

[Joe Hershberger]

Hi Duncan,

The subject of all these patches ("Integrating TCP and wget into
u-boot") is what should be the title of a cover letter. You need to
give each patch a reasonable subject about that patch, not all of them
together.

On Thu, Mar 1, 2018 at 8:59 PM,   wrote:
> From: Duncan Hare 
>
> All the code is new, and not copied from any source.

This is what should be inside the "Commit-notes:" section... All the
things you currently have there should be outside.

>
>>
> 
>
> Commit-notes

You are missing a ':' so the tool is not detecting this.

>
> Routine tcp_print_buffer() is used to print portions of
> non zero terminated buffers. If there is an existing routine
> please let me know. I'm from the world of length fields
> not zero terminated strings (zOS).
>
> TCP Prtocol stack,
>
> Why TCP:
>
> Currently u-boot file transfers are done using tftp or NFS,
> both over udp. This requires a request to be sent from client
> (u-boot) to the boot server for every block of data.
>
> For a 4 Mbyte kernel, with a 1k block size this requires
> 4,000 request for a block.
>
> Using a large block size, one greater than the Ethernet
> maximum frame size limitation, would require fragmentation,
> which u-boot supports. However, missing fragment recovery
> requires timeout detection and re-transmission requests
> for missing fragments.
>
> UDP is ideally suited to fast single packet exchanges,
> inquiry/response, for example dns, becuse of the lack of
> connection overhead.
>
> UDP as a file transport mechanism is slow, even in low
> latency networks, because file transfer with udp requires
> poll/response mechanism to provide transfer integrity.
>
> In networks with large latency, for example: the internet,
> UDP is even slower. What is a 30 second transfer on a local
> boot server and LAN increase to over 3 minutes, because of
> all the requests/response traffic.
>
> This was anticipated in the evolution of the IP protocols
> and TCP was developed and then enhanced for high latency high
> bandwidth networks.
>
> The current standard is TCP with selective acknowledgment.
>
> In our testing we have reduce kernel transmission time to
> around 0.4 seconds for a 4Mbyte kernel, with a 100 Mbps
> downlink.
>
> END
>
> Signed-off-by: Duncan Hare 
> ---
>
> Changes in v7:
> Integrating TCP and wget into u-boot

A much more appropriate thing to have put here would be something like
"Fixed naming of x variable" and "Changed file location of z.h". The
point of this is what you changed in this version of the patch.

>
>  include/net.h |   8 +-
>  include/net/tcp.h | 218 
>  net/Kconfig   |  35 +--
>  net/Makefile  |   2 +-
>  net/net.c |  51 +++-
>  net/tcp.c | 749 
> ++
>  6 files changed, 1024 insertions(+), 39 deletions(-)
>  create mode 100644 include/net/tcp.h
>  create mode 100644 net/tcp.c
>
> diff --git a/include/net.h b/include/net.h
> index 7e5f5a6a5b..e29d804a23 100644
> --- a/include/net.h
> +++ b/include/net.h
> @@ -548,7 +548,7 @@ extern int  net_restart_wrap;   /* Tried all 
> network devices */
>
>  enum proto_t {
> BOOTP, RARP, ARP, TFTPGET, DHCP, PING, DNS, NFS, CDP, NETCONS, SNTP,
> -   TFTPSRV, TFTPPUT, LINKLOCAL
> +   TFTPSRV, TFTPPUT, LINKLOCAL, WGET
>  };
>
>  extern charnet_boot_file_name[1024];/* Boot File name */
> @@ -681,11 +681,15 @@ static inline void net_send_packet(uchar *pkt, int len)
>   * @param payload_len Length of data after the UDP header
>   */
>  int net_send_ip_packet(uchar *ether, struct in_addr dest, int dport, int 
> sport,
> -  int payload_len, int proto);
> +  int payload_len, int proto, u8 action, u32 tcp_seq_num,
> +  u32 tcp_ack_num);
>
>  int net_send_udp_packet(uchar *ether, struct in_addr dest, int dport,
> int sport, int payload_len);
>
> +int net_send_tcp_packet(int payload_len, int dport, int sport, u8 action,
> +   u32 tcp_seq_num, u32 tcp_ack_num);
> +
>  /* Processes a received packet */
>  void net_process_received_packet(uchar *in_packet, int len);
>
> diff --git a/include/net/tcp.h b/include/net/tcp.h
> new file mode 100644
> index 00..81f263351e
> --- /dev/null
> +++ b/include/net/tcp.h
> @@ -0,0 +1,218 @@
> +/*
> + * TCP Support for file transfer.
> + *
> + * Copyright 2017 Duncan Hare, All rights reserved.
> + *
> + *  SPDX-License-Identifier:GPL-2.0
> + */
> +
> +#define TCP_ACTIVITY 127   /* Activity on downloading  */
> +
> +struct ip_tcp_hdr {
> +   u8  ip_hl_v;/* header length and version*/
> +   u8  ip_tos; /* type of service  */
> +   u16 ip_len; /* total length */
> +   u16 ip_id;  /* 

Re: [U-Boot] [PATCH v7 4/4] Fixed minor formatting errors.

[Joe Hershberger]

On Thu, Mar 1, 2018 at 9:00 PM,   wrote:
> From: Duncan Hare 
>
> Too long a line in wget, line 386
> Embedded blanks and tabs in clarifying comments in tcp.c

These changes should be squashed into the previous patches.

>
> Signed-off-by: Duncan Hare 
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Re: [U-Boot] [PATCH 1/1] net: mvpp2x: add check after calloc

[Joe Hershberger]

On Tue, Mar 6, 2018 at 8:39 PM, Heinrich Schuchardt  wrote:
> After allocating plat the pointer is checked.
> Afterwards name is allocated and not checked.
>
> Add the missing check to avoid a possible NULL dereference.
>
> Signed-off-by: Heinrich Schuchardt 

Acked-by: Joe Hershberger 
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Re: [U-Boot] [PATCH 3/4] Handle NETCONSOLE and SPL enabled

[Joe Hershberger]

On Wed, Mar 7, 2018 at 4:40 AM, Jason Kridner  wrote:
> From: Jason Kridner 
>
> NETCONSOLE isn't compiled in with SPL, so the include file needs to recognize 
> that.
>
> Signed-off-by: Jason Kridner 
> Cc: Joe Hershberger 

Acked-by: Joe Hershberger 
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Re: [U-Boot] [U-Boot PATCH v2 2/2] defconfig: k2l_hs_evm: Add k2l_hs_evm_defconfig

[Andrew F. Davis]

On 03/06/2018 10:10 AM, Madan Srinivas wrote:
> Adds a dedicated defconfig to build TI K2L secure
> devices and updates MAINTAINERS.
> 
> k2l_hs_evm_defconfig is created from the k2l_evm_defconfig
> and removes support for SPL, as SPL is not supported on K2
> HS devices. Corrects SYS_TEXT_BASE for HS devices.
> 
> Also adds TI_SECURE_DEVICE and FIT_IMAGE_POST_PROCESS to
> include support for secure image creation and authentication
> 
> Signed-off-by: Madan Srinivas 
> 
> ---


Acked-by: Andrew F. Davis 


> 
> Changes in v2:
>   - Updates MAINTAINERS with K2L HS
> 
>  MAINTAINERS  |  1 +
>  configs/k2l_hs_evm_defconfig | 43 +++
>  2 files changed, 44 insertions(+)
>  create mode 100644 configs/k2l_hs_evm_defconfig
> 
> diff --git a/MAINTAINERS b/MAINTAINERS
> index f42cb22..4f29b16 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -486,6 +486,7 @@ F:configs/dra7xx_hs_evm_defconfig
>  F:   configs/k2hk_hs_evm_defconfig
>  F:   configs/k2e_hs_evm_defconfig
>  F:   configs/k2g_hs_evm_defconfig
> +F:   configs/k2l_hs_evm_defconfig
>  
>  TQ GROUP
>  #M:  Martin Krause 
> diff --git a/configs/k2l_hs_evm_defconfig b/configs/k2l_hs_evm_defconfig
> new file mode 100644
> index 000..cc002d3
> --- /dev/null
> +++ b/configs/k2l_hs_evm_defconfig
> @@ -0,0 +1,43 @@
> +CONFIG_ARM=y
> +CONFIG_ARCH_KEYSTONE=y
> +CONFIG_TI_SECURE_DEVICE=y
> +CONFIG_SYS_TEXT_BASE=0xC60
> +CONFIG_TI_COMMON_CMD_OPTIONS=y
> +CONFIG_TARGET_K2L_EVM=y
> +CONFIG_DEFAULT_DEVICE_TREE="keystone-k2l-evm"
> +CONFIG_FIT_IMAGE_POST_PROCESS=y
> +CONFIG_OF_BOARD_SETUP=y
> +CONFIG_SYS_CONSOLE_INFO_QUIET=y
> +CONFIG_VERSION_VARIABLE=y
> +CONFIG_BOARD_EARLY_INIT_F=y
> +CONFIG_HUSH_PARSER=y
> +# CONFIG_CMD_FLASH is not set
> +# CONFIG_CMD_GPIO is not set
> +# CONFIG_CMD_GPT is not set
> +# CONFIG_CMD_MMC is not set
> +CONFIG_CMD_NAND=y
> +# CONFIG_CMD_SETEXPR is not set
> +CONFIG_MTDIDS_DEFAULT="nand0=davinci_nand.0"
> +CONFIG_MTDPARTS_DEFAULT="mtdparts=davinci_nand.0:1024k(bootloader)ro,512k(params)ro,-(ubifs)"
> +CONFIG_CMD_UBI=y
> +CONFIG_ISO_PARTITION=y
> +CONFIG_EFI_PARTITION=y
> +CONFIG_OF_CONTROL=y
> +CONFIG_ENV_IS_IN_NAND=y
> +CONFIG_NET_RANDOM_ETHADDR=y
> +CONFIG_DM=y
> +CONFIG_TI_AEMIF=y
> +# CONFIG_MMC is not set
> +CONFIG_DM_SPI_FLASH=y
> +CONFIG_SPI_FLASH=y
> +CONFIG_SPI_FLASH_STMICRO=y
> +CONFIG_PHYLIB=y
> +CONFIG_DM_ETH=y
> +CONFIG_DM_SERIAL=y
> +CONFIG_SYS_NS16550=y
> +CONFIG_DM_SPI=y
> +CONFIG_DAVINCI_SPI=y
> +CONFIG_USB=y
> +CONFIG_USB_XHCI_HCD=y
> +CONFIG_USB_XHCI_DWC3=y
> +CONFIG_USB_STORAGE=y
> 
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Re: [U-Boot] [UBOOT PATCH v3] microblaze: wdt: Added Kconfig support for CONFIG_XILINX_TB_WATCHDOG

[Michal Simek]

On 7.3.2018 06:12, Vipul Kumar wrote:
> This patch added Kconfig support for CONFIG_XILINX_TB_WATCHDOG
> and enabled it in respective defconfig.
> 
> Signed-off-by: Vipul Kumar 
> Signed-off-by: Siva Durga Prasad Paladugu 
> ---
> Changes in v3:
> - Removed select hw_watchdog
> - Branch: u-boot-microblaze/kconfig
> ---
>  configs/microblaze-generic_defconfig | 1 +
>  drivers/watchdog/Kconfig | 6 ++
>  include/configs/microblaze-generic.h | 1 -
>  3 files changed, 7 insertions(+), 1 deletion(-)
> 
> diff --git a/configs/microblaze-generic_defconfig 
> b/configs/microblaze-generic_defconfig
> index 699dc44..fba3820 100644
> --- a/configs/microblaze-generic_defconfig
> +++ b/configs/microblaze-generic_defconfig
> @@ -63,3 +63,4 @@ CONFIG_XILINX_AXIEMAC=y
>  CONFIG_XILINX_EMACLITE=y
>  CONFIG_SYS_NS16550=y
>  CONFIG_XILINX_UARTLITE=y
> +CONFIG_XILINX_TB_WATCHDOG=y
> diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
> index fc46b67..bd209fa 100644
> --- a/drivers/watchdog/Kconfig
> +++ b/drivers/watchdog/Kconfig
> @@ -78,4 +78,10 @@ config WDT_ORION
>  Select this to enable Orion watchdog timer, which can be found on 
> some
>  Marvell Armada chips.
>  
> +config XILINX_TB_WATCHDOG
> + bool "Xilinx watchdog timer support"
> + depends on MICROBLAZE && !SPL_BUILD

Again this !SPL_BUILD is not working.


> + help
> +   Available for Xilinx Axi platforms to service timebase watchdog timer.
> +
>  endmenu
> diff --git a/include/configs/microblaze-generic.h 
> b/include/configs/microblaze-generic.h
> index 73c3c2a..391b26a 100644
> --- a/include/configs/microblaze-generic.h
> +++ b/include/configs/microblaze-generic.h
> @@ -50,7 +50,6 @@
>  # define CONFIG_WATCHDOG_IRQ XILINX_WATCHDOG_IRQ
>  # ifndef CONFIG_SPL_BUILD
>  #  define CONFIG_HW_WATCHDOG
> -#  define CONFIG_XILINX_TB_WATCHDOG
>  # endif
>  #endif
>  
> 

Thanks,
Michal



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Re: [U-Boot] [PATCH v2] common: add a prototype for mach_cpu_init()

[Tom Rini]

On Wed, Mar 07, 2018 at 03:28:20PM +0100, Patrick Delaunay wrote:

> avoid warning: no previous prototype for ‘mach_cpu_init’
> 
> Signed-off-by: Patrick Delaunay 

Reviewed-by: Tom Rini 

-- 
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[U-Boot] [PATCH] arm: Disable the strict alignment of data on armv7

[Michal Simek]

From: Nitin Jain 

This patch is used for disable the strict alignment of data
to avoid the memory alignment issues.

Also setup this option for Xilinx Zynq.

Signed-off-by: Nitin Jain 
Signed-off-by: Siva Durga Prasad Paladugu 
Signed-off-by: Michal Simek 
---

Not sure if there is any side effects but our tests don't show up any
issue with disabling this bit.

---
 arch/arm/Kconfig   | 1 +
 arch/arm/cpu/armv7/Kconfig | 6 ++
 arch/arm/cpu/armv7/start.S | 2 ++
 3 files changed, 9 insertions(+)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index a66d04eadfcb..4b5c64c8ba8b 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -778,6 +778,7 @@ config ARCH_ZYNQ
imply CMD_CLK
imply FAT_WRITE
imply CMD_SPL
+   imply ARMV7_MEM_ALIGN_DISABLE
 
 config ARCH_ZYNQMP
bool "Xilinx ZynqMP based platform"
diff --git a/arch/arm/cpu/armv7/Kconfig b/arch/arm/cpu/armv7/Kconfig
index b9c4f4e79b9b..d5c0f0ebab17 100644
--- a/arch/arm/cpu/armv7/Kconfig
+++ b/arch/arm/cpu/armv7/Kconfig
@@ -58,4 +58,10 @@ config ARMV7_LPAE
Say Y here to use the long descriptor page table format. This is
required if U-Boot runs in HYP mode.
 
+config ARMV7_MEM_ALIGN_DISABLE
+   bool "Disable strict alignment of data"
+   help
+Enabling this option disables strict alignment for armv7 by
+setting the alignment bit in system control register of cp15.
+
 endif
diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index 7e2695761e98..795b702a5f9c 100644
--- a/arch/arm/cpu/armv7/start.S
+++ b/arch/arm/cpu/armv7/start.S
@@ -150,7 +150,9 @@ ENTRY(cpu_init_cp15)
mrc p15, 0, r0, c1, c0, 0
bic r0, r0, #0x2000 @ clear bits 13 (--V-)
bic r0, r0, #0x0007 @ clear bits 2:0 (-CAM)
+#ifndef CONFIG_ARMV7_MEM_ALIGN_DISABLE
orr r0, r0, #0x0002 @ set bit 1 (--A-) Align
+#endif
orr r0, r0, #0x0800 @ set bit 11 (Z---) BTB
 #ifdef CONFIG_SYS_ICACHE_OFF
bic r0, r0, #0x1000 @ clear bit 12 (I) I-cache
-- 
1.9.1

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[U-Boot] [PATCH] arm64: zynqmp: Remove ep108 board

[Michal Simek]

ZynqMP Emulation board is no longer tested and there is no reason to
keep maintaining it.

Signed-off-by: Michal Simek 
---

 arch/arm/dts/Makefile  |   1 -
 arch/arm/dts/zynqmp-ep108-clk.dtsi | 172 ---
 arch/arm/dts/zynqmp-ep108.dts  | 235 -
 configs/xilinx_zynqmp_ep_defconfig | 102 
 include/configs/xilinx_zynqmp_ep.h |  24 
 5 files changed, 534 deletions(-)
 delete mode 100644 arch/arm/dts/zynqmp-ep108-clk.dtsi
 delete mode 100644 arch/arm/dts/zynqmp-ep108.dts
 delete mode 100644 configs/xilinx_zynqmp_ep_defconfig
 delete mode 100644 include/configs/xilinx_zynqmp_ep.h

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 20a4c37d48af..dd691429621c 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -146,7 +146,6 @@ dtb-$(CONFIG_ARCH_ZYNQ) += \
zynq-zturn-myir.dtb \
zynq-zybo.dtb
 dtb-$(CONFIG_ARCH_ZYNQMP) += \
-   zynqmp-ep108.dtb\
zynqmp-mini-emmc.dtb\
zynqmp-mini-nand.dtb\
zynqmp-zcu102-revA.dtb  \
diff --git a/arch/arm/dts/zynqmp-ep108-clk.dtsi 
b/arch/arm/dts/zynqmp-ep108-clk.dtsi
deleted file mode 100644
index 12d9fe149888..
--- a/arch/arm/dts/zynqmp-ep108-clk.dtsi
+++ /dev/null
@@ -1,172 +0,0 @@
-/*
- * clock specification for Xilinx ZynqMP ep108 development board
- *
- * (C) Copyright 2015, Xilinx, Inc.
- *
- * Michal Simek 
- *
- * SPDX-License-Identifier:GPL-2.0+
- */
-
-/ {
-   misc_clk: misc_clk {
-   compatible = "fixed-clock";
-   #clock-cells = <0>;
-   clock-frequency = <2500>;
-   u-boot,dm-pre-reloc;
-   };
-
-   i2c_clk: i2c_clk {
-   compatible = "fixed-clock";
-   #clock-cells = <0x0>;
-   clock-frequency = <1>;
-   };
-
-   sata_clk: sata_clk {
-   compatible = "fixed-clock";
-   #clock-cells = <0>;
-   clock-frequency = <7500>;
-   };
-
-   dp_aclk: clock0 {
-   compatible = "fixed-clock";
-   #clock-cells = <0>;
-   clock-frequency = <5000>;
-   clock-accuracy = <100>;
-   };
-
-   clk100: clk100 {
-   compatible = "fixed-clock";
-   #clock-cells = <0>;
-   clock-frequency = <1>;
-   };
-
-   clk600: clk600 {
-   compatible = "fixed-clock";
-   #clock-cells = <0>;
-   clock-frequency = <6>;
-   };
-
-   dp_aud_clk: clock1 {
-   compatible = "fixed-clock";
-   #clock-cells = <0>;
-   clock-frequency = <22579200>;
-   clock-accuracy = <100>;
-   };
-};
-
- {
-   clocks = <_clk _clk>;
-};
-
- {
-   clocks = <_clk _clk>;
-};
-
-_dma_chan1 {
-   clocks = <>, <>;
-};
-
-_dma_chan2 {
-   clocks = <>, <>;
-};
-
-_dma_chan3 {
-   clocks = <>, <>;
-};
-
-_dma_chan4 {
-   clocks = <>, <>;
-};
-
-_dma_chan5 {
-   clocks = <>, <>;
-};
-
-_dma_chan6 {
-   clocks = <>, <>;
-};
-
-_dma_chan7 {
-   clocks = <>, <>;
-};
-
-_dma_chan8 {
-   clocks = <>, <>;
-};
-
- {
-   clocks = <_clk>, <_clk>, <_clk>;
-};
-
- {
-   clocks = <_clk>;
-};
-
- {
-   clocks = <_clk>;
-};
-
- {
-   clocks = <_clk>;
-};
-
- {
-   clocks = <_clk _clk>;
-};
-
- {
-   clocks = <_clk _clk>;
-};
-
- {
-   clocks = <_clk>;
-};
-
- {
-   clocks = <_clk>, <_clk>;
-};
-
- {
-   clocks = <_clk>, <_clk>;
-};
-
- {
-   clocks = <_clk _clk>;
-};
-
- {
-   clocks = <_clk _clk>;
-};
-
- {
-   clocks = <_clk _clk>;
-};
-
- {
-   clocks = <_clk>, <_clk>;
-};
-
- {
-   clocks = <_clk>, <_clk>;
-};
-
- {
-   clocks= <_clk>;
-};
-
-_drm {
-   clocks = <_clk>;
-};
-
-_dp {
-   clocks = <_aclk>, <_aud_clk>;
-};
-
-_dp_snd_codec0 {
-   clocks = <_aud_clk>;
-};
-
-_dpdma {
-   clocks = <_clk>;
-};
diff --git a/arch/arm/dts/zynqmp-ep108.dts b/arch/arm/dts/zynqmp-ep108.dts
deleted file mode 100644
index a16ffdc3f0ce..
--- a/arch/arm/dts/zynqmp-ep108.dts
+++ /dev/null
@@ -1,235 +0,0 @@
-/*
- * dts file for Xilinx ZynqMP ep108 development board
- *
- * (C) Copyright 2014 - 2015, Xilinx, Inc.
- *
- * Michal Simek 
- *
- * SPDX-License-Identifier:GPL-2.0+
- */
-
-/dts-v1/;
-
-#include "zynqmp.dtsi"
-#include "zynqmp-ep108-clk.dtsi"
-
-/ {
-   model = "ZynqMP EP108";
-
-   aliases {
-   ethernet0 = 
-   mmc0 = 
-   mmc1 = 
-   serial0 = 
-   spi0 = 
-   spi1 = 
-   spi2 = 
-   usb0 = 
-   usb1 = 
-   };
-
-   chosen {
-   bootargs = "earlycon";
-   stdout-path = 

Re: [U-Boot] [PATCH 1/1] scripts/coccinelle: add some more coccinelle tests

[Tom Rini]

On Wed, Mar 07, 2018 at 02:57:19AM +0100, Heinrich Schuchardt wrote:

> kmerr: verify that malloc and calloc are followed by a check to verify
> that we are not out of memory.
> 
> badzero: Compare pointer-typed values to NULL rather than 0
> 
> Both checks are copied from the Linux kernel archive.
> 
> Signed-off-by: Heinrich Schuchardt 
> ---
>  scripts/coccinelle/null/badzero.cocci | 238 
> ++
>  scripts/coccinelle/null/kmerr.cocci   |  72 ++
>  2 files changed, 310 insertions(+)
>  create mode 100644 scripts/coccinelle/null/badzero.cocci
>  create mode 100644 scripts/coccinelle/null/kmerr.cocci
> 
> diff --git a/scripts/coccinelle/null/badzero.cocci 
> b/scripts/coccinelle/null/badzero.cocci
> new file mode 100644
> index 00..f597c8007b
> --- /dev/null
> +++ b/scripts/coccinelle/null/badzero.cocci
> @@ -0,0 +1,238 @@
> +/// Compare pointer-typed values to NULL rather than 0
> +///
> +//# This makes an effort to choose between !x and x == NULL.  !x is used
> +//# if it has previously been used with the function used to initialize x.
> +//# This relies on type information.  More type information can be obtained
> +//# using the option -all_includes and the option -I to specify an
> +//# include path.
> +//
> +// Confidence: High
> +// Copyright: (C) 2012 Julia Lawall, INRIA/LIP6.  GPLv2.
> +// Copyright: (C) 2012 Gilles Muller, INRIA/LiP6.  GPLv2.
> +// URL: http://coccinelle.lip6.fr/
> +// Requires: 1.0.0
> +// Options:

We should probably be adding an SPDX tag here.  Or, adding one in Linux
and pulling it in then?  Thanks!

-- 
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Re: [U-Boot] [PATCH 4/4] am335x: am335x_evm_usbspl_defconfig: NETCONSOLE

[Tom Rini]

On Wed, Mar 07, 2018 at 05:40:44AM -0500, Jason Kridner wrote:

> Enable NETCONSOLE by default. Still requires changes to the boot
> environment to enable on the platform.
> 
> Signed-of-by: Jason Kridner 
> Cc: Tom Rini 

Reviewed-by: Tom Rini 

-- 
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[U-Boot] [PATCH v2] common: add a prototype for mach_cpu_init()

[Patrick Delaunay]

avoid warning: no previous prototype for ‘mach_cpu_init’

Signed-off-by: Patrick Delaunay 
---

Changes in v2:
- add return info for functions mach_cpu_init() and arch_cpu_init()

 include/common.h | 14 ++
 1 file changed, 14 insertions(+)

diff --git a/include/common.h b/include/common.h
index 0fe9439..57ae790 100644
--- a/include/common.h
+++ b/include/common.h
@@ -471,9 +471,23 @@ intis_core_valid (unsigned int);
  * CPU- or SoC- specific init needed to continue the init sequence. See
  * board_f.c for where it is called. If this is not provided, a default
  * version (which does nothing) will be used.
+ *
+ * @return: 0 on success, otherwise error
  */
 int arch_cpu_init(void);
 
+/**
+ * mach_cpu_init() - SoC/machine dependent CPU setup
+ *
+ * This is called after arch_cpu_init(). It should handle any
+ * SoC or machine specific init needed to continue the init sequence. See
+ * board_f.c for where it is called. If this is not provided, a default
+ * version (which does nothing) will be used.
+ *
+ * @return: 0 on success, otherwise error
+ */
+int mach_cpu_init(void);
+
 void s_init(void);
 
 intcheckcpu  (void);
-- 
2.7.4

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Re: [U-Boot] [PATCH 3/4] Handle NETCONSOLE and SPL enabled

[Tom Rini]

On Wed, Mar 07, 2018 at 05:40:43AM -0500, Jason Kridner wrote:

> From: Jason Kridner 
> 
> NETCONSOLE isn't compiled in with SPL, so the include file needs to recognize 
> that.
> 
> Signed-off-by: Jason Kridner 
> Cc: Joe Hershberger 

Reviewed-by: Tom Rini 

-- 
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Re: [U-Boot] [PATCH 1/4] Add support for BeagleBoard.org PocketBeagle

[Tom Rini]

On Wed, Mar 07, 2018 at 05:40:41AM -0500, Jason Kridner wrote:

> Texas Instruments AM3358 based low-cost board using Octavo Systems OSD3358 SIP
> with built-in TPS65217 PMIC and 512MB DDR3. Board features small 35mm x
> 55mm size, high-speed USB OTG, microSD and 72 0.1" expansion header
> pins with 2xSPI, 2xI2C, 2xUART, USB, 8xADC, up-to-44 GPIO, PRU pins and much 
> more.
> 
> https://beagleboard.org/pocket
> 
> This was tested using the am335x_evm_usbspl_defconfig.
> 
> Note that MII pins are enabled despite not having Ethernet on this
> board. This avoids an issue where otherwise many timeout errors would be
> generated. See https://e2e.ti.com/support/arm/sitara_arm/f/791/t/298976
> for some related discussion.
> 
> Signed-off-by: Jason Kridner 
> Cc: Tom Rini 

Reviewed-by: Tom Rini 

-- 
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Re: [U-Boot] [PATCH 2/4] am335x_evm: scan more partitions and use uname_r

[Tom Rini]

On Wed, Mar 07, 2018 at 05:40:42AM -0500, Jason Kridner wrote:

> This enables mainline u-boot to boot the BeagleBoard.org Debian
> distribution builds without extensive environment modifications.
> 
> Some boot layouts only have a single partition on the
> MMC/eMMC. This will scan those partitions after the second
> partition that was already being scanned.
> 
> Some layouts use uname_r to define the kernel being used for the boot to
> support multiple kernels stored within the boot file system without
> using symlinks.
> 
> See http://elinux.org/Beagleboard:U-boot_partitioning_layout_2.0 for
> more details on the BeagleBoard.org Debian image layout.
> 
> Signed-off-by: Jason Kridner 
> Cc: Robert Nelson 
> Cc: Tom Rini 
> ---
>  include/configs/am335x_evm.h |  5 -
>  include/environment/ti/mmc.h | 13 +
>  2 files changed, 13 insertions(+), 5 deletions(-)
> 
> diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h
> index 8d45b6fade..32fe0e0cd5 100644
> --- a/include/configs/am335x_evm.h
> +++ b/include/configs/am335x_evm.h
> @@ -61,7 +61,10 @@
>  #define BOOTENV_DEV_LEGACY_MMC(devtypeu, devtypel, instance) \
>   "bootcmd_" #devtypel #instance "=" \
>   "setenv mmcdev " #instance"; "\
> - "setenv bootpart " #instance":2 ; "\
> + "setenv bootpart " #instance":2; "\
> + "run mmcboot;"\
> + "setenv mmcdev " #instance"; "\
> + "setenv bootpart " #instance":1; "\
>   "run mmcboot\0"
>  
>  #define BOOTENV_DEV_NAME_LEGACY_MMC(devtypeu, devtypel, instance) \
> diff --git a/include/environment/ti/mmc.h b/include/environment/ti/mmc.h
> index 4305ebdaaf..b803ecccb7 100644
> --- a/include/environment/ti/mmc.h
> +++ b/include/environment/ti/mmc.h
> @@ -23,9 +23,10 @@
>   "bootenvfile=uEnv.txt\0" \
>   "importbootenv=echo Importing environment from mmc${mmcdev} ...; " \
>   "env import -t ${loadaddr} ${filesize}\0" \
> - "loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenvfile}\0" \
> - "loadimage=load ${devtype} ${bootpart} ${loadaddr} 
> ${bootdir}/${bootfile}\0" \
> - "loadfdt=load ${devtype} ${bootpart} ${fdtaddr} 
> ${bootdir}/${fdtfile}\0" \
> + "loadbootenv=if fatload mmc ${mmcdev} ${loadaddr} 
> ${bootdir}/${bootenvfile}; then echo Found ${bootdir}/${bootenvfile} in FAT 
> partition; else load mmc ${mmcdev} ${loadaddr} ${bootdir}/${bootenvfile}; 
> fi\0" \
> + "loadimage=if test -n ${uname_r}; then load ${devtype} ${bootpart} 
> ${loadaddr} ${bootdir}/vmlinuz-${uname_r}; run loadrd; else load ${devtype} 
> ${bootpart} ${loadaddr} ${bootdir}/${bootfile}; fi\0" \
> + "loadrd=load ${devtype} ${bootpart} ${rdaddr} 
> ${bootdir}/initrd.img-${uname_r}; setenv rdsize ${filesize}\0" \
> + "loadfdt=if test -n ${uname_r}; then load ${devtype} ${bootpart} 
> ${fdtaddr} ${bootdir}/dtbs/${uname_r}/${fdtfile}; else load ${devtype} 
> ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}; fi;\0" \
>   "envboot=mmc dev ${mmcdev}; " \
>   "if mmc rescan; then " \
>   "echo SD/MMC found on device ${mmcdev};" \
> @@ -45,7 +46,11 @@
>   "mmcloados=run args_mmc; " \
>   "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
>   "if run loadfdt; then " \
> - "bootz ${loadaddr} - ${fdtaddr}; " \
> + "if test -n ${uname_r}; then " \
> + "bootz ${loadaddr} ${rdaddr}:${rdsize} 
> ${fdtaddr}; " \
> + "else " \
> + "bootz ${loadaddr} - ${fdtaddr}; " \
> + "fi; " \
>   "else " \
>   "if test ${boot_fdt} = try; then " \
>   "bootz; " \

Why does this all differ from the usual Debian case?  Thanks!

-- 
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Re: [U-Boot] [U-Boot PATCH v2 1/2] configs: k2l: Updates u-boot env to install secure boot monitor

[Tom Rini]

On Tue, Mar 06, 2018 at 11:10:09AM -0500, Madan Srinivas wrote:

> This patch updates the default u-boot env for K2L HS devices
> to install the secure boot monitor and load the fitImage during
> boot.
> 
> Signed-off-by: Madan Srinivas 
> Acked-by: Andrew F. Davis 
> 

Reviewed-by: Tom Rini 

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Re: [U-Boot] imx: get_ticks in syscounter.c get miscompiled by GCC 6

[Tom Rini]

On Wed, Mar 07, 2018 at 10:42:44AM -0300, Fabio Estevam wrote:
> Hi Yasushi ,
> 
> On Wed, Mar 7, 2018 at 2:57 AM, Yasushi SHOJI  wrote:
> 
> > Do you guys really want to put volatile on all of these now?
> > We are at rc4 and Tom is planing to cut the release
> > March 12th.
> 
> This can be done at a later step.

Yes.  And it should be a little bit manual too.  For example, using your
regex (thanks!) I see we have some powerpc code that's doing
asm("eieio") and that should be eieio() (which is in turn an asm
volatile ...), as well as some sync;isync or just sync/isync that should
be sync();isync(); or similar.  And people that know x86 might have some
useful comments there too.

> > I'm attaching a tentative patch to fix only syscounter.c.
> > If it looks good, I'l resend it by git-send-email.
> 
> Patch looks good. Make sure to add your Signed-off-by line, then you
> can send it via git send-email.

Yes please, thanks!

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Re: [U-Boot] [U-Boot PATCH v2 2/2] defconfig: k2l_hs_evm: Add k2l_hs_evm_defconfig

[Tom Rini]

On Tue, Mar 06, 2018 at 11:10:10AM -0500, Madan Srinivas wrote:

> Adds a dedicated defconfig to build TI K2L secure
> devices and updates MAINTAINERS.
> 
> k2l_hs_evm_defconfig is created from the k2l_evm_defconfig
> and removes support for SPL, as SPL is not supported on K2
> HS devices. Corrects SYS_TEXT_BASE for HS devices.
> 
> Also adds TI_SECURE_DEVICE and FIT_IMAGE_POST_PROCESS to
> include support for secure image creation and authentication
> 
> Signed-off-by: Madan Srinivas 
> 

Reviewed-by: Tom Rini 

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Re: [U-Boot] [PATCH 03/16] common: add a prototype for mach_cpu_init()

[Patrick DELAUNAY]

Hi Simon

> -Original Message-
> From: s...@google.com [mailto:s...@google.com] On Behalf Of Simon Glass
> 
> Hi Patrick,
> 
> On 5 March 2018 at 07:24, Patrick Delaunay  wrote:
> >
> > avoid warning: no previous prototype for ‘mach_cpu_init’

> > +/**
> > + * mach_cpu_init() - SoC/machine dependent CPU setup
> > + *
> > + * This is called after arch_cpu_init(). It should handle any
> > + * SoC or machine specific init needed to continue the init sequence.
> > +See
> > + * board_f.c for where it is called. If this is not provided, a
> > +default
> > + * version (which does nothing) will be used.
> 
> Great, but can you please add @return docs?

Yes, I will do it
@return: 0 on success, otherwise error

I will also add the same for arch_cpu_init() in the same patch...

but after check, the warning is no more present in the v1 Serie after rework 
before push,
because mach_stm32mp don't use mach_cpu_init() but arch_cpu_init().

So this patch is not more required for my stm32mp arch (and I will remove it in 
V2 serie)

But I will sent today just this patch in v2 (without Serie).

> 
> Regards,
> Simon

Regards
Patrick
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[U-Boot] [PATCH] arm64: zynqmp: Correct EG/EV part detection logic

[Michal Simek]

From: Siva Durga Prasad Paladugu 

The vcu disable bit in efuse ipdisable register is valid only
if PL powered up so, consider PL powerup status for determing
EG/EV part. If PL is not powered up, ignore EG/EV part of string.
The PL powerup status will be filled by pmufw based on PL PROGB
status in the 9th bit of version field.

Signed-off-by: Siva Durga Prasad Paladugu 
Signed-off-by: Michal Simek 
---

 board/xilinx/zynqmp/zynqmp.c | 50 ++--
 1 file changed, 39 insertions(+), 11 deletions(-)

diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c
index b9825ddaa881..0d1bd5412b16 100644
--- a/board/xilinx/zynqmp/zynqmp.c
+++ b/board/xilinx/zynqmp/zynqmp.c
@@ -31,6 +31,7 @@ static const struct {
u32 id;
u32 ver;
char *name;
+   bool evexists;
 } zynqmp_devices[] = {
{
.id = 0x10,
@@ -53,11 +54,13 @@ static const struct {
{
.id = 0x20,
.name = "5ev",
+   .evexists = 1,
},
{
.id = 0x20,
.ver = 0x100,
.name = "5eg",
+   .evexists = 1,
},
{
.id = 0x20,
@@ -67,11 +70,13 @@ static const struct {
{
.id = 0x21,
.name = "4ev",
+   .evexists = 1,
},
{
.id = 0x21,
.ver = 0x100,
.name = "4eg",
+   .evexists = 1,
},
{
.id = 0x21,
@@ -81,11 +86,13 @@ static const struct {
{
.id = 0x30,
.name = "7ev",
+   .evexists = 1,
},
{
.id = 0x30,
.ver = 0x100,
.name = "7eg",
+   .evexists = 1,
},
{
.id = 0x30,
@@ -219,20 +226,48 @@ int chip_id(unsigned char id)
return val;
 }
 
+#define ZYNQMP_VERSION_SIZE9
+#define ZYNQMP_PL_STATUS_BIT   9
+#define ZYNQMP_PL_STATUS_MASK  BIT(ZYNQMP_PL_STATUS_BIT)
+#define ZYNQMP_CSU_VERSION_MASK~(ZYNQMP_PL_STATUS_MASK)
+
 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
!defined(CONFIG_SPL_BUILD)
 static char *zynqmp_get_silicon_idcode_name(void)
 {
u32 i, id, ver;
+   char *buf;
+   static char name[ZYNQMP_VERSION_SIZE];
 
id = chip_id(IDCODE);
ver = chip_id(IDCODE2);
 
for (i = 0; i < ARRAY_SIZE(zynqmp_devices); i++) {
-   if (zynqmp_devices[i].id == id && zynqmp_devices[i].ver == ver)
-   return zynqmp_devices[i].name;
+   if ((zynqmp_devices[i].id == id) &&
+   (zynqmp_devices[i].ver == (ver &
+   ZYNQMP_CSU_VERSION_MASK))) {
+   strncat(name, "zu", 2);
+   strncat(name, zynqmp_devices[i].name,
+   ZYNQMP_VERSION_SIZE - 3);
+   break;
+   }
}
-   return "unknown";
+
+   if (i >= ARRAY_SIZE(zynqmp_devices))
+   return "unknown";
+
+   if (!zynqmp_devices[i].evexists)
+   return name;
+
+   if (ver & ZYNQMP_PL_STATUS_MASK)
+   return name;
+
+   if (strstr(name, "eg") || strstr(name, "ev")) {
+   buf = strstr(name, "e");
+   *buf = '\0';
+   }
+
+   return name;
 }
 #endif
 
@@ -250,8 +285,6 @@ int board_early_init_f(void)
return ret;
 }
 
-#define ZYNQMP_VERSION_SIZE9
-
 int board_init(void)
 {
printf("EL Level:\tEL%d\n", current_el());
@@ -260,12 +293,7 @@ int board_init(void)
 !defined(CONFIG_SPL_BUILD) || (defined(CONFIG_SPL_FPGA_SUPPORT) && \
 defined(CONFIG_SPL_BUILD))
if (current_el() != 3) {
-   static char version[ZYNQMP_VERSION_SIZE];
-
-   strncat(version, "zu", 2);
-   zynqmppl.name = strncat(version,
-   zynqmp_get_silicon_idcode_name(),
-   ZYNQMP_VERSION_SIZE - 3);
+   zynqmppl.name = zynqmp_get_silicon_idcode_name();
printf("Chip ID:\t%s\n", zynqmppl.name);
fpga_init();
fpga_add(fpga_xilinx, );
-- 
1.9.1

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[U-Boot] [PATCH] arm64: zynqmp: Print the value of pl clocks and wdt clock using clk dump

[Michal Simek]

From: Vipul Kumar 

This patch print pl clocks (pl0...pl3) and watchdog
clock using clk dump.

Signed-off-by: Vipul Kumar 
Signed-off-by: Michal Simek 
---

 drivers/clk/clk_zynqmp.c | 75 
 1 file changed, 75 insertions(+)

diff --git a/drivers/clk/clk_zynqmp.c b/drivers/clk/clk_zynqmp.c
index bcc62904f174..4ef8662af560 100644
--- a/drivers/clk/clk_zynqmp.c
+++ b/drivers/clk/clk_zynqmp.c
@@ -226,6 +226,18 @@ static u32 zynqmp_clk_get_register(enum zynqmp_clk id)
return CRL_APB_CAN0_REF_CTRL;
case can1_ref:
return CRL_APB_CAN1_REF_CTRL;
+   case pl0:
+   return CRL_APB_PL0_REF_CTRL;
+   case pl1:
+   return CRL_APB_PL1_REF_CTRL;
+   case pl2:
+   return CRL_APB_PL2_REF_CTRL;
+   case pl3:
+   return CRL_APB_PL3_REF_CTRL;
+   case wdt:
+   return CRF_APB_TOPSW_LSBUS_CTRL;
+   case iopll_to_fpd:
+   return CRL_APB_IOPLL_TO_FPD_CTRL;
default:
debug("Invalid clk id%d\n", id);
}
@@ -278,6 +290,22 @@ static enum zynqmp_clk zynqmp_clk_get_peripheral_pll(u32 
clk_ctrl)
}
 }
 
+static enum zynqmp_clk zynqmp_clk_get_wdt_pll(u32 clk_ctrl)
+{
+   u32 srcsel = (clk_ctrl & CLK_CTRL_SRCSEL_MASK) >>
+ CLK_CTRL_SRCSEL_SHIFT;
+
+   switch (srcsel) {
+   case 2:
+   return iopll_to_fpd;
+   case 3:
+   return dpll;
+   case 0 ... 1:
+   default:
+   return apll;
+   }
+}
+
 static ulong zynqmp_clk_get_pll_src(ulong clk_ctrl,
struct zynqmp_clk_priv *priv,
bool is_pre_src)
@@ -420,6 +448,49 @@ static ulong zynqmp_clk_get_peripheral_rate(struct 
zynqmp_clk_priv *priv,
DIV_ROUND_CLOSEST(pllrate, div0), div1);
 }
 
+static ulong zynqmp_clk_get_wdt_rate(struct zynqmp_clk_priv *priv,
+enum zynqmp_clk id, bool two_divs)
+{
+   enum zynqmp_clk pll;
+   u32 clk_ctrl, div0;
+   u32 div1 = 1;
+   int ret;
+   ulong pllrate;
+
+   ret = zynqmp_mmio_read(zynqmp_clk_get_register(id), _ctrl);
+   if (ret) {
+   printf("%d %s mio read fail\n", __LINE__, __func__);
+   return -EIO;
+   }
+
+   div0 = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;
+   if (!div0)
+   div0 = 1;
+
+   pll = zynqmp_clk_get_wdt_pll(clk_ctrl);
+   if (two_divs) {
+   ret = zynqmp_mmio_read(zynqmp_clk_get_register(pll), _ctrl);
+   if (ret) {
+   printf("%d %s mio read fail\n", __LINE__, __func__);
+   return -EIO;
+   }
+   div1 = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;
+   if (!div1)
+   div1 = 1;
+   }
+
+   if (pll == iopll_to_fpd)
+   pll = iopll;
+
+   pllrate = zynqmp_clk_get_pll_rate(priv, pll);
+   if (IS_ERR_VALUE(pllrate))
+   return pllrate;
+
+   return
+   DIV_ROUND_CLOSEST(
+   DIV_ROUND_CLOSEST(pllrate, div0), div1);
+}
+
 static unsigned long zynqmp_clk_calc_peripheral_two_divs(ulong rate,
   ulong pll_rate,
   u32 *div0, u32 *div1)
@@ -510,8 +581,12 @@ static ulong zynqmp_clk_get_rate(struct clk *clk)
return zynqmp_clk_get_ddr_rate(priv);
case gem0_ref ... gem3_ref:
case qspi_ref ... can1_ref:
+   case pl0 ... pl3:
two_divs = true;
return zynqmp_clk_get_peripheral_rate(priv, id, two_divs);
+   case wdt:
+   two_divs = true;
+   return zynqmp_clk_get_wdt_rate(priv, id, two_divs);
default:
return -ENXIO;
}
-- 
1.9.1

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[U-Boot] [PATCH] arm64: zynqmp: nand: Fixed NAND erase issue for size 1GiB or more

[Michal Simek]

From: Vipul Kumar 

NAND erase was not happening for size 1GiB or more. Erase
command was executing successfully but in actual, it was not
erasing.
This patch fixed erase issue for 1 GiB or more size nand.

Signed-off-by: Vipul Kumar 
Signed-off-by: Michal Simek 
---

 drivers/mtd/nand/arasan_nfc.c | 7 ---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/mtd/nand/arasan_nfc.c b/drivers/mtd/nand/arasan_nfc.c
index 3c9a0215c53e..9c82c7db33fb 100644
--- a/drivers/mtd/nand/arasan_nfc.c
+++ b/drivers/mtd/nand/arasan_nfc.c
@@ -86,7 +86,7 @@ struct arasan_nand_command_format {
 #define ARASAN_NAND_CMD_ADDR_CYCL_MASK 0x7000
 #define ARASAN_NAND_CMD_ADDR_CYCL_SHIFT28
 
-#define ARASAN_NAND_MEM_ADDR1_PAGE_MASK0x
+#define ARASAN_NAND_MEM_ADDR1_PAGE_MASK0x
 #define ARASAN_NAND_MEM_ADDR1_COL_MASK 0x
 #define ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT   16
 #define ARASAN_NAND_MEM_ADDR2_PAGE_MASK0xFF
@@ -795,10 +795,11 @@ static int arasan_nand_erase(struct 
arasan_nand_command_format *curr_cmd,
 
writel(reg_val, _nand_base->cmd_reg);
 
-   page = (page_addr << ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT) &
+   page = (page_addr >> ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT) &
ARASAN_NAND_MEM_ADDR1_PAGE_MASK;
column = page_addr & ARASAN_NAND_MEM_ADDR1_COL_MASK;
-   writel(page | column, _nand_base->memadr_reg1);
+   writel(column | (page << ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT),
+  _nand_base->memadr_reg1);
 
reg_val = readl(_nand_base->memadr_reg2);
reg_val &= ~ARASAN_NAND_MEM_ADDR2_PAGE_MASK;
-- 
1.9.1

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Re: [U-Boot] imx: get_ticks in syscounter.c get miscompiled by GCC 6

[Fabio Estevam]

Hi Yasushi ,

On Wed, Mar 7, 2018 at 2:57 AM, Yasushi SHOJI  wrote:

> Do you guys really want to put volatile on all of these now?
> We are at rc4 and Tom is planing to cut the release
> March 12th.

This can be done at a later step.

> I'm attaching a tentative patch to fix only syscounter.c.
> If it looks good, I'l resend it by git-send-email.

Patch looks good. Make sure to add your Signed-off-by line, then you
can send it via git send-email.

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Re: [U-Boot] [PATCH 0/2] [for 2018.03] RPi: Drain RX queue on setbrg

[Alexander Graf]

On 03/07/2018 02:07 PM, Peter Robinson wrote:

On Tue, Mar 6, 2018 at 1:13 PM, Alexander Graf  wrote:

We had a few reports coming in from people that had their autoboot chain
aborted after pinmuxing support was added for the RPi.

The culprit is easy: The UARTs may have been enabled before, but muxed
to an incorrect pin. That pin may have pulled the RX line down which again
lead to lots of zero bytes gathered in the RX buffer.

The easy fix for that is to drain the RX queue every time we set the baud
rate.

This patch set is the minimally intrusive fix for the RPi. We may want to
do that generically for all serial devices later.

Alexander Graf (2):
   serial_bcm283x_mu: Flush RX queue after setting baud rate
   bcm283x_pl011: Flush RX queue after setting baud rate

This causes mixed effects for me, a regression on the RPi2 using the
pl011, but fixes the issue on the RPi3. Both my RPi2 have serial
console and playing with the enable in config.txt doesn't seem to have
any effect on whether they auto boot or not but with it commented out
I seem to get more random chars.


Thanks a lot for testing! I'll try it on a rpi2 later tonight and check 
why it's failing.



Alex

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Re: [U-Boot] [PATCH 0/2] [for 2018.03] RPi: Drain RX queue on setbrg

[Peter Robinson]

On Tue, Mar 6, 2018 at 1:13 PM, Alexander Graf  wrote:
> We had a few reports coming in from people that had their autoboot chain
> aborted after pinmuxing support was added for the RPi.
>
> The culprit is easy: The UARTs may have been enabled before, but muxed
> to an incorrect pin. That pin may have pulled the RX line down which again
> lead to lots of zero bytes gathered in the RX buffer.
>
> The easy fix for that is to drain the RX queue every time we set the baud
> rate.
>
> This patch set is the minimally intrusive fix for the RPi. We may want to
> do that generically for all serial devices later.
>
> Alexander Graf (2):
>   serial_bcm283x_mu: Flush RX queue after setting baud rate
>   bcm283x_pl011: Flush RX queue after setting baud rate

This causes mixed effects for me, a regression on the RPi2 using the
pl011, but fixes the issue on the RPi3. Both my RPi2 have serial
console and playing with the enable in config.txt doesn't seem to have
any effect on whether they auto boot or not but with it commented out
I seem to get more random chars.

Peter
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Re: [U-Boot] [PATCH 2/2] bcm283x_pl011: Flush RX queue after setting baud rate

[Peter Robinson]

On Tue, Mar 6, 2018 at 1:13 PM, Alexander Graf  wrote:
> After the UART was initialized, we may still have bogus data in the
> RX queue if it was enabled with incorrect pin muxing before.
>
> So let's flush the RX queue whenever we initialize baud rates.
>
> This fixes a regression with the dynamic pinmuxing code when enable_uart=1
> is not set in config.txt on Raspberry Pis that use pl011 for serial.

This causes my RPi2 devices not to actually boot. When I connected a
HDMI monitor to one of them I get the rainbow square.

Peter


> Fixes: caf2233b28 ("bcm283x: Add pinctrl driver")
> Reported-by: Göran Lundberg 
> Reported-by: Peter Robinson 
> Signed-off-by: Alexander Graf 
> ---
>  drivers/serial/serial_bcm283x_pl011.c  | 25 -
>  drivers/serial/serial_pl01x.c  | 10 +-
>  drivers/serial/serial_pl01x_internal.h |  7 ++-
>  3 files changed, 35 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/serial/serial_bcm283x_pl011.c 
> b/drivers/serial/serial_bcm283x_pl011.c
> index bfd39f84f3..2c6fb267ff 100644
> --- a/drivers/serial/serial_bcm283x_pl011.c
> +++ b/drivers/serial/serial_bcm283x_pl011.c
> @@ -9,6 +9,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
>  #include "serial_pl01x_internal.h"
>
>  /*
> @@ -55,6 +56,28 @@ static int bcm283x_pl011_serial_ofdata_to_platdata(struct 
> udevice *dev)
> return 0;
>  }
>
> +static int bcm283x_pl011_serial_setbrg(struct udevice *dev, int baudrate)
> +{
> +   int r;
> +
> +   r = pl01x_serial_setbrg(dev, baudrate);
> +
> +   /*
> +* We may have been muxed to a bogus line before. Drain the RX
> +* queue so we start at a clean slate.
> +*/
> +   while (pl01x_serial_getc(dev) == -EAGAIN) ;
> +
> +   return r;
> +}
> +
> +static const struct dm_serial_ops bcm283x_pl011_serial_ops = {
> +   .putc = pl01x_serial_putc,
> +   .pending = pl01x_serial_pending,
> +   .getc = pl01x_serial_getc,
> +   .setbrg = bcm283x_pl011_serial_setbrg,
> +};
> +
>  static const struct udevice_id bcm283x_pl011_serial_id[] = {
> {.compatible = "brcm,bcm2835-pl011", .data = TYPE_PL011},
> {}
> @@ -67,7 +90,7 @@ U_BOOT_DRIVER(bcm283x_pl011_uart) = {
> .ofdata_to_platdata = 
> of_match_ptr(bcm283x_pl011_serial_ofdata_to_platdata),
> .platdata_auto_alloc_size = sizeof(struct pl01x_serial_platdata),
> .probe  = pl01x_serial_probe,
> -   .ops= _serial_ops,
> +   .ops= _pl011_serial_ops,
> .flags  = DM_FLAG_PRE_RELOC,
> .priv_auto_alloc_size = sizeof(struct pl01x_priv),
>  };
> diff --git a/drivers/serial/serial_pl01x.c b/drivers/serial/serial_pl01x.c
> index 23d9d839cb..45f1282770 100644
> --- a/drivers/serial/serial_pl01x.c
> +++ b/drivers/serial/serial_pl01x.c
> @@ -273,7 +273,7 @@ __weak struct serial_device *default_serial_console(void)
>
>  #ifdef CONFIG_DM_SERIAL
>
> -static int pl01x_serial_setbrg(struct udevice *dev, int baudrate)
> +int pl01x_serial_setbrg(struct udevice *dev, int baudrate)
>  {
> struct pl01x_serial_platdata *plat = dev_get_platdata(dev);
> struct pl01x_priv *priv = dev_get_priv(dev);
> @@ -299,21 +299,21 @@ int pl01x_serial_probe(struct udevice *dev)
> return 0;
>  }
>
> -static int pl01x_serial_getc(struct udevice *dev)
> +int pl01x_serial_getc(struct udevice *dev)
>  {
> struct pl01x_priv *priv = dev_get_priv(dev);
>
> return pl01x_getc(priv->regs);
>  }
>
> -static int pl01x_serial_putc(struct udevice *dev, const char ch)
> +int pl01x_serial_putc(struct udevice *dev, const char ch)
>  {
> struct pl01x_priv *priv = dev_get_priv(dev);
>
> return pl01x_putc(priv->regs, ch);
>  }
>
> -static int pl01x_serial_pending(struct udevice *dev, bool input)
> +int pl01x_serial_pending(struct udevice *dev, bool input)
>  {
> struct pl01x_priv *priv = dev_get_priv(dev);
> unsigned int fr = readl(>regs->fr);
> @@ -324,7 +324,7 @@ static int pl01x_serial_pending(struct udevice *dev, bool 
> input)
> return fr & UART_PL01x_FR_TXFF ? 0 : 1;
>  }
>
> -const struct dm_serial_ops pl01x_serial_ops = {
> +static const struct dm_serial_ops pl01x_serial_ops = {
> .putc = pl01x_serial_putc,
> .pending = pl01x_serial_pending,
> .getc = pl01x_serial_getc,
> diff --git a/drivers/serial/serial_pl01x_internal.h 
> b/drivers/serial/serial_pl01x_internal.h
> index c56dd54c7b..d4605f24a3 100644
> --- a/drivers/serial/serial_pl01x_internal.h
> +++ b/drivers/serial/serial_pl01x_internal.h
> @@ -43,7 +43,12 @@ struct pl01x_regs {
>
>  int pl01x_serial_ofdata_to_platdata(struct udevice *dev);
>  int pl01x_serial_probe(struct udevice *dev);
> -extern const struct dm_serial_ops pl01x_serial_ops;
> +
> +/* Needed for external pl01x_serial_ops drivers */
> +int pl01x_serial_putc(struct udevice *dev, const char ch);
> +int 

Re: [U-Boot] [PATCH 1/2] serial_bcm283x_mu: Flush RX queue after setting baud rate

[Peter Robinson]

On Tue, Mar 6, 2018 at 1:13 PM, Alexander Graf  wrote:
> After the UART was initialized, we may still have bogus data in the
> RX queue if it was enabled with incorrect pin muxing before.
>
> So let's flush the RX queue whenever we initialize baud rates.
>
> This fixes a regression with the dynamic pinmuxing code when enable_uart=1
> is not set in config.txt.
>
> Fixes: caf2233b28 ("bcm283x: Add pinctrl driver")
> Reported-by: Göran Lundberg 
> Reported-by: Peter Robinson 
> Signed-off-by: Alexander Graf 

Tested-by: Peter Robinson 

Tested on both 32 bit using extlinux and 64 bit using uEFI boots. The
32 bit one, the one I saw issues with, didn't enable enable_uart
because it's attached to HDMI without a serial console, the 64 does
have serial console with the option in config.txt

> ---
>  drivers/serial/serial_bcm283x_mu.c | 8 +++-
>  1 file changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/serial/serial_bcm283x_mu.c 
> b/drivers/serial/serial_bcm283x_mu.c
> index 40029fadbc..d87b44e902 100644
> --- a/drivers/serial/serial_bcm283x_mu.c
> +++ b/drivers/serial/serial_bcm283x_mu.c
> @@ -51,6 +51,8 @@ struct bcm283x_mu_priv {
> struct bcm283x_mu_regs *regs;
>  };
>
> +static int bcm283x_mu_serial_getc(struct udevice *dev);
> +
>  static int bcm283x_mu_serial_setbrg(struct udevice *dev, int baudrate)
>  {
> struct bcm283x_mu_serial_platdata *plat = dev_get_platdata(dev);
> @@ -59,13 +61,17 @@ static int bcm283x_mu_serial_setbrg(struct udevice *dev, 
> int baudrate)
> u32 divider;
>
> if (plat->skip_init)
> -   return 0;
> +   goto out;
>
> divider = plat->clock / (baudrate * 8);
>
> writel(BCM283X_MU_LCR_DATA_SIZE_8, >lcr);
> writel(divider - 1, >baud);
>
> +out:
> +   /* Flush the RX queue - all data in there is bogus */
> +   while (bcm283x_mu_serial_getc(dev) != -EAGAIN) ;
> +
> return 0;
>  }
>
> --
> 2.12.3
>
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[U-Boot] [PATCH 4/4] am335x: am335x_evm_usbspl_defconfig: NETCONSOLE

[Jason Kridner]

Enable NETCONSOLE by default. Still requires changes to the boot
environment to enable on the platform.

Signed-of-by: Jason Kridner 
Cc: Tom Rini 
---
 configs/am335x_evm_usbspl_defconfig | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/configs/am335x_evm_usbspl_defconfig 
b/configs/am335x_evm_usbspl_defconfig
index e4bf757923..19f7c49951 100644
--- a/configs/am335x_evm_usbspl_defconfig
+++ b/configs/am335x_evm_usbspl_defconfig
@@ -6,7 +6,13 @@ CONFIG_AM33XX=y
 CONFIG_DISTRO_DEFAULTS=y
 # CONFIG_ANDROID_BOOT_IMAGE is not set
 CONFIG_BOOTCOMMAND="if test ${boot_fit} -eq 1; then run update_to_fit; fi; run 
findfdt; run init_console; run envboot; run distro_bootcmd"
+CONFIG_CONSOLE_MUX=y
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+# CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE is not set
+CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
 CONFIG_SYS_CONSOLE_INFO_QUIET=y
+# CONFIG_SYS_STDIO_DEREGISTER is not set
+# CONFIG_FIT_EMBED is not set
 CONFIG_VERSION_VARIABLE=y
 CONFIG_ARCH_MISC_INIT=y
 CONFIG_SPL=y
@@ -50,3 +56,4 @@ CONFIG_USB_ETHER=y
 CONFIG_LZO=y
 CONFIG_OF_LIBFDT=y
 CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_NETCONSOLE=y
-- 
2.15.1

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[U-Boot] [PATCH 2/4] am335x_evm: scan more partitions and use uname_r

[Jason Kridner]

This enables mainline u-boot to boot the BeagleBoard.org Debian
distribution builds without extensive environment modifications.

Some boot layouts only have a single partition on the
MMC/eMMC. This will scan those partitions after the second
partition that was already being scanned.

Some layouts use uname_r to define the kernel being used for the boot to
support multiple kernels stored within the boot file system without
using symlinks.

See http://elinux.org/Beagleboard:U-boot_partitioning_layout_2.0 for
more details on the BeagleBoard.org Debian image layout.

Signed-off-by: Jason Kridner 
Cc: Robert Nelson 
Cc: Tom Rini 
---
 include/configs/am335x_evm.h |  5 -
 include/environment/ti/mmc.h | 13 +
 2 files changed, 13 insertions(+), 5 deletions(-)

diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h
index 8d45b6fade..32fe0e0cd5 100644
--- a/include/configs/am335x_evm.h
+++ b/include/configs/am335x_evm.h
@@ -61,7 +61,10 @@
 #define BOOTENV_DEV_LEGACY_MMC(devtypeu, devtypel, instance) \
"bootcmd_" #devtypel #instance "=" \
"setenv mmcdev " #instance"; "\
-   "setenv bootpart " #instance":2 ; "\
+   "setenv bootpart " #instance":2; "\
+   "run mmcboot;"\
+   "setenv mmcdev " #instance"; "\
+   "setenv bootpart " #instance":1; "\
"run mmcboot\0"
 
 #define BOOTENV_DEV_NAME_LEGACY_MMC(devtypeu, devtypel, instance) \
diff --git a/include/environment/ti/mmc.h b/include/environment/ti/mmc.h
index 4305ebdaaf..b803ecccb7 100644
--- a/include/environment/ti/mmc.h
+++ b/include/environment/ti/mmc.h
@@ -23,9 +23,10 @@
"bootenvfile=uEnv.txt\0" \
"importbootenv=echo Importing environment from mmc${mmcdev} ...; " \
"env import -t ${loadaddr} ${filesize}\0" \
-   "loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenvfile}\0" \
-   "loadimage=load ${devtype} ${bootpart} ${loadaddr} 
${bootdir}/${bootfile}\0" \
-   "loadfdt=load ${devtype} ${bootpart} ${fdtaddr} 
${bootdir}/${fdtfile}\0" \
+   "loadbootenv=if fatload mmc ${mmcdev} ${loadaddr} 
${bootdir}/${bootenvfile}; then echo Found ${bootdir}/${bootenvfile} in FAT 
partition; else load mmc ${mmcdev} ${loadaddr} ${bootdir}/${bootenvfile}; fi\0" 
\
+   "loadimage=if test -n ${uname_r}; then load ${devtype} ${bootpart} 
${loadaddr} ${bootdir}/vmlinuz-${uname_r}; run loadrd; else load ${devtype} 
${bootpart} ${loadaddr} ${bootdir}/${bootfile}; fi\0" \
+   "loadrd=load ${devtype} ${bootpart} ${rdaddr} 
${bootdir}/initrd.img-${uname_r}; setenv rdsize ${filesize}\0" \
+   "loadfdt=if test -n ${uname_r}; then load ${devtype} ${bootpart} 
${fdtaddr} ${bootdir}/dtbs/${uname_r}/${fdtfile}; else load ${devtype} 
${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}; fi;\0" \
"envboot=mmc dev ${mmcdev}; " \
"if mmc rescan; then " \
"echo SD/MMC found on device ${mmcdev};" \
@@ -45,7 +46,11 @@
"mmcloados=run args_mmc; " \
"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
"if run loadfdt; then " \
-   "bootz ${loadaddr} - ${fdtaddr}; " \
+   "if test -n ${uname_r}; then " \
+   "bootz ${loadaddr} ${rdaddr}:${rdsize} 
${fdtaddr}; " \
+   "else " \
+   "bootz ${loadaddr} - ${fdtaddr}; " \
+   "fi; " \
"else " \
"if test ${boot_fdt} = try; then " \
"bootz; " \
-- 
2.15.1

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[U-Boot] [PATCH 3/4] Handle NETCONSOLE and SPL enabled

[Jason Kridner]

From: Jason Kridner 

NETCONSOLE isn't compiled in with SPL, so the include file needs to recognize 
that.

Signed-off-by: Jason Kridner 
Cc: Joe Hershberger 
---
 include/net.h | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/include/net.h b/include/net.h
index 455b48f6c7..3101096e9a 100644
--- a/include/net.h
+++ b/include/net.h
@@ -676,7 +676,7 @@ int net_send_udp_packet(uchar *ether, struct in_addr dest, 
int dport,
 /* Processes a received packet */
 void net_process_received_packet(uchar *in_packet, int len);
 
-#ifdef CONFIG_NETCONSOLE
+#if defined(CONFIG_NETCONSOLE) && !defined(CONFIG_SPL_BUILD)
 void nc_start(void);
 int nc_input_packet(uchar *pkt, struct in_addr src_ip, unsigned dest_port,
unsigned src_port, unsigned len);
@@ -684,7 +684,7 @@ int nc_input_packet(uchar *pkt, struct in_addr src_ip, 
unsigned dest_port,
 
 static __always_inline int eth_is_on_demand_init(void)
 {
-#ifdef CONFIG_NETCONSOLE
+#if defined(CONFIG_NETCONSOLE) && !defined(CONFIG_SPL_BUILD)
extern enum proto_t net_loop_last_protocol;
 
return net_loop_last_protocol != NETCONS;
@@ -695,7 +695,7 @@ static __always_inline int eth_is_on_demand_init(void)
 
 static inline void eth_set_last_protocol(int protocol)
 {
-#ifdef CONFIG_NETCONSOLE
+#if defined(CONFIG_NETCONSOLE) && !defined(CONFIG_SPL_BUILD)
extern enum proto_t net_loop_last_protocol;
 
net_loop_last_protocol = protocol;
-- 
2.15.1

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[U-Boot] [PATCH 1/4] Add support for BeagleBoard.org PocketBeagle

[Jason Kridner]

Texas Instruments AM3358 based low-cost board using Octavo Systems OSD3358 SIP
with built-in TPS65217 PMIC and 512MB DDR3. Board features small 35mm x
55mm size, high-speed USB OTG, microSD and 72 0.1" expansion header
pins with 2xSPI, 2xI2C, 2xUART, USB, 8xADC, up-to-44 GPIO, PRU pins and much 
more.

https://beagleboard.org/pocket

This was tested using the am335x_evm_usbspl_defconfig.

Note that MII pins are enabled despite not having Ethernet on this
board. This avoids an issue where otherwise many timeout errors would be
generated. See https://e2e.ti.com/support/arm/sitara_arm/f/791/t/298976
for some related discussion.

Signed-off-by: Jason Kridner 
Cc: Tom Rini 
---
 board/ti/am335x/board.c  | 10 ++
 board/ti/am335x/board.h  |  7 ++-
 board/ti/am335x/mux.c|  3 +++
 include/configs/am335x_evm.h |  2 ++
 4 files changed, 17 insertions(+), 5 deletions(-)

diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c
index b144fd1821..87bdd2d63d 100644
--- a/board/ti/am335x/board.c
+++ b/board/ti/am335x/board.c
@@ -264,7 +264,7 @@ const struct dpll_params *get_dpll_ddr_params(void)
 
if (board_is_evm_sk())
return _ddr3_303MHz[ind];
-   else if (board_is_bone_lt() || board_is_icev2())
+   else if (board_is_pb() || board_is_bone_lt() || board_is_icev2())
return _ddr3_400MHz[ind];
else if (board_is_evm_15_or_later())
return _ddr3_303MHz[ind];
@@ -295,7 +295,7 @@ const struct dpll_params *get_dpll_mpu_params(void)
if (bone_not_connected_to_ac_power())
freq = MPUPLL_M_600;
 
-   if (board_is_bone_lt())
+   if (board_is_pb() || board_is_bone_lt())
freq = MPUPLL_M_1000;
 
switch (freq) {
@@ -341,7 +341,7 @@ static void scale_vcores_bone(int freq)
 * Override what we have detected since we know if we have
 * a Beaglebone Black it supports 1GHz.
 */
-   if (board_is_bone_lt())
+   if (board_is_pb() || board_is_bone_lt())
freq = MPUPLL_M_1000;
 
switch (freq) {
@@ -542,7 +542,7 @@ void sdram_init(void)
if (board_is_evm_sk())
config_ddr(303, _evmsk, _data,
   _cmd_ctrl_data, _emif_reg_data, 0);
-   else if (board_is_bone_lt())
+   else if (board_is_pb() || board_is_bone_lt())
config_ddr(400, _bonelt,
   _beagleblack_data,
   _beagleblack_cmd_ctrl_data,
@@ -931,6 +931,8 @@ int board_fit_config_name_match(const char *name)
return 0;
else if (board_is_bone_lt() && !strcmp(name, "am335x-boneblack"))
return 0;
+   else if (board_is_pb() && !strcmp(name, "am335x-pocketbeagle"))
+   return 0;
else if (board_is_evm_sk() && !strcmp(name, "am335x-evmsk"))
return 0;
else if (board_is_bbg1() && !strcmp(name, "am335x-bonegreen"))
diff --git a/board/ti/am335x/board.h b/board/ti/am335x/board.h
index e13fcff02a..bab5b77f34 100644
--- a/board/ti/am335x/board.h
+++ b/board/ti/am335x/board.h
@@ -34,6 +34,11 @@ static inline int board_is_bone_lt(void)
return board_ti_is("A335BNLT");
 }
 
+static inline int board_is_pb(void)
+{
+   return board_ti_is("A335PBGL");
+}
+
 static inline int board_is_bbg1(void)
 {
return board_is_bone_lt() && !strncmp(board_ti_get_rev(), "BBG1", 4);
@@ -41,7 +46,7 @@ static inline int board_is_bbg1(void)
 
 static inline int board_is_beaglebonex(void)
 {
-   return board_is_bone() || board_is_bone_lt() || board_is_bbg1();
+   return board_is_pb() || board_is_bone() || board_is_bone_lt() || 
board_is_bbg1();
 }
 
 static inline int board_is_evm_sk(void)
diff --git a/board/ti/am335x/mux.c b/board/ti/am335x/mux.c
index ad85b3a19a..aa187605d0 100644
--- a/board/ti/am335x/mux.c
+++ b/board/ti/am335x/mux.c
@@ -390,6 +390,9 @@ void enable_board_pin_mux(void)
 #else
configure_module_pin_mux(mmc1_pin_mux);
 #endif
+   } else if (board_is_pb()) {
+   configure_module_pin_mux(mii1_pin_mux);
+   configure_module_pin_mux(mmc0_pin_mux);
} else if (board_is_icev2()) {
configure_module_pin_mux(mmc0_pin_mux);
configure_module_pin_mux(gpio0_18_pin_mux);
diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h
index 158b7d4e8e..8d45b6fade 100644
--- a/include/configs/am335x_evm.h
+++ b/include/configs/am335x_evm.h
@@ -133,6 +133,8 @@
"setenv fdtfile am335x-bone.dtb; fi; " \
"if test $board_name = A335BNLT; then " \
"setenv fdtfile am335x-boneblack.dtb; fi; " \
+   "if test $board_name = A335PBGL; then " \
+   "setenv fdtfile am335x-pocketbeagle.dtb; fi; " \
"if test $board_name = BBBW; then " \
"setenv fdtfile 

[U-Boot] [PATCH 0/4] Add support for BeagleBoard.org PocketBeagle

[Jason Kridner]

This series sets up the am335x_evm_usbspl_defconfig to boot the TI
AM335x based BeagleBoard.org PocketBeagle using the BeagleBoard.org
provided Debian images and enables NETCONSOLE over USB when the
environment is updated as needed.

Jason Kridner (4):
  Add support for BeagleBoard.org PocketBeagle
  am335x_evm: scan more partitions and use uname_r
  Handle NETCONSOLE and SPL enabled
  am335x: am335x_evm_usbspl_defconfig: NETCONSOLE

 board/ti/am335x/board.c | 10 ++
 board/ti/am335x/board.h |  7 ++-
 board/ti/am335x/mux.c   |  3 +++
 configs/am335x_evm_usbspl_defconfig |  7 +++
 include/configs/am335x_evm.h|  7 ++-
 include/environment/ti/mmc.h| 13 +
 include/net.h   |  6 +++---
 7 files changed, 40 insertions(+), 13 deletions(-)

-- 
2.15.1

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Re: [U-Boot] [PATCH] omap3_logic: Enable DM_SPI

[Jagan Teki]

On Wed, Mar 7, 2018 at 4:53 PM, Adam Ford  wrote:
> With the introduction of ("Boards,Need,to,Switch,DM] spi: omap3_spi:
> Full dm conversion"), Driver Model for McSPI is now available on the
> omap3.  This enables the config by default on omap3_logic boards.
>
> Signed-off-by: Adam Ford 

Reviewed-by: Jagan Teki 
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[U-Boot] [PATCH] omap3_logic: Enable DM_SPI

[Adam Ford]

With the introduction of ("Boards,Need,to,Switch,DM] spi: omap3_spi:
Full dm conversion"), Driver Model for McSPI is now available on the
omap3.  This enables the config by default on omap3_logic boards.

Signed-off-by: Adam Ford 

diff --git a/configs/omap3_logic_defconfig b/configs/omap3_logic_defconfig
index c3e999e..519b2a0 100644
--- a/configs/omap3_logic_defconfig
+++ b/configs/omap3_logic_defconfig
@@ -47,6 +47,7 @@ CONFIG_SMC911X=y
 CONFIG_SMC911X_BASE=0x0800
 CONFIG_SMC911X_32_BIT=y
 CONFIG_SYS_NS16550=y
+CONFIG_DM_SPI=y
 CONFIG_OMAP3_SPI=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
-- 
2.7.4

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Re: [U-Boot] [PATCH v2 2/2][Boards Need to Switch DM] spi: omap3_spi: Full dm conversion

[Adam Ford]

On Tue, Mar 6, 2018 at 11:00 PM, Jagan Teki  wrote:
> omap3_spi now support dt along with platform data,
> respective boards need to switch into dm for the same.
>
> Signed-off-by: Jagan Teki 
> ---
> Changes for v2:
> - Fixes omap3_spi_ofdata_to_platdata, build

Thanks for fixing that.
>

Tested-by: Adam Ford  #omap3_logic

>  drivers/spi/Kconfig  |  14 +-
>  drivers/spi/omap3_spi.c  | 342 
> +++
>  include/dm/platform_data/spi_omap3.h |  16 ++
>  3 files changed, 125 insertions(+), 247 deletions(-)
>  create mode 100644 include/dm/platform_data/spi_omap3.h
>
> diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
> index fd3f115ccf..56c337f664 100644
> --- a/drivers/spi/Kconfig
> +++ b/drivers/spi/Kconfig
> @@ -99,6 +99,13 @@ config MVEBU_A3700_SPI
>   used to access the SPI NOR flash on platforms embedding this
>   Marvell IP core.
>
> +config OMAP3_SPI
> +   bool "McSPI driver for OMAP"
> +   help
> + SPI master controller for OMAP24XX and later Multichannel SPI
> + (McSPI). This driver be used to access SPI chips on platforms
> + embedding this OMAP3 McSPI IP core.
> +
>  config PIC32_SPI
> bool "Microchip PIC32 SPI driver"
> depends on MACH_PIC32
> @@ -291,11 +298,4 @@ config MXS_SPI
>   Enable the MXS SPI controller driver. This driver can be used
>   on the i.MX23 and i.MX28 SoCs.
>
> -config OMAP3_SPI
> -   bool "McSPI driver for OMAP"
> -   help
> - SPI master controller for OMAP24XX and later Multichannel SPI
> - (McSPI). This driver be used to access SPI chips on platforms
> - embedding this OMAP3 McSPI IP core.
> -
>  endmenu # menu "SPI Support"
> diff --git a/drivers/spi/omap3_spi.c b/drivers/spi/omap3_spi.c
> index b8a0bf495a..a6f1533985 100644
> --- a/drivers/spi/omap3_spi.c
> +++ b/drivers/spi/omap3_spi.c
> @@ -22,6 +22,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
>
>  DECLARE_GLOBAL_DATA_PTR;
>
> @@ -109,9 +110,6 @@ struct mcspi {
>  };
>
>  struct omap3_spi_priv {
> -#ifndef CONFIG_DM_SPI
> -   struct spi_slave slave;
> -#endif
> struct mcspi *regs;
> unsigned int cs;
> unsigned int freq;
> @@ -312,12 +310,16 @@ static int omap3_spi_txrx(struct omap3_spi_priv *priv, 
> unsigned int len,
> return 0;
>  }
>
> -static int _spi_xfer(struct omap3_spi_priv *priv, unsigned int bitlen,
> -const void *dout, void *din, unsigned long flags)
> +static int omap3_spi_xfer(struct udevice *dev, unsigned int bitlen,
> + const void *dout, void *din, unsigned long flags)
>  {
> -   unsigned intlen;
> +   struct udevice *bus = dev->parent;
> +   struct omap3_spi_priv *priv = dev_get_priv(bus);
> +   struct dm_spi_slave_platdata *slave_plat = 
> dev_get_parent_platdata(dev);
> +   unsigned int len;
> int ret = -1;
>
> +   priv->cs = slave_plat->cs;
> if (priv->wordlen < 4 || priv->wordlen > 32) {
> printf("omap3_spi: invalid wordlen %d\n", priv->wordlen);
> return -1;
> @@ -353,78 +355,6 @@ static int _spi_xfer(struct omap3_spi_priv *priv, 
> unsigned int bitlen,
> return ret;
>  }
>
> -static void _omap3_spi_set_speed(struct omap3_spi_priv *priv)
> -{
> -   uint32_t confr, div = 0;
> -
> -   confr = readl(>regs->channel[priv->cs].chconf);
> -
> -   /* Calculate clock divisor. Valid range: 0x0 - 0xC ( /1 - /4096 ) */
> -   if (priv->freq) {
> -   while (div <= 0xC && (OMAP3_MCSPI_MAX_FREQ / (1 << div))
> -   > priv->freq)
> -   div++;
> -   } else {
> -div = 0xC;
> -   }
> -
> -   /* set clock divisor */
> -   confr &= ~OMAP3_MCSPI_CHCONF_CLKD_MASK;
> -   confr |= div << 2;
> -
> -   omap3_spi_write_chconf(priv, confr);
> -}
> -
> -static void _omap3_spi_set_mode(struct omap3_spi_priv *priv)
> -{
> -   uint32_t confr;
> -
> -   confr = readl(>regs->channel[priv->cs].chconf);
> -
> -   /* standard 4-wire master mode:  SCK, MOSI/out, MISO/in, nCS
> -* REVISIT: this controller could support SPI_3WIRE mode.
> -*/
> -   if (priv->pin_dir == MCSPI_PINDIR_D0_IN_D1_OUT) {
> -   confr &= ~(OMAP3_MCSPI_CHCONF_IS|OMAP3_MCSPI_CHCONF_DPE1);
> -   confr |= OMAP3_MCSPI_CHCONF_DPE0;
> -   } else {
> -   confr &= ~OMAP3_MCSPI_CHCONF_DPE0;
> -   confr |= OMAP3_MCSPI_CHCONF_IS|OMAP3_MCSPI_CHCONF_DPE1;
> -   }
> -
> -   /* set SPI mode 0..3 */
> -   confr &= ~(OMAP3_MCSPI_CHCONF_POL | OMAP3_MCSPI_CHCONF_PHA);
> -   if (priv->mode & SPI_CPHA)
> -   confr |= OMAP3_MCSPI_CHCONF_PHA;
> -   if (priv->mode & SPI_CPOL)
> -   confr |= OMAP3_MCSPI_CHCONF_POL;
> -
> -   

Re: [U-Boot] [PATCH] spi: atcspi200: Full dm conversion

[Jagan Teki]

On 07-Mar-2018 1:12 PM, "陳建志"  wrote:

2018-03-07 15:20 GMT+08:00 Jagan Teki :
> On Wed, Mar 7, 2018 at 12:34 PM, Andes  wrote:
>> From: Rick Chen 
>>
>> atcspi200_spi now support dt along with platform data.
>>
>> Signed-off-by: Rick Chen 
>> Signed-off-by: Rick Chen 
>> Signed-off-by: Greentime Hu 
>> ---
>>  drivers/spi/atcspi200_spi.c  |  134
++
>>  include/dm/platform_data/spi_atcspi200.h |   15 
>
> I have seen only two boards using this driver (adp-ae3xx_defconfig,
> nx25-ae250_defconfig) and both are enabled DM_SPI with OF_CONTROL why
> we need to have platdata for this? here [1] is non-dm code drop.
>
> [1] https://patchwork.ozlabs.org/patch/882404/

Hi Tagan Teki

I just refer to [PATCH][Boards Need to Switch DM] spi: davinci: Full
dm conversion
And have this modification.

So it is not necessary to add platdata for atcspi200_spi, just drop
non-dm code, right ?


There are two boards using this driver adp-ae3xx_defconfig and
nx25-ae250_defconfig,
both of them use DM_SPL with dr. With this reason it is not require to add
pdata here?
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[U-Boot] [PATCH 2/2] dm: led: auto probe() LEDs with "default-state"

[linux-kernel-dev]

From: Patrick Bruenn 

To avoid board specificy LED activation code, automatically
activate gpio-leds with "default-state" property during bind().

Signed-off-by: Patrick Bruenn 
---

 drivers/led/led_gpio.c | 9 +
 1 file changed, 9 insertions(+)

diff --git a/drivers/led/led_gpio.c b/drivers/led/led_gpio.c
index e68d8d3864..d2fe3d5ad5 100644
--- a/drivers/led/led_gpio.c
+++ b/drivers/led/led_gpio.c
@@ -11,6 +11,7 @@
 #include 
 #include 
 #include 
+#include 
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -120,6 +121,14 @@ static int led_gpio_bind(struct udevice *parent)
return ret;
uc_plat = dev_get_uclass_platdata(dev);
uc_plat->label = label;
+
+   if (ofnode_read_string(node, "default-state")) {
+   struct udevice *devp;
+
+   ret = uclass_get_device_tail(dev, 0, );
+   if (ret)
+   return ret;
+   }
}
 
return 0;
-- 
2.11.0


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[U-Boot] [PATCH 1/2] dm: led: Support "default-state" property

[linux-kernel-dev]

From: Patrick Bruenn 

Add support for the device tree property "default-state". This feature
might be useful for LEDs indicating "power on" or similar states.

Note: Even with this commit gpio-leds remain in reset state. That's
because the led_gpio is not probed until DM_FLAG_ACTIVATED is set.

Signed-off-by: Patrick Bruenn 

---

 drivers/led/led_gpio.c | 16 +++-
 1 file changed, 15 insertions(+), 1 deletion(-)

diff --git a/drivers/led/led_gpio.c b/drivers/led/led_gpio.c
index 9976635887..e68d8d3864 100644
--- a/drivers/led/led_gpio.c
+++ b/drivers/led/led_gpio.c
@@ -60,11 +60,25 @@ static int led_gpio_probe(struct udevice *dev)
 {
struct led_uc_plat *uc_plat = dev_get_uclass_platdata(dev);
struct led_gpio_priv *priv = dev_get_priv(dev);
+   const char *default_state;
+   int ret;
 
/* Ignore the top-level LED node */
if (!uc_plat->label)
return 0;
-   return gpio_request_by_name(dev, "gpios", 0, >gpio, GPIOD_IS_OUT);
+
+   ret = gpio_request_by_name(dev, "gpios", 0, >gpio, GPIOD_IS_OUT);
+   if (ret)
+   return ret;
+
+   default_state = dev_read_string(dev, "default-state");
+   if (default_state) {
+   if (!strncmp(default_state, "on", 2))
+   gpio_led_set_state(dev, LEDST_ON);
+   else if (!strncmp(default_state, "off", 3))
+   gpio_led_set_state(dev, LEDST_OFF);
+   }
+   return 0;
 }
 
 static int led_gpio_remove(struct udevice *dev)
-- 
2.11.0


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[U-Boot] [PATCH 0/2] This series adds support for gpio-leds "default-state" property. The

[linux-kernel-dev]

From: Patrick Bruenn 

main usecase in mind are LEDs which indicate a state like "power on".
With this patchset applied, all you have to do is:
Add a gpio-led node with 'default-state = "on";' property to your device
tree. And the LED will automatically light up during U-Boot startup.


Patrick Bruenn (2):
  dm: led: Support "default-state" property
  dm: led: auto probe() LEDs with "default-state"

 drivers/led/led_gpio.c | 25 -
 1 file changed, 24 insertions(+), 1 deletion(-)

-- 
2.11.0


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[U-Boot] [PATCH v2 3/3] ubs: xhci-dwc3: Enable USB3 PHY when available

[Vignesh R]

DWC3 USB3 controllers will need USB3 PHY to be enabled, in addition to
USB2 PHY, to be functional. Therefore enable USB3 PHY when available.

Signed-off-by: Vignesh R 
---
 drivers/usb/host/xhci-dwc3.c | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/drivers/usb/host/xhci-dwc3.c b/drivers/usb/host/xhci-dwc3.c
index e61a04eeb8a8..1022dd551241 100644
--- a/drivers/usb/host/xhci-dwc3.c
+++ b/drivers/usb/host/xhci-dwc3.c
@@ -23,6 +23,7 @@ DECLARE_GLOBAL_DATA_PTR;
 
 struct xhci_dwc3_platdata {
struct phy usb_phy;
+   struct phy usb3_phy;
 };
 
 void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode)
@@ -175,6 +176,13 @@ static int xhci_dwc3_probe(struct udevice *dev)
return ret;
}
 
+   ret = xhci_dwc3_setup_phy(dev, 1, >usb3_phy);
+   if (ret) {
+   pr_err("Failed to setup USB3 PHY for %s\n", dev->name);
+   xhci_dwc3_shutdown_phy(>usb_phy);
+   return ret;
+   }
+
dwc3_reg = (struct dwc3 *)((char *)(hccr) + DWC3_REG_OFFSET);
 
dwc3_core_init(dwc3_reg);
@@ -198,6 +206,9 @@ static int xhci_dwc3_remove(struct udevice *dev)
if (ret)
pr_err("Can't shutdown USB PHY for %s\n", dev->name);
 
+   ret = xhci_dwc3_shutdown_phy(>usb3_phy);
+   if (ret)
+   pr_err("Can't shutdown USB3 PHY for %s\n", dev->name);
 
return xhci_deregister(dev);
 }
-- 
2.16.2

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[U-Boot] [PATCH v2 2/3] usb: xhci-dwc3: Refractor PHY operations into separate function

[Vignesh R]

Refractor PHY get/init/poweron and PHY poweroff/exit operations into
separate function so that its easy to support multiple PHYs.

Signed-off-by: Vignesh R 
---
 drivers/usb/host/xhci-dwc3.c | 75 
 1 file changed, 48 insertions(+), 27 deletions(-)

diff --git a/drivers/usb/host/xhci-dwc3.c b/drivers/usb/host/xhci-dwc3.c
index cf1986bebd07..e61a04eeb8a8 100644
--- a/drivers/usb/host/xhci-dwc3.c
+++ b/drivers/usb/host/xhci-dwc3.c
@@ -112,39 +112,69 @@ void dwc3_set_fladj(struct dwc3 *dwc3_reg, u32 val)
 }
 
 #ifdef CONFIG_DM_USB
-static int xhci_dwc3_probe(struct udevice *dev)
+static int xhci_dwc3_setup_phy(struct udevice *dev, int index, struct phy *phy)
 {
-   struct xhci_dwc3_platdata *plat = dev_get_platdata(dev);
-   struct xhci_hcor *hcor;
-   struct xhci_hccr *hccr;
-   struct dwc3 *dwc3_reg;
-   enum usb_dr_mode dr_mode;
-   int ret;
-
-   hccr = (struct xhci_hccr *)((uintptr_t)dev_read_addr(dev));
-   hcor = (struct xhci_hcor *)((uintptr_t)hccr +
-   HC_LENGTH(xhci_readl(&(hccr)->cr_capbase)));
+   int ret = 0;
 
-   ret = generic_phy_get_by_index(dev, 0, >usb_phy);
+   ret = generic_phy_get_by_index(dev, index, phy);
if (ret) {
if (ret != -ENOENT) {
pr_err("Failed to get USB PHY for %s\n", dev->name);
return ret;
}
} else {
-   ret = generic_phy_init(>usb_phy);
+   ret = generic_phy_init(phy);
if (ret) {
pr_err("Can't init USB PHY for %s\n", dev->name);
return ret;
}
-
-   ret = generic_phy_power_on(>usb_phy);
+   ret = generic_phy_power_on(phy);
if (ret) {
pr_err("Can't power on USB PHY for %s\n", dev->name);
+   generic_phy_exit(phy);
return ret;
}
}
 
+   return 0;
+}
+
+static int xhci_dwc3_shutdown_phy(struct phy *phy)
+{
+   int ret = 0;
+
+   if (generic_phy_valid(phy)) {
+   ret = generic_phy_power_off(phy);
+   if (ret)
+   return ret;
+
+   ret = generic_phy_exit(phy);
+   if (ret)
+   return ret;
+   }
+
+   return 0;
+}
+
+static int xhci_dwc3_probe(struct udevice *dev)
+{
+   struct xhci_dwc3_platdata *plat = dev_get_platdata(dev);
+   struct xhci_hcor *hcor;
+   struct xhci_hccr *hccr;
+   struct dwc3 *dwc3_reg;
+   enum usb_dr_mode dr_mode;
+   int ret;
+
+   hccr = (struct xhci_hccr *)((uintptr_t)dev_read_addr(dev));
+   hcor = (struct xhci_hcor *)((uintptr_t)hccr +
+   HC_LENGTH(xhci_readl(&(hccr)->cr_capbase)));
+
+   ret = xhci_dwc3_setup_phy(dev, 0, >usb_phy);
+   if (ret) {
+   pr_err("Failed to setup USB PHY for %s\n", dev->name);
+   return ret;
+   }
+
dwc3_reg = (struct dwc3 *)((char *)(hccr) + DWC3_REG_OFFSET);
 
dwc3_core_init(dwc3_reg);
@@ -164,19 +194,10 @@ static int xhci_dwc3_remove(struct udevice *dev)
struct xhci_dwc3_platdata *plat = dev_get_platdata(dev);
int ret;
 
-   if (generic_phy_valid(>usb_phy)) {
-   ret = generic_phy_power_off(>usb_phy);
-   if (ret) {
-   pr_err("Can't poweroff USB PHY for %s\n", dev->name);
-   return ret;
-   }
+   ret = xhci_dwc3_shutdown_phy(>usb_phy);
+   if (ret)
+   pr_err("Can't shutdown USB PHY for %s\n", dev->name);
 
-   ret = generic_phy_exit(>usb_phy);
-   if (ret) {
-   pr_err("Can't deinit USB PHY for %s\n", dev->name);
-   return ret;
-   }
-   }
 
return xhci_deregister(dev);
 }
-- 
2.16.2

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[U-Boot] [PATCH v2 0/3] xhci-dwc3: Couple of fixes for USB3 support

[Vignesh R]

This series has couple of fixes needed to get DWC3 USB3 controller to
talk to USB3 devices on AM57xx SoCs.

v2:
* Refractor PHY operations into separate functions.


Vignesh R (3):
  usb: xhci-dwc3: Power on USB PHY before using
  usb: xhc-dwc3: Refractor PHY operations into separate function
  ubs: xhci-dwc3: Enable USB3 PHY when available

 drivers/usb/host/xhci-dwc3.c | 80 ++--
 1 file changed, 62 insertions(+), 18 deletions(-)

-- 
2.16.2

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[U-Boot] [PATCH v2 1/3] usb: xhci-dwc3: Power on USB PHY before using

[Vignesh R]

It is wrong that expect .phy_init() to also power on the PHY. Therefore,
explicitly, call generic_phy_power_on() after generic_phy_power_init() in
order to power on PHY before using it.

Signed-off-by: Vignesh R 
Reviewed-by: Bin Meng 
---
 drivers/usb/host/xhci-dwc3.c | 12 
 1 file changed, 12 insertions(+)

diff --git a/drivers/usb/host/xhci-dwc3.c b/drivers/usb/host/xhci-dwc3.c
index 258d1cd00a08..cf1986bebd07 100644
--- a/drivers/usb/host/xhci-dwc3.c
+++ b/drivers/usb/host/xhci-dwc3.c
@@ -137,6 +137,12 @@ static int xhci_dwc3_probe(struct udevice *dev)
pr_err("Can't init USB PHY for %s\n", dev->name);
return ret;
}
+
+   ret = generic_phy_power_on(>usb_phy);
+   if (ret) {
+   pr_err("Can't power on USB PHY for %s\n", dev->name);
+   return ret;
+   }
}
 
dwc3_reg = (struct dwc3 *)((char *)(hccr) + DWC3_REG_OFFSET);
@@ -159,6 +165,12 @@ static int xhci_dwc3_remove(struct udevice *dev)
int ret;
 
if (generic_phy_valid(>usb_phy)) {
+   ret = generic_phy_power_off(>usb_phy);
+   if (ret) {
+   pr_err("Can't poweroff USB PHY for %s\n", dev->name);
+   return ret;
+   }
+
ret = generic_phy_exit(>usb_phy);
if (ret) {
pr_err("Can't deinit USB PHY for %s\n", dev->name);
-- 
2.16.2

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Re: [U-Boot] [PATCH RFC 0/2] sunxi: Build u-boot-sunxi-with-spl.bin on ARM64 as well

[Maxime Ripard]

On Tue, Mar 06, 2018 at 11:38:20PM +0200, Tuomas Tynkkynen wrote:
> For some reason we seem to have documented how to build
> u-boot-sunxi-with-spl.bin manually with cat but not have a build system
> rule for it. Let's fix this to have the file built by default just like
> it is on 32-bit sunxi boards.
> 
> Build-tested only.

Acked-by: Maxime Ripard 

Thanks!
Maxime

-- 
Maxime Ripard, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com


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