Re: [RFC Patch] arm: kirkwood: nsa310s: Use Marvell uclass mvgbe and PHY driver for DM Ethernet

[Tony Dinh]

On Thu, Apr 7, 2022 at 10:39 PM Stefan Roese  wrote:
>
> Hi Tony,
>
> On 4/8/22 07:03, Tony Dinh wrote:
> > Hi all,
> >
> > This is a work-in-progress patch that I'm working on, to clean up the
> > DM Ethernet code for the Zyxel NSA310S board (Kirkwood 88F6702 A1).
> >
> > This NSA310s board Ethernet has some quirks that it does not work
> > quite the same way as other Kirwood boards with the similar network
> > chip (MV88E1318), such as the Sheevaplug and the Dreamplug.
> >
> > Currently, in the NSA310S board file we use CONFIG_RESET_PHY_R to
> > execute reset_phy() during initialization. And the reset_phy() code in
> > this board file is ad-hoc, does not involve  Marvell PHY driver (which
> > it should be). So I'm following the same pattern that I've done for
> > the Sheevaplug: use the uclass drivers/net/mvgbe.c (CONFIG_MVGBE) to
> > bring up Ethernet, removing the reset_phy() code, and enable
> > CONFIG_PHY_MARVEL.
> >
> > With this board, I could not get it to work the same way as for the
> > Sheevaplug to bring up the PHY automatically. I had to insert the
> > ad-hoc code to set RGMII delay in the __mvgbe_phy_init() function in
> > mvgbe.c, so the phy_connect() call will find the PHY. The PHY Id is
> > 1410e90, same as in the Sheevaplug and Dreamplug. Please see this in
> > the patch below (it's only a hack to see the PHY can be brought up
> > this way).
>
> Looking at drivers/net/phy/marvell.c I see that m88e1310_config()
> does exactly this rx/tx delay configuration:
>
> /* Marvell 88E1310 */
> static int m88e1310_config(struct phy_device *phydev)
> {
> ...
> /* Set RGMII delay */
> phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_PAGE, 0x0002);
> reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_RGMII_CTRL);
> reg |= 0x0030;
> phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_RGMII_CTRL, reg);
>
> Are you sure that this functions is not called while probing /
> enabling the network interface?
>
> > With the Sheevaplug and Dreamplug, there is no need to do this hack.
> > The uclass mvgbe did all the work, by the time phy_connect() is
> > executed, the PHY was already up and working fine. And then the
> > Marvell PHY driver kicks in, setting up the rest.
> >
> > Perhaps we need code in the uclass MVGBE that handles this in a
> > generic way? These are the Marvell PHY  driver functions invoked after
> > phy_connect() was successful. This happens in all 3 boards
> > (Sheevaplug, Dreamplug, and NSA310s).
> >
> > m88e1310_config
> > m88e1011s_startup
>
> Ah okay, It's executed.
>
> > I would appreciate hearing some explanation and perhaps some
> > suggestion/guidance about this topic.
>
> If all 3 boards use the same ethernet driver with the same configuration
> (e.g. CONFIG_PHYLIB, CONFIG_EM_ETH etc) and the same PHY, there should
> of course be no need to handle this differently for this Zyxel board.
> I suggest to continue debugging to see, why this really is necessary.
> Perhaps some soft-reset of the PHY clears this rx/tx delay again?

That's interesting. I recall trying miiphy_reset before phy_connect,
but not phy_reset. I'll try that.

By the way, without doing something to make the PHY available at that
point, the phy_connect would fail, so the Marvell PHY driver was never
invoked later.

> Additionally your patch seems to be indented incorrectly. This makes
> reviewing a bit harder.

Sorry about that! I forgot to run checkpatch since it is an RFC patch.
Will send the V2 patch for this.

Thanks for looking at this,
Tony


>
> Thanks,
> Stefan
>
> > Thanks,
> > Tony
> >
> > diff --git a/board/zyxel/nsa310s/nsa310s.c b/board/zyxel/nsa310s/nsa310s.c
> > index b71de4e11f..78d472d56c 100644
> > --- a/board/zyxel/nsa310s/nsa310s.c
> > +++ b/board/zyxel/nsa310s/nsa310s.c
> > @@ -1,22 +1,49 @@
> >   // SPDX-License-Identifier: GPL-2.0+
> >   /*
> > - * Copyright (C) 2015, 2021 Tony Dinh 
> > + * Copyright (C) 2015, 2021-2022 Tony Dinh 
> >* Copyright (C) 2015 Gerald Kerma 
> >*/
> >
> >   #include 
> >   #include 
> > -#include 
> > -#include 
> > +#include 
> >   #include 
> >   #include 
> >   #include 
> >   #include 
> >   #include 
> > -#include "nsa310s.h"
> > +#include 
> >
> >   DECLARE_GLOBAL_DATA_PTR;
> >
> > +/*
> > + * low GPIO's
> > + */
> > +#define HDD1_GREEN_LED BIT(16)
> > +#define HDD1_RED_LED BIT(13)
> > +#define USB_GREEN_LED BIT(15)
> > +#define USB_POWER BIT(21)
> > +#define SYS_GREEN_LED BIT(28)
> > +#define SYS_ORANGE_LED BIT(29)
> > +
> > +#define COPY_GREEN_LED BIT(22)
> > +#define COPY_RED_LED BIT(23)
> > +
> > +#define PIN_USB_GREEN_LED 15
> > +#define PIN_USB_POWER 21
> > +
> > +#define NSA310S_OE_LOW (~(0))
> > +#define NSA310S_VAL_LOW (SYS_GREEN_LED | USB_POWER)
> > +
> > +/*
> > + * high GPIO's
> > +*/
> > +#define HDD2_GREEN_LED BIT(2)
> > +#define HDD2_POWER BIT(1)
> > +
> > +#define NSA310S_OE_HIGH (~(0))
> > +#define NSA310S_VAL_HIGH (HDD2_POWER)
> > +
> >   int board_early_init_f(void)
> >   {
> >/*
> > 

Re: [RFC Patch] arm: kirkwood: nsa310s: Use Marvell uclass mvgbe and PHY driver for DM Ethernet

[Stefan Roese]

Hi Tony,

On 4/8/22 07:03, Tony Dinh wrote:

Hi all,

This is a work-in-progress patch that I'm working on, to clean up the
DM Ethernet code for the Zyxel NSA310S board (Kirkwood 88F6702 A1).

This NSA310s board Ethernet has some quirks that it does not work
quite the same way as other Kirwood boards with the similar network
chip (MV88E1318), such as the Sheevaplug and the Dreamplug.

Currently, in the NSA310S board file we use CONFIG_RESET_PHY_R to
execute reset_phy() during initialization. And the reset_phy() code in
this board file is ad-hoc, does not involve  Marvell PHY driver (which
it should be). So I'm following the same pattern that I've done for
the Sheevaplug: use the uclass drivers/net/mvgbe.c (CONFIG_MVGBE) to
bring up Ethernet, removing the reset_phy() code, and enable
CONFIG_PHY_MARVEL.

With this board, I could not get it to work the same way as for the
Sheevaplug to bring up the PHY automatically. I had to insert the
ad-hoc code to set RGMII delay in the __mvgbe_phy_init() function in
mvgbe.c, so the phy_connect() call will find the PHY. The PHY Id is
1410e90, same as in the Sheevaplug and Dreamplug. Please see this in
the patch below (it's only a hack to see the PHY can be brought up
this way).


Looking at drivers/net/phy/marvell.c I see that m88e1310_config()
does exactly this rx/tx delay configuration:

/* Marvell 88E1310 */
static int m88e1310_config(struct phy_device *phydev)
{
...
/* Set RGMII delay */
phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_PAGE, 0x0002);
reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_RGMII_CTRL);
reg |= 0x0030;
phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_RGMII_CTRL, reg);

Are you sure that this functions is not called while probing /
enabling the network interface?


With the Sheevaplug and Dreamplug, there is no need to do this hack.
The uclass mvgbe did all the work, by the time phy_connect() is
executed, the PHY was already up and working fine. And then the
Marvell PHY driver kicks in, setting up the rest.

Perhaps we need code in the uclass MVGBE that handles this in a
generic way? These are the Marvell PHY  driver functions invoked after
phy_connect() was successful. This happens in all 3 boards
(Sheevaplug, Dreamplug, and NSA310s).

m88e1310_config
m88e1011s_startup


Ah okay, It's executed.


I would appreciate hearing some explanation and perhaps some
suggestion/guidance about this topic.


If all 3 boards use the same ethernet driver with the same configuration
(e.g. CONFIG_PHYLIB, CONFIG_EM_ETH etc) and the same PHY, there should
of course be no need to handle this differently for this Zyxel board.
I suggest to continue debugging to see, why this really is necessary.
Perhaps some soft-reset of the PHY clears this rx/tx delay again?

Additionally your patch seems to be indented incorrectly. This makes
reviewing a bit harder.

Thanks,
Stefan


Thanks,
Tony

diff --git a/board/zyxel/nsa310s/nsa310s.c b/board/zyxel/nsa310s/nsa310s.c
index b71de4e11f..78d472d56c 100644
--- a/board/zyxel/nsa310s/nsa310s.c
+++ b/board/zyxel/nsa310s/nsa310s.c
@@ -1,22 +1,49 @@
  // SPDX-License-Identifier: GPL-2.0+
  /*
- * Copyright (C) 2015, 2021 Tony Dinh 
+ * Copyright (C) 2015, 2021-2022 Tony Dinh 
   * Copyright (C) 2015 Gerald Kerma 
   */

  #include 
  #include 
-#include 
-#include 
+#include 
  #include 
  #include 
  #include 
  #include 
  #include 
-#include "nsa310s.h"
+#include 

  DECLARE_GLOBAL_DATA_PTR;

+/*
+ * low GPIO's
+ */
+#define HDD1_GREEN_LED BIT(16)
+#define HDD1_RED_LED BIT(13)
+#define USB_GREEN_LED BIT(15)
+#define USB_POWER BIT(21)
+#define SYS_GREEN_LED BIT(28)
+#define SYS_ORANGE_LED BIT(29)
+
+#define COPY_GREEN_LED BIT(22)
+#define COPY_RED_LED BIT(23)
+
+#define PIN_USB_GREEN_LED 15
+#define PIN_USB_POWER 21
+
+#define NSA310S_OE_LOW (~(0))
+#define NSA310S_VAL_LOW (SYS_GREEN_LED | USB_POWER)
+
+/*
+ * high GPIO's
+*/
+#define HDD2_GREEN_LED BIT(2)
+#define HDD2_POWER BIT(1)
+
+#define NSA310S_OE_HIGH (~(0))
+#define NSA310S_VAL_HIGH (HDD2_POWER)
+
  int board_early_init_f(void)
  {
   /*
@@ -80,87 +107,7 @@ int board_init(void)
   return 0;
  }

-static int fdt_get_phy_addr(const char *path)
+int board_eth_init(struct bd_info *bis)
  {
- const void *fdt = gd->fdt_blob;
- const u32 *reg;
- const u32 *val;
- int node, phandle, addr;
-
- /* Find the node by its full path */
- node = fdt_path_offset(fdt, path);
- if (node >= 0) {
- /* Look up phy-handle */
- val = fdt_getprop(fdt, node, "phy-handle", NULL);
- if (val) {
- phandle = fdt32_to_cpu(*val);
- if (!phandle)
- return -1;
- /* Follow it to its node */
- node = fdt_node_offset_by_phandle(fdt, phandle);
- if (node) {
- /* Look up reg */
- reg = fdt_getprop(fdt, node, "reg", NULL);
- if (reg) {
- addr = fdt32_to_cpu(*reg);
- return addr;
- }
- }
- }
- }
- return -1;
-}
-
-#ifdef CONFIG_RESET_PHY_R
-void reset_phy(void)
-{
- u16 reg;
- u16 phyaddr;
- char *name = "ethernet-controller@72000";
- char *eth0_path = 

[RFC Patch] arm: kirkwood: nsa310s: Use Marvell uclass mvgbe and PHY driver for DM Ethernet

[Tony Dinh]

Hi all,

This is a work-in-progress patch that I'm working on, to clean up the
DM Ethernet code for the Zyxel NSA310S board (Kirkwood 88F6702 A1).

This NSA310s board Ethernet has some quirks that it does not work
quite the same way as other Kirwood boards with the similar network
chip (MV88E1318), such as the Sheevaplug and the Dreamplug.

Currently, in the NSA310S board file we use CONFIG_RESET_PHY_R to
execute reset_phy() during initialization. And the reset_phy() code in
this board file is ad-hoc, does not involve  Marvell PHY driver (which
it should be). So I'm following the same pattern that I've done for
the Sheevaplug: use the uclass drivers/net/mvgbe.c (CONFIG_MVGBE) to
bring up Ethernet, removing the reset_phy() code, and enable
CONFIG_PHY_MARVEL.

With this board, I could not get it to work the same way as for the
Sheevaplug to bring up the PHY automatically. I had to insert the
ad-hoc code to set RGMII delay in the __mvgbe_phy_init() function in
mvgbe.c, so the phy_connect() call will find the PHY. The PHY Id is
1410e90, same as in the Sheevaplug and Dreamplug. Please see this in
the patch below (it's only a hack to see the PHY can be brought up
this way).

With the Sheevaplug and Dreamplug, there is no need to do this hack.
The uclass mvgbe did all the work, by the time phy_connect() is
executed, the PHY was already up and working fine. And then the
Marvell PHY driver kicks in, setting up the rest.

Perhaps we need code in the uclass MVGBE that handles this in a
generic way? These are the Marvell PHY  driver functions invoked after
phy_connect() was successful. This happens in all 3 boards
(Sheevaplug, Dreamplug, and NSA310s).

m88e1310_config
m88e1011s_startup

I would appreciate hearing some explanation and perhaps some
suggestion/guidance about this topic.

Thanks,
Tony

diff --git a/board/zyxel/nsa310s/nsa310s.c b/board/zyxel/nsa310s/nsa310s.c
index b71de4e11f..78d472d56c 100644
--- a/board/zyxel/nsa310s/nsa310s.c
+++ b/board/zyxel/nsa310s/nsa310s.c
@@ -1,22 +1,49 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright (C) 2015, 2021 Tony Dinh 
+ * Copyright (C) 2015, 2021-2022 Tony Dinh 
  * Copyright (C) 2015 Gerald Kerma 
  */

 #include 
 #include 
-#include 
-#include 
+#include 
 #include 
 #include 
 #include 
 #include 
 #include 
-#include "nsa310s.h"
+#include 

 DECLARE_GLOBAL_DATA_PTR;

+/*
+ * low GPIO's
+ */
+#define HDD1_GREEN_LED BIT(16)
+#define HDD1_RED_LED BIT(13)
+#define USB_GREEN_LED BIT(15)
+#define USB_POWER BIT(21)
+#define SYS_GREEN_LED BIT(28)
+#define SYS_ORANGE_LED BIT(29)
+
+#define COPY_GREEN_LED BIT(22)
+#define COPY_RED_LED BIT(23)
+
+#define PIN_USB_GREEN_LED 15
+#define PIN_USB_POWER 21
+
+#define NSA310S_OE_LOW (~(0))
+#define NSA310S_VAL_LOW (SYS_GREEN_LED | USB_POWER)
+
+/*
+ * high GPIO's
+*/
+#define HDD2_GREEN_LED BIT(2)
+#define HDD2_POWER BIT(1)
+
+#define NSA310S_OE_HIGH (~(0))
+#define NSA310S_VAL_HIGH (HDD2_POWER)
+
 int board_early_init_f(void)
 {
  /*
@@ -80,87 +107,7 @@ int board_init(void)
  return 0;
 }

-static int fdt_get_phy_addr(const char *path)
+int board_eth_init(struct bd_info *bis)
 {
- const void *fdt = gd->fdt_blob;
- const u32 *reg;
- const u32 *val;
- int node, phandle, addr;
-
- /* Find the node by its full path */
- node = fdt_path_offset(fdt, path);
- if (node >= 0) {
- /* Look up phy-handle */
- val = fdt_getprop(fdt, node, "phy-handle", NULL);
- if (val) {
- phandle = fdt32_to_cpu(*val);
- if (!phandle)
- return -1;
- /* Follow it to its node */
- node = fdt_node_offset_by_phandle(fdt, phandle);
- if (node) {
- /* Look up reg */
- reg = fdt_getprop(fdt, node, "reg", NULL);
- if (reg) {
- addr = fdt32_to_cpu(*reg);
- return addr;
- }
- }
- }
- }
- return -1;
-}
-
-#ifdef CONFIG_RESET_PHY_R
-void reset_phy(void)
-{
- u16 reg;
- u16 phyaddr;
- char *name = "ethernet-controller@72000";
- char *eth0_path = "/ocp@f100/ethernet-controller@72000/ethernet0-port@0";
-
- if (miiphy_set_current_dev(name))
- return;
-
- phyaddr = fdt_get_phy_addr(eth0_path);
- if (phyaddr < 0)
- return;
-
- /* set RGMII delay */
- miiphy_write(name, phyaddr, MV88E1318_PGADR_REG, MV88E1318_MAC_CTRL_PG);
- miiphy_read(name, phyaddr, MV88E1318_MAC_CTRL_REG, );
- reg |= (MV88E1318_RGMII_RX_CTRL | MV88E1318_RGMII_TX_CTRL);
- miiphy_write(name, phyaddr, MV88E1318_MAC_CTRL_REG, reg);
- miiphy_write(name, phyaddr, MV88E1318_PGADR_REG, 0);
-
- /* reset PHY */
- if (miiphy_reset(name, phyaddr))
- return;
-
- /*
- * ZyXEL NSA310S uses the 88E1310S Alaska (interface identical to 88E1318)
- * and has an MCU attached to the LED[2] via tristate interrupt
- */
-
- /* switch to LED register page */
- miiphy_write(name, phyaddr, MV88E1318_PGADR_REG, MV88E1318_LED_PG);
- /* read out LED polarity register */
- miiphy_read(name, phyaddr, MV88E1318_LED_POL_REG, );
- /* clear 4, set 5 - LED2 low, tri-state */
- reg &= ~(MV88E1318_LED2_4);
- reg |= (MV88E1318_LED2_5);
- /* write back LED polarity register */
- miiphy_write(name, phyaddr, MV88E1318_LED_POL_REG, reg);

Re: [RFC PATCH 1/7] spl: Add generic spl_load function

[Stefan Roese]

On 4/7/22 17:10, Sean Anderson wrote:



On 4/6/22 1:30 AM, Stefan Roese wrote:

On 4/1/22 21:03, Sean Anderson wrote:

Implementers of SPL_LOAD_IMAGE_METHOD have to correctly determine what
type of image is being loaded and then call the appropriate image load
function correctly. This is tricky, because some image load functions
expect the whole image to already be loaded (CONFIG_SPL_LOAD_FIT_FULL),
some will load the image automatically using spl_load_info.read()
(CONFIG_SPL_LOAD_FIT/CONFIG_SPL_LOAD_IMX_CONTAINER), and some just parse
the header and expect the caller to do the actual loading afterwards
(legacy/raw images). Load methods often only support a subset of the
above methods, meaning that not all image types can be used with all
load methods. Further, the code to invoke these functions is
duplicated between different load functions.

To address this problem, this commit introduces a "spl_load" function.
It aims to handle image detection and correct invocation of each of the
parse/load functions. spl_simple_read is a wrapper around
spl_load_info.read with get_aligned_image* functions inlined for size
purposes. Additionally, we assume that bl_len is a power of 2 so we can
do bitshifts instead of divisions (which is smaller and faster).

Signed-off-by: Sean Anderson 
---

   common/spl/spl.c | 61 
   include/spl.h    | 30 +++-
   2 files changed, 90 insertions(+), 1 deletion(-)

diff --git a/common/spl/spl.c b/common/spl/spl.c
index b452d4feeb..f26df7ac3f 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -398,6 +398,67 @@ int spl_parse_image_header(struct spl_image_info 
*spl_image,
   return 0;
   }
   +static int spl_simple_read(struct spl_load_info *info, void *buf, size_t 
size,
+   size_t offset)
+{
+    int ret;
+    size_t bl_len = info->filename ? ARCH_DMA_MINALIGN : bl_len;
+    size_t bl_mask = bl_len - 1;
+    size_t bl_shift = ffs(bl_mask);
+    size_t overhead = offset & bl_mask;
+


Nitpicking comment:

It's preferred in general to use the reverse XMAS tree ordering of the
declared variables. So I would expect at least to have "int ret" as
last statement above. If you address this, then please in the complete
series.


I thought only Linux's net subsystem had this requirement. I can reorder
things for you if you'd like. However, some of these variables have
dependencies so they cannot all be reordered :)


Thanks. Perhaps it's only my personal preference. I find it more
structured this way. Still I think that I remember having seen this
request of reverse XMAS tree ordering here on the U-Boot list as well.

Nevertheless this is no blocker whatsoever. Please make such changes
only if a v2 of the patches is required.

Thanks,
Stefan


--Sean


Reviewed-by: Stefan Roese 

Thanks,
Stefan


+    buf -= overhead;
+    size = (size + overhead + bl_mask) >> bl_shift;
+    offset = offset >> bl_shift;
+
+    ret = info->read(info, offset, size, buf);
+    return ret == size ? 0 : -EIO;
+}
+
+int spl_load(struct spl_image_info *spl_image,
+ const struct spl_boot_device *bootdev, struct spl_load_info *info,
+ struct image_header *header, size_t size, size_t sector)
+{
+    int ret;
+    size_t offset = sector * info->bl_len;
+
+    if (image_get_magic(header) == FDT_MAGIC) {
+    if (IS_ENABLED(CONFIG_SPL_LOAD_FIT_FULL)) {
+    void *buf;
+
+    /*
+ * In order to support verifying images in the FIT, we
+ * need to load the whole FIT into memory. Try and
+ * guess how much we need to load by using the total
+ * size. This will fail for FITs with external data,
+ * but there's not much we can do about that.
+ */
+    if (!size)
+    size = roundup(fdt_totalsize(header), 4);
+    buf = spl_get_load_buffer(0, size);
+    ret = spl_simple_read(info, buf, size, offset);
+    if (ret)
+    return ret;
+
+    return spl_parse_image_header(spl_image, bootdev, buf);
+    }
+
+    if (IS_ENABLED(CONFIG_SPL_LOAD_FIT))
+    return spl_load_simple_fit(spl_image, info, sector,
+   header);
+    }
+
+    if (IS_ENABLED(CONFIG_SPL_LOAD_IMX_CONTAINER))
+    return spl_load_imx_container(spl_image, info, sector);
+
+    ret = spl_parse_image_header(spl_image, bootdev, header);
+    if (ret)
+    return ret;
+
+    return spl_simple_read(info, (void *)spl_image->load_addr,
+   spl_image->size, offset + spl_image->offset);
+}
+
   __weak void __noreturn jump_to_image_no_args(struct spl_image_info 
*spl_image)
   {
   typedef void __noreturn (*image_entry_noargs_t)(void);
diff --git a/include/spl.h b/include/spl.h
index 8ceb3c0f09..6606f4e5f6 100644
--- a/include/spl.h
+++ b/include/spl.h
@@ -236,7 +236,7 @@ struct spl_image_info {
    *
    * @dev: Pointer to the device, e.g. struct mmc *
 

[PATCH 13/13] scripts: config_whitelist: drop CONFIG_MMCROOT

[Peng Fan (OSS)]

From: Peng Fan 

Drop CONFIG_MMCROOT, no users now.

Signed-off-by: Peng Fan 
---
 scripts/config_whitelist.txt | 1 -
 1 file changed, 1 deletion(-)

diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index 12208c7a2f8..3318086917d 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -451,7 +451,6 @@ CONFIG_MII_DEFAULT_TSEC
 CONFIG_MISC_COMMON
 CONFIG_MIU_2BIT_21_7_INTERLEAVED
 CONFIG_MIU_2BIT_INTERLEAVED
-CONFIG_MMCROOT
 CONFIG_MMC_DEFAULT_DEV
 CONFIG_MMC_SUNXI_SLOT
 CONFIG_MONITOR_IS_IN_RAM
-- 
2.35.1

[PATCH 12/13] configs: drop CONFIG_MMCROOT

[Peng Fan (OSS)]

From: Peng Fan 

CONFIG_MMCROOT is only used to set mmcroot, no need a dedicated macro.

Script as below
"
 for i in `ls include/configs/*.h`
 do
 mmcroot=`sed -n '/define.*MMCROOT/ p' $i  | awk -F\" '{ print $2;}'`

 if [ ! -n "$mmcroot" ]; then
continue
 fi

 sed -i '/define.*MMCROOT/ d' $i
 sed -i 's,\" CONFIG_MMCROOT \",'$mmcroot',g' $i

 done
"

Signed-off-by: Peng Fan 
---
 include/configs/aristainetos2.h  | 3 +--
 include/configs/capricorn-common.h   | 1 -
 include/configs/cgtqmx8.h| 3 +--
 include/configs/cl-som-imx7.h| 1 -
 include/configs/imx7-cm.h| 3 +--
 include/configs/imx8mm-cl-iot-gate.h | 3 +--
 include/configs/imx8mm_evk.h | 3 +--
 include/configs/imx8mn_evk.h | 3 +--
 include/configs/imx8mp_evk.h | 3 +--
 include/configs/imx8mp_rsb3720.h | 3 +--
 include/configs/imx8mq_cm.h  | 3 +--
 include/configs/imx8mq_evk.h | 3 +--
 include/configs/imx8mq_phanbell.h| 3 +--
 include/configs/imx8qm_mek.h | 3 +--
 include/configs/imx8qm_rom7720.h | 3 +--
 include/configs/imx8qxp_mek.h| 3 +--
 include/configs/imx8ulp_evk.h| 3 +--
 include/configs/liteboard.h  | 3 +--
 include/configs/mx6sllevk.h  | 3 +--
 include/configs/mx6ul_14x14_evk.h| 3 +--
 include/configs/mx6ullevk.h  | 3 +--
 include/configs/mx7ulp_com.h | 3 +--
 include/configs/mx7ulp_evk.h | 3 +--
 include/configs/phycore_imx8mm.h | 1 -
 include/configs/phycore_imx8mp.h | 1 -
 include/configs/pico-imx8mq.h| 3 +--
 include/configs/xpress.h | 3 +--
 27 files changed, 23 insertions(+), 50 deletions(-)

diff --git a/include/configs/aristainetos2.h b/include/configs/aristainetos2.h
index ab20ad17b16..8ee97f1d4e3 100644
--- a/include/configs/aristainetos2.h
+++ b/include/configs/aristainetos2.h
@@ -26,7 +26,6 @@
 
 #include "mx6_common.h"
 
-#define CONFIG_MMCROOT "/dev/mmcblk0p1"
 
 /* MMC Configs */
 #define CONFIG_SYS_FSL_ESDHC_ADDR  USDHC1_BASE_ADDR
@@ -182,7 +181,7 @@
"${pubkey}\0" \
"mainRargs=setenv bootargs console=${console},${baudrate} " \
"rescue_sysnum=${rescue_sysnum} root=${emmcroot} 
rootfstype=ext4\0" \
-   "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
+   "mmcroot=/dev/mmcblk0p1 rootwait rw\0" \
"mmcargs=setenv bootargs console=${console},${baudrate} " \
"root=${mmcroot}\0" \
"mmcRargs=setenv bootargs console=${console},${baudrate} " \
diff --git a/include/configs/capricorn-common.h 
b/include/configs/capricorn-common.h
index 58d7a3a8ce2..08534cd1a30 100644
--- a/include/configs/capricorn-common.h
+++ b/include/configs/capricorn-common.h
@@ -109,7 +109,6 @@
 #define CONFIG_SYS_INIT_SP_ADDR0x8020
 
 /* On CCP board, USDHC1 is for eMMC */
-#define CONFIG_MMCROOT "/dev/mmcblk0p2"  /* eMMC */
 
 #define CONFIG_SYS_SDRAM_BASE  0x8000
 #define PHYS_SDRAM_1   0x8000
diff --git a/include/configs/cgtqmx8.h b/include/configs/cgtqmx8.h
index bd5c072382a..4b4694ec071 100644
--- a/include/configs/cgtqmx8.h
+++ b/include/configs/cgtqmx8.h
@@ -78,7 +78,7 @@
"fdt_file=imx8qm-cgt-qmx8.dtb\0" \
"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
"mmcpart=1\0" \
-   "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
+   "mmcroot=/dev/mmcblk1p2 rootwait rw\0" \
"mmcautodetect=yes\0" \
"mmcargs=setenv bootargs console=${console},${baudrate} root=${mmcroot} 
earlycon\0 " \
"loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} 
${script};\0" \
@@ -122,7 +122,6 @@
 
 #define CONFIG_SYS_INIT_SP_ADDR0x8020
 
-#define CONFIG_MMCROOT "/dev/mmcblk1p2"  /* USDHC2 */
 #define CONFIG_SYS_FSL_USDHC_NUM   3
 
 #define CONFIG_SYS_SDRAM_BASE  0x8000
diff --git a/include/configs/cl-som-imx7.h b/include/configs/cl-som-imx7.h
index 8af80f58f8e..4b494d8aeef 100644
--- a/include/configs/cl-som-imx7.h
+++ b/include/configs/cl-som-imx7.h
@@ -104,7 +104,6 @@
 #define CONFIG_SYS_FSL_ESDHC_ADDR   USDHC1_BASE_ADDR
 
 #define CONFIG_SYS_FSL_USDHC_NUM   2
-#define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC1 */
 #endif
 
 /* USB Configs */
diff --git a/include/configs/imx7-cm.h b/include/configs/imx7-cm.h
index 46ca1c58145..2d9f8bb510b 100644
--- a/include/configs/imx7-cm.h
+++ b/include/configs/imx7-cm.h
@@ -31,7 +31,7 @@
"fdt_addr=0x8300\0" \
"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
"mmcpart=1\0" \
-   "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
+   "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
"mmcargs=setenv bootargs console=${console},${baudrate} " \
"root=${mmcroot}\0" \
"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} 
${image}\0" \
@@ -83,7 +83,6 @@
 #define CONFIG_SYS_FSL_ESDHC_ADDR   USDHC1_BASE_ADDR
 

[PATCH 11/13] configs: imx: drop IMX_FEC_BASE

[Peng Fan (OSS)]

From: Peng Fan 

IMX_FEC_BASE is not used in these boards, so drop it.

Signed-off-by: Peng Fan 
---
 include/configs/apalis-imx8x.h   | 1 -
 include/configs/aristainetos2.h  | 1 -
 include/configs/cm_fx6.h | 1 -
 include/configs/colibri-imx6ull.h| 1 -
 include/configs/dh_imx6.h| 1 -
 include/configs/imx8mm-cl-iot-gate.h | 1 -
 include/configs/imx8mm_beacon.h  | 1 -
 include/configs/imx8mm_evk.h | 1 -
 include/configs/imx8mn_beacon.h  | 1 -
 include/configs/imx8mq_evk.h | 1 -
 include/configs/imx8mq_phanbell.h| 1 -
 include/configs/imx8ulp_evk.h| 1 -
 include/configs/kontron_pitx_imx8m.h | 1 -
 include/configs/liteboard.h  | 1 -
 include/configs/m53menlo.h   | 1 -
 include/configs/mccmon6.h| 1 -
 include/configs/mx6sxsabresd.h   | 1 -
 include/configs/mx6ul_14x14_evk.h| 2 --
 include/configs/npi_imx6ull.h| 1 -
 include/configs/pico-imx6.h  | 1 -
 include/configs/pico-imx6ul.h| 1 -
 include/configs/pico-imx8mq.h| 1 -
 include/configs/somlabs_visionsom_6ull.h | 1 -
 include/configs/tqma6.h  | 1 -
 include/configs/verdin-imx8mm.h  | 1 -
 include/configs/vf610twr.h   | 1 -
 include/configs/vining_2000.h| 1 -
 include/configs/xpress.h | 1 -
 28 files changed, 29 deletions(-)

diff --git a/include/configs/apalis-imx8x.h b/include/configs/apalis-imx8x.h
index 71a80f38bbb..762bc49e671 100644
--- a/include/configs/apalis-imx8x.h
+++ b/include/configs/apalis-imx8x.h
@@ -120,7 +120,6 @@
 
 /* Networking */
 #define CONFIG_FEC_ENET_DEV 0
-#define IMX_FEC_BASE   0x5b04
 #define CONFIG_FEC_MXC_PHYADDR  0x4
 #define PHY_ANEG_TIMEOUT 2
 
diff --git a/include/configs/aristainetos2.h b/include/configs/aristainetos2.h
index 611b6d724e1..ab20ad17b16 100644
--- a/include/configs/aristainetos2.h
+++ b/include/configs/aristainetos2.h
@@ -31,7 +31,6 @@
 /* MMC Configs */
 #define CONFIG_SYS_FSL_ESDHC_ADDR  USDHC1_BASE_ADDR
 
-#define IMX_FEC_BASE   ENET_BASE_ADDR
 #define CONFIG_FEC_MXC_PHYADDR 0
 
 #define CONFIG_SYS_SPI_ST_ENABLE_WP_PIN
diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h
index f836f920bd8..600999b8e72 100644
--- a/include/configs/cm_fx6.h
+++ b/include/configs/cm_fx6.h
@@ -147,7 +147,6 @@
 
 /* Ethernet */
 #define CONFIG_FEC_MXC_PHYADDR 0
-#define IMX_FEC_BASE   ENET_BASE_ADDR
 
 /* USB */
 #define CONFIG_MXC_USB_PORTSC  (PORT_PTS_UTMI | PORT_PTS_PTW)
diff --git a/include/configs/colibri-imx6ull.h 
b/include/configs/colibri-imx6ull.h
index 53bfab499ac..ef6de1cf14e 100644
--- a/include/configs/colibri-imx6ull.h
+++ b/include/configs/colibri-imx6ull.h
@@ -16,7 +16,6 @@
 #define PHYS_SDRAM_SIZESZ_1G
 
 /* ENET1 */
-#define IMX_FEC_BASE   ENET2_BASE_ADDR
 
 /* MMC Config */
 #define CONFIG_SYS_FSL_ESDHC_ADDR  0
diff --git a/include/configs/dh_imx6.h b/include/configs/dh_imx6.h
index 3d3fab517e3..2b14464dff1 100644
--- a/include/configs/dh_imx6.h
+++ b/include/configs/dh_imx6.h
@@ -31,7 +31,6 @@
 #define CONFIG_SYS_BOOTCOUNT_BE
 
 /* FEC ethernet */
-#define IMX_FEC_BASE   ENET_BASE_ADDR
 #define CONFIG_FEC_MXC_PHYADDR 7
 
 /* MMC Configs */
diff --git a/include/configs/imx8mm-cl-iot-gate.h 
b/include/configs/imx8mm-cl-iot-gate.h
index cd1eafdd5c9..fcb0bd465ed 100644
--- a/include/configs/imx8mm-cl-iot-gate.h
+++ b/include/configs/imx8mm-cl-iot-gate.h
@@ -154,7 +154,6 @@
 #define CONFIG_FEC_MXC_PHYADDR 0
 #define FEC_QUIRK_ENET_MAC
 
-#define IMX_FEC_BASE   0x30BE
 
 /* USB Configs */
 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
diff --git a/include/configs/imx8mm_beacon.h b/include/configs/imx8mm_beacon.h
index 5ac2c7a869a..368a02e602b 100644
--- a/include/configs/imx8mm_beacon.h
+++ b/include/configs/imx8mm_beacon.h
@@ -103,6 +103,5 @@
 /* FEC*/
 #define CONFIG_FEC_MXC_PHYADDR  0
 #define FEC_QUIRK_ENET_MAC
-#define IMX_FEC_BASE   0x30BE
 
 #endif
diff --git a/include/configs/imx8mm_evk.h b/include/configs/imx8mm_evk.h
index e0611126ece..80851b66325 100644
--- a/include/configs/imx8mm_evk.h
+++ b/include/configs/imx8mm_evk.h
@@ -81,6 +81,5 @@
 #define CONFIG_FEC_MXC_PHYADDR  0
 #define FEC_QUIRK_ENET_MAC
 
-#define IMX_FEC_BASE   0x30BE
 
 #endif
diff --git a/include/configs/imx8mn_beacon.h b/include/configs/imx8mn_beacon.h
index e6cb5d23be1..0082d2e4f2a 100644
--- a/include/configs/imx8mn_beacon.h
+++ b/include/configs/imx8mn_beacon.h
@@ -120,7 +120,6 @@
 #if defined(CONFIG_FEC_MXC)
 #define CONFIG_FEC_MXC_PHYADDR 0
 #define FEC_QUIRK_ENET_MAC
-#define IMX_FEC_BASE   0x30BE
 #endif /* CONFIG_FEC_MXC */
 
 #endif
diff --git a/include/configs/imx8mq_evk.h 

[PATCH 10/13] configs: phycore_imx8mm/p: drop unused SDHC macro

[Peng Fan (OSS)]

From: Peng Fan 

With SPL_DM_MMC and DM_MMC, the two macros not needed, drop it.
 CONFIG_SYS_FSL_USDHC_NUM
 CONFIG_SYS_FSL_ESDHC_ADDR

Signed-off-by: Peng Fan 
---
 include/configs/phycore_imx8mm.h | 4 
 include/configs/phycore_imx8mp.h | 4 
 2 files changed, 8 deletions(-)

diff --git a/include/configs/phycore_imx8mm.h b/include/configs/phycore_imx8mm.h
index 7438d0a4647..528cda0dbe3 100644
--- a/include/configs/phycore_imx8mm.h
+++ b/include/configs/phycore_imx8mm.h
@@ -92,8 +92,4 @@
 #define CONFIG_SYS_MAXARGS 64
 #define CONFIG_SYS_BARGSIZECONFIG_SYS_CBSIZE
 
-/* USDHC */
-#define CONFIG_SYS_FSL_USDHC_NUM   2
-#define CONFIG_SYS_FSL_ESDHC_ADDR   0
-
 #endif /* __PHYCORE_IMX8MM_H */
diff --git a/include/configs/phycore_imx8mp.h b/include/configs/phycore_imx8mp.h
index 8c5ffeef544..db530965a2a 100644
--- a/include/configs/phycore_imx8mp.h
+++ b/include/configs/phycore_imx8mp.h
@@ -92,8 +92,4 @@
 #define CONFIG_SYS_MAXARGS 64
 #define CONFIG_SYS_BARGSIZECONFIG_SYS_CBSIZE
 
-/* USDHC */
-#define CONFIG_SYS_FSL_USDHC_NUM   2
-#define CONFIG_SYS_FSL_ESDHC_ADDR   0
-
 #endif /* __PHYCORE_IMX8MP_H */
-- 
2.35.1

[PATCH 09/13] configs: imx8mm/n_venice: drop unused SDHC macro

[Peng Fan (OSS)]

From: Peng Fan 

With SPL_DM_MMC and DM_MMC, the two macros not needed, drop it.
 CONFIG_SYS_FSL_USDHC_NUM
 CONFIG_SYS_FSL_ESDHC_ADDR

Signed-off-by: Peng Fan 
---
 include/configs/imx8mm_venice.h | 4 
 include/configs/imx8mn_venice.h | 3 ---
 2 files changed, 7 deletions(-)

diff --git a/include/configs/imx8mm_venice.h b/include/configs/imx8mm_venice.h
index 1952bde8587..2fd1bce7a61 100644
--- a/include/configs/imx8mm_venice.h
+++ b/include/configs/imx8mm_venice.h
@@ -95,10 +95,6 @@
 #define CONFIG_SYS_PBSIZE  (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)
 
-/* USDHC */
-#define CONFIG_SYS_FSL_USDHC_NUM   2
-#define CONFIG_SYS_FSL_ESDHC_ADDR  0
-
 /* FEC */
 #define CONFIG_FEC_MXC_PHYADDR  0
 #define FEC_QUIRK_ENET_MAC
diff --git a/include/configs/imx8mn_venice.h b/include/configs/imx8mn_venice.h
index d954e8e3c56..ed606401360 100644
--- a/include/configs/imx8mn_venice.h
+++ b/include/configs/imx8mn_venice.h
@@ -91,9 +91,6 @@
 #define CONFIG_SYS_BARGSIZECONFIG_SYS_CBSIZE
 #define CONFIG_SYS_PBSIZE  (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)
-/* USDHC */
-#define CONFIG_SYS_FSL_USDHC_NUM   2
-#define CONFIG_SYS_FSL_ESDHC_ADDR  0
 
 /* FEC */
 #define CONFIG_FEC_MXC_PHYADDR  0
-- 
2.35.1

[PATCH 08/13] configs: imx8mm/n_beacon: drop unused SDHC macro

[Peng Fan (OSS)]

From: Peng Fan 

With SPL_DM_MMC and DM_MMC, the two macros not needed, drop it.
 CONFIG_SYS_FSL_USDHC_NUM
 CONFIG_SYS_FSL_ESDHC_ADDR

Signed-off-by: Peng Fan 
---
 include/configs/imx8mm_beacon.h | 4 
 include/configs/imx8mn_beacon.h | 4 
 2 files changed, 8 deletions(-)

diff --git a/include/configs/imx8mm_beacon.h b/include/configs/imx8mm_beacon.h
index e4805951fae..5ac2c7a869a 100644
--- a/include/configs/imx8mm_beacon.h
+++ b/include/configs/imx8mm_beacon.h
@@ -100,10 +100,6 @@
 #define CONFIG_SYS_PBSIZE  (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)
 
-/* USDHC */
-#define CONFIG_SYS_FSL_USDHC_NUM   2
-#define CONFIG_SYS_FSL_ESDHC_ADDR  0
-
 /* FEC*/
 #define CONFIG_FEC_MXC_PHYADDR  0
 #define FEC_QUIRK_ENET_MAC
diff --git a/include/configs/imx8mn_beacon.h b/include/configs/imx8mn_beacon.h
index 7fed9a38c1d..e6cb5d23be1 100644
--- a/include/configs/imx8mn_beacon.h
+++ b/include/configs/imx8mn_beacon.h
@@ -116,10 +116,6 @@
 #define CONFIG_SYS_PBSIZE  (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)
 
-/* USDHC */
-#define CONFIG_SYS_FSL_USDHC_NUM   2
-#define CONFIG_SYS_FSL_ESDHC_ADDR  0
-
 /* ENET Config */
 #if defined(CONFIG_FEC_MXC)
 #define CONFIG_FEC_MXC_PHYADDR 0
-- 
2.35.1

[PATCH 07/13] configs: verdin-imx8m: drop unused SDHC macro

[Peng Fan (OSS)]

From: Peng Fan 

With SPL_DM_MMC and DM_MMC, the two macros not needed, drop it.
 CONFIG_SYS_FSL_USDHC_NUM
 CONFIG_SYS_FSL_ESDHC_ADDR

Signed-off-by: Peng Fan 
---
 include/configs/verdin-imx8mm.h | 3 ---
 include/configs/verdin-imx8mp.h | 4 
 2 files changed, 7 deletions(-)

diff --git a/include/configs/verdin-imx8mm.h b/include/configs/verdin-imx8mm.h
index 9fe6231e8d2..3e0fe58188b 100644
--- a/include/configs/verdin-imx8mm.h
+++ b/include/configs/verdin-imx8mm.h
@@ -97,9 +97,6 @@
 #define CONFIG_SYS_BARGSIZECONFIG_SYS_CBSIZE
 #define CONFIG_SYS_PBSIZE  (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)
-/* USDHC */
-#define CONFIG_SYS_FSL_USDHC_NUM   2
-#define CONFIG_SYS_FSL_ESDHC_ADDR  0
 
 /* ENET */
 #define CONFIG_FEC_MXC_PHYADDR  7
diff --git a/include/configs/verdin-imx8mp.h b/include/configs/verdin-imx8mp.h
index 9e29dc19033..eb2bd867edb 100644
--- a/include/configs/verdin-imx8mp.h
+++ b/include/configs/verdin-imx8mp.h
@@ -116,8 +116,4 @@
 #define CONFIG_SYS_PBSIZE  (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)
 
-/* USDHC */
-#define CONFIG_SYS_FSL_USDHC_NUM   2
-#define CONFIG_SYS_FSL_ESDHC_ADDR  0
-
 #endif /* __VERDIN_IMX8MP_H */
-- 
2.35.1

[PATCH 06/13] configs: imx8qm/qxp_evk: drop unused SDHC macro

[Peng Fan (OSS)]

From: Peng Fan 

With SPL_DM_MMC and DM_MMC, the two macros not needed, drop it.
 CONFIG_SYS_FSL_USDHC_NUM
 CONFIG_SYS_FSL_ESDHC_ADDR

Signed-off-by: Peng Fan 
---
 include/configs/imx8qm_mek.h  | 5 -
 include/configs/imx8qxp_mek.h | 5 -
 2 files changed, 10 deletions(-)

diff --git a/include/configs/imx8qm_mek.h b/include/configs/imx8qm_mek.h
index 0fe38e61c4b..8a269225778 100644
--- a/include/configs/imx8qm_mek.h
+++ b/include/configs/imx8qm_mek.h
@@ -29,10 +29,6 @@
 #define CONFIG_SPL_ABORT_ON_RAW_IMAGE
 #endif
 
-#define CONFIG_SYS_FSL_ESDHC_ADDR   0
-#define USDHC1_BASE_ADDR0x5B01
-#define USDHC2_BASE_ADDR0x5B02
-
 #ifdef CONFIG_AHAB_BOOT
 #define AHAB_ENV "sec_boot=yes\0"
 #else
@@ -122,7 +118,6 @@
 
 /* On LPDDR4 board, USDHC1 is for eMMC, USDHC2 is for SD on CPU board */
 #define CONFIG_MMCROOT "/dev/mmcblk1p2"  /* USDHC2 */
-#define CONFIG_SYS_FSL_USDHC_NUM   2
 
 #define CONFIG_SYS_SDRAM_BASE  0x8000
 #define PHYS_SDRAM_1   0x8000
diff --git a/include/configs/imx8qxp_mek.h b/include/configs/imx8qxp_mek.h
index beb35c93435..01577932884 100644
--- a/include/configs/imx8qxp_mek.h
+++ b/include/configs/imx8qxp_mek.h
@@ -27,10 +27,6 @@
 #define CONFIG_SPL_ABORT_ON_RAW_IMAGE
 #endif
 
-#define CONFIG_SYS_FSL_ESDHC_ADDR   0
-#define USDHC1_BASE_ADDR0x5B01
-#define USDHC2_BASE_ADDR0x5B02
-
 #ifdef CONFIG_AHAB_BOOT
 #define AHAB_ENV "sec_boot=yes\0"
 #else
@@ -120,7 +116,6 @@
 
 /* On LPDDR4 board, USDHC1 is for eMMC, USDHC2 is for SD on CPU board */
 #define CONFIG_MMCROOT "/dev/mmcblk1p2"  /* USDHC2 */
-#define CONFIG_SYS_FSL_USDHC_NUM   2
 
 #define CONFIG_SYS_SDRAM_BASE  0x8000
 #define PHYS_SDRAM_1   0x8000
-- 
2.35.1

[PATCH 05/13] configs: mx7dsabresd: drop unused SDHC macro

[Peng Fan (OSS)]

From: Peng Fan 

With SPL_DM_MMC and DM_MMC, the two macros not needed, drop it.
 CONFIG_SYS_FSL_USDHC_NUM
 CONFIG_SYS_FSL_ESDHC_ADDR

Signed-off-by: Peng Fan 
---
 include/configs/mx7dsabresd.h | 9 -
 1 file changed, 9 deletions(-)

diff --git a/include/configs/mx7dsabresd.h b/include/configs/mx7dsabresd.h
index d411b1a3866..aaad232f0e4 100644
--- a/include/configs/mx7dsabresd.h
+++ b/include/configs/mx7dsabresd.h
@@ -14,9 +14,6 @@
 
 #define CONFIG_MXC_UART_BASEUART1_IPS_BASE_ADDR
 
-/* MMC Config*/
-#define CONFIG_SYS_FSL_ESDHC_ADDR   0
-
 #ifdef CONFIG_IMX_BOOTAUX
 /* Set to QSPI1 A flash at default */
 #define CONFIG_SYS_AUXCORE_BOOTDATA 0x6000
@@ -111,12 +108,6 @@
 /* DMA stuff, needed for GPMI/MXS NAND support */
 #endif
 
-#ifdef CONFIG_NAND_MXS
-#define CONFIG_SYS_FSL_USDHC_NUM   1
-#else
-#define CONFIG_SYS_FSL_USDHC_NUM   2
-#endif
-
 /* USB Configs */
 #define CONFIG_MXC_USB_PORTSC  (PORT_PTS_UTMI | PORT_PTS_PTW)
 
-- 
2.35.1

[PATCH 04/13] configs: mx6sxsabresd: drop CONFIG_SYS_FSL_USDHC_NUM

[Peng Fan (OSS)]

From: Peng Fan 

With DM_MMC, CONFIG_SYS_FSL_USDHC_NUM is not needed.

Signed-off-by: Peng Fan 
---
 include/configs/mx6sxsabresd.h | 2 --
 1 file changed, 2 deletions(-)

diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h
index b679d13dc04..2552fc0222e 100644
--- a/include/configs/mx6sxsabresd.h
+++ b/include/configs/mx6sxsabresd.h
@@ -149,6 +149,4 @@
 #endif
 #endif
 
-#define CONFIG_SYS_FSL_USDHC_NUM   3
-
 #endif /* __CONFIG_H */
-- 
2.35.1

[PATCH 03/13] configs: imx8mn_evk: drop unused SDHC macro

[Peng Fan (OSS)]

From: Peng Fan 

With SPL_DM_MMC and DM_MMC, the two macros not needed, drop it.
 #define CONFIG_SYS_FSL_USDHC_NUM   2
 #define CONFIG_SYS_FSL_ESDHC_ADDR  0

Signed-off-by: Peng Fan 
---
 include/configs/imx8mn_evk.h | 5 -
 1 file changed, 5 deletions(-)

diff --git a/include/configs/imx8mn_evk.h b/include/configs/imx8mn_evk.h
index 142fc3e4fff..f969314d6b2 100644
--- a/include/configs/imx8mn_evk.h
+++ b/include/configs/imx8mn_evk.h
@@ -77,9 +77,4 @@
 #define CONFIG_SYS_PBSIZE  (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)
 
-/* USDHC */
-
-#define CONFIG_SYS_FSL_USDHC_NUM   2
-#define CONFIG_SYS_FSL_ESDHC_ADDR  0
-
 #endif
-- 
2.35.1

[PATCH 02/13] configs: imx8mp_evk: drop unused SDHC macro

[Peng Fan (OSS)]

From: Peng Fan 

With SPL_DM_MMC and DM_MMC, the two macros not needed, drop it.
 #define CONFIG_SYS_FSL_USDHC_NUM   2
 #define CONFIG_SYS_FSL_ESDHC_ADDR  0

Signed-off-by: Peng Fan 
---
 include/configs/imx8mp_evk.h | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/include/configs/imx8mp_evk.h b/include/configs/imx8mp_evk.h
index 5b185cf1de2..35fc27bb370 100644
--- a/include/configs/imx8mp_evk.h
+++ b/include/configs/imx8mp_evk.h
@@ -90,7 +90,4 @@
 #define CONFIG_SYS_PBSIZE  (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)
 
-#define CONFIG_SYS_FSL_USDHC_NUM   2
-#define CONFIG_SYS_FSL_ESDHC_ADDR  0
-
 #endif
-- 
2.35.1

[PATCH 01/13] configs: imx8mm_evk: drop unused SDHC macro

[Peng Fan (OSS)]

From: Peng Fan 

With SPL_DM_MMC and DM_MMC, the two macros not needed, drop it.
 #define CONFIG_SYS_FSL_USDHC_NUM   2
 #define CONFIG_SYS_FSL_ESDHC_ADDR  0

Signed-off-by: Peng Fan 
---
 include/configs/imx8mm_evk.h | 5 -
 1 file changed, 5 deletions(-)

diff --git a/include/configs/imx8mm_evk.h b/include/configs/imx8mm_evk.h
index 32c937abb0e..e0611126ece 100644
--- a/include/configs/imx8mm_evk.h
+++ b/include/configs/imx8mm_evk.h
@@ -78,11 +78,6 @@
 #define CONFIG_SYS_PBSIZE  (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)
 
-/* USDHC */
-
-#define CONFIG_SYS_FSL_USDHC_NUM   2
-#define CONFIG_SYS_FSL_ESDHC_ADDR  0
-
 #define CONFIG_FEC_MXC_PHYADDR  0
 #define FEC_QUIRK_ENET_MAC
 
-- 
2.35.1

[PATCH 00/13] configs: clean up SDHC marco and MMCROOT

[Peng Fan (OSS)]

From: Peng Fan 

For platforms with DM_MMC and SPL_DM_MMC, the SDHC macros are not needed.
CONFIG_MMCROOT could be actually dropped.
Drop IMX_FEC_BASE for boards that not use it

Tom, Stefano

this patches changes lots of files, not only imx, to avoid conflict, Tom
would you directly pick up if no issues?

Thanks.

Peng Fan (13):
  configs: imx8mm_evk: drop unused SDHC macro
  configs: imx8mp_evk: drop unused SDHC macro
  configs: imx8mn_evk: drop unused SDHC macro
  configs: mx6sxsabresd: drop CONFIG_SYS_FSL_USDHC_NUM
  configs: mx7dsabresd: drop unused SDHC macro
  configs: imx8qm/qxp_evk: drop unused SDHC macro
  configs: verdin-imx8m: drop unused SDHC macro
  configs: imx8mm/n_beacon: drop unused SDHC macro
  configs: imx8mm/n_venice: drop unused SDHC macro
  configs: phycore_imx8mm/p: drop unused SDHC macro
  configs: imx: drop IMX_FEC_BASE
  configs: drop CONFIG_MMCROOT
  scripts: config_whitelist: drop CONFIG_MMCROOT

 include/configs/apalis-imx8x.h   | 1 -
 include/configs/aristainetos2.h  | 4 +---
 include/configs/capricorn-common.h   | 1 -
 include/configs/cgtqmx8.h| 3 +--
 include/configs/cl-som-imx7.h| 1 -
 include/configs/cm_fx6.h | 1 -
 include/configs/colibri-imx6ull.h| 1 -
 include/configs/dh_imx6.h| 1 -
 include/configs/imx7-cm.h| 3 +--
 include/configs/imx8mm-cl-iot-gate.h | 4 +---
 include/configs/imx8mm_beacon.h  | 5 -
 include/configs/imx8mm_evk.h | 9 +
 include/configs/imx8mm_venice.h  | 4 
 include/configs/imx8mn_beacon.h  | 5 -
 include/configs/imx8mn_evk.h | 8 +---
 include/configs/imx8mn_venice.h  | 3 ---
 include/configs/imx8mp_evk.h | 6 +-
 include/configs/imx8mp_rsb3720.h | 3 +--
 include/configs/imx8mq_cm.h  | 3 +--
 include/configs/imx8mq_evk.h | 4 +---
 include/configs/imx8mq_phanbell.h| 4 +---
 include/configs/imx8qm_mek.h | 8 +---
 include/configs/imx8qm_rom7720.h | 3 +--
 include/configs/imx8qxp_mek.h| 8 +---
 include/configs/imx8ulp_evk.h| 4 +---
 include/configs/kontron_pitx_imx8m.h | 1 -
 include/configs/liteboard.h  | 4 +---
 include/configs/m53menlo.h   | 1 -
 include/configs/mccmon6.h| 1 -
 include/configs/mx6sllevk.h  | 3 +--
 include/configs/mx6sxsabresd.h   | 3 ---
 include/configs/mx6ul_14x14_evk.h| 5 +
 include/configs/mx6ullevk.h  | 3 +--
 include/configs/mx7dsabresd.h| 9 -
 include/configs/mx7ulp_com.h | 3 +--
 include/configs/mx7ulp_evk.h | 3 +--
 include/configs/npi_imx6ull.h| 1 -
 include/configs/phycore_imx8mm.h | 5 -
 include/configs/phycore_imx8mp.h | 5 -
 include/configs/pico-imx6.h  | 1 -
 include/configs/pico-imx6ul.h| 1 -
 include/configs/pico-imx8mq.h| 4 +---
 include/configs/somlabs_visionsom_6ull.h | 1 -
 include/configs/tqma6.h  | 1 -
 include/configs/verdin-imx8mm.h  | 4 
 include/configs/verdin-imx8mp.h  | 4 
 include/configs/vf610twr.h   | 1 -
 include/configs/vining_2000.h| 1 -
 include/configs/xpress.h | 4 +---
 scripts/config_whitelist.txt | 1 -
 50 files changed, 23 insertions(+), 144 deletions(-)

-- 
2.35.1

Re: [PATCH 5/6] net: add MV88E61xx DSA driver

[Marek Behún]

On Thu, 7 Apr 2022 16:03:12 -0700
Tim Harvey  wrote:

> Is there a move to try and move all network drivers to DM_MDIO
> eliminating the need for struct mii_dev* within those drivers?

Yes.

Marek

[PATCH 2/2] ARM: dts: imx8mm: Add i.MX8M Mini Toradex Verdin based Menlo board

[Marek Vasut]

Add new board based on the Toradex Verdin iMX8M Mini SoM, the MX8Menlo.
The board is a compatible replacement for i.MX53 M53Menlo and features
USB, multiple UARTs, ethernet, LEDs, SD and eMMC.

Signed-off-by: Marek Vasut 
Cc: Fabio Estevam 
Cc: Marcel Ziswiler 
Cc: Max Krummenacher 
Cc: Peng Fan 
Cc: Stefano Babic 
---
 arch/arm/dts/Makefile|   1 +
 arch/arm/dts/imx8mm-mx8menlo-u-boot.dtsi |  38 +++
 arch/arm/dts/imx8mm-mx8menlo.dts | 325 +++
 arch/arm/mach-imx/imx8m/Kconfig  |   8 +
 board/menlo/mx8menlo/Kconfig |  39 +++
 board/menlo/mx8menlo/MAINTAINERS |   7 +
 board/menlo/mx8menlo/Makefile|  25 ++
 board/menlo/mx8menlo/mx8menlo.c  |  56 
 configs/imx8mm-mx8menlo_defconfig| 120 +
 include/configs/imx8mm-mx8menlo.h|  36 +++
 10 files changed, 655 insertions(+)
 create mode 100644 arch/arm/dts/imx8mm-mx8menlo-u-boot.dtsi
 create mode 100644 arch/arm/dts/imx8mm-mx8menlo.dts
 create mode 100644 board/menlo/mx8menlo/Kconfig
 create mode 100644 board/menlo/mx8menlo/MAINTAINERS
 create mode 100644 board/menlo/mx8menlo/Makefile
 create mode 100644 board/menlo/mx8menlo/mx8menlo.c
 create mode 100644 configs/imx8mm-mx8menlo_defconfig
 create mode 100644 include/configs/imx8mm-mx8menlo.h

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index cd9a820f956..d80ebc4f26c 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -905,6 +905,7 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
imx8mm-icore-mx8mm-edimm2.2.dtb \
imx8mm-kontron-n801x-s.dtb \
imx8mm-kontron-n801x-s-lvds.dtb \
+   imx8mm-mx8menlo.dtb \
imx8mm-venice.dtb \
imx8mm-venice-gw71xx-0x.dtb \
imx8mm-venice-gw72xx-0x.dtb \
diff --git a/arch/arm/dts/imx8mm-mx8menlo-u-boot.dtsi 
b/arch/arm/dts/imx8mm-mx8menlo-u-boot.dtsi
new file mode 100644
index 000..b87cef9bf99
--- /dev/null
+++ b/arch/arm/dts/imx8mm-mx8menlo-u-boot.dtsi
@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * Copyright 2021-2022 Marek Vasut 
+ */
+#include "imx8mm-verdin-u-boot.dtsi"
+
+/ {
+   chosen {
+   stdout-path = 
+   };
+
+   aliases {
+   /delete-property/ eeprom1;
+   /delete-property/ eeprom2;
+   usbphy0 = 
+   usbphy1 = 
+   };
+};
+
+ {
+   /delete-node/ codec@1a;
+};
+
+_uart1 {
+   /delete-property/ u-boot,dm-spl;
+};
+
+_uart2 {
+   u-boot,dm-spl;
+};
+
+ {
+   /delete-property/ u-boot,dm-spl;
+};
+
+ {
+   u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/imx8mm-mx8menlo.dts b/arch/arm/dts/imx8mm-mx8menlo.dts
new file mode 100644
index 000..adfd8fd8cb6
--- /dev/null
+++ b/arch/arm/dts/imx8mm-mx8menlo.dts
@@ -0,0 +1,325 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * Copyright 2021-2022 Marek Vasut 
+ */
+
+#include "imx8mm-verdin.dts"
+
+/ {
+   model = "MENLO MX8MM EMBEDDED DEVICE";
+   compatible = "menlo,mx8menlo",
+"toradex,verdin-imx8mm",
+"fsl,imx8mm";
+
+   /delete-node/ gpio-keys;
+
+   leds {
+   compatible = "gpio-leds";
+   pinctrl-names = "default";
+   pinctrl-0 = <_led>;
+
+   user1 {
+   label = "TestLed601";
+   gpios = < 18 GPIO_ACTIVE_HIGH>;
+   linux,default-trigger = "mmc0";
+   };
+
+   user2 {
+   label = "TestLed602";
+   gpios = < 10 GPIO_ACTIVE_HIGH>;
+   linux,default-trigger = "heartbeat";
+   };
+   };
+
+   beeper {
+   compatible = "gpio-beeper";
+   pinctrl-names = "default";
+   pinctrl-0 = <_beeper>;
+   gpios = < 3 GPIO_ACTIVE_HIGH>;
+   };
+};
+
+ {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   pinctrl-names = "default";
+   pinctrl-0 = <_ecspi1>;
+   cs-gpios = < 9 GPIO_ACTIVE_LOW>;
+   status = "okay";
+
+   /* CAN controller on the baseboard */
+   canfd: can@0 {
+   compatible = "microchip,mcp2518fd";
+   clocks = <>;
+   gpio-controller;
+   interrupt-parent = <>;
+   interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
+   reg = <0>;
+   spi-max-frequency = <200>;
+   status = "okay";
+   };
+
+};
+
+ {
+   pinctrl-0 = <_ecspi2 _gpio1>;
+   cs-gpios = < 13 GPIO_ACTIVE_LOW>, < 4 GPIO_ACTIVE_LOW>;
+   status = "disabled";
+};
+
+ {
+   max-speed = <100>;
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+
+   flash@0 {
+   reg = <0>;
+   #address-cells = <1>;
+   #size-cells = <1>;
+   compatible = "jedec,spi-nor";
+   spi-max-frequency = <6600>;
+   spi-rx-bus-width = 

[PATCH 1/2] ARM: imx8mm: verdin-imx8mm: Rework board_early_init()

[Marek Vasut]

Rename board_early_init_f() to board_early_init(), since this function
has nothing to do with actual board_early_init_f() as used throughout
U-Boot. The board_early_init() is function local to this board used to
configure UART and WDT pinmux. Wrap init_uart_clk() into this function
so that early UART init would be all in one place. Turn the function
into __weak one, so it could be overridden in case custom carrier board
uses different UART or needs custom IOMUX settings.

Signed-off-by: Marek Vasut 
Cc: Fabio Estevam 
Cc: Marcel Ziswiler 
Cc: Max Krummenacher 
Cc: Peng Fan 
Cc: Stefano Babic 
---
 board/toradex/verdin-imx8mm/spl.c | 10 --
 1 file changed, 4 insertions(+), 6 deletions(-)

diff --git a/board/toradex/verdin-imx8mm/spl.c 
b/board/toradex/verdin-imx8mm/spl.c
index 97d6a31da15..4e6128c3314 100644
--- a/board/toradex/verdin-imx8mm/spl.c
+++ b/board/toradex/verdin-imx8mm/spl.c
@@ -88,17 +88,17 @@ static iomux_v3_cfg_t const wdog_pads[] = {
IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B  | MUX_PAD_CTRL(WDOG_PAD_CTRL),
 };
 
-int board_early_init_f(void)
+__weak void board_early_init(void)
 {
struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
 
+   init_uart_clk(0);
+
imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
 
set_wdog_reset(wdog);
 
imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
-
-   return 0;
 }
 
 int power_init_board(void)
@@ -140,9 +140,7 @@ void board_init_f(ulong dummy)
 
arch_cpu_init();
 
-   init_uart_clk(0);
-
-   board_early_init_f();
+   board_early_init();
 
timer_init();
 
-- 
2.35.1

[PATCH v2] image: fdt: Fix DT relocation handling with multiple DRAM banks with gap

[Marek Vasut]

The current implementation of boot_relocate_fdt() places DT at the
highest usable DRAM address, which is calculated as:
  env_get_bootm_low() + env_get_bootm_mapsize()
which by default becomes gd->ram_base + gd->ram_size.

Systems like i.MX53 can have multiple DRAM banks with gap between them,
e.g. have DRAM at 0x7000-0x8fff and 0xb000-0xcfff , so
for them the calculated highest DRAM address is 0xafff, which is
exactly in the gap and thus not usable.

Fix this by iterating over all DRAM banks and tracking the remaining
amount of the total mapping size obtained from env_get_bootm_mapsize().
Limit the maximum LMB area size to each bank, to avoid using nonexistent
DRAM.

Reviewed-by: Simon Glass 
Signed-off-by: Marek Vasut 
Cc: Heinrich Schuchardt 
Cc: Simon Glass 
Cc: Tom Rini 
---
V2: Collect RB, rebase on v2022.04+
---
 boot/image-fdt.c | 40 
 1 file changed, 36 insertions(+), 4 deletions(-)

diff --git a/boot/image-fdt.c b/boot/image-fdt.c
index 692a9ad3e42..fe2fc3351ba 100644
--- a/boot/image-fdt.c
+++ b/boot/image-fdt.c
@@ -165,8 +165,11 @@ int boot_relocate_fdt(struct lmb *lmb, char 
**of_flat_tree, ulong *of_size)
 {
void*fdt_blob = *of_flat_tree;
void*of_start = NULL;
+   u64 start, size, usable;
char*fdt_high;
+   ulong   mapsize, low;
ulong   of_len = 0;
+   int bank;
int err;
int disable_relocation = 0;
 
@@ -206,10 +209,39 @@ int boot_relocate_fdt(struct lmb *lmb, char 
**of_flat_tree, ulong *of_size)
(void *)(ulong) lmb_alloc(lmb, of_len, 0x1000);
}
} else {
-   of_start =
-   (void *)(ulong) lmb_alloc_base(lmb, of_len, 0x1000,
-  env_get_bootm_mapsize()
-  + env_get_bootm_low());
+   mapsize = env_get_bootm_mapsize();
+   low = env_get_bootm_low();
+   of_start = NULL;
+
+   for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
+   start = gd->bd->bi_dram[bank].start;
+   size = gd->bd->bi_dram[bank].size;
+
+   /* DRAM bank addresses are too low, skip it. */
+   if (start + size < low)
+   continue;
+
+   usable = min(size, (u64)mapsize);
+
+   /*
+* At least part of this DRAM bank is usable, try
+* using it for LMB allocation.
+*/
+   of_start =
+   (void *)(ulong) lmb_alloc_base(lmb, of_len, 0x1000,
+  start + usable);
+   /* Allocation succeeded, use this block. */
+   if (of_start != NULL)
+   break;
+
+   /*
+* Reduce the mapping size in the next bank
+* by the size of attempt in current bank.
+*/
+   mapsize -= usable - max(start, (u64)low);
+   if (!mapsize)
+   break;
+   }
}
 
if (of_start == NULL) {
-- 
2.35.1

Re: [PATCH] pci: Do not enable PCIe ASMedia ASM2824 workaround by default

[Maciej W. Rozycki]

On Thu, 7 Apr 2022, Stefan Roese wrote:

> > Hello! What do you think about this change? I think it is good
> > compromise between enable this workaround for all builds on all boards
> > and enable it only based on device id. Or would it be better to restrict
> > this workaround just for ASM2824 device like the last iteration of
> > kernel patch?
> 
> I'm not sure if we should name this "workaround" ASM2824, even though
> it's currently (only) targeted exactly for this PCIe switch. It might
> be helpful for other PCIe switches as well. So perhaps it's better to
> give this function a more generic name instead? With this change, it
> makes perhaps also sense to keep this function in pci_auto.c but also
> rename the Kconfig option to some more generic version.

 By now I have become somewhat tired arguing and explaining matters over 
and over again as things have been moving as slow as molasses in this 
area, but one point I want to raise here is while it is indeed the ASM2824 
device that seems problematic, it may actually be downstream, so you won't 
know it's there until you go through the workaround, as observed with the 
root port of the SiFive FU740-C000 SOC (which has a separate workaround in 
U-boot, clearly for the same issue; cf. `pcie_sifive_force_gen1').  So it 
looks like the erratum is going to show up with some device combinations 
in which the device enumerator may not have a way to know an ASM2824 is 
there until the workaround applied to an upstream device has let the link 
work.

 And as I previously already mentioned the Linux version of the workaround 
is only activated by the vendor:device ID because you cannot busy-loop 
polling on the Link Training bit in Linux (while you can do it in U-Boot, 
because U-Boot is not an OS).  Arguably I could have broadened it to cover 
all Gen 3+ devices and poll on the Data Link Layer Link Active bit, which 
doesn't require busy-looping for meaningful results, but that would still 
leave Gen 2 devices out and chances are the system boots from U-Boot with 
the generic workaround applied and the link already negotiated at 2.5GT/s.

 NB the ASM2824 switch has been used with option cards as well, e.g. 
, so it can be there in any system 
that has a connector of any kind that lets one use PCIe option cards.

 FWIW,

  Maciej

Re: [PATCH 5/6] net: add MV88E61xx DSA driver

[Tim Harvey]

On Thu, Apr 7, 2022 at 2:31 PM Vladimir Oltean  wrote:
>
> On Thu, Apr 07, 2022 at 01:33:58PM -0700, Tim Harvey wrote:
> > I guess I'll have to invest in tagging packets if you won't accept the
> > simplistic approach of not having to tag frames knowing that only one
> > port is active at a time.
>
> I genuinely don't know where you got the impression from that I don't
> accept the simplistic approach. I gave you an option to make the xmit
> and receive ops actually optional at the DSA uclass level so you don't
> have to come up with a make-believe tag parsing function. In the end
> it goes towards the simplification of the Marvell driver. Let's let them
> battle it out for a while and if tag insertion/parsing won't be
> necessary even for multi-switch systems we can discuss about removing
> that logic completely.

Ok... sorry I misunderstood.

>
> > That said, I have no idea if or when I will re-visit this. Adding a
> > DSA version of this driver was something on my personal wish list and
> > not something that was necessary by any means by my employer so I may
> > have to just drop it as I don't have the personal time to work through
> > this part of it or unravelling the mii bus mess in the fec_mxc driver.
> > It seems to me there is an issue with trying to create DM_MDIO drivers
> > in general as most dt's I've seen wouldn't support the requirements
> > yet configure DM_MDIO anyway (meaning if you implemented it you would
> > break those boards as I found).
>
> I don't know why there are boards which set CONFIG_DM_MDIO and then
> fight against the current trying to survive that config being set.
> Maybe you can look into disabling that config option on boards that
> aren't prepared to handle it?

There might not be many boards that would 'break'. Here's what uses
FEC_MXC and DM_MDIO:
$ grep -H CONFIG_FEC_MXC configs/* | awk -F: '{ print $1 }' | xargs grep DM_MDIO
configs/colibri_imx7_defconfig:CONFIG_DM_MDIO=y
configs/colibri_imx7_emmc_defconfig:CONFIG_DM_MDIO=y
configs/ge_b1x5v2_defconfig:CONFIG_DM_MDIO=y
configs/gwventana_emmc_defconfig:CONFIG_DM_MDIO=y
configs/gwventana_gw5904_defconfig:CONFIG_DM_MDIO=y
configs/gwventana_nand_defconfig:CONFIG_DM_MDIO=y
configs/imx7_cm_defconfig:CONFIG_DM_MDIO=y
configs/imx7_cm_defconfig:CONFIG_DM_MDIO_MUX=y
configs/imx8mm_venice_defconfig:CONFIG_DM_MDIO=y
configs/imx8mn_venice_defconfig:CONFIG_DM_MDIO=y
configs/imx8mp_venice_defconfig:CONFIG_DM_MDIO=y
configs/m53menlo_defconfig:CONFIG_DM_MDIO=y
configs/mx7dsabresd_defconfig:CONFIG_DM_MDIO=y
configs/mx7dsabresd_defconfig:CONFIG_DM_MDIO_MUX=y
configs/mx7dsabresd_qspi_defconfig:CONFIG_DM_MDIO=y
configs/mx7dsabresd_qspi_defconfig:CONFIG_DM_MDIO_MUX=y
configs/opos6uldev_defconfig:CONFIG_DM_MDIO=y
configs/pcm058_defconfig:CONFIG_DM_MDIO=y
configs/pico-dwarf-imx7d_defconfig:CONFIG_DM_MDIO=y
configs/pico-hobbit-imx7d_defconfig:CONFIG_DM_MDIO=y
configs/pico-imx7d_bl33_defconfig:CONFIG_DM_MDIO=y
configs/pico-imx7d_defconfig:CONFIG_DM_MDIO=y
configs/pico-nymph-imx7d_defconfig:CONFIG_DM_MDIO=y
configs/pico-pi-imx7d_defconfig:CONFIG_DM_MDIO=y
configs/udoo_neo_defconfig:CONFIG_DM_MDIO=y

The venice/gwventana ones are mine so I can easily test/fix. For the
others just looking at their CONFIG_DEFAULT_DEVICE_TREE and
eliminating duplicates I see:

I believe these would break:
arch/arm/dts/imx7-colibri-rawnand.dts (no mdio subnode)
arch/arm/dts/imx7-colibri-emmc.dts (no mdio subnode)
arch/arm/dts/imx6sx-udoo-neo-basic.dts (no phy-mode)

These should be ok; have phy-mode, phy-handle, mdio subnode
arch/arm/dts/imx6dl-b1x5v2.dts
arch/arm/dts/imx7-cm.dts
arch/arm/dts/imx53-m53menlo.dts
arch/arm/dts/imx6ul-opos6uldev.dts
arch/arm/dts/imx6q-phytec-mira-rdk-nand.dts
arch/arm/dts/imx7d-pico-pi.dts

These may be ok; has phy-mode, phy-handle, mdio subnode for fec1, but
missing mdio subnode for fec2 (but should use mdio from fec1)
arch/arm/dts/imx7d-sdb.dts
arch/arm/dts/imx7d-sdb-qspi.dts

I feel like I would need to get all board maintainers using FEC_MXC to
sign-off that their boards still work.

But then there is this issue of CONFIG_DM_ETH_PHY that still throws
around the concept of struct mii_dev* (which I think should have been
handled by switching to DM_MDIO). There are now three drivers using
this and I'm not sure what to do with that. There are 28 boards using
CONFIG_DM_ETH_PHY (and likely some which are not even using one of the
three drivers that even use CONFIG_DM_ETH_PHY).

Is there a move to try and move all network drivers to DM_MDIO
eliminating the need for struct mii_dev* within those drivers?

Best Regards,

Tim

Re: [PATCH] btrfs: Fix compilation on big endian systems

[Qu Wenruo]

On 2022/4/7 20:51, Pali Rohár wrote:

Fix following two compile errors on big endian systems:

   CC  fs/btrfs/btrfs.o
In file included from include/linux/byteorder/big_endian.h:107,
  from ./arch/powerpc/include/asm/byteorder.h:82,
  from ./arch/powerpc/include/asm/bitops.h:8,
  from include/linux/bitops.h:152,
  from include/uuid.h:9,
  from fs/btrfs/btrfs.c:10:
fs/btrfs/conv-funcs.h: In function ‘btrfs_key_to_disk’:
include/linux/byteorder/generic.h:90:21: error: ‘__cpu_to_le16’ undeclared 
(first use in this function); did you mean ‘__cpu_to_le16p’?
  #define cpu_to_le16 __cpu_to_le16
  ^
fs/btrfs/conv-funcs.h:79:10: note: in expansion of macro ‘cpu_to_le16’
__u16: cpu_to_le16, \
   ^~~

   CC  fs/btrfs/compression.o
In file included from ./arch/powerpc/include/asm/unaligned.h:9,
  from fs/btrfs/compression.c:16:
include/linux/unaligned/access_ok.h:6:19: error: redefinition of 
‘get_unaligned_le16’
  static inline u16 get_unaligned_le16(const void *p)
^~
In file included from fs/btrfs/ctree.h:16,
  from fs/btrfs/btrfs.h:12,
  from fs/btrfs/compression.c:8:
include/linux/unaligned/le_byteshift.h:40:19: note: previous definition of 
‘get_unaligned_le16’ was here
  static inline u16 get_unaligned_le16(const void *p)
^~

Include file asm/unaligned.h contains arch specific macros and functions
for unaligned access as opposite to linux/unaligned le_byteshift.h which
contains macros and functions specific to little endian systems only.

Signed-off-by: Pali Rohár 


Reviewed-by: Qu Wenruo 

Thanks,
Qu

---
  fs/btrfs/btrfs.h | 2 +-
  fs/btrfs/ctree.h | 2 +-
  2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/fs/btrfs/btrfs.h b/fs/btrfs/btrfs.h
index 7d8b395b2646..a52587e0637a 100644
--- a/fs/btrfs/btrfs.h
+++ b/fs/btrfs/btrfs.h
@@ -9,7 +9,7 @@
  #define __BTRFS_BTRFS_H__

  #include 
-#include "conv-funcs.h"
+#include "ctree.h"

  extern struct btrfs_info btrfs_info;
  extern struct btrfs_fs_info *current_fs_info;
diff --git a/fs/btrfs/ctree.h b/fs/btrfs/ctree.h
index 219c410b189f..55112318a330 100644
--- a/fs/btrfs/ctree.h
+++ b/fs/btrfs/ctree.h
@@ -13,7 +13,7 @@
  #include 
  #include 
  #include 
-#include 
+#include 
  #include 
  #include "kernel-shared/btrfs_tree.h"
  #include "crypto/hash.h"

Re: [PATCH] arm: dts: imx8mp: Import GPCv2 subset, HSIOMIX and USB PD

[Tim Harvey]

On Fri, Apr 1, 2022 at 7:55 AM Marek Vasut  wrote:
>
> Add DT bindings for a subset of GPCv2 which handles USB and PCIe PDs,
> HSIOMIX PD controller and missing USB PD properties. This is required
> to bring up the DWC3 USB controller up.
>
> This is based on linux next and patches which are still pending
> review, but which are likely going to be part of Linux 5.19:
> b2d67d7bdf74 ("arm64: dts: imx8mp: disable usb3_phy1")
> 290918c72a29 ("arm64: dts: imx8mp: Add memory for USB3 glue layer to usb3 
> nodes")
> https://www.spinics.net/lists/arm-kernel/msg958501.html
>
> Signed-off-by: Marek Vasut 
> Cc: Fabio Estevam 
> Cc: Peng Fan 
> Cc: Stefano Babic 
> ---
>  arch/arm/dts/imx8mp.dtsi | 72 ++--
>  1 file changed, 70 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/dts/imx8mp.dtsi b/arch/arm/dts/imx8mp.dtsi
> index f9d64253c8a..79b65750da9 100644
> --- a/arch/arm/dts/imx8mp.dtsi
> +++ b/arch/arm/dts/imx8mp.dtsi
> @@ -4,6 +4,7 @@
>   */
>
>  #include 
> +#include 
>  #include 
>  #include 
>  #include 
> @@ -434,6 +435,44 @@
> interrupts = ;
> #reset-cells = <1>;
> };
> +
> +   gpc: gpc@303a {
> +   compatible = "fsl,imx8mp-gpc";
> +   reg = <0x303a 0x1000>;
> +   interrupt-parent = <>;
> +   interrupt-controller;
> +   #interrupt-cells = <3>;
> +
> +   pgc {
> +   #address-cells = <1>;
> +   #size-cells = <0>;
> +
> +   pgc_pcie_phy: power-domain@1 {
> +   #power-domain-cells = <0>;
> +   reg = 
> ;
> +   };
> +
> +   pgc_usb1_phy: power-domain@2 {
> +   #power-domain-cells = <0>;
> +   reg = 
> ;
> +   };
> +
> +   pgc_usb2_phy: power-domain@3 {
> +   #power-domain-cells = <0>;
> +   reg = 
> ;
> +   };
> +
> +   pgc_hsiomix: power-domains@17 {
> +   #power-domain-cells = <0>;
> +   reg = 
> ;
> +   clocks = < 
> IMX8MP_CLK_HSIO_AXI>,
> +< 
> IMX8MP_CLK_HSIO_ROOT>;
> +   assigned-clocks = < 
> IMX8MP_CLK_HSIO_AXI>;
> +   assigned-clock-parents = 
> < IMX8MP_SYS_PLL2_500M>;
> +   assigned-clock-rates = 
> <5>;
> +   };
> +   };
> +   };
> };
>
> aips2: bus@3040 {
> @@ -842,6 +881,28 @@
> };
> };
>
> +   aips4: bus@32c0 {
> +   compatible = "fsl,aips-bus", "simple-bus";
> +   reg = <0x32c0 0x40>;
> +   #address-cells = <1>;
> +   #size-cells = <1>;
> +   ranges;
> +
> +   hsio_blk_ctrl: blk-ctrl@32f1 {
> +   compatible = "fsl,imx8mp-hsio-blk-ctrl", 
> "syscon";
> +   reg = <0x32f1 0x24>;
> +   clocks = < IMX8MP_CLK_USB_ROOT>,
> +< IMX8MP_CLK_PCIE_ROOT>;
> +   clock-names = "usb", "pcie";
> +   power-domains = <_hsiomix>, 
> <_hsiomix>,
> +   <_usb1_phy>, 
> <_usb2_phy>,
> +   <_hsiomix>, 
> <_pcie_phy>;
> +   power-domain-names = "bus", "usb", "usb-phy1",
> +"usb-phy2", "pcie", 
> "pcie-phy";
> +   #power-domain-cells = <1>;
> +   };
> +   };
> +
> gic: interrupt-controller@3880 {
> compatible = "arm,gic-v3";
> reg = <0x3880 0x1>,
> @@ -865,17 +926,20 @@
> clock-names = "phy";
> assigned-clocks = < IMX8MP_CLK_USB_PHY_REF>;
> 

Re: [PATCH 2/2] usb: dwc3: Implement .glue_configure for i.MX8MP

[Tim Harvey]

On Fri, Apr 1, 2022 at 7:32 AM Marek Vasut  wrote:
>
> The i.MX8MP glue needs to be configured based on a couple of DT
> properties, implement .glue_configure callback to parse those DT
> properties and configure the glue accordingly.
>
> Signed-off-by: Marek Vasut 
> Cc: Angus Ainslie 
> Cc: Bin Meng 
> Cc: Fabio Estevam 
> Cc: Kunihiko Hayashi 
> Cc: Michal Simek 
> Cc: Peng Fan 
> Cc: Stefano Babic 
> ---
>  drivers/usb/dwc3/dwc3-generic.c | 52 +
>  1 file changed, 52 insertions(+)
>
> diff --git a/drivers/usb/dwc3/dwc3-generic.c b/drivers/usb/dwc3/dwc3-generic.c
> index 7e3814207e4..6cf844cb483 100644
> --- a/drivers/usb/dwc3/dwc3-generic.c
> +++ b/drivers/usb/dwc3/dwc3-generic.c
> @@ -223,6 +223,57 @@ struct dwc3_glue_ops {
>enum usb_dr_mode mode);
>  };
>
> +void dwc3_imx8mp_glue_configure(struct udevice *dev, int index,
> +   enum usb_dr_mode mode)
> +{
> +/* USB glue registers */
> +#define USB_CTRL0  0x00
> +#define USB_CTRL1  0x04
> +
> +#define USB_CTRL0_PORTPWR_EN   BIT(12) /* 1 - PPC enabled (default) */
> +#define USB_CTRL0_USB3_FIXED   BIT(22) /* 1 - USB3 permanent attached */
> +#define USB_CTRL0_USB2_FIXED   BIT(23) /* 1 - USB2 permanent attached */
> +
> +#define USB_CTRL1_OC_POLARITY  BIT(16) /* 0 - HIGH / 1 - LOW */
> +#define USB_CTRL1_PWR_POLARITY BIT(17) /* 0 - HIGH / 1 - LOW */
> +   fdt_addr_t regs = dev_read_addr_index(dev, 1);
> +   void *base = map_physmem(regs, 0x8, MAP_NOCACHE);
> +   u32 value;
> +
> +   value = readl(base + USB_CTRL0);
> +
> +   if (dev_read_bool(dev, "fsl,permanently-attached"))
> +   value |= (USB_CTRL0_USB2_FIXED | USB_CTRL0_USB3_FIXED);
> +   else
> +   value &= ~(USB_CTRL0_USB2_FIXED | USB_CTRL0_USB3_FIXED);
> +
> +   if (dev_read_bool(dev, "fsl,disable-port-power-control"))
> +   value &= ~(USB_CTRL0_PORTPWR_EN);
> +   else
> +   value |= USB_CTRL0_PORTPWR_EN;
> +
> +   writel(value, base + USB_CTRL0);
> +
> +   value = readl(base + USB_CTRL1);
> +   if (dev_read_bool(dev, "fsl,over-current-active-low"))
> +   value |= USB_CTRL1_OC_POLARITY;
> +   else
> +   value &= ~USB_CTRL1_OC_POLARITY;
> +
> +   if (dev_read_bool(dev, "fsl,power-active-low"))
> +   value |= USB_CTRL1_PWR_POLARITY;
> +   else
> +   value &= ~USB_CTRL1_PWR_POLARITY;
> +
> +   writel(value, base + USB_CTRL1);
> +
> +   unmap_physmem(base, MAP_NOCACHE);
> +}
> +
> +struct dwc3_glue_ops imx8mp_ops = {
> +   .glue_configure = dwc3_imx8mp_glue_configure,
> +};
> +
>  void dwc3_ti_glue_configure(struct udevice *dev, int index,
> enum usb_dr_mode mode)
>  {
> @@ -464,6 +515,7 @@ static const struct udevice_id dwc3_glue_ids[] = {
> { .compatible = "rockchip,rk3328-dwc3" },
> { .compatible = "rockchip,rk3399-dwc3" },
> { .compatible = "qcom,dwc3" },
> +   { .compatible = "fsl,imx8mp-dwc3", .data = (ulong)_ops },
> { .compatible = "fsl,imx8mq-dwc3" },
> { .compatible = "intel,tangier-dwc3" },
> { }
> --
> 2.35.1
>

Thanks for working on this!

This helps get DWC3 USB working on IMX8MP.

For both patches in this series:
Tested-By: Tim Harvey  #imx8mp-venice-gw74xx

Best Regards,

Tim

Re: [PATCH v2] clk: imx8mp: Fill in DWC3 USB, USB PHY, HSIOMIX clock

[Tim Harvey]

On Wed, Apr 6, 2022 at 9:03 PM Peng Fan (OSS)  wrote:
>
>
>
> On 2022/4/1 22:30, Marek Vasut wrote:
> > Add clock tables required to bring up DWC3 USB, USB PHY and HSIOMIX domain.
> >
> > Signed-off-by: Marek Vasut 
> > Cc: Fabio Estevam 
> > Cc: Peng Fan 
> > Cc: Stefano Babic 
> > Cc: Ye Li 
>
> Reviewed-by: Peng Fan 
>
> > ---
> > V2: - Get and probe 24m clock without registering it again (suggested by Ye)
> >  - Add 32k clock the same way for usb_root_clk
> > ---
> >   drivers/clk/imx/clk-imx8mp.c | 30 ++
> >   1 file changed, 30 insertions(+)
> >
> > diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c
> > index c77500bcce0..041ba5321a3 100644
> > --- a/drivers/clk/imx/clk-imx8mp.c
> > +++ b/drivers/clk/imx/clk-imx8mp.c
> > @@ -76,6 +76,10 @@ static const char *imx8mp_a53_sels[] = {"clock-osc-24m", 
> > "arm_pll_out", "sys_pll
> >   "sys_pll2_1000m", "sys_pll1_800m", 
> > "sys_pll1_400m",
> >   "audio_pll1_out", "sys_pll3_out", };
> >
> > +static const char *imx8mp_hsio_axi_sels[] = {"clock-osc-24m", 
> > "sys_pll2_500m", "sys_pll1_800m",
> > +  "sys_pll2_100m", 
> > "sys_pll2_200m", "clk_ext2",
> > +  "clk_ext4", "audio_pll2_out", };
> > +
> >   static const char *imx8mp_main_axi_sels[] = {"clock-osc-24m", 
> > "sys_pll2_333m", "sys_pll1_800m",
> >"sys_pll2_250m", 
> > "sys_pll2_1000m", "audio_pll1_out",
> >"video_pll1_out", 
> > "sys_pll1_100m",};
> > @@ -156,6 +160,14 @@ static const char *imx8mp_uart4_sels[] = 
> > {"clock-osc-24m", "sys_pll1_80m", "sys_
> > "sys_pll2_100m", "sys_pll3_out", 
> > "clk_ext2",
> > "clk_ext3", "audio_pll2_out", };
> >
> > +static const char *imx8mp_usb_core_ref_sels[] = {"clock-osc-24m", 
> > "sys_pll1_100m", "sys_pll1_40m",
> > +  "sys_pll2_100m", 
> > "sys_pll2_200m", "clk_ext2",
> > +  "clk_ext3", 
> > "audio_pll2_out", };
> > +
> > +static const char *imx8mp_usb_phy_ref_sels[] = {"clock-osc-24m", 
> > "sys_pll1_100m", "sys_pll1_40m",
> > + "sys_pll2_100m", 
> > "sys_pll2_200m", "clk_ext2",
> > + "clk_ext3", "audio_pll2_out", 
> > };
> > +
> >   static const char *imx8mp_gic_sels[] = {"clock-osc-24m", "sys_pll2_200m", 
> > "sys_pll1_40m",
> >   "sys_pll2_100m", "sys_pll1_800m",
> >   "sys_pll2_500m", "clk_ext4", 
> > "audio_pll2_out" };
> > @@ -276,7 +288,9 @@ static struct clk_ops imx8mp_clk_ops = {
> >
> >   static int imx8mp_clk_probe(struct udevice *dev)
> >   {
> > + struct clk osc_24m_clk, osc_32k_clk;
> >   void __iomem *base;
> > + int ret;
> >
> >   base = (void *)ANATOP_BASE_ADDR;
> >
> > @@ -324,6 +338,16 @@ static int imx8mp_clk_probe(struct udevice *dev)
> >   clk_dm(IMX8MP_SYS_PLL2_500M, imx_clk_fixed_factor("sys_pll2_500m", 
> > "sys_pll2_out", 1, 2));
> >   clk_dm(IMX8MP_SYS_PLL2_1000M, imx_clk_fixed_factor("sys_pll2_1000m", 
> > "sys_pll2_out", 1, 1));
> >
> > + ret = clk_get_by_name(dev, "osc_24m", _24m_clk);
> > + if (ret)
> > + return ret;
> > + clk_dm(IMX8MP_CLK_24M, dev_get_clk_ptr(osc_24m_clk.dev));
> > +
> > + ret = clk_get_by_name(dev, "osc_32k", _32k_clk);
> > + if (ret)
> > + return ret;
> > + clk_dm(IMX8MP_CLK_32K, dev_get_clk_ptr(osc_32k_clk.dev));
> > +
> >   base = dev_read_addr_ptr(dev);
> >   if (!base)
> >   return -EINVAL;
> > @@ -332,6 +356,7 @@ static int imx8mp_clk_probe(struct udevice *dev)
> >   clk_dm(IMX8MP_CLK_A53_CG, imx_clk_gate3("arm_a53_cg", "arm_a53_src", 
> > base + 0x8000, 28));
> >   clk_dm(IMX8MP_CLK_A53_DIV, imx_clk_divider2("arm_a53_div", 
> > "arm_a53_cg", base + 0x8000, 0, 3));
> >
> > + clk_dm(IMX8MP_CLK_HSIO_AXI, imx8m_clk_composite("hsio_axi", 
> > imx8mp_hsio_axi_sels, base + 0x8380));
> >   clk_dm(IMX8MP_CLK_MAIN_AXI, imx8m_clk_composite_critical("main_axi", 
> > imx8mp_main_axi_sels, base + 0x8800));
> >   clk_dm(IMX8MP_CLK_ENET_AXI, imx8m_clk_composite_critical("enet_axi", 
> > imx8mp_enet_axi_sels, base + 0x8880));
> >   clk_dm(IMX8MP_CLK_NAND_USDHC_BUS, 
> > imx8m_clk_composite_critical("nand_usdhc_bus", imx8mp_nand_usdhc_sels, base 
> > + 0x8900));
> > @@ -361,6 +386,8 @@ static int imx8mp_clk_probe(struct udevice *dev)
> >   clk_dm(IMX8MP_CLK_UART2, imx8m_clk_composite("uart2", 
> > imx8mp_uart2_sels, base + 0xaf80));
> >   clk_dm(IMX8MP_CLK_UART3, imx8m_clk_composite("uart3", 
> > imx8mp_uart3_sels, base + 0xb000));
> >   clk_dm(IMX8MP_CLK_UART4, 

Re: [PATCH] phy: phy-imx8mq-usb: Add support for i.MX8MP USB PHY

[Tim Harvey]

On Thu, Mar 31, 2022 at 6:26 PM Marek Vasut  wrote:
>
> Add initial support for i.MX8MP USB PHY, i.MX8MP USB is similar to
> the i.MX8MQ, except for clock and power domain design customization.
>
> Signed-off-by: Marek Vasut 
> Cc: Fabio Estevam 
> Cc: Peng Fan 
> Cc: Stefano Babic 
> ---
>  drivers/phy/Kconfig  |  6 ++--
>  drivers/phy/phy-imx8mq-usb.c | 66 +---
>  2 files changed, 65 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
> index d79798429b1..c01d9e09b90 100644
> --- a/drivers/phy/Kconfig
> +++ b/drivers/phy/Kconfig
> @@ -275,11 +275,11 @@ config PHY_MTK_TPHY
>   so you can easily distinguish them by banks layout.
>
>  config PHY_IMX8MQ_USB
> -   bool "NXP i.MX8MQ USB PHY Driver"
> +   bool "NXP i.MX8MQ/i.MX8MP USB PHY Driver"
> depends on PHY
> -   depends on IMX8MQ
> +   depends on IMX8MQ || IMX8MP
> help
> - Support the USB3.0 PHY in NXP i.MX8MQ SoC
> + Support the USB3.0 PHY in NXP i.MX8MQ or i.MX8MP SoC
>
>  config PHY_XILINX_ZYNQMP
> tristate "Xilinx ZynqMP PHY driver"
> diff --git a/drivers/phy/phy-imx8mq-usb.c b/drivers/phy/phy-imx8mq-usb.c
> index afbc7ad8dd4..69f01de5553 100644
> --- a/drivers/phy/phy-imx8mq-usb.c
> +++ b/drivers/phy/phy-imx8mq-usb.c
> @@ -9,7 +9,9 @@
>  #include 
>  #include 
>  #include 
> +#include 
>  #include 
> +#include 
>  #include 
>  #include 
>
> @@ -68,17 +70,22 @@
>  #define PHY_STS0_FSVPLUS   BIT(3)
>  #define PHY_STS0_FSVMINUS  BIT(2)
>
> +enum imx8mpq_phy_type {
> +   IMX8MQ_PHY,
> +   IMX8MP_PHY,
> +};
> +
>  struct imx8mq_usb_phy {
>  #if CONFIG_IS_ENABLED(CLK)
> struct clk phy_clk;
>  #endif
> void __iomem *base;
> +   enum imx8mpq_phy_type type;
>  };
>
>  static const struct udevice_id imx8mq_usb_phy_of_match[] = {
> -   {
> -   .compatible = "fsl,imx8mq-usb-phy",
> -   },
> +   { .compatible = "fsl,imx8mq-usb-phy", .data = IMX8MQ_PHY },
> +   { .compatible = "fsl,imx8mp-usb-phy", .data = IMX8MP_PHY },
> {},
>  };
>
> @@ -111,6 +118,56 @@ static int imx8mq_usb_phy_init(struct phy *usb_phy)
> return 0;
>  }
>
> +static int imx8mp_usb_phy_init(struct phy *usb_phy)
> +{
> +   struct udevice *dev = usb_phy->dev;
> +   struct imx8mq_usb_phy *imx_phy = dev_get_priv(dev);
> +   u32 value;
> +
> +   /* USB3.0 PHY signal fsel for 24M ref */
> +   value = readl(imx_phy->base + PHY_CTRL0);
> +   value &= ~PHY_CTRL0_FSEL_MASK;
> +   value |= FIELD_PREP(PHY_CTRL0_FSEL_MASK, PHY_CTRL0_FSEL_24M);
> +   writel(value, imx_phy->base + PHY_CTRL0);
> +
> +   /* Disable alt_clk_en and use internal MPLL clocks */
> +   value = readl(imx_phy->base + PHY_CTRL6);
> +   value &= ~(PHY_CTRL6_ALT_CLK_SEL | PHY_CTRL6_ALT_CLK_EN);
> +   writel(value, imx_phy->base + PHY_CTRL6);
> +
> +   value = readl(imx_phy->base + PHY_CTRL1);
> +   value &= ~(PHY_CTRL1_VDATSRCENB0 | PHY_CTRL1_VDATDETENB0);
> +   value |= PHY_CTRL1_RESET | PHY_CTRL1_ATERESET;
> +   writel(value, imx_phy->base + PHY_CTRL1);
> +
> +   value = readl(imx_phy->base + PHY_CTRL0);
> +   value |= PHY_CTRL0_REF_SSP_EN;
> +   writel(value, imx_phy->base + PHY_CTRL0);
> +
> +   value = readl(imx_phy->base + PHY_CTRL2);
> +   value |= PHY_CTRL2_TXENABLEN0 | PHY_CTRL2_OTG_DISABLE;
> +   writel(value, imx_phy->base + PHY_CTRL2);
> +
> +   udelay(10);
> +
> +   value = readl(imx_phy->base + PHY_CTRL1);
> +   value &= ~(PHY_CTRL1_RESET | PHY_CTRL1_ATERESET);
> +   writel(value, imx_phy->base + PHY_CTRL1);
> +
> +   return 0;
> +}
> +
> +static int imx8mpq_usb_phy_init(struct phy *usb_phy)
> +{
> +   struct udevice *dev = usb_phy->dev;
> +   struct imx8mq_usb_phy *imx_phy = dev_get_priv(dev);
> +
> +   if (imx_phy->type == IMX8MP_PHY)
> +   return imx8mp_usb_phy_init(usb_phy);
> +   else
> +   return imx8mq_usb_phy_init(usb_phy);
> +}
> +
>  static int imx8mq_usb_phy_power_on(struct phy *usb_phy)
>  {
> struct udevice *dev = usb_phy->dev;
> @@ -158,7 +215,7 @@ static int imx8mq_usb_phy_exit(struct phy *usb_phy)
>  }
>
>  struct phy_ops imx8mq_usb_phy_ops = {
> -   .init = imx8mq_usb_phy_init,
> +   .init = imx8mpq_usb_phy_init,
> .power_on = imx8mq_usb_phy_power_on,
> .power_off = imx8mq_usb_phy_power_off,
> .exit = imx8mq_usb_phy_exit,
> @@ -168,6 +225,7 @@ int imx8mq_usb_phy_probe(struct udevice *dev)
>  {
> struct imx8mq_usb_phy *priv = dev_get_priv(dev);
>
> +   priv->type = dev_get_driver_data(dev);
> priv->base = dev_read_addr_ptr(dev);
>
> if (!priv->base)
> --
> 2.35.1
>

Thanks for working on this!

This helps get DWC3 USB working on IMX8MP.

Tested-By: Tim Harvey  #imx8mp-venice-gw74xx

Best Regards,

Tim

Re: [PATCH] imx: power-domain: Add i.MX8MP support

[Tim Harvey]

On Thu, Apr 7, 2022 at 1:33 AM Marek Vasut  wrote:
>
> On 4/7/22 06:01, Peng Fan (OSS) wrote:
> >
> >
> > On 2022/4/1 9:12, Marek Vasut wrote:
> >> Add i.MX8MP power domain handling into the driver. This is based on the
> >> Linux GPCv2 driver state which is soon to be in Linux next.
> >
> > Do we really need this in U-Boot? You will also port the blk-ctrl part?
> > That would be lots code!
>
> I already did sent HSIOMIX driver too, that's all we need to get USB and
> PCIe going in U-Boot, and get U-Boot working without running ATF, which
> makes new platform bring up far easier.
>
> The "lots of code" that's in Linux is for graphics pipeline and we don't
> need that in U-Boot, so we conveniently avoid it here.

Marek,

Thanks for working on this!

This helps get DWC3 USB working on IMX8MP.

Tested-By: Tim Harvey  #imx8mp-venice-gw74xx

Best Regards,

Tim

Re: [PATCH v2] imx: power-domain: Add i.MX8MP HSIOMIX driver

[Tim Harvey]

On Fri, Apr 1, 2022 at 7:06 AM Marek Vasut  wrote:
>
> Add trivial driver for i.MX8MP HSIOMIX handling. This is responsible
> for enabling the GPCv2 power domains and clock for USB 3.0 and PCIe
> in the correct order. Currently supported is the USB 3.0 part which
> can be tested, PCIe support should be easy to add.
>
> Signed-off-by: Marek Vasut 
> Cc: Fabio Estevam 
> Cc: Peng Fan 
> Cc: Stefano Babic 
> ---
> V2: Drop two left over unused variables which triggered build warning
> ---
>  drivers/power/domain/Kconfig  |   7 ++
>  drivers/power/domain/Makefile |   1 +
>  drivers/power/domain/imx8mp-hsiomix.c | 159 ++
>  3 files changed, 167 insertions(+)
>  create mode 100644 drivers/power/domain/imx8mp-hsiomix.c
>
> diff --git a/drivers/power/domain/Kconfig b/drivers/power/domain/Kconfig
> index 04fc0054323..7e1b8c072fa 100644
> --- a/drivers/power/domain/Kconfig
> +++ b/drivers/power/domain/Kconfig
> @@ -40,6 +40,13 @@ config IMX8M_POWER_DOMAIN
>   Enable support for manipulating NXP i.MX8M on-SoC power domains via
>   requests to the ATF.
>
> +config IMX8MP_HSIOMIX_BLKCTRL
> +   bool "Enable i.MX8MP HSIOMIX domain driver"
> +   depends on POWER_DOMAIN && IMX8MP
> +   select CLK
> +   help
> + Enable support for manipulating NXP i.MX8MP on-SoC HSIOMIX block 
> controller.
> +
>  config MTK_POWER_DOMAIN
> bool "Enable the MediaTek power domain driver"
> depends on POWER_DOMAIN && ARCH_MEDIATEK
> diff --git a/drivers/power/domain/Makefile b/drivers/power/domain/Makefile
> index 7c8af67dbd6..e6244776216 100644
> --- a/drivers/power/domain/Makefile
> +++ b/drivers/power/domain/Makefile
> @@ -8,6 +8,7 @@ obj-$(CONFIG_APPLE_PMGR_POWER_DOMAIN) += apple-pmgr.o
>  obj-$(CONFIG_BCM6328_POWER_DOMAIN) += bcm6328-power-domain.o
>  obj-$(CONFIG_IMX8_POWER_DOMAIN) += imx8-power-domain-legacy.o 
> imx8-power-domain.o
>  obj-$(CONFIG_IMX8M_POWER_DOMAIN) += imx8m-power-domain.o
> +obj-$(CONFIG_IMX8MP_HSIOMIX_BLKCTRL) += imx8mp-hsiomix.o
>  obj-$(CONFIG_MTK_POWER_DOMAIN) += mtk-power-domain.o
>  obj-$(CONFIG_MESON_GX_VPU_POWER_DOMAIN) += meson-gx-pwrc-vpu.o
>  obj-$(CONFIG_MESON_EE_POWER_DOMAIN) += meson-ee-pwrc.o
> diff --git a/drivers/power/domain/imx8mp-hsiomix.c 
> b/drivers/power/domain/imx8mp-hsiomix.c
> new file mode 100644
> index 000..6a721a934a7
> --- /dev/null
> +++ b/drivers/power/domain/imx8mp-hsiomix.c
> @@ -0,0 +1,159 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2022 Marek Vasut 
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +#include 
> +
> +#define GPR_REG0   0x0
> +#define  PCIE_CLOCK_MODULE_EN  BIT(0)
> +#define  USB_CLOCK_MODULE_EN   BIT(1)
> +
> +struct imx8mp_hsiomix_priv {
> +   void __iomem *base;
> +   struct clk clk_usb;
> +   struct power_domain pd_bus;
> +   struct power_domain pd_usb;
> +   struct power_domain pd_usb_phy1;
> +   struct power_domain pd_usb_phy2;
> +};
> +
> +static int imx8mp_hsiomix_on(struct power_domain *power_domain)
> +{
> +   struct udevice *dev = power_domain->dev;
> +   struct imx8mp_hsiomix_priv *priv = dev_get_priv(dev);
> +   struct power_domain *domain;
> +   int ret;
> +
> +   ret = power_domain_on(>pd_bus);
> +   if (ret)
> +   return ret;
> +
> +   if (power_domain->id == IMX8MP_HSIOBLK_PD_USB) {
> +   domain = >pd_usb;
> +   } else if (power_domain->id == IMX8MP_HSIOBLK_PD_USB_PHY1) {
> +   domain = >pd_usb_phy1;
> +   } else if (power_domain->id == IMX8MP_HSIOBLK_PD_USB_PHY2) {
> +   domain = >pd_usb_phy2;
> +   } else {
> +   ret = -EINVAL;
> +   goto err_pd;
> +   }
> +
> +   ret = power_domain_on(domain);
> +   if (ret)
> +   goto err_pd;
> +
> +   ret = clk_enable(>clk_usb);
> +   if (ret)
> +   goto err_clk;
> +
> +   if (power_domain->id == IMX8MP_HSIOBLK_PD_USB)
> +   setbits_le32(priv->base + GPR_REG0, USB_CLOCK_MODULE_EN);
> +
> +   return 0;
> +
> +err_clk:
> +   power_domain_off(domain);
> +err_pd:
> +   power_domain_off(>pd_bus);
> +   return ret;
> +}
> +
> +static int imx8mp_hsiomix_off(struct power_domain *power_domain)
> +{
> +   struct udevice *dev = power_domain->dev;
> +   struct imx8mp_hsiomix_priv *priv = dev_get_priv(dev);
> +
> +   if (power_domain->id == IMX8MP_HSIOBLK_PD_USB)
> +   clrbits_le32(priv->base + GPR_REG0, USB_CLOCK_MODULE_EN);
> +
> +   clk_disable(>clk_usb);
> +
> +   if (power_domain->id == IMX8MP_HSIOBLK_PD_USB)
> +   power_domain_off(>pd_usb);
> +   else if (power_domain->id == IMX8MP_HSIOBLK_PD_USB_PHY1)
> +   power_domain_off(>pd_usb_phy1);
> +   else if (power_domain->id == IMX8MP_HSIOBLK_PD_USB_PHY2)
> +   power_domain_off(>pd_usb_phy2);

Re: [PATCH 3/3] imx: power-domain: Get rid of SMCCC dependency

[Tim Harvey]

On Wed, Mar 30, 2022 at 8:04 PM Marek Vasut  wrote:
>
> This driver is the only SMCCC dependency in iMX8M U-Boot port. Rework
> the driver based on Linux GPCv2 driver to directly control the GPCv2
> block instead of using SMCCC calls. This way, U-Boot can operate the
> i.MX8M power domains without depending on anything else.
>
> This is losely based on Linux GPCv2 driver. The GPU, VPU, MIPI power
> domains are not supported to save space, since they are not useful in
> the bootloader. The only domains kept are ones for HSIO, PCIe, USB.
>
> Signed-off-by: Marek Vasut 
> Cc: Fabio Estevam 
> Cc: Peng Fan 
> Cc: Stefano Babic 
> ---
> NOTE: So far this is tested on MX8MM and MX8MN. MX8MQ is not tested.
> ---
>  drivers/power/domain/Kconfig  |   1 +
>  drivers/power/domain/imx8m-power-domain.c | 379 --
>  2 files changed, 361 insertions(+), 19 deletions(-)
>
> diff --git a/drivers/power/domain/Kconfig b/drivers/power/domain/Kconfig
> index 93d2599d83c..04fc0054323 100644
> --- a/drivers/power/domain/Kconfig
> +++ b/drivers/power/domain/Kconfig
> @@ -35,6 +35,7 @@ config IMX8_POWER_DOMAIN
>  config IMX8M_POWER_DOMAIN
> bool "Enable i.MX8M power domain driver"
> depends on POWER_DOMAIN && ARCH_IMX8M
> +   select CLK
> help
>   Enable support for manipulating NXP i.MX8M on-SoC power domains via
>   requests to the ATF.
> diff --git a/drivers/power/domain/imx8m-power-domain.c 
> b/drivers/power/domain/imx8m-power-domain.c
> index c32dbcc31ae..e2e41cf5fee 100644
> --- a/drivers/power/domain/imx8m-power-domain.c
> +++ b/drivers/power/domain/imx8m-power-domain.c
> @@ -4,6 +4,7 @@
>   */
>
>  #include 
> +#include 
>  #include 
>  #include 
>  #include 
> @@ -12,52 +13,361 @@
>  #include 
>  #include 
>  #include 
> +#include 
>  #include 
> -#include 
> +#include 
> +#include 
> +
> +#include 
> +#include 
> +#include 
>
>  DECLARE_GLOBAL_DATA_PTR;
>
> +#define GPC_PGC_CPU_MAPPING0x0ec
> +
> +#define IMX8M_PCIE2_A53_DOMAIN BIT(15)
> +#define IMX8M_OTG2_A53_DOMAIN  BIT(5)
> +#define IMX8M_OTG1_A53_DOMAIN  BIT(4)
> +#define IMX8M_PCIE1_A53_DOMAIN BIT(3)
> +
> +#define IMX8MM_OTG2_A53_DOMAIN BIT(5)
> +#define IMX8MM_OTG1_A53_DOMAIN BIT(4)
> +#define IMX8MM_PCIE_A53_DOMAIN BIT(3)
> +
> +#define IMX8MN_OTG1_A53_DOMAIN BIT(4)
> +#define IMX8MN_MIPI_A53_DOMAIN BIT(2)
> +
> +#define GPC_PU_PGC_SW_PUP_REQ  0x0f8
> +#define GPC_PU_PGC_SW_PDN_REQ  0x104
> +
> +#define IMX8M_PCIE2_SW_Pxx_REQ BIT(13)
> +#define IMX8M_OTG2_SW_Pxx_REQ  BIT(3)
> +#define IMX8M_OTG1_SW_Pxx_REQ  BIT(2)
> +#define IMX8M_PCIE1_SW_Pxx_REQ BIT(1)
> +
> +#define IMX8MM_OTG2_SW_Pxx_REQ BIT(3)
> +#define IMX8MM_OTG1_SW_Pxx_REQ BIT(2)
> +#define IMX8MM_PCIE_SW_Pxx_REQ BIT(1)
> +
> +#define IMX8MN_OTG1_SW_Pxx_REQ BIT(2)
> +#define IMX8MN_MIPI_SW_Pxx_REQ BIT(0)
> +
> +#define GPC_M4_PU_PDN_FLG  0x1bc
> +
> +#define GPC_PU_PWRHSK  0x1fc
> +
> +#define IMX8MM_HSIO_HSK_PWRDNACKN  (BIT(23) | BIT(24))
> +#define IMX8MM_HSIO_HSK_PWRDNREQN  (BIT(5) | BIT(6))
> +
> +#define IMX8MN_HSIO_HSK_PWRDNACKN  BIT(23)
> +#define IMX8MN_HSIO_HSK_PWRDNREQN  BIT(5)
> +
> +/*
> + * The PGC offset values in Reference Manual
> + * (Rev. 1, 01/2018 and the older ones) GPC chapter's
> + * GPC_PGC memory map are incorrect, below offset
> + * values are from design RTL.
> + */
> +#define IMX8M_PGC_PCIE117
> +#define IMX8M_PGC_OTG1 18
> +#define IMX8M_PGC_OTG2 19
> +#define IMX8M_PGC_PCIE229
> +
> +#define IMX8MM_PGC_PCIE17
> +#define IMX8MM_PGC_OTG118
> +#define IMX8MM_PGC_OTG219
> +
> +#define IMX8MN_PGC_OTG118
> +
> +#define GPC_PGC_CTRL(n)(0x800 + (n) * 0x40)
> +#define GPC_PGC_SR(n)  (GPC_PGC_CTRL(n) + 0xc)
> +
> +#define GPC_PGC_CTRL_PCR   BIT(0)
> +
> +struct imx_pgc_regs {
> +   u16 map;
> +   u16 pup;
> +   u16 pdn;
> +   u16 hsk;
> +};
> +
> +struct imx_pgc_domain {
> +   unsigned long pgc;
> +
> +   const struct {
> +   u32 pxx;
> +   u32 map;
> +   u32 hskreq;
> +   u32 hskack;
> +   } bits;
> +
> +   const bool keep_clocks;
> +};
> +
> +struct imx_pgc_domain_data {
> +   const struct imx_pgc_domain *domains;
> +   size_t domains_num;
> +   const struct imx_pgc_regs *pgc_regs;
> +};
> +
>  struct imx8m_power_domain_plat {
> +   struct power_domain pd;
> +   

Re: [PATCH 5/6] net: add MV88E61xx DSA driver

[Vladimir Oltean]

On Thu, Apr 07, 2022 at 01:33:58PM -0700, Tim Harvey wrote:
> I guess I'll have to invest in tagging packets if you won't accept the
> simplistic approach of not having to tag frames knowing that only one
> port is active at a time.

I genuinely don't know where you got the impression from that I don't
accept the simplistic approach. I gave you an option to make the xmit
and receive ops actually optional at the DSA uclass level so you don't
have to come up with a make-believe tag parsing function. In the end
it goes towards the simplification of the Marvell driver. Let's let them
battle it out for a while and if tag insertion/parsing won't be
necessary even for multi-switch systems we can discuss about removing
that logic completely.

> That said, I have no idea if or when I will re-visit this. Adding a
> DSA version of this driver was something on my personal wish list and
> not something that was necessary by any means by my employer so I may
> have to just drop it as I don't have the personal time to work through
> this part of it or unravelling the mii bus mess in the fec_mxc driver.
> It seems to me there is an issue with trying to create DM_MDIO drivers
> in general as most dt's I've seen wouldn't support the requirements
> yet configure DM_MDIO anyway (meaning if you implemented it you would
> break those boards as I found).

I don't know why there are boards which set CONFIG_DM_MDIO and then
fight against the current trying to survive that config being set.
Maybe you can look into disabling that config option on boards that
aren't prepared to handle it?

Re: [PATCH 1/2] Kconfig: Change SYS_MALLOC_F_LEN default to 0x2000

[Thomas Chou]

Hi Tom,

On 4/7/22 09:33, Tom Rini wrote:

The most commonly used value today is 0x2000 and not 0x400.  Rework the
Kconfig logic to use this more frequently used value as the default.
Signed-off-by: Tom Rini 
---
To make this patch more reviewable, I've omitted the defconfigs where
the in-use value is now the default value.  I've cc'd so many
maintainers however as a frequent issue when enabling more DM migrations
is SYS_MALLOC_F_LEN being too small and 0x400 not being enough and
something like 0x2000 being more reasonable, especially on platforms
that can otherwise easily handle a little more memory usage.
---
  Kconfig   | 9 +++--
  configs/10m50_defconfig   | 1 +
  configs/3c120_defconfig   | 1 +


Reviewed-by: Thomas Chou 

Re: [PATCH 5/6] net: add MV88E61xx DSA driver

[Tim Harvey]

On Sat, Apr 2, 2022 at 4:17 PM Vladimir Oltean  wrote:
>
> On Fri, Apr 01, 2022 at 01:24:48PM -0700, Tim Harvey wrote:
> > > > > Why is mv88e61xx_dsa_xmit() no-op?
> > > >
> > > > For DSA dsa-uclass calls the switch master eth device send function
> > > > after calling the dsa_ops->xmit function so that a dsa driver can add
> > > > any header/footer if needed. The function is required but in my case I
> > > > don't care about header/footer tagging or vlan as only 1 port is
> > > > active at a time in U-Boot so I just return success.
> > >
> > > So if I make one port active, the other are completely disabled? They
> > > won't even switch? Is that how DSA uclass is supposed to work in U-Boot?
> > >
> > > I would think that it should be somehow configurable instead.
> >
> > Marek,
> >
> > I'll let Vladimir correct me if I'm wrong but my understanding is DSA
> > in U-Boot is not intended to allow switches to forward packets on
> > their own from port to port but instead just for forwarding packets
> > between the active port and the MAC connected to the CPU (at least
> > that's what I intended when I wrote the ksz9477 dsa driver
> > previously).
> >
> > In my opinion what a DSA driver provides is avoidance of putting
> > switches in forwarding mode having the potential of easily creating
> > bridge loops. With the existing mv88e61xx driver I've had users create
> > bridge loops often.
>
> DM_DSA follows the guiding principle that the user doesn't care about
> the switch more than being able to transfer a boot image through TFTP
> without causing switching loops in the network. The way this is achieved
> is by following the "port extender" model which is exactly the way in
> which Linux DSA was first introduced, prior to having support for L2
> bridging offloads via switchdev. For U-Boot, packet forwarding across
> front ports is effectively a non-goal. In fact, what we want to avoid is
> the proliferation of bloatware such as cmd/ethsw.c, which can and will
> be abused to preconfigure a switch from the bootloader so you won't have
> to manage it from Linux.

Vladimir,

I also want to avoid the proliferation of bloatware which is primarily
why I want to avoid having to muck with packets when there is only one
port active at a time which I feel is completely unnecessary.

>
> Tim, I accept that U-Boot's Ethernet usage model (a single device active
> at a time, with RX in synchronous poll mode) simplifies DM_DSA to the
> point that creating/parsing DSA tags (which serve the purpose of
> multiplexing/demultiplexing packets to/from switch ports) on the CPU is
> more or less redundant when said multiplexing can be achieved on a time
> basis by disabling all the ports except the required source/destination
> switch port and the CPU port. This holds true even when DM_DSA gains
> support for multi-switch setups.
>
> What I would like, however, is to avoid driver code putting pressure on
> the DSA uclass code. I don't really like the tracking of the priv->active_port
> as being the port on which ->port_enable was last called. The only reason
> this is done is to appease the "port_index != port_pdata->index" check
> from dsa_port_recv(). In turn, this is because the ->xmit() and ->rcv()
> DSA ops are not optional. Let's make them optional instead, instead of
> adding code to a C file that indirectly depends on the code structure
> from another C file.
>
> But ->port_enable() and ->port_disable() are optional too, and that's
> not okay, because if the driver doesn't provide a way to enable/disable
> ports, packets can flow anywhere.
>
> I suggest making it clear to driver writers that it has to be one or the
> other by sanitizing the ops:
>
> diff --git a/net/dsa-uclass.c b/net/dsa-uclass.c
> index 9ff55a02fb23..ea860fa715bb 100644
> --- a/net/dsa-uclass.c
> +++ b/net/dsa-uclass.c
> @@ -342,6 +342,19 @@ U_BOOT_DRIVER(dsa_port) = {
> .plat_auto = sizeof(struct eth_pdata),
>  };
>
> +static int dsa_sanitize_ops(struct udevice *dev)
> +{
> +   struct dsa_ops *ops = dsa_get_ops(dev);
> +
> +   if ((!ops->xmit || !ops->rcv) &&
> +   (!ops->port_enable && !ops->port_disable)) {
> +   dev_err(dev, "Packets cannot be steered to ports\n");
> +   return -EINVAL;
> +   }
> +
> +   return 0;
> +}
> +
>  /*
>   * This function mostly deals with pulling information out of the device tree
>   * into the pdata structure.
> @@ -358,6 +371,10 @@ static int dsa_post_bind(struct udevice *dev)
> if (!ofnode_valid(node))
> return -ENODEV;
>
> +   err = dsa_sanitize_ops(dev);
> +   if (err)
> +   return err;
> +
> pdata->master_node = ofnode_null();
>
> node = ofnode_find_subnode(node, "ports");
>
>
> Then we can properly make rcv() and xmit() optional at the level of the
> DSA uclass. This way we avoid the tail chasing approach of pretending
> that "return priv->active_port" _is_ the way to decode a packet for a
> certain 

[RFC] Data structure for information handoff between firmware boot stages

[Jose Marinho]

Hi All,

The topic of information handoff between TF-A's BL31 and BL33 (e.g. U-boot 
proper, EDK2) was discussed last year in the TF-A and U-boot mailing lists [1], 
[2].

Examples of information to be handed off between firmware stages are the TPM 
log, HOB nodes, etc.
Having a standard data structure which is usable/supported by every community 
contributes to code reuse and leads to simpler codebase maintenance.

Some already existing data structures, such as the UEFI HOB list [3], and the 
Bloblist from U-boot, were proposed to be employed for the handoffs.
There are pros and cons with both HOBs and Bloblist.
The discussion settled with a consensus that a data structure ought to be 
defined which encapsulates the best traits of HOBs and Bloblist.

Properties that the data structure should have:
- node types identified by an integer,
- easily relocatable,
- straightforward to append new nodes,
- easy to read and append to from resource constrained environments.

The data structure should be suitable to pass information between different 
firmware stages, such as:
U-boot SPL -> BL31 -> U-boot
BL1 -> BL2 -> BL31 -> U-boot

As requested in the ML, an initial proposal was drafted [4].
The document [4] is an initial proposal (at an alpha stage).
The document [4] is being circulated for the purpose of gathering initial 
feedback.
This proposal is closely aligned with an ongoing effort in the u-boot mailing 
list [5].
The proposal defines 1) a set of standard nodes and 2) the registers used at 
the handoff boundary.

Standard nodes:
- fdt node: HW description fdt,
- HOB node,
- ACPI table node: the main use-case for this node is to carry the TPM log.

The document [4] accommodates an OEM range, which enables IMPDEF nodes to be 
caried in the handoff list.
By definition, the nodes in the OEM range are not standard and can be defined 
per-platform.

Note: the document [4] encapsulates the standard node definition as that is the 
simplest approach for feedback gathering.
Once there is sufficient consensus around the proposal, the standard node 
definitions should be moved to a project independent repository. The repository 
location is TBD.
The list of standard nodes is expected to grow with community contribution.

Kind Regards,
Jose

[1] 
https://lists.trustedfirmware.org/archives/list/t...@lists.trustedfirmware.org/message/LUIUOVGUMVWID5RUMTYA463KGIU2EHIU/
[2] 
https://lore.kernel.org/u-boot/CAODwPW_FwFN1E84cV1+nC1aiahiwOL-TV=mp_6o8h0y9+pc...@mail.gmail.com/
[3] https://uefi.org/sites/default/files/resources/PI_Spec_1_6.pdf
[4] https://developer.arm.com/documentation/den0135/a
[5] https://lore.kernel.org/u-boot/20220113022625.413990-1-...@chromium.org/

Re: [PATCH] mtd: spi-nor-ids: Add Winbond W25Q128JW ID

[Marek Vasut]

On 3/9/22 04:18, Marek Vasut wrote:

Add ID for Winbond W25Q128JW device. This is a 128 Mbit QSPI NOR.
Tested on W25Q128JWPIM part.

Signed-off-by: Marek Vasut 
Cc: Horatiu Vultur 
Cc: Jagan Teki 
Cc: Simon Goldschmidt 
Cc: Stefan Roese 
Cc: Vignesh R 
---
  drivers/mtd/spi/spi-nor-ids.c | 5 +
  1 file changed, 5 insertions(+)

diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
index b551ebd75ef..e2d09fc747d 100644
--- a/drivers/mtd/spi/spi-nor-ids.c
+++ b/drivers/mtd/spi/spi-nor-ids.c
@@ -345,6 +345,11 @@ const struct flash_info spi_nor_ids[] = {
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
},
+   {
+   INFO("w25q128jw", 0xef8018, 0, 64 * 1024, 256,
+   SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
+   SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
+   },
{
INFO("w25q256fw", 0xef6019, 0, 64 * 1024, 512,
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |


It would be good to apply this patch.

Re: [PATCH] dt-bindings: nvmem: u-boot, env: add Broadcom's variant binding

[Rob Herring]

On Thu, Apr 07, 2022 at 04:55:14AM -0700, Joel Peshkin wrote:
> Hi Rafal,
> 
>The first 32b value is a magic number (endian swapped mnemonic of "uEnv"
> short for "u-boot environment").   Finding that magic number of a 4K
> boundary followed by a length and then a u-boot environment with a valid
> CRC permits a scan of the flash partition to locate the environment without
> knowing a-priori where it is.

So it doesn't need to be described in DT? But how does one identify 
whether to scan the flash or not. You wouldn't want to do that one every 
platform. IOW, it's a sufficient discovery mechanism for a custom build, 
but not generic OS.

Rob

Re: [PATCH v2 1/2] env: setenv add resolve value option

[Tom Rini]

On Fri, Nov 19, 2021 at 12:36:46PM +0800, Artem Lapkin wrote:
> Add possibility setup env variable with additional resolving vars inside

> value.
> 
> Usage examples:
> 
> => setenv a hello; setenv b world; setenv c '${a} ${b}'
> => setenv -r d '${c}! ${a}...'
> => printenv d
> d=hello world! hello...
> 
> /* internal usage example */
> env_resolve("d", "${c}! ${a}...");
> /* d="hello world! hello..." */
> 
> Signed-off-by: Artem Lapkin 
> Reviewed-by: Simon Glass 

This break building on a number of platforms such as am335x_evm.

-- 
Tom


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[PATCH 1/2] Kconfig: Change SYS_MALLOC_F_LEN default to 0x2000

[Tom Rini]

The most commonly used value today is 0x2000 and not 0x400.  Rework the
Kconfig logic to use this more frequently used value as the default.

Cc: Andrew F. Davis 
Cc: Alex Nemirovsky 
Cc: Alexey Brodkin 
Cc: Alison Wang 
Cc: Anastasiia Lukianenko 
Cc: Andes 
Cc: Andre Przywara 
Cc: Bharat Gooty 
Cc: David Lechner 
Cc: Dzmitry Sankouski 
Cc: Enric Balletbo i Serra 
Cc: Eugeniy Paltsev 
Cc: Fabio Estevam 
Cc: Gerald Kerma 
Cc: Gregory CLEMENT 
Cc: Holger Brunck 
Cc: Jaehoon Chung 
Cc: Jassi Brar 
Cc: Kristian Amlie 
Cc: Krzysztof Kozlowski 
Cc: Liviu Dudau 
Cc: Luka Perkov 
Cc: Lukasz Majewski 
Cc: Marek Vasut 
Cc: Masami Hiramatsu 
Cc: Matthias Brugger 
Cc: Max Filippov 
Cc: Michael Walle 
Cc: Michal Simek 
Cc: Minkyu Kang 
Cc: Nikita Kiryanov 
Cc: Nobuhiro Iwamatsu 
Cc: Oleksandr Andrushchenko 
Cc: Otavio Salvador 
Cc: Patrice Chotard 
Cc: Paul Burton 
Cc: Paul Kocialkowski 
Cc: Priyanka Jain 
Cc: Rajesh Bhagat 
Cc: Rayagonda Kokatanur 
Cc: Sergey Temerkhanov 
Cc: Simon Glass 
Cc: Stefan Bosch 
Cc: Stephan Gerhold 
Cc: Tetsuyuki Kobayashi 
Cc: Thomas Chou 
Cc: Thomas Fitzsimmons 
Cc: Thomas Weber 
Cc: Tony Dinh 
Cc: Trevor Woerner 
Cc: Vitaly Andrianov 
Cc: Vladimir Zapolskiy 
Cc: liuhao 
Cc: lixinde 
Cc: shuyiqi 
Cc: weichangzheng 
Signed-off-by: Tom Rini 
---
To make this patch more reviewable, I've omitted the defconfigs where
the in-use value is now the default value.  I've cc'd so many
maintainers however as a frequent issue when enabling more DM migrations
is SYS_MALLOC_F_LEN being too small and 0x400 not being enough and
something like 0x2000 being more reasonable, especially on platforms
that can otherwise easily handle a little more memory usage.
---
 Kconfig   | 9 +++--
 configs/10m50_defconfig   | 1 +
 configs/3c120_defconfig   | 1 +
 configs/a3y17lte_defconfig| 1 +
 configs/a5y17lte_defconfig| 1 +
 configs/a7y17lte_defconfig| 1 +
 configs/adp-ae3xx_defconfig   | 1 +
 configs/adp-ag101p_defconfig  | 1 +
 configs/am43xx_evm_qspiboot_defconfig | 1 +
 configs/armadillo-800eva_defconfig| 1 +
 configs/arndale_defconfig | 1 +
 configs/axs101_defconfig  | 1 +
 configs/axs103_defconfig  | 1 +
 configs/bcm7260_defconfig | 1 +
 configs/bcm7445_defconfig | 1 +
 configs/bcm_ns3_defconfig | 1 +
 configs/boston32r2_defconfig  | 1 +
 configs/boston32r2el_defconfig| 1 +
 configs/boston32r6_defconfig  | 1 +
 configs/boston32r6el_defconfig| 1 +
 configs/boston64r2_defconfig  | 1 +
 configs/boston64r2el_defconfig| 1 +
 configs/boston64r6_defconfig  | 1 +
 configs/boston64r6el_defconfig| 1 +
 configs/cm_t43_defconfig  | 1 +
 configs/cortina_presidio-asic-base_defconfig  | 1 +
 configs/cortina_presidio-asic-emmc_defconfig  | 1 +
 configs/cortina_presidio-asic-pnand_defconfig | 1 +
 configs/devkit3250_defconfig  | 1 +
 configs/devkit8000_defconfig  | 1 +
 configs/durian_defconfig  | 1 +
 configs/ea-lpc3250devkitv2_defconfig  | 1 +
 configs/emsdp_defconfig   | 1 +
 configs/grpeach_defconfig | 1 +
 configs/gurnard_defconfig | 1 +
 configs/highbank_defconfig| 1 +
 configs/hsdk_4xd_defconfig| 1 +
 configs/hsdk_defconfig| 1 +
 configs/igep00x0_defconfig| 1 +
 configs/iot_devkit_defconfig  | 1 +
 configs/k2e_evm_defconfig | 1 +
 configs/k2e_hs_evm_defconfig  | 1 +
 configs/k2g_evm_defconfig | 1 +
 configs/k2g_hs_evm_defconfig  | 1 +
 configs/k2hk_evm_defconfig| 1 +
 configs/k2hk_hs_evm_defconfig | 1 +
 configs/k2l_evm_defconfig | 1 +
 configs/k2l_hs_evm_defconfig  | 1 +
 configs/km_kirkwood_128m16_defconfig  | 1 +
 configs/km_kirkwood_defconfig | 1 +
 configs/km_kirkwood_pci_defconfig | 1 +
 configs/kmcoge5un_defconfig   | 1 +
 configs/kmnusa_defconfig  | 1 +
 configs/kmsuse2_defconfig | 1 +
 configs/kzm9g_defconfig   | 1 +
 configs/legoev3_defconfig | 1 +
 configs/ls2080aqds_nand_defconfig | 1 +
 configs/ls2080aqds_qspi_defconfig | 1 +
 configs/ls2080aqds_sdcard_defconfig   | 1 +
 configs/ls2080ardb_nand_defconfig | 1 +
 configs/lschlv2_defconfig | 1 +
 configs/lsxhl_defconfig   | 1 +
 

[PATCH 2/2] am33xx: Update SYS_MALLOC_F_LEN to use 0x2000 as the default

[Tom Rini]

A number of platforms here had already been increasing the size a bit,
so lets moving all of them up.

Signed-off-by: Tom Rini 
---
 Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Kconfig b/Kconfig
index 8935df616201..4f1e4d8a13d3 100644
--- a/Kconfig
+++ b/Kconfig
@@ -252,7 +252,7 @@ config SYS_MALLOC_F_LEN
default 0x600 if ARCH_ZYNQMP_R5 || ARCH_ZYNQMP
default 0x800 if ARCH_ZYNQ || ROCKCHIP_RK3128 || ROCKCHIP_RK3188 || \
 ROCKCHIP_RK322X || X86
-   default 0x1000 if AM33XX || ARCH_MESON || ARCH_BMIPS || ARCH_MTMIPS
+   default 0x1000 if ARCH_MESON || ARCH_BMIPS || ARCH_MTMIPS
default 0x1800 if ARCH_TEGRA
default 0x4000 if SANDBOX || RISCV || ARCH_APPLE || ROCKCHIP_RK3368 || \
  ROCKCHIP_RK3399
-- 
2.25.1

Re: [RFC PATCH 1/7] spl: Add generic spl_load function

[Sean Anderson]

On 4/6/22 1:30 AM, Stefan Roese wrote:
> On 4/1/22 21:03, Sean Anderson wrote:
>> Implementers of SPL_LOAD_IMAGE_METHOD have to correctly determine what
>> type of image is being loaded and then call the appropriate image load
>> function correctly. This is tricky, because some image load functions
>> expect the whole image to already be loaded (CONFIG_SPL_LOAD_FIT_FULL),
>> some will load the image automatically using spl_load_info.read()
>> (CONFIG_SPL_LOAD_FIT/CONFIG_SPL_LOAD_IMX_CONTAINER), and some just parse
>> the header and expect the caller to do the actual loading afterwards
>> (legacy/raw images). Load methods often only support a subset of the
>> above methods, meaning that not all image types can be used with all
>> load methods. Further, the code to invoke these functions is
>> duplicated between different load functions.
>>
>> To address this problem, this commit introduces a "spl_load" function.
>> It aims to handle image detection and correct invocation of each of the
>> parse/load functions. spl_simple_read is a wrapper around
>> spl_load_info.read with get_aligned_image* functions inlined for size
>> purposes. Additionally, we assume that bl_len is a power of 2 so we can
>> do bitshifts instead of divisions (which is smaller and faster).
>>
>> Signed-off-by: Sean Anderson 
>> ---
>>
>>   common/spl/spl.c | 61 
>>   include/spl.h    | 30 +++-
>>   2 files changed, 90 insertions(+), 1 deletion(-)
>>
>> diff --git a/common/spl/spl.c b/common/spl/spl.c
>> index b452d4feeb..f26df7ac3f 100644
>> --- a/common/spl/spl.c
>> +++ b/common/spl/spl.c
>> @@ -398,6 +398,67 @@ int spl_parse_image_header(struct spl_image_info 
>> *spl_image,
>>   return 0;
>>   }
>>   +static int spl_simple_read(struct spl_load_info *info, void *buf, size_t 
>> size,
>> +   size_t offset)
>> +{
>> +    int ret;
>> +    size_t bl_len = info->filename ? ARCH_DMA_MINALIGN : bl_len;
>> +    size_t bl_mask = bl_len - 1;
>> +    size_t bl_shift = ffs(bl_mask);
>> +    size_t overhead = offset & bl_mask;
>> +
> 
> Nitpicking comment:
> 
> It's preferred in general to use the reverse XMAS tree ordering of the
> declared variables. So I would expect at least to have "int ret" as
> last statement above. If you address this, then please in the complete
> series.

I thought only Linux's net subsystem had this requirement. I can reorder
things for you if you'd like. However, some of these variables have
dependencies so they cannot all be reordered :)

--Sean

> Reviewed-by: Stefan Roese 
> 
> Thanks,
> Stefan
> 
>> +    buf -= overhead;
>> +    size = (size + overhead + bl_mask) >> bl_shift;
>> +    offset = offset >> bl_shift;
>> +
>> +    ret = info->read(info, offset, size, buf);
>> +    return ret == size ? 0 : -EIO;
>> +}
>> +
>> +int spl_load(struct spl_image_info *spl_image,
>> + const struct spl_boot_device *bootdev, struct spl_load_info *info,
>> + struct image_header *header, size_t size, size_t sector)
>> +{
>> +    int ret;
>> +    size_t offset = sector * info->bl_len;
>> +
>> +    if (image_get_magic(header) == FDT_MAGIC) {
>> +    if (IS_ENABLED(CONFIG_SPL_LOAD_FIT_FULL)) {
>> +    void *buf;
>> +
>> +    /*
>> + * In order to support verifying images in the FIT, we
>> + * need to load the whole FIT into memory. Try and
>> + * guess how much we need to load by using the total
>> + * size. This will fail for FITs with external data,
>> + * but there's not much we can do about that.
>> + */
>> +    if (!size)
>> +    size = roundup(fdt_totalsize(header), 4);
>> +    buf = spl_get_load_buffer(0, size);
>> +    ret = spl_simple_read(info, buf, size, offset);
>> +    if (ret)
>> +    return ret;
>> +
>> +    return spl_parse_image_header(spl_image, bootdev, buf);
>> +    }
>> +
>> +    if (IS_ENABLED(CONFIG_SPL_LOAD_FIT))
>> +    return spl_load_simple_fit(spl_image, info, sector,
>> +   header);
>> +    }
>> +
>> +    if (IS_ENABLED(CONFIG_SPL_LOAD_IMX_CONTAINER))
>> +    return spl_load_imx_container(spl_image, info, sector);
>> +
>> +    ret = spl_parse_image_header(spl_image, bootdev, header);
>> +    if (ret)
>> +    return ret;
>> +
>> +    return spl_simple_read(info, (void *)spl_image->load_addr,
>> +   spl_image->size, offset + spl_image->offset);
>> +}
>> +
>>   __weak void __noreturn jump_to_image_no_args(struct spl_image_info 
>> *spl_image)
>>   {
>>   typedef void __noreturn (*image_entry_noargs_t)(void);
>> diff --git a/include/spl.h b/include/spl.h
>> index 8ceb3c0f09..6606f4e5f6 100644
>> --- a/include/spl.h
>> +++ b/include/spl.h
>> @@ -236,7 +236,7 @@ struct spl_image_info {
>>    *
>>    * @dev: Pointer to the device, e.g. struct mmc *
>>    * @priv: Private data for the device
>> - 

Re: [PATCH v3] imx8/ls10xx: Use a sane SYS_MALLOC_F_LEN default

[Tom Rini]

On Sat, Mar 26, 2022 at 11:47:40AM -0300, Fabio Estevam wrote:
> From: Fabio Estevam 

> 
> When adding new features to imx8m boards, such as DM clock support,
> the malloc area can be exhausted.
> 
> To avoid such issue, provide a reasonable default for the
> SYS_MALLOC_F_LEN size.
> 
> Quoting Tom Rini:
> 
> "This seems to be an area where everyone is either:
> - Kicking the value up a bit for themselves
> - Having hard to figure out problems booting the platform because it's
>   too small a value until they see someone else picked a larger value.
> 
> So lets raise these a bit and get some acks, please."
> 
> Suggested-by: Heinrich Schuchardt 
> Signed-off-by: Fabio Estevam 
> Tested-by: Adam Ford  #imx8mm-beacon, imx8mn-beacon
> Tested-by: Heiko Thiery 

Applied to u-boot/master, thanks!

-- 
Tom


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Re: [PATCH 01/18] buildman: Update default config to build for sandbox

[Tom Rini]

On Mon, Feb 28, 2022 at 12:08:18PM -0700, Simon Glass wrote:

> At present the default .buildman file written by buildman does not specify
> a default toolchain. Add an 'other' line so this works correctly and
> sandbox builds run as expected.
> 
> Signed-off-by: Simon Glass 

For the series, applied to u-boot/master, thanks!

-- 
Tom


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Re: [PATCH] misc: atsha204a: Fix big endian support

[Tom Rini]

On Thu, Apr 07, 2022 at 03:31:25PM +0200, Stefan Roese wrote:

> Added Tom to To...
> 
> On 4/7/22 10:29, Pali Rohár wrote:
> > On Monday 04 April 2022 09:43:21 Stefan Roese wrote:
> > > On 4/3/22 00:36, Pali Rohár wrote:
> > > > Callers of function atsha204a_crc16() expect to return value in host cpu
> > > > endianity. So remove cpu_to_le16() conversion.
> > > > 
> > > > Signed-off-by: Pali Rohár 
> > > 
> > > Reviewed-by: Stefan Roese 
> > 
> > Hello Stefan! Would you or somebody else take this patch?
> > 
> > Because I have some other u-boot generic patches which touches this
> > driver and I'm waiting until this simple change would be merged first.
> 
> In general I could do this. But I'm leaving for a vacation in a few days
> and I'm not sure, if I can squeeze enough "free time" to handle my
> "U-Boot work".
> 
> Tom, could you please pull this patch directly?

OK, I'll assign it to myself in patchwork.

-- 
Tom


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[PATCH] Fix BMP display when the image stretches beyond border

[Vitaly Wool]

When an image stretches beyond the display border, one still needs
to seek to the next pixel line to display the visible part of that
image correctly.

Signed-off-by: Vitaly Wool 
---
 drivers/video/video_bmp.c | 15 +++
 1 file changed, 7 insertions(+), 8 deletions(-)

diff --git a/drivers/video/video_bmp.c b/drivers/video/video_bmp.c
index 4d2d961696..d0177daf58 100644
--- a/drivers/video/video_bmp.c
+++ b/drivers/video/video_bmp.c
@@ -238,7 +238,7 @@ int video_bmp_display(struct udevice *dev, ulong bmp_image, 
int x, int y,
struct bmp_image *bmp = map_sysmem(bmp_image, 0);
uchar *bmap;
ushort padded_width;
-   unsigned long width, height, byte_width;
+   unsigned long width, vis_width, height, byte_width;
unsigned long pwidth = priv->xsize;
unsigned colours, bpix, bmp_bpix;
enum video_format eformat;
@@ -297,8 +297,7 @@ int video_bmp_display(struct udevice *dev, ulong bmp_image, 
int x, int y,
video_splash_align_axis(, priv->ysize, height);
}
 
-   if ((x + width) > pwidth)
-   width = pwidth - x;
+   vis_width = min(pwidth - x, width);
if ((y + height) > priv->ysize)
height = priv->ysize - y;
 
@@ -318,7 +317,7 @@ int video_bmp_display(struct udevice *dev, ulong bmp_image, 
int x, int y,
debug("compressed %d %d\n", compression, BMP_BI_RLE8);
if (compression == BMP_BI_RLE8) {
video_display_rle8_bitmap(dev, bmp, bpix, 
palette, fb,
- x, y, width, height);
+ x, y, vis_width, 
height);
break;
}
}
@@ -330,7 +329,7 @@ int video_bmp_display(struct udevice *dev, ulong bmp_image, 
int x, int y,
 
for (i = 0; i < height; ++i) {
WATCHDOG_RESET();
-   for (j = 0; j < width; j++) {
+   for (j = 0; j < vis_width; j++) {
write_pix8(fb, bpix, eformat, palette, bmap);
bmap++;
fb += bpix / 8;
@@ -343,7 +342,7 @@ int video_bmp_display(struct udevice *dev, ulong bmp_image, 
int x, int y,
if (IS_ENABLED(CONFIG_BMP_16BPP)) {
for (i = 0; i < height; ++i) {
WATCHDOG_RESET();
-   for (j = 0; j < width; j++) {
+   for (j = 0; j < vis_width; j++) {
*fb++ = *bmap++;
*fb++ = *bmap++;
}
@@ -355,7 +354,7 @@ int video_bmp_display(struct udevice *dev, ulong bmp_image, 
int x, int y,
case 24:
if (IS_ENABLED(CONFIG_BMP_24BPP)) {
for (i = 0; i < height; ++i) {
-   for (j = 0; j < width; j++) {
+   for (j = 0; j < vis_width; j++) {
if (bpix == 16) {
/* 16bit 565RGB format */
*(u16 *)fb = ((bmap[2] >> 3)
@@ -389,7 +388,7 @@ int video_bmp_display(struct udevice *dev, ulong bmp_image, 
int x, int y,
case 32:
if (IS_ENABLED(CONFIG_BMP_32BPP)) {
for (i = 0; i < height; ++i) {
-   for (j = 0; j < width; j++) {
+   for (j = 0; j < vis_width; j++) {
if (eformat == VIDEO_X2R10G10B10) {
u32 pix;
 
-- 
2.30.2

Re: [PATCH] misc: atsha204a: Fix big endian support

[Stefan Roese]

Added Tom to To...

On 4/7/22 10:29, Pali Rohár wrote:

On Monday 04 April 2022 09:43:21 Stefan Roese wrote:

On 4/3/22 00:36, Pali Rohár wrote:

Callers of function atsha204a_crc16() expect to return value in host cpu
endianity. So remove cpu_to_le16() conversion.

Signed-off-by: Pali Rohár 


Reviewed-by: Stefan Roese 


Hello Stefan! Would you or somebody else take this patch?

Because I have some other u-boot generic patches which touches this
driver and I'm waiting until this simple change would be merged first.


In general I could do this. But I'm leaving for a vacation in a few days
and I'm not sure, if I can squeeze enough "free time" to handle my
"U-Boot work".

Tom, could you please pull this patch directly?

Thanks,
Stefan




Thanks,
Stefan


---
   drivers/misc/atsha204a-i2c.c | 2 +-
   1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/misc/atsha204a-i2c.c b/drivers/misc/atsha204a-i2c.c
index b89463babb56..63fe541dade3 100644
--- a/drivers/misc/atsha204a-i2c.c
+++ b/drivers/misc/atsha204a-i2c.c
@@ -146,7 +146,7 @@ static u16 atsha204a_crc16(const u8 *buffer, size_t len)
while (len--)
crc = crc16_byte(crc, *buffer++);
-   return cpu_to_le16(crc);
+   return crc;
   }
   static int atsha204a_send(struct udevice *dev, const u8 *buf, u8 len)


Viele Grüße,
Stefan Roese

--
DENX Software Engineering GmbH,  Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: s...@denx.de


Viele Grüße,
Stefan Roese

--
DENX Software Engineering GmbH,  Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: s...@denx.de

Re: [PATCH 0/6] introduce Arm FF-A support

[Tom Rini]

On Thu, Apr 07, 2022 at 01:54:24PM +0100, Abdellatif El Khlifi wrote:
> On Wed, Apr 06, 2022 at 03:47:11PM -0400, Tom Rini wrote:
> > On Tue, Mar 29, 2022 at 04:16:53PM +0100, abdellatif.elkhl...@arm.com wrote:
> > > From: Abdellatif El Khlifi 
> > > 
> > > This patchset adds support for Arm FF-A (Arm Firmware Framework for 
> > > Armv8-A v1.0).
> > > 
> > > FF-A support is generic by design and can be used by any Arm platform.
> > > 
> > > The features added are as follows:
> > > 
> > > 1/ FF-A device driver
> > > 2/ armffa command
> > > 3/ FF-A Sandbox driver
> > > 4/ FF-A Sandbox test cases
> > > 5/ FF-A MM communication
> > > 
> > > 
> > > The suggested design sees FF-A as a data bus allowing data exchange with 
> > > the firmware
> > > running under TrustZone HW (such as Optee). The same approach was 
> > > followed in the
> > > FF-A driver in Linux kernel 
> > > (https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/firmware/arm_ffa/bus.c?h=v5.15#n211))
> > > 
> > > u-boot boards using FF-A can provide a device tree node in a 
> > > -u-boot.dtsi file.
> > > Since the node can not be hosted in Linux device tree, we suggest using 
> > > u-boot device tree.
> > 
> > Why can't the node be in the upstream tree?  It should be, so that it
> > can be shared between all users.  Especially since there's in-Linux
> > users?
> > 
> > -- 
> > Tom
> 
> Linux already has an FF-A bus driver and doesn't use a device tree node for 
> FF-A.
> 
> The Linux driver registers FF-A as a bus:
> 
> int arm_ffa_bus_init(void)
> {
>   return bus_register(_bus_type);
> }
> 
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/firmware/arm_ffa/bus.c?h=v5.15#n211
> 
> So, there is no user for the node in Linux. That's why we suggest hosting the 
> node in the u-boot device tree (a u-boot.dtsi file)

OK, but you can still push it upstream as it's not required to have an
in tree user.

-- 
Tom


signature.asc
Description: PGP signature

Re: [PATCH 0/6] introduce Arm FF-A support

[Abdellatif El Khlifi]

On Wed, Apr 06, 2022 at 03:47:11PM -0400, Tom Rini wrote:
> On Tue, Mar 29, 2022 at 04:16:53PM +0100, abdellatif.elkhl...@arm.com wrote:
> > From: Abdellatif El Khlifi 
> > 
> > This patchset adds support for Arm FF-A (Arm Firmware Framework for Armv8-A 
> > v1.0).
> > 
> > FF-A support is generic by design and can be used by any Arm platform.
> > 
> > The features added are as follows:
> > 
> > 1/ FF-A device driver
> > 2/ armffa command
> > 3/ FF-A Sandbox driver
> > 4/ FF-A Sandbox test cases
> > 5/ FF-A MM communication
> > 
> > 
> > The suggested design sees FF-A as a data bus allowing data exchange with 
> > the firmware
> > running under TrustZone HW (such as Optee). The same approach was followed 
> > in the
> > FF-A driver in Linux kernel 
> > (https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/firmware/arm_ffa/bus.c?h=v5.15#n211))
> > 
> > u-boot boards using FF-A can provide a device tree node in a 
> > -u-boot.dtsi file.
> > Since the node can not be hosted in Linux device tree, we suggest using 
> > u-boot device tree.
> 
> Why can't the node be in the upstream tree?  It should be, so that it
> can be shared between all users.  Especially since there's in-Linux
> users?
> 
> -- 
> Tom

Linux already has an FF-A bus driver and doesn't use a device tree node for 
FF-A.

The Linux driver registers FF-A as a bus:

int arm_ffa_bus_init(void)
{
return bus_register(_bus_type);
}

https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/firmware/arm_ffa/bus.c?h=v5.15#n211

So, there is no user for the node in Linux. That's why we suggest hosting the 
node in the u-boot device tree (a u-boot.dtsi file)

[PATCH] Make ci_udc available in SPL

[Manuel Traut]

This is needed for SDP downloads of eg. fitimages
in SPL stage.

Signed-off-by: Manuel Traut 
---
 common/spl/Kconfig  |  10 +++
 common/usb_hub.c|   4 +
 drivers/usb/gadget/Makefile |  18 ++--
 drivers/usb/gadget/ci_udc.c | 159 +---
 drivers/usb/gadget/ci_udc.h |   2 +-
 drivers/usb/host/Makefile   |   2 +-
 6 files changed, 98 insertions(+), 97 deletions(-)

diff --git a/common/spl/Kconfig b/common/spl/Kconfig
index dc319adeac..f5545d2cb2 100644
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@@ -1181,6 +1181,16 @@ config SPL_USB_GADGET

 if SPL_USB_GADGET

+config SPL_CI_UDC
+   bool "Support USB CI UDC controller in SPL"
+   help
+ Enables CI UDC driver to be available in SPL
+
+config SPL_USB_EHCI_HCD
+   bool "Support USB EHCI Host in SPL"
+   help
+ Enables EHCI host driver in SPL.
+
 config SPL_USB_ETHER
bool "Support USB Ethernet drivers"
depends on SPL_NET
diff --git a/common/usb_hub.c b/common/usb_hub.c
index ba11a188ca..d572d7dd17 100644
--- a/common/usb_hub.c
+++ b/common/usb_hub.c
@@ -166,7 +166,9 @@ static void usb_hub_power_on(struct usb_hub_device 
*hub)

int i;
struct usb_device *dev;
unsigned pgood_delay = hub->desc.bPwrOn2PwrGood * 2;
+#ifndef CONFIG_SPL_BUILD
const char *env;
+#endif

dev = hub->pusb_dev;

@@ -185,6 +187,7 @@ static void usb_hub_power_on(struct usb_hub_device 
*hub)

return;
 #endif

+#ifndef CONFIG_SPL_BUILD
/*
 * Wait for power to become stable,
 * plus spec-defined max time for device to connect
@@ -196,6 +199,7 @@ static void usb_hub_power_on(struct usb_hub_device 
*hub)

pgood_delay = max(pgood_delay,
  (unsigned)simple_strtol(env, NULL, 0));
debug("pgood_delay=%dms\n", pgood_delay);
+#endif

/*
 * Do a minimum delay of the larger value of 100ms or pgood_delay
diff --git a/drivers/usb/gadget/Makefile b/drivers/usb/gadget/Makefile
index d5d891b205..df88ae2f30 100644
--- a/drivers/usb/gadget/Makefile
+++ b/drivers/usb/gadget/Makefile
@@ -21,16 +21,16 @@ obj-$(CONFIG_USB_GADGET_DWC2_OTG) += dwc2_udc_otg.o
 obj-$(CONFIG_USB_GADGET_DWC2_OTG_PHY) += dwc2_udc_otg_phy.o
 obj-$(CONFIG_USB_GADGET_FOTG210) += fotg210.o
 obj-$(CONFIG_USB_GADGET_MAX3420) += max3420_udc.o
-obj-$(CONFIG_CI_UDC)   += ci_udc.o
+obj-$(CONFIG_$(SPL_)CI_UDC)+= ci_udc.o
 ifndef CONFIG_SPL_BUILD
-obj-$(CONFIG_USB_GADGET_DOWNLOAD) += g_dnl.o
-obj-$(CONFIG_USB_FUNCTION_THOR) += f_thor.o
-obj-$(CONFIG_DFU_OVER_USB) += f_dfu.o
-obj-$(CONFIG_USB_FUNCTION_MASS_STORAGE) += f_mass_storage.o
-obj-$(CONFIG_USB_FUNCTION_FASTBOOT) += f_fastboot.o
-obj-$(CONFIG_USB_FUNCTION_SDP) += f_sdp.o
-obj-$(CONFIG_USB_FUNCTION_ROCKUSB) += f_rockusb.o
-obj-$(CONFIG_USB_FUNCTION_ACM) += f_acm.o
+obj-$(CONFIG_$(SPL_)USB_GADGET_DOWNLOAD) += g_dnl.o
+obj-$(CONFIG_$(SPL_)USB_FUNCTION_THOR) += f_thor.o
+obj-$(CONFIG_$(SPL_)DFU_OVER_USB) += f_dfu.o
+obj-$(CONFIG_$(SPL_)USB_FUNCTION_MASS_STORAGE) += f_mass_storage.o
+obj-$(CONFIG_$(SPL_)USB_FUNCTION_FASTBOOT) += f_fastboot.o
+obj-$(CONFIG_$(SPL_)USB_FUNCTION_SDP) += f_sdp.o
+obj-$(CONFIG_$(SPL_)USB_FUNCTION_ROCKUSB) += f_rockusb.o
+obj-$(CONFIG_$(SPL_)USB_FUNCTION_ACM)  += f_acm.o
 endif
 endif
 ifdef CONFIG_USB_ETHER
diff --git a/drivers/usb/gadget/ci_udc.c b/drivers/usb/gadget/ci_udc.c
index 542684c1c3..2e274331fe 100644
--- a/drivers/usb/gadget/ci_udc.c
+++ b/drivers/usb/gadget/ci_udc.c
@@ -25,6 +25,7 @@
 #include 
 #include "../host/ehci.h"
 #include "ci_udc.h"
+#include 

 /*
  * Check if the system has too long cachelines. If the cachelines are
@@ -94,10 +95,42 @@ static struct usb_request *
 ci_ep_alloc_request(struct usb_ep *ep, unsigned int gfp_flags);
 static void ci_ep_free_request(struct usb_ep *ep, struct usb_request 
*_req);


+static int ci_gadget_start(struct usb_gadget *g, struct 
usb_gadget_driver *d);

+static int ci_gadget_stop(struct usb_gadget *g);
+
 static struct usb_gadget_ops ci_udc_ops = {
-   .pullup = ci_pullup,
+   .pullup= ci_pullup,
+   .udc_start = ci_gadget_start,
+   .udc_stop  = ci_gadget_stop,
+};
+
+static struct ci_drv controller = {
+   .gadget = {
+   .name   = "ci_udc",
+   .ops= _udc_ops,
+   .is_dualspeed = 1,
+   .is_otg = 0,
+   .is_a_peripheral = 0,
+   .b_hnp_enable = 0,
+   .a_hnp_support = 0,
+   .a_alt_hnp_support = 0,
+   },
 };

+static int ci_gadget_start(struct usb_gadget *g, struct 
usb_gadget_driver *d)

+{
+   controller.driver = d;
+   printf("Registered gadget driver %s\n", controller.gadget.name);
+   return 0;
+}
+
+static int ci_gadget_stop(struct usb_gadget *g)
+{
+   printf("Unregistered gadget driver %s\n", controller.gadget.name);
+   controller.driver = 0;
+   return 0;
+}
+
 static struct usb_ep_ops ci_ep_ops = {

Re: [PATCH] btrfs: Fix compilation on big endian systems

[Marek Behún]

On Thu,  7 Apr 2022 14:51:03 +0200
Pali Rohár  wrote:

> Fix following two compile errors on big endian systems:
> 
>   CC  fs/btrfs/btrfs.o
> In file included from include/linux/byteorder/big_endian.h:107,
>  from ./arch/powerpc/include/asm/byteorder.h:82,
>  from ./arch/powerpc/include/asm/bitops.h:8,
>  from include/linux/bitops.h:152,
>  from include/uuid.h:9,
>  from fs/btrfs/btrfs.c:10:
> fs/btrfs/conv-funcs.h: In function ‘btrfs_key_to_disk’:
> include/linux/byteorder/generic.h:90:21: error: ‘__cpu_to_le16’ undeclared 
> (first use in this function); did you mean ‘__cpu_to_le16p’?
>  #define cpu_to_le16 __cpu_to_le16
>  ^
> fs/btrfs/conv-funcs.h:79:10: note: in expansion of macro ‘cpu_to_le16’
>__u16: cpu_to_le16, \
>   ^~~
> 
>   CC  fs/btrfs/compression.o
> In file included from ./arch/powerpc/include/asm/unaligned.h:9,
>  from fs/btrfs/compression.c:16:
> include/linux/unaligned/access_ok.h:6:19: error: redefinition of 
> ‘get_unaligned_le16’
>  static inline u16 get_unaligned_le16(const void *p)
>^~
> In file included from fs/btrfs/ctree.h:16,
>  from fs/btrfs/btrfs.h:12,
>  from fs/btrfs/compression.c:8:
> include/linux/unaligned/le_byteshift.h:40:19: note: previous definition of 
> ‘get_unaligned_le16’ was here
>  static inline u16 get_unaligned_le16(const void *p)
>^~
> 
> Include file asm/unaligned.h contains arch specific macros and functions
> for unaligned access as opposite to linux/unaligned le_byteshift.h which
> contains macros and functions specific to little endian systems only.
> 
> Signed-off-by: Pali Rohár 

Reviewed-by: Marek Behún 

[PATCH] fs: Allow to compile FS_BTRFS when SPL is enabled

[Pali Rohár]

Currently there is no btrfs support in SPL. But macro CONFIG_FS_BTRFS is
defined also when building SPL. When both FS_BTRFS and SPL are enabled
then build process throw compile error.

Fix check for btrfs code in fstypes[] to allow compiling FS_BTRFS only in
proper U-Boot.

Signed-off-by: Pali Rohár 
---
 fs/fs.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/fs/fs.c b/fs/fs.c
index b4306cf8499e..100a2a63810a 100644
--- a/fs/fs.c
+++ b/fs/fs.c
@@ -267,6 +267,7 @@ static struct fstype_info fstypes[] = {
},
 #endif
 #endif
+#ifndef CONFIG_SPL_BUILD
 #ifdef CONFIG_FS_BTRFS
{
.fstype = FS_TYPE_BTRFS,
@@ -286,6 +287,7 @@ static struct fstype_info fstypes[] = {
.ln = fs_ln_unsupported,
},
 #endif
+#endif
 #if CONFIG_IS_ENABLED(FS_SQUASHFS)
{
.fstype = FS_TYPE_SQUASHFS,
-- 
2.20.1

[PATCH] btrfs: Fix compilation on big endian systems

[Pali Rohár]

Fix following two compile errors on big endian systems:

  CC  fs/btrfs/btrfs.o
In file included from include/linux/byteorder/big_endian.h:107,
 from ./arch/powerpc/include/asm/byteorder.h:82,
 from ./arch/powerpc/include/asm/bitops.h:8,
 from include/linux/bitops.h:152,
 from include/uuid.h:9,
 from fs/btrfs/btrfs.c:10:
fs/btrfs/conv-funcs.h: In function ‘btrfs_key_to_disk’:
include/linux/byteorder/generic.h:90:21: error: ‘__cpu_to_le16’ undeclared 
(first use in this function); did you mean ‘__cpu_to_le16p’?
 #define cpu_to_le16 __cpu_to_le16
 ^
fs/btrfs/conv-funcs.h:79:10: note: in expansion of macro ‘cpu_to_le16’
   __u16: cpu_to_le16, \
  ^~~

  CC  fs/btrfs/compression.o
In file included from ./arch/powerpc/include/asm/unaligned.h:9,
 from fs/btrfs/compression.c:16:
include/linux/unaligned/access_ok.h:6:19: error: redefinition of 
‘get_unaligned_le16’
 static inline u16 get_unaligned_le16(const void *p)
   ^~
In file included from fs/btrfs/ctree.h:16,
 from fs/btrfs/btrfs.h:12,
 from fs/btrfs/compression.c:8:
include/linux/unaligned/le_byteshift.h:40:19: note: previous definition of 
‘get_unaligned_le16’ was here
 static inline u16 get_unaligned_le16(const void *p)
   ^~

Include file asm/unaligned.h contains arch specific macros and functions
for unaligned access as opposite to linux/unaligned le_byteshift.h which
contains macros and functions specific to little endian systems only.

Signed-off-by: Pali Rohár 
---
 fs/btrfs/btrfs.h | 2 +-
 fs/btrfs/ctree.h | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/fs/btrfs/btrfs.h b/fs/btrfs/btrfs.h
index 7d8b395b2646..a52587e0637a 100644
--- a/fs/btrfs/btrfs.h
+++ b/fs/btrfs/btrfs.h
@@ -9,7 +9,7 @@
 #define __BTRFS_BTRFS_H__
 
 #include 
-#include "conv-funcs.h"
+#include "ctree.h"
 
 extern struct btrfs_info btrfs_info;
 extern struct btrfs_fs_info *current_fs_info;
diff --git a/fs/btrfs/ctree.h b/fs/btrfs/ctree.h
index 219c410b189f..55112318a330 100644
--- a/fs/btrfs/ctree.h
+++ b/fs/btrfs/ctree.h
@@ -13,7 +13,7 @@
 #include 
 #include 
 #include 
-#include 
+#include 
 #include 
 #include "kernel-shared/btrfs_tree.h"
 #include "crypto/hash.h"
-- 
2.20.1

Re: [PATCH 1/9] net: gmac_rockchip: Fix misuse of GENMASK macro

[David Wu]

Hi Pierre-Clément,

Thanks for your correction, there was wrong mask here.
Reviewed-by: David Wu 

在 2022/4/6 23:08, Kever Yang 写道:

Add David,

Hi David,

     Could you help to check this patch?


Thanks,
- Kever
On 2022/3/16 23:39, Pierre-Clément Tosi wrote:

Swap the arguments as that seems to have been the author's intention.

Note: This fix wasn't tested on hardware and will result in more bits
   being set by the underlying writel() in rk_clrsetreg(), which
   might bring unexpected behavioural changes.

Fixes: b07911840025 ("net: gmac_rockchip: add support for px30")
Signed-off-by: Pierre-Clément Tosi 
Cc: Joe Hershberger 
Cc: Heiko Stuebner 
Cc: Kever Yang 
Cc: Tom Rini 
---
  drivers/net/gmac_rockchip.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/gmac_rockchip.c b/drivers/net/gmac_rockchip.c
index 04008d2b19..0ecbcdf641 100644
--- a/drivers/net/gmac_rockchip.c
+++ b/drivers/net/gmac_rockchip.c
@@ -350,7 +350,7 @@ static void px30_gmac_set_to_rmii(struct 
gmac_rockchip_plat *pdata)

  struct px30_grf *grf;
  enum {
  PX30_GMAC_PHY_INTF_SEL_SHIFT = 4,
-    PX30_GMAC_PHY_INTF_SEL_MASK  = GENMASK(4, 6),
+    PX30_GMAC_PHY_INTF_SEL_MASK  = GENMASK(6, 4),
  PX30_GMAC_PHY_INTF_SEL_RMII  = BIT(6),
  };

[PATCH] LS1043ARDB, LS1046ARDB, LS1088ARDB: Enable SPL_OF_CONTROL in SECURE Boot defconfig

[Kshitiz Varshney]

If enable SPL_DM without SPL_OF_CONTROL,
build errors "undefined reference to fdt_get_resource",
is coming in function `caam_jr_probe'.
Added SPL_OF_CONTROL to remove the error.

Signed-off-by: Kshitiz Varshney 
---
 configs/ls1043ardb_nand_SECURE_BOOT_defconfig| 1 +
 configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig  | 1 +
 configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig  | 1 +
 configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig | 1 +
 4 files changed, 4 insertions(+)

diff --git a/configs/ls1043ardb_nand_SECURE_BOOT_defconfig 
b/configs/ls1043ardb_nand_SECURE_BOOT_defconfig
index 3ca7dac9e8..e7d7a43351 100644
--- a/configs/ls1043ardb_nand_SECURE_BOOT_defconfig
+++ b/configs/ls1043ardb_nand_SECURE_BOOT_defconfig
@@ -45,6 +45,7 @@ CONFIG_MP=y
 
CONFIG_MTDPARTS_DEFAULT="mtdparts=6000.nor:2m@0x10(nor_bank0_uboot),40m@0x110(nor_bank0_fit),7m(nor_bank0_user),2m@0x410(nor_bank4_uboot),40m@0x510(nor_bank4_fit),-(nor_bank4_user);7e80.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_DM=y
diff --git a/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig 
b/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig
index 06c1ce5053..c83492c814 100644
--- a/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig
+++ b/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig
@@ -45,6 +45,7 @@ CONFIG_MP=y
 
CONFIG_MTDPARTS_DEFAULT="mtdparts=6000.nor:2m@0x10(nor_bank0_uboot),40m@0x110(nor_bank0_fit),7m(nor_bank0_user),2m@0x410(nor_bank4_uboot),40m@0x510(nor_bank4_fit),-(nor_bank4_user);7e80.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_DM=y
diff --git a/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig 
b/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig
index 5caf24f800..7f2285424a 100644
--- a/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig
+++ b/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig
@@ -45,6 +45,7 @@ CONFIG_MP=y
 
CONFIG_MTDPARTS_DEFAULT="mtdparts=155.spi-0:1m(rcw),15m(u-boot),48m(kernel.itb);7e80.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_DM=y
diff --git a/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig 
b/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig
index 24e4ba7229..0598160fcb 100644
--- a/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig
+++ b/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig
@@ -50,6 +50,7 @@ CONFIG_CMD_USB=y
 CONFIG_CMD_CACHE=y
 CONFIG_MP=y
 CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_NET_RANDOM_ETHADDR=y
-- 
2.25.1

[PATCH v2 01/52] mips: octeon: Add misc cvmx-* header files

[Stefan Roese]

From: Aaron Williams 

Import misc cvmx-helper header files from 2013 U-Boot. They will be used
by the later added drivers to support networking on the MIPS Octeon II /
III platforms.

Signed-off-by: Aaron Williams 
Signed-off-by: Stefan Roese 
---
 arch/mips/mach-octeon/include/mach/cvmx-agl.h |   45 +
 .../mach-octeon/include/mach/cvmx-config.h|  128 ++
 arch/mips/mach-octeon/include/mach/cvmx-fau.h |  581 +
 .../mips/mach-octeon/include/mach/cvmx-mdio.h |  516 
 .../include/mach/cvmx-pki-cluster.h   |  343 ++
 arch/mips/mach-octeon/include/mach/cvmx-pko.h |  213 
 .../include/mach/cvmx-pko3-resources.h|   36 +
 .../mips/mach-octeon/include/mach/cvmx-pko3.h | 1052 +
 .../mach-octeon/include/mach/cvmx-range.h |   23 +
 9 files changed, 2937 insertions(+)
 create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-agl.h
 create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-config.h
 create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-fau.h
 create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-mdio.h
 create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-pki-cluster.h
 create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-pko.h
 create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-pko3-resources.h
 create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-pko3.h
 create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-range.h

diff --git a/arch/mips/mach-octeon/include/mach/cvmx-agl.h 
b/arch/mips/mach-octeon/include/mach/cvmx-agl.h
new file mode 100644
index ..4afb3a48bfdc
--- /dev/null
+++ b/arch/mips/mach-octeon/include/mach/cvmx-agl.h
@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2018-2022 Marvell International Ltd.
+ *
+ * Functions for AGL (RGMII) commong initialization, configuration.
+ */
+
+#ifndef __CVMX_AGL_H__
+#define __CVMX_AGL_H__
+
+/*
+ * @param port to enable
+ *
+ * @return Zero on success, negative on failure
+ */
+int cvmx_agl_enable(int port);
+
+cvmx_helper_link_info_t cvmx_agl_link_get(int port);
+
+/*
+ * Set MII/RGMII link based on mode.
+ *
+ * @param port   interface port to set the link.
+ * @param link_info  Link status
+ *
+ * @return   0 on success and 1 on failure
+ */
+int cvmx_agl_link_set(int port, cvmx_helper_link_info_t link_info);
+
+/**
+ * Disables the sending of flow control (pause) frames on the specified
+ * AGL (RGMII) port(s).
+ *
+ * @param interface Which interface (0 or 1)
+ * @param port_mask Mask (4bits) of which ports on the interface to disable
+ *  backpressure on.
+ *  1 => disable backpressure
+ *  0 => enable backpressure
+ *
+ * @return 0 on success
+ * -1 on error
+ */
+int cvmx_agl_set_backpressure_override(u32 interface, uint32_t port_mask);
+
+#endif /* __CVMX_AGL_H__ */
diff --git a/arch/mips/mach-octeon/include/mach/cvmx-config.h 
b/arch/mips/mach-octeon/include/mach/cvmx-config.h
new file mode 100644
index ..4f66a3cce524
--- /dev/null
+++ b/arch/mips/mach-octeon/include/mach/cvmx-config.h
@@ -0,0 +1,128 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2018-2022 Marvell International Ltd.
+ */
+
+#ifndef __CVMX_CONFIG_H__
+#define __CVMX_CONFIG_H__
+
+/* Config Specific Defines /
+#define CVMX_LLM_NUM_PORTS 1
+
+/**< PKO queues per port for interface 0 (ports 0-15) */
+#define CVMX_PKO_QUEUES_PER_PORT_INTERFACE0 1
+
+/**< PKO queues per port for interface 1 (ports 16-31) */
+#define CVMX_PKO_QUEUES_PER_PORT_INTERFACE1 1
+
+/**< PKO queues per port for interface 4 (AGL) */
+#define CVMX_PKO_QUEUES_PER_PORT_INTERFACE4 1
+
+/**< Limit on the number of PKO ports enabled for interface 0 */
+#define CVMX_PKO_MAX_PORTS_INTERFACE0 CVMX_HELPER_PKO_MAX_PORTS_INTERFACE0
+
+/**< Limit on the number of PKO ports enabled for interface 1 */
+#define CVMX_PKO_MAX_PORTS_INTERFACE1 CVMX_HELPER_PKO_MAX_PORTS_INTERFACE1
+
+/**< PKO queues per port for PCI (ports 32-35) */
+#define CVMX_PKO_QUEUES_PER_PORT_PCI 1
+
+/**< PKO queues per port for Loop devices (ports 36-39) */
+#define CVMX_PKO_QUEUES_PER_PORT_LOOP 1
+
+/**< PKO queues per port for SRIO0 devices (ports 40-41) */
+#define CVMX_PKO_QUEUES_PER_PORT_SRIO0 1
+
+/**< PKO queues per port for SRIO1 devices (ports 42-43) */
+#define CVMX_PKO_QUEUES_PER_PORT_SRIO1 1
+
+/* FPA allocation */
+/* Pool sizes in bytes, must be multiple of a cache line */
+#define CVMX_FPA_POOL_0_SIZE (16 * CVMX_CACHE_LINE_SIZE)
+#define CVMX_FPA_POOL_1_SIZE (1 * CVMX_CACHE_LINE_SIZE)
+#define CVMX_FPA_POOL_2_SIZE (8 * CVMX_CACHE_LINE_SIZE)
+#define CVMX_FPA_POOL_3_SIZE (2 * CVMX_CACHE_LINE_SIZE)
+#define CVMX_FPA_POOL_4_SIZE (0 * CVMX_CACHE_LINE_SIZE)
+#define CVMX_FPA_POOL_5_SIZE (0 * CVMX_CACHE_LINE_SIZE)
+#define CVMX_FPA_POOL_6_SIZE (8 * CVMX_CACHE_LINE_SIZE)
+#define CVMX_FPA_POOL_7_SIZE (0 * 

[PATCH v2 42/52] mips: octeon: Misc changes to existing C files for upcoming eth support

[Stefan Roese]

This patch includes misc changes to already present Octeon MIPS C files
files, which are necessary for the upcoming ethernet support.

The changes are mostly:
- DM GPIO & I2C infrastructure
- Coding style cleanup while reworking of the code

Signed-off-by: Stefan Roese 
---
 arch/mips/mach-octeon/cvmx-bootmem.c |   3 +-
 arch/mips/mach-octeon/cvmx-helper-cfg.c  | 655 +
 arch/mips/mach-octeon/cvmx-helper-fdt.c  | 898 ++-
 arch/mips/mach-octeon/cvmx-helper-util.c | 248 ---
 arch/mips/mach-octeon/cvmx-helper.c  | 845 +
 5 files changed, 230 insertions(+), 2419 deletions(-)

diff --git a/arch/mips/mach-octeon/cvmx-bootmem.c 
b/arch/mips/mach-octeon/cvmx-bootmem.c
index 9bd644d68bd8..52e58b4c1761 100644
--- a/arch/mips/mach-octeon/cvmx-bootmem.c
+++ b/arch/mips/mach-octeon/cvmx-bootmem.c
@@ -1189,7 +1189,7 @@ s64 cvmx_bootmem_phy_mem_list_init(u64 mem_size,
if (mem_size > OCTEON_DDR1_SIZE) {
__cvmx_bootmem_phy_free(OCTEON_DDR1_BASE, OCTEON_DDR1_SIZE, 0);
__cvmx_bootmem_phy_free(OCTEON_DDR2_BASE,
-   mem_size - OCTEON_DDR1_SIZE, 0);
+   mem_size - OCTEON_DDR2_BASE, 0);
} else {
__cvmx_bootmem_phy_free(OCTEON_DDR1_BASE, mem_size, 0);
}
@@ -1349,7 +1349,6 @@ s64 cvmx_bootmem_phy_mem_list_init_multi(u8 node_mask,
addr += sizeof(struct cvmx_bootmem_named_block_desc);
}
 
-   // test-only: DEBUG ifdef???
cvmx_bootmem_phy_list_print();
 
return 1;
diff --git a/arch/mips/mach-octeon/cvmx-helper-cfg.c 
b/arch/mips/mach-octeon/cvmx-helper-cfg.c
index 494108f0cdb7..a3f4ff0eeb5f 100644
--- a/arch/mips/mach-octeon/cvmx-helper-cfg.c
+++ b/arch/mips/mach-octeon/cvmx-helper-cfg.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * Copyright (C) 2020 Marvell International Ltd.
+ * Copyright (C) 2020-2022 Marvell International Ltd.
  *
  * Helper Functions for the Configuration Framework
  */
@@ -100,7 +100,6 @@ static u64 cvmx_cfg_opts[CVMX_HELPER_CFG_OPT_MAX] = {
 static int cvmx_cfg_max_pko_engines; /* # of PKO DMA engines allocated */
 static int cvmx_pko_queue_alloc(u64 port, int count);
 static void cvmx_init_port_cfg(void);
-static const int dbg;
 
 int __cvmx_helper_cfg_pknd(int xiface, int index)
 {
@@ -184,16 +183,6 @@ int __cvmx_helper_cfg_pko_max_engine(void)
return cvmx_cfg_max_pko_engines;
 }
 
-int cvmx_helper_cfg_opt_set(cvmx_helper_cfg_option_t opt, uint64_t val)
-{
-   if (opt >= CVMX_HELPER_CFG_OPT_MAX)
-   return -1;
-
-   cvmx_cfg_opts[opt] = val;
-
-   return 0;
-}
-
 uint64_t cvmx_helper_cfg_opt_get(cvmx_helper_cfg_option_t opt)
 {
if (opt >= CVMX_HELPER_CFG_OPT_MAX)
@@ -298,18 +287,6 @@ int cvmx_pko_queue_init_from_cvmx_config_non_pknd(void)
return 0;
 }
 
-int cvmx_helper_pko_queue_config_get(int node, 
cvmx_user_static_pko_queue_config_t *cfg)
-{
-   *cfg = __cvmx_pko_queue_static_config[node];
-   return 0;
-}
-
-int cvmx_helper_pko_queue_config_set(int node, 
cvmx_user_static_pko_queue_config_t *cfg)
-{
-   __cvmx_pko_queue_static_config[node] = *cfg;
-   return 0;
-}
-
 static int queue_range_init;
 
 int init_cvmx_pko_que_range(void)
@@ -376,91 +353,6 @@ static int cvmx_pko_queue_alloc(u64 port, int count)
return 0;
 }
 
-/*
- * return the queues for "port"
- *
- * @param  port   the port for which the queues are returned
- *
- * Return:  0 on success
- * -1 on failure
- */
-int cvmx_pko_queue_free(uint64_t port)
-{
-   int ret_val = -1;
-
-   init_cvmx_pko_que_range();
-   if (port >= CVMX_HELPER_CFG_MAX_PKO_QUEUES) {
-   debug("ERROR: %s port=%d > %d", __func__, (int)port,
- CVMX_HELPER_CFG_MAX_PKO_QUEUES);
-   return -1;
-   }
-
-   ret_val = cvmx_free_global_resource_range_with_base(
-   CVMX_GR_TAG_PKO_QUEUES, 
cvmx_pko_queue_table[port].ccppp_queue_base,
-   cvmx_pko_queue_table[port].ccppp_num_queues);
-   if (ret_val != 0)
-   return ret_val;
-
-   cvmx_pko_queue_table[port].ccppp_num_queues = 0;
-   cvmx_pko_queue_table[port].ccppp_queue_base = 
CVMX_HELPER_CFG_INVALID_VALUE;
-   ret_val = 0;
-   return ret_val;
-}
-
-void cvmx_pko_queue_free_all(void)
-{
-   int i;
-
-   for (i = 0; i < CVMX_HELPER_CFG_MAX_PKO_PORT; i++)
-   if (cvmx_pko_queue_table[i].ccppp_queue_base !=
-   CVMX_HELPER_CFG_INVALID_VALUE)
-   cvmx_pko_queue_free(i);
-}
-
-void cvmx_pko_queue_show(void)
-{
-   int i;
-
-   cvmx_show_global_resource_range(CVMX_GR_TAG_PKO_QUEUES);
-   for (i = 0; i < CVMX_HELPER_CFG_MAX_PKO_PORT; i++)
-   if (cvmx_pko_queue_table[i].ccppp_queue_base !=
-   CVMX_HELPER_CFG_INVALID_VALUE)
-   debug("port=%d que_base=%d 

Re: [PATCH] arm: mvebu: a37xx: Add support for writing Security OTP values

[Marek Behún]

On Thu,  7 Apr 2022 11:32:10 +0200
Pali Rohár  wrote:

> Implement write support for Security OTP values via mailbox API commands
> MBOX_CMD_OTP_WRITE_32B and MBOX_CMD_OTP_WRITE.
> 
> Write support for North and South Bridge OTPs are not implemented as these
> OTPs are already burned in factory with some data.
> 
> Signed-off-by: Pali Rohár 
> ---
> This patch depends on series which implements read support for A3720 OTP:
> https://patchwork.ozlabs.org/project/uboot/list/?series=287578=*
> 
> Stefan, what do you think, should be enable write support by default. Or
> should it be hidden under some other CONFIG option? Becaue currently
> CONFIG_CMD_FUSE enable both read and write support (or what driver
> implements).
> ---
>  arch/arm/mach-mvebu/armada3700/efuse.c | 50 --
>  1 file changed, 48 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm/mach-mvebu/armada3700/efuse.c 
> b/arch/arm/mach-mvebu/armada3700/efuse.c
> index 50c73f36c565..07d5f394354c 100644
> --- a/arch/arm/mach-mvebu/armada3700/efuse.c
> +++ b/arch/arm/mach-mvebu/armada3700/efuse.c
> @@ -113,6 +113,41 @@ static int rwtm_otp_read(u8 row, u32 word, u32 *data)
>   return res;
>  }
>  
> +static int rwtm_otp_write(u8 row, u32 word, u32 data)
> +{
> + u32 in[4];
> + int res = -EINVAL;
> +
> + if (word < 2) {
> + /*
> +  * MBOX_CMD_OTP_WRITE_32B command is supported by Marvell
> +  * fuse.bin firmware and also by new CZ.NIC wtmi firmware.
> +  * This command writes only selected bits to OTP and does
> +  * not calculate ECC bits. It does not allow to write the
> +  * lock bit.
> +  */
> + in[0] = row;
> + in[1] = word * 32;
> + in[2] = data;
> + res = mbox_do_cmd(MBOX_CMD_OTP_WRITE_32B, in, 3, NULL, 0);
> + } else if (word == 2 && !(data & ~0x1)) {
> + /*
> +  * MBOX_CMD_OTP_WRITE command is supported only by new CZ.NIC
> +  * wtmi firmware and allows to write any bit to OTP, including
> +  * the lock bit. It does not calculate or write ECC bits too.
> +  * For compatibility with Marvell fuse.bin firmware, use this
> +  * command only for writing the lock bit.
> +  */
> + in[0] = row;
> + in[1] = 0;
> + in[2] = 0;
> + in[3] = data;
> + res = mbox_do_cmd(MBOX_CMD_OTP_WRITE, in, 4, NULL, 0);
> + }
> +
> + return res;
> +}
> +
>  /*
>   * Banks 0-43 are used for accessing Security OTP (44 rows with 67 bits via 
> 44 banks and words 0-2)
>   * Bank 44 is used for accessing North Bridge OTP (69 bits via words 0-2)
> @@ -154,8 +189,19 @@ int fuse_read(u32 bank, u32 word, u32 *val)
>  
>  int fuse_prog(u32 bank, u32 word, u32 val)
>  {
> - /* TODO: not implemented yet */
> - return -ENOSYS;
> + if (bank <= RWTM_MAX_BANK) {
> + if (word >= RWTM_ROW_WORDS)
> + return -EINVAL;
> + return rwtm_otp_write(bank, word, val);
> + } else if (bank == OTP_NB_BANK) {
> + /* TODO: not implemented yet */
> + return -ENOSYS;
> + } else if (bank == OTP_SB_BANK) {
> + /* TODO: not implemented yet */
> + return -ENOSYS;
> + } else {
> + return -EINVAL;
> + }
>  }
>  
>  int fuse_sense(u32 bank, u32 word, u32 *val)

Reviewed-by: Marek Behún 

Re: [PATCH] arm: mvebu: Add support for reading LD0 and LD1 eFuse

[Marek Behún]

On Thu, 7 Apr 2022 13:53:23 +0200
Pali Rohár  wrote:

> On Wednesday 06 April 2022 21:21:59 Marek Behún wrote:
> > On Wed,  6 Apr 2022 14:18:18 +0200
> > Pali Rohár  wrote:
> >   
> > > Armada 385 contains 64 lines of HD eFuse and 2 lines of LD eFuse. HD eFuse
> > > is used for secure boot and each line is 64 bits long + 1 lock bit. LD
> > > eFuse lines are 256 bits long + 1 lock bit. LD 0 line is reserved for
> > > Marvell Internal Use and LD 1 line is for General Purpose Data. U-Boot
> > > already contains HD eFuse reading and programming support.
> > > 
> > > This patch implements LD eFuse reading support. LD 0 line is mapped to
> > > U-Boot fuse bank 64 and LD 1 line to fuse bank 65.
> > > 
> > > LD 0 Marvell Internal Use line seems that was burned in factory with some
> > > data and can be read by U-Boot fuse command:
> > >   
> > >   => fuse read 64 0 9
> > > 
> > > LD 1 General Purpose Data line is by default empty and can be read by
> > > U-Boot fuse command:
> > >   
> > >   => fuse read 65 0 9
> > > 
> > > Signed-off-by: Pali Rohár   
> > 
> > I am not sure whether this can be used safely on Turris Omnia - there
> > was some issue with voltage or something, I know for sure that burning
> > does not work on Omnia, but I am not sure if the issue also prevents
> > stable reading.  
> 
> On A385 there is errata only for programming OTP bits.
> 
> > Are the values you read always the same? Even across power cycles?
> > 
> > Marek  
> 
> Reading is working fine and is stable also after power cycles. Marvell
> Internal Use contains data which are same after more reads.

In that case
Reviewed-by: Marek Behún 

Re: [PATCH] arm: mvebu: Add support for reading LD0 and LD1 eFuse

[Pali Rohár]

On Wednesday 06 April 2022 21:21:59 Marek Behún wrote:
> On Wed,  6 Apr 2022 14:18:18 +0200
> Pali Rohár  wrote:
> 
> > Armada 385 contains 64 lines of HD eFuse and 2 lines of LD eFuse. HD eFuse
> > is used for secure boot and each line is 64 bits long + 1 lock bit. LD
> > eFuse lines are 256 bits long + 1 lock bit. LD 0 line is reserved for
> > Marvell Internal Use and LD 1 line is for General Purpose Data. U-Boot
> > already contains HD eFuse reading and programming support.
> > 
> > This patch implements LD eFuse reading support. LD 0 line is mapped to
> > U-Boot fuse bank 64 and LD 1 line to fuse bank 65.
> > 
> > LD 0 Marvell Internal Use line seems that was burned in factory with some
> > data and can be read by U-Boot fuse command:
> > 
> >   => fuse read 64 0 9  
> > 
> > LD 1 General Purpose Data line is by default empty and can be read by
> > U-Boot fuse command:
> > 
> >   => fuse read 65 0 9  
> > 
> > Signed-off-by: Pali Rohár 
> 
> I am not sure whether this can be used safely on Turris Omnia - there
> was some issue with voltage or something, I know for sure that burning
> does not work on Omnia, but I am not sure if the issue also prevents
> stable reading.

On A385 there is errata only for programming OTP bits.

> Are the values you read always the same? Even across power cycles?
> 
> Marek

Reading is working fine and is stable also after power cycles. Marvell
Internal Use contains data which are same after more reads.

Re: [PATCH v2] IOMUX: Fix access past end of console_devices

[Andy Shevchenko]

On Wed, Apr 06, 2022 at 02:36:35PM -0400, Sean Anderson wrote:
> We should only access console_devices[file][i] once we have checked that i
> < cd_count[file]. Otherwise, we will access uninitialized memory at the end
> of the loop. console_devices[file][i] should not be NULL, but putting the
> assignment in the loop condition allows us to ensure that i is checked
> beforehand. This isn't a bug, but it does make valgrind stop complaining.

Acked-by: Andy Shevchenko 

> Fixes: 400797cad3 ("IOMUX: Split out for_each_console_dev() helper macro")
> Signed-off-by: Sean Anderson 
> Reviewed-by: Andrew Scull 
> ---
> 
> Changes in v2:
> - Put each clause of the for loop on its own line
> 
>  include/iomux.h | 8 
>  1 file changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/include/iomux.h b/include/iomux.h
> index 37f5f6dee6..35caa697eb 100644
> --- a/include/iomux.h
> +++ b/include/iomux.h
> @@ -24,10 +24,10 @@ extern struct stdio_dev **console_devices[MAX_FILES];
>   */
>  extern int cd_count[MAX_FILES];
>  
> -#define for_each_console_dev(i, file, dev)   \
> - for (i = 0, dev = console_devices[file][i]; \
> -  i < cd_count[file];\
> -  i++, dev = console_devices[file][i])
> +#define for_each_console_dev(i, file, dev)   \
> + for (i = 0; \
> +  i < cd_count[file] && (dev = console_devices[file][i]);\
> +  i++)
>  
>  int iomux_match_device(struct stdio_dev **, const int, struct stdio_dev *);
>  int iomux_doenv(const int, const char *);
> -- 
> 2.35.1
> 

-- 
With Best Regards,
Andy Shevchenko

[PATCH 08/11] board: freescale: p1_p2_rdb_pc: Use named macros for i2c bus num and address

[Pali Rohár]

Replace hardcoded boot i2c bus num and address by existing macros when
generating env for CONFIG_EXTRA_ENV_SETTINGS.

Same macros are used in U-Boot board code when reading information from
boot i2c data.

Signed-off-by: Pali Rohár 
---
 include/configs/p1_p2_rdb_pc.h | 24 
 1 file changed, 12 insertions(+), 12 deletions(-)

diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
index 7b5a8dd9e509..cb3b1a1da05d 100644
--- a/include/configs/p1_p2_rdb_pc.h
+++ b/include/configs/p1_p2_rdb_pc.h
@@ -568,28 +568,28 @@
 
 #ifdef __SW_BOOT_NOR
 #define __NOR_RST_CMD  \
-norboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NOR 1; \
-i2c mw 18 3 __SW_BOOT_MASK 1; reset
+norboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 
__SW_BOOT_NOR 1; \
+i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset
 #endif
 #ifdef __SW_BOOT_SPI
 #define __SPI_RST_CMD  \
-spiboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SPI 1; \
-i2c mw 18 3 __SW_BOOT_MASK 1; reset
+spiboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 
__SW_BOOT_SPI 1; \
+i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset
 #endif
 #ifdef __SW_BOOT_SD
 #define __SD_RST_CMD   \
-sdboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SD 1; \
-i2c mw 18 3 __SW_BOOT_MASK 1; reset
+sdboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 
__SW_BOOT_SD 1; \
+i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset
 #endif
 #ifdef __SW_BOOT_NAND
 #define __NAND_RST_CMD \
-nandboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NAND 1; \
-i2c mw 18 3 __SW_BOOT_MASK 1; reset
+nandboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 
__SW_BOOT_NAND 1; \
+i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset
 #endif
 #ifdef __SW_BOOT_PCIE
 #define __PCIE_RST_CMD \
-pciboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_PCIE 1; \
-i2c mw 18 3 __SW_BOOT_MASK 1; reset
+pciboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 
__SW_BOOT_PCIE 1; \
+i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset
 #endif
 
 #defineCONFIG_EXTRA_ENV_SETTINGS   \
@@ -616,9 +616,9 @@ i2c mw 18 3 __SW_BOOT_MASK 1; reset
 "nandbootaddr=10\0"\
 "nandfdtaddr=8\0"  \
 "ramdisk_size=12\0"\
-"map_lowernorbank=i2c dev 1; i2c mw 18 1 02 1; i2c mw 18 3 fd 1\0" \
-"map_uppernorbank=i2c dev 1; i2c mw 18 1 00 1; i2c mw 18 3 fd 1\0" \
 __VSCFW_ADDR   \
+"map_lowernorbank=i2c dev "__stringify(CONFIG_SYS_SPD_BUS_NUM)"; i2c mw 
"__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 1 02 1; i2c mw 
"__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 3 fd 1\0" \
+"map_uppernorbank=i2c dev "__stringify(CONFIG_SYS_SPD_BUS_NUM)"; i2c mw 
"__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 1 00 1; i2c mw 
"__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 3 fd 1\0" \
 __stringify(__NOR_RST_CMD)"\0" \
 __stringify(__SPI_RST_CMD)"\0" \
 __stringify(__SD_RST_CMD)"\0" \
-- 
2.20.1

[PATCH 11/11] board: freescale: p1_p2_rdb_pc: Add env commands norlowerboot, norupperboot, sd2boot and defboot

[Pali Rohár]

All *boot env commands overrides default BootROM boot location via i2c.
BootROM then starts booting U-Boot from this specified location instead of
the default one.

Add new env command defboot which reverts BootROM boot location to the
default value, which in most cases is configurable by HW DIP switches.

And add new env commands norlowerboot, norupperboot, sd2boot to boot from
other locations. norlowerboot would instruct BootROM to boot from lower NOR
bank, norupperboot from upper NOR bank and sd2boot from SD card with
alternative configuration.

Signed-off-by: Pali Rohár 
---
 include/configs/p1_p2_bootrom.h | 14 +
 include/configs/p1_p2_rdb_pc.h  | 37 +
 2 files changed, 51 insertions(+)

diff --git a/include/configs/p1_p2_bootrom.h b/include/configs/p1_p2_bootrom.h
index a1f61b788cf7..d1e91049606b 100644
--- a/include/configs/p1_p2_bootrom.h
+++ b/include/configs/p1_p2_bootrom.h
@@ -15,6 +15,14 @@
 #define CHANGE_BOOTROM_SOURCE_DEF_NOR_BANK_CMD 
CHANGE_BOOTROM_SOURCE_CMD(__SW_BOOT_NOR, __SW_BOOT_MASK)
 #endif
 
+#ifdef __SW_BOOT_NOR_BANK_LO
+#define CHANGE_BOOTROM_SOURCE_LOWER_NOR_BANK_CMD 
CHANGE_BOOTROM_SOURCE_CMD(__SW_BOOT_NOR_BANK_LO, __SW_BOOT_NOR_BANK_MASK)
+#endif
+
+#ifdef __SW_BOOT_NOR_BANK_UP
+#define CHANGE_BOOTROM_SOURCE_UPPER_NOR_BANK_CMD 
CHANGE_BOOTROM_SOURCE_CMD(__SW_BOOT_NOR_BANK_UP, __SW_BOOT_NOR_BANK_MASK)
+#endif
+
 #ifdef __SW_BOOT_SPI
 #define CHANGE_BOOTROM_SOURCE_SPI_CMD CHANGE_BOOTROM_SOURCE_CMD(__SW_BOOT_SPI, 
__SW_BOOT_MASK)
 #endif
@@ -23,6 +31,10 @@
 #define CHANGE_BOOTROM_SOURCE_SD_CMD CHANGE_BOOTROM_SOURCE_CMD(__SW_BOOT_SD, 
__SW_BOOT_MASK)
 #endif
 
+#ifdef __SW_BOOT_SD2
+#define CHANGE_BOOTROM_SOURCE_SD2_CMD CHANGE_BOOTROM_SOURCE_CMD(__SW_BOOT_SD2, 
__SW_BOOT_MASK)
+#endif
+
 #ifdef __SW_BOOT_NAND
 #define CHANGE_BOOTROM_SOURCE_NAND_CMD 
CHANGE_BOOTROM_SOURCE_CMD(__SW_BOOT_NAND, __SW_BOOT_MASK)
 #endif
@@ -30,3 +42,5 @@
 #ifdef __SW_BOOT_PCIE
 #define CHANGE_BOOTROM_SOURCE_PCIE_CMD 
CHANGE_BOOTROM_SOURCE_CMD(__SW_BOOT_PCIE, __SW_BOOT_MASK)
 #endif
+
+#define CHANGE_BOOTROM_SOURCE_DEF_CMD CHANGE_BOOTROM_SOURCE_CMD(0x00, 0xff)
diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
index d41b31081017..ac8199a88aa0 100644
--- a/include/configs/p1_p2_rdb_pc.h
+++ b/include/configs/p1_p2_rdb_pc.h
@@ -25,6 +25,9 @@
 #define __SW_NOR_BANK_MASK 0xfd
 #define __SW_NOR_BANK_UP   0x00
 #define __SW_NOR_BANK_LO   0x02
+#define __SW_BOOT_NOR_BANK_UP  0x5c /* (__SW_BOOT_NOR | __SW_NOR_BANK_UP) */
+#define __SW_BOOT_NOR_BANK_LO  0x5e /* (__SW_BOOT_NOR | __SW_NOR_BANK_LO) */
+#define __SW_BOOT_NOR_BANK_MASK0x01 /* (__SW_BOOT_MASK & 
__SW_NOR_BANK_MASK) */
 #define CONFIG_SYS_L2_SIZE (256 << 10)
 #endif
 
@@ -54,6 +57,9 @@
 #define __SW_NOR_BANK_MASK 0xfd
 #define __SW_NOR_BANK_UP   0x00
 #define __SW_NOR_BANK_LO   0x02
+#define __SW_BOOT_NOR_BANK_UP  0x64 /* (__SW_BOOT_NOR | __SW_NOR_BANK_UP) */
+#define __SW_BOOT_NOR_BANK_LO  0x66 /* (__SW_BOOT_NOR | __SW_NOR_BANK_LO) */
+#define __SW_BOOT_NOR_BANK_MASK0x01 /* (__SW_BOOT_MASK & 
__SW_NOR_BANK_MASK) */
 #define CONFIG_SYS_L2_SIZE (256 << 10)
 /*
  * Dynamic MTD Partition support with mtdparts
@@ -73,6 +79,9 @@
 #define __SW_NOR_BANK_MASK 0xfd
 #define __SW_NOR_BANK_UP   0x00
 #define __SW_NOR_BANK_LO   0x02
+#define __SW_BOOT_NOR_BANK_UP  0xc8 /* (__SW_BOOT_NOR | __SW_NOR_BANK_UP) */
+#define __SW_BOOT_NOR_BANK_LO  0xca /* (__SW_BOOT_NOR | __SW_NOR_BANK_LO) */
+#define __SW_BOOT_NOR_BANK_MASK0x01 /* (__SW_BOOT_MASK & 
__SW_NOR_BANK_MASK) */
 #define CONFIG_SYS_L2_SIZE (512 << 10)
 /*
  * Dynamic MTD Partition support with mtdparts
@@ -595,6 +604,18 @@
 #define __NOR_RST_CMD ""
 #endif
 
+#ifdef CHANGE_BOOTROM_SOURCE_LOWER_NOR_BANK_CMD
+#define __NOR_LOWER_RST_CMD 
"norlowerboot="__stringify(CHANGE_BOOTROM_SOURCE_LOWER_NOR_BANK_CMD)"; reset\0"
+#else
+#define __NOR_LOWER_RST_CMD ""
+#endif
+
+#ifdef CHANGE_BOOTROM_SOURCE_UPPER_NOR_BANK_CMD
+#define __NOR_UPPER_RST_CMD 
"norupperboot="__stringify(CHANGE_BOOTROM_SOURCE_UPPER_NOR_BANK_CMD)"; reset\0"
+#else
+#define __NOR_UPPER_RST_CMD ""
+#endif
+
 #ifdef CHANGE_BOOTROM_SOURCE_SPI_CMD
 #define __SPI_RST_CMD "spiboot="__stringify(CHANGE_BOOTROM_SOURCE_SPI_CMD)"; 
reset\0"
 #else
@@ -607,6 +628,12 @@
 #define __SD_RST_CMD ""
 #endif
 
+#ifdef CHANGE_BOOTROM_SOURCE_SD2_CMD
+#define __SD2_RST_CMD "sd2boot="__stringify(CHANGE_BOOTROM_SOURCE_SD2_CMD)"; 
reset\0"
+#else
+#define __SD2_RST_CMD ""
+#endif
+
 #ifdef CHANGE_BOOTROM_SOURCE_NAND_CMD
 #define __NAND_RST_CMD 
"nandboot="__stringify(CHANGE_BOOTROM_SOURCE_NAND_CMD)"; reset\0"
 #else
@@ -619,6 +646,12 @@
 #define __PCIE_RST_CMD ""
 #endif
 
+#ifdef CHANGE_BOOTROM_SOURCE_DEF_CMD
+#define __DEF_RST_CMD "defboot="__stringify(CHANGE_BOOTROM_SOURCE_DEF_CMD)"; 
reset\0"
+#else
+#define __DEF_RST_CMD ""
+#endif
+
 #defineCONFIG_EXTRA_ENV_SETTINGS   \
 "netdev=eth0\0"\
 "uboot=" 

[PATCH 06/11] board: freescale: p1_p2_rdb_pc: Move ifdef for USB/eLBC check to correct place

[Pali Rohár]

Whole section about USB/eLBC configuration seems to be P1020 specific. So
add ifdefs to not compile it on other platforms (e.g. P2020).

Signed-off-by: Pali Rohár 
---
 board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c 
b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
index fc581bdb2a40..1b28f1bbc776 100644
--- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
+++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
@@ -354,9 +354,9 @@ int ft_board_setup(void *blob, struct bd_info *bd)
 #if defined(CONFIG_TARGET_P1020RDB_PD) || defined(CONFIG_TARGET_P1020RDB_PC)
const char *soc_usb_compat = "fsl-usb2-dr";
int usb_err, usb1_off, usb2_off;
-#endif
 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
int err;
+#endif
 #endif
 
ft_cpu_setup(blob, bd);
@@ -375,6 +375,7 @@ int ft_board_setup(void *blob, struct bd_info *bd)
fsl_fdt_fixup_dr_usb(blob, bd);
 #endif
 
+#if defined(CONFIG_TARGET_P1020RDB_PD) || defined(CONFIG_TARGET_P1020RDB_PC)
 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
/* Delete eLBC node as it is muxed with USB2 controller */
if (hwconfig("usb2")) {
@@ -396,7 +397,6 @@ int ft_board_setup(void *blob, struct bd_info *bd)
}
 #endif
 
-#if defined(CONFIG_TARGET_P1020RDB_PD) || defined(CONFIG_TARGET_P1020RDB_PC)
 /* Delete USB2 node as it is muxed with eLBC */
usb1_off = fdt_node_offset_by_compatible(blob, -1,
soc_usb_compat);
-- 
2.20.1

[PATCH 09/11] board: freescale: p1_p2_rdb_pc: Define SW macros for lower and upper NOR banks

[Pali Rohár]

Replace hardcoded i2c hex values for NOR banks by named SW macros in
map_lowernorbank/map_uppernorbank env commands.

Signed-off-by: Pali Rohár 
---
 include/configs/p1_p2_rdb_pc.h | 13 +++--
 1 file changed, 11 insertions(+), 2 deletions(-)

diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
index cb3b1a1da05d..995bd983cef1 100644
--- a/include/configs/p1_p2_rdb_pc.h
+++ b/include/configs/p1_p2_rdb_pc.h
@@ -22,6 +22,9 @@
 #define __SW_BOOT_SD   0x9c
 #define __SW_BOOT_NAND 0xec
 #define __SW_BOOT_PCIE 0x6c
+#define __SW_NOR_BANK_MASK 0xfd
+#define __SW_NOR_BANK_UP   0x00
+#define __SW_NOR_BANK_LO   0x02
 #define CONFIG_SYS_L2_SIZE (256 << 10)
 #endif
 
@@ -48,6 +51,9 @@
 #define __SW_BOOT_SD   0x24
 #define __SW_BOOT_NAND 0x44
 #define __SW_BOOT_PCIE 0x74
+#define __SW_NOR_BANK_MASK 0xfd
+#define __SW_NOR_BANK_UP   0x00
+#define __SW_NOR_BANK_LO   0x02
 #define CONFIG_SYS_L2_SIZE (256 << 10)
 /*
  * Dynamic MTD Partition support with mtdparts
@@ -64,6 +70,9 @@
 #define __SW_BOOT_SD2  0x18
 #define __SW_BOOT_NAND 0xe8
 #define __SW_BOOT_PCIE 0xa8
+#define __SW_NOR_BANK_MASK 0xfd
+#define __SW_NOR_BANK_UP   0x00
+#define __SW_NOR_BANK_LO   0x02
 #define CONFIG_SYS_L2_SIZE (512 << 10)
 /*
  * Dynamic MTD Partition support with mtdparts
@@ -617,8 +626,8 @@ i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset
 "nandfdtaddr=8\0"  \
 "ramdisk_size=12\0"\
 __VSCFW_ADDR   \
-"map_lowernorbank=i2c dev "__stringify(CONFIG_SYS_SPD_BUS_NUM)"; i2c mw 
"__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 1 02 1; i2c mw 
"__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 3 fd 1\0" \
-"map_uppernorbank=i2c dev "__stringify(CONFIG_SYS_SPD_BUS_NUM)"; i2c mw 
"__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 1 00 1; i2c mw 
"__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 3 fd 1\0" \
+"map_lowernorbank=i2c dev "__stringify(CONFIG_SYS_SPD_BUS_NUM)"; i2c mw 
"__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 1 "__stringify(__SW_NOR_BANK_LO)" 1; 
i2c mw "__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 3 
"__stringify(__SW_NOR_BANK_MASK)" 1\0" \
+"map_uppernorbank=i2c dev "__stringify(CONFIG_SYS_SPD_BUS_NUM)"; i2c mw 
"__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 1 "__stringify(__SW_NOR_BANK_UP)" 1; 
i2c mw "__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 3 
"__stringify(__SW_NOR_BANK_MASK)" 1\0" \
 __stringify(__NOR_RST_CMD)"\0" \
 __stringify(__SPI_RST_CMD)"\0" \
 __stringify(__SD_RST_CMD)"\0" \
-- 
2.20.1

[PATCH 05/11] board: freescale: p1_p2_rdb_pc: Fix page attributes for second 1G SDRAM map

[Pali Rohár]

Like for first 1G SDRAM map, do not enable Caching-inhibited nor Guarded
attribute for second 1G SDRAM mapping. Whole 2G SDRAM should use caches and
also allow speculative loading (by not setting Guarded attribute).

Also enable Memory Coherency attribute for second 1G SDRAM map. In commit
316f0d0f8f3c ("powerpc: mpc85xx: Fix static TLB table for SDRAM") it was
enabled for all SDRAM maps on all other boards, just missed this one case.

As a last thing, first 1G SDRAM map has wrong comment, so adjust it.

Signed-off-by: Pali Rohár 
---
 board/freescale/p1_p2_rdb_pc/tlb.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/board/freescale/p1_p2_rdb_pc/tlb.c 
b/board/freescale/p1_p2_rdb_pc/tlb.c
index fcd7a55199f0..5931ec650bd8 100644
--- a/board/freescale/p1_p2_rdb_pc/tlb.c
+++ b/board/freescale/p1_p2_rdb_pc/tlb.c
@@ -79,16 +79,16 @@ struct fsl_e_tlb_entry tlb_table[] = {
 
 #if defined(CONFIG_SYS_RAMBOOT) || \
(defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR))
-   /* *I*G - eSDHC/eSPI/NAND boot */
+   /* **M** - 1G DDR for eSDHC/eSPI/NAND boot */
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
0, 8, BOOKE_PAGESZ_1G, 1),
 
 #if defined(CONFIG_TARGET_P1020RDB_PD)
-   /* 2G DDR on P1020MBG, map the second 1G */
+   /* **M** - 2G DDR on P1020MBG, map the second 1G */
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x4000,
CONFIG_SYS_DDR_SDRAM_BASE + 0x4000,
-   MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+   MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
0, 9, BOOKE_PAGESZ_1G, 1),
 #endif
 #endif /* RAMBOOT/SPL */
-- 
2.20.1

[PATCH 03/11] board: freescale: p1_p2_rdb_pc: Fix parsing negated upper 4 bits from boot input data

[Pali Rohár]

On some boards upper 4 bits of i2c boot input data (register 0) are
negated. So negate read input data back prior processing them.

Fixes printing correct rom_loc: value.

Signed-off-by: Pali Rohár 
---
 board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c 
b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
index 29502a5c05c2..766a82386079 100644
--- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
+++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
@@ -202,6 +202,10 @@ int checkboard(void)
}
#endif
 
+#ifdef __SW_BOOT_IN_NEG_UPPER4
+   in = (~in & 0xf0) | (in & 0x0f);
+#endif
+
val = (in & io_config) | (out & (~io_config));
 
puts("rom_loc: ");
-- 
2.20.1

[PATCH 10/11] board: freescale: p1_p2_rdb_pc: Move BootROM change source macros to p1_p2_bootrom.h

[Pali Rohár]

Code for changing BootROM source is platform generic and can be used by any
P1* and P2* compatible board. Not only by RDB boards which use config
header file p1_p2_rdb_pc.h.

So move this code from p1_p2_rdb_pc.h to p1_p2_bootrom.h and cleanup macros
for generating boot source env variables in CONFIG_EXTRA_ENV_SETTINGS.

This allows to use code for changing BootROM source also by other boards in
future.

Signed-off-by: Pali Rohár 
---
 include/configs/p1_p2_bootrom.h | 32 +++
 include/configs/p1_p2_rdb_pc.h  | 73 +
 2 files changed, 78 insertions(+), 27 deletions(-)
 create mode 100644 include/configs/p1_p2_bootrom.h

diff --git a/include/configs/p1_p2_bootrom.h b/include/configs/p1_p2_bootrom.h
new file mode 100644
index ..a1f61b788cf7
--- /dev/null
+++ b/include/configs/p1_p2_bootrom.h
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: GPL-2.0+
+// (C) 2022 Pali Rohár 
+
+#define CHANGE_BOOTROM_SOURCE_CMD(SOURCE, MASK) i2c dev 
CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 SOURCE 1; i2c mw 
CONFIG_SYS_I2C_PCA9557_ADDR 3 MASK 1
+
+#ifdef __SW_NOR_BANK_LO
+#define CHANGE_BOOTROM_LOWER_NOR_BANK_CMD 
CHANGE_BOOTROM_SOURCE_CMD(__SW_NOR_BANK_LO, __SW_NOR_BANK_MASK)
+#endif
+
+#ifdef __SW_NOR_BANK_UP
+#define CHANGE_BOOTROM_UPPER_NOR_BANK_CMD 
CHANGE_BOOTROM_SOURCE_CMD(__SW_NOR_BANK_UP, __SW_NOR_BANK_MASK)
+#endif
+
+#ifdef __SW_BOOT_NOR
+#define CHANGE_BOOTROM_SOURCE_DEF_NOR_BANK_CMD 
CHANGE_BOOTROM_SOURCE_CMD(__SW_BOOT_NOR, __SW_BOOT_MASK)
+#endif
+
+#ifdef __SW_BOOT_SPI
+#define CHANGE_BOOTROM_SOURCE_SPI_CMD CHANGE_BOOTROM_SOURCE_CMD(__SW_BOOT_SPI, 
__SW_BOOT_MASK)
+#endif
+
+#ifdef __SW_BOOT_SD
+#define CHANGE_BOOTROM_SOURCE_SD_CMD CHANGE_BOOTROM_SOURCE_CMD(__SW_BOOT_SD, 
__SW_BOOT_MASK)
+#endif
+
+#ifdef __SW_BOOT_NAND
+#define CHANGE_BOOTROM_SOURCE_NAND_CMD 
CHANGE_BOOTROM_SOURCE_CMD(__SW_BOOT_NAND, __SW_BOOT_MASK)
+#endif
+
+#ifdef __SW_BOOT_PCIE
+#define CHANGE_BOOTROM_SOURCE_PCIE_CMD 
CHANGE_BOOTROM_SOURCE_CMD(__SW_BOOT_PCIE, __SW_BOOT_MASK)
+#endif
diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
index 995bd983cef1..d41b31081017 100644
--- a/include/configs/p1_p2_rdb_pc.h
+++ b/include/configs/p1_p2_rdb_pc.h
@@ -79,6 +79,8 @@
  */
 #endif
 
+#include "p1_p2_bootrom.h"
+
 #ifdef CONFIG_SDCARD
 #define CONFIG_SPL_FLUSH_IMAGE
 #define CONFIG_SPL_TARGET  "u-boot-with-spl.bin"
@@ -575,30 +577,46 @@
 #define CONFIG_BOOTFILE"uImage"
 #define CONFIG_UBOOTPATH   u-boot.bin /* U-Boot image on TFTP server */
 
-#ifdef __SW_BOOT_NOR
-#define __NOR_RST_CMD  \
-norboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 
__SW_BOOT_NOR 1; \
-i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset
+#ifdef CHANGE_BOOTROM_LOWER_NOR_BANK_CMD
+#define __MAP_NOR_LOWER_CMD 
"map_lowernorbank="__stringify(CHANGE_BOOTROM_LOWER_NOR_BANK_CMD)"\0"
+#else
+#define __MAP_NOR_LOWER_CMD ""
+#endif
+
+#ifdef CHANGE_BOOTROM_UPPER_NOR_BANK_CMD
+#define __MAP_NOR_UPPER_CMD 
"map_uppernorbank="__stringify(CHANGE_BOOTROM_UPPER_NOR_BANK_CMD)"\0"
+#else
+#define __MAP_NOR_UPPER_CMD ""
+#endif
+
+#ifdef CHANGE_BOOTROM_SOURCE_DEF_NOR_BANK_CMD
+#define __NOR_RST_CMD 
"norboot="__stringify(CHANGE_BOOTROM_SOURCE_DEF_NOR_BANK_CMD)"; reset\0"
+#else
+#define __NOR_RST_CMD ""
 #endif
-#ifdef __SW_BOOT_SPI
-#define __SPI_RST_CMD  \
-spiboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 
__SW_BOOT_SPI 1; \
-i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset
+
+#ifdef CHANGE_BOOTROM_SOURCE_SPI_CMD
+#define __SPI_RST_CMD "spiboot="__stringify(CHANGE_BOOTROM_SOURCE_SPI_CMD)"; 
reset\0"
+#else
+#define __SPI_RST_CMD ""
 #endif
-#ifdef __SW_BOOT_SD
-#define __SD_RST_CMD   \
-sdboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 
__SW_BOOT_SD 1; \
-i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset
+
+#ifdef CHANGE_BOOTROM_SOURCE_SD_CMD
+#define __SD_RST_CMD "sdboot="__stringify(CHANGE_BOOTROM_SOURCE_SD_CMD)"; 
reset\0"
+#else
+#define __SD_RST_CMD ""
 #endif
-#ifdef __SW_BOOT_NAND
-#define __NAND_RST_CMD \
-nandboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 
__SW_BOOT_NAND 1; \
-i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset
+
+#ifdef CHANGE_BOOTROM_SOURCE_NAND_CMD
+#define __NAND_RST_CMD 
"nandboot="__stringify(CHANGE_BOOTROM_SOURCE_NAND_CMD)"; reset\0"
+#else
+#define __NAND_RST_CMD ""
 #endif
-#ifdef __SW_BOOT_PCIE
-#define __PCIE_RST_CMD \
-pciboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 
__SW_BOOT_PCIE 1; \
-i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset
+
+#ifdef CHANGE_BOOTROM_SOURCE_PCIE_CMD
+#define __PCIE_RST_CMD "pciboot="__stringify(CHANGE_BOOTROM_SOURCE_PCIE_CMD)"; 
reset\0"
+#else
+#define __PCIE_RST_CMD ""
 #endif
 
 #defineCONFIG_EXTRA_ENV_SETTINGS   \
@@ -626,13 +644,14 @@ i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; 
reset

[PATCH 04/11] board: freescale: p1_p2_rdb_pc: Do not set MPC85xx_PMUXCR_SDHC_WP bit when SDHC_WP is used as GPIO

[Pali Rohár]

When MPC85xx_PMUXCR_SDHC_WP is set then SDHC controller automatically makes
inserted SD card readonly if GPIO[9] is active.

In some design GPIO[9] pin does not have to be connected to SD card
write-protect pin and can be used as GPIO.

So do not set MPC85xx_PMUXCR_SDHC_WP bit when GPIO[9] is not used for
SDHC_WP functionality.

Signed-off-by: Pali Rohár 
---
 board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c 
b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
index 766a82386079..fc581bdb2a40 100644
--- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
+++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
@@ -147,8 +147,10 @@ int board_early_init_f(void)
 {
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 
-   setbits_be32(>pmuxcr,
-   (MPC85xx_PMUXCR_SDHC_CD | MPC85xx_PMUXCR_SDHC_WP));
+   setbits_be32(>pmuxcr, MPC85xx_PMUXCR_SDHC_CD);
+#ifndef SDHC_WP_IS_GPIO
+   setbits_be32(>pmuxcr, MPC85xx_PMUXCR_SDHC_WP);
+#endif
clrbits_be32(>sdhcdcr, SDHCDCR_CD_INV);
 
clrbits_be32(>pmuxcr, MPC85xx_PMUXCR_SD_DATA);
-- 
2.20.1

[PATCH 02/11] board: freescale: p1_p2_rdb_pc: Detect both P2020 SD switch configurations

[Pali Rohár]

As written in comment, P2020 has two possible SD switch configurations.
Extend code to detect both of them.

Signed-off-by: Pali Rohár 
---
 board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 4 
 include/configs/p1_p2_rdb_pc.h  | 3 ++-
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c 
b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
index 186887336354..29502a5c05c2 100644
--- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
+++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
@@ -207,6 +207,10 @@ int checkboard(void)
puts("rom_loc: ");
if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_SD) {
puts("sd");
+#ifdef __SW_BOOT_SD2
+   } else if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_SD2) {
+   puts("sd");
+#endif
 #ifdef __SW_BOOT_SPI
} else if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_SPI) {
puts("spi");
diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
index 370772053e63..ecc6e0c644bf 100644
--- a/include/configs/p1_p2_rdb_pc.h
+++ b/include/configs/p1_p2_rdb_pc.h
@@ -60,7 +60,8 @@
 #define __SW_BOOT_MASK 0x03
 #define __SW_BOOT_NOR  0xc8
 #define __SW_BOOT_SPI  0x28
-#define __SW_BOOT_SD   0x68 /* or 0x18 */
+#define __SW_BOOT_SD   0x68
+#define __SW_BOOT_SD2  0x18
 #define __SW_BOOT_NAND 0xe8
 #define __SW_BOOT_PCIE 0xa8
 #define CONFIG_SYS_L2_SIZE (512 << 10)
-- 
2.20.1

[PATCH 07/11] board: freescale: p1_p2_rdb_pc: Fix env $vscfw_addr

[Pali Rohár]

Do not stringify env $vscfw_addr two times (once implicitly via string
operator "" and second time explicitly via __stringify() macro) and allow
to compile U-Boot without CONFIG_VSC7385_ENET (when __VSCFW_ADDR was not
defined and so macro name was stringified into CONFIG_EXTRA_ENV_SETTINGS).

Signed-off-by: Pali Rohár 
---
 include/configs/p1_p2_rdb_pc.h | 8 ++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
index ecc6e0c644bf..7b5a8dd9e509 100644
--- a/include/configs/p1_p2_rdb_pc.h
+++ b/include/configs/p1_p2_rdb_pc.h
@@ -351,7 +351,7 @@
 
 /* Vsc7385 switch */
 #ifdef CONFIG_VSC7385_ENET
-#define __VSCFW_ADDR   "vscfw_addr=ef00"
+#define __VSCFW_ADDR   "vscfw_addr=ef00\0"
 #define CONFIG_SYS_VSC7385_BASE0xffb0
 
 #ifdef CONFIG_PHYS_64BIT
@@ -370,6 +370,10 @@
 #define CONFIG_VSC7385_IMAGE_SIZE  8192
 #endif
 
+#ifndef __VSCFW_ADDR
+#define __VSCFW_ADDR ""
+#endif
+
 /*
  * Config the L2 Cache as L2 SRAM
 */
@@ -614,7 +618,7 @@ i2c mw 18 3 __SW_BOOT_MASK 1; reset
 "ramdisk_size=12\0"\
 "map_lowernorbank=i2c dev 1; i2c mw 18 1 02 1; i2c mw 18 3 fd 1\0" \
 "map_uppernorbank=i2c dev 1; i2c mw 18 1 00 1; i2c mw 18 3 fd 1\0" \
-__stringify(__VSCFW_ADDR)"\0" \
+__VSCFW_ADDR   \
 __stringify(__NOR_RST_CMD)"\0" \
 __stringify(__SPI_RST_CMD)"\0" \
 __stringify(__SD_RST_CMD)"\0" \
-- 
2.20.1

[PATCH 01/11] board: freescale: p1_p2_rdb_pc: Do not hang in checkboard()

[Pali Rohár]

Like in all other checks in checkboard() function, do not hang on error.

Signed-off-by: Pali Rohár 
---
 board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c 
b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
index 19ece1229631..186887336354 100644
--- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
+++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
@@ -182,7 +182,7 @@ int checkboard(void)
if (ret) {
printf("%s: Cannot find udev for a bus %d\n", __func__,
   bus_num);
-   return -ENXIO;
+   return 0; /* Don't want to hang() on this error */
}
 
if (dm_i2c_read(dev, 0, , 1) < 0 ||
-- 
2.20.1

[PATCH 00/11] board: freescale: p1_p2_rdb_pc: Various cleanups and fixes

[Pali Rohár]

This patch series contains various cleanups and fixes for shared P1*/P2*
board code and preparation for introducing support for another P2020 board.

Pali Rohár (11):
  board: freescale: p1_p2_rdb_pc: Do not hang in checkboard()
  board: freescale: p1_p2_rdb_pc: Detect both P2020 SD switch
configurations
  board: freescale: p1_p2_rdb_pc: Fix parsing negated upper 4 bits from
boot input data
  board: freescale: p1_p2_rdb_pc: Do not set MPC85xx_PMUXCR_SDHC_WP bit
when SDHC_WP is used as GPIO
  board: freescale: p1_p2_rdb_pc: Fix page attributes for second 1G
SDRAM map
  board: freescale: p1_p2_rdb_pc: Move ifdef for USB/eLBC check to
correct place
  board: freescale: p1_p2_rdb_pc: Fix env $vscfw_addr
  board: freescale: p1_p2_rdb_pc: Use named macros for i2c bus num and
address
  board: freescale: p1_p2_rdb_pc: Define SW macros for lower and upper
NOR banks
  board: freescale: p1_p2_rdb_pc: Move BootROM change source macros to
p1_p2_bootrom.h
  board: freescale: p1_p2_rdb_pc: Add env commands norlowerboot,
norupperboot, sd2boot and defboot

 board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c |  20 ++-
 board/freescale/p1_p2_rdb_pc/tlb.c  |   6 +-
 include/configs/p1_p2_bootrom.h |  46 +++
 include/configs/p1_p2_rdb_pc.h  | 130 +++-
 4 files changed, 164 insertions(+), 38 deletions(-)
 create mode 100644 include/configs/p1_p2_bootrom.h

-- 
2.20.1

Re: [PATCH 08/11] virtio: sandbox: Bind RNG rather than block device

[Andrew Scull]

On Thu, 7 Apr 2022 at 08:20, Heinrich Schuchardt  wrote:
>
> On 3/31/22 12:09, Andrew Scull wrote:
> > The virtio-rng driver is extremely simple, making it suitable for
> > testing more of the virtio uclass logic. Have the sandbox driver bind
> > the virtio-rng driver rather than the virtio-blk driver so it can be
> > used in tests.
>
> test/dm/rng.c assumes that drivers/rng/sandbox_rng.c is providing the
> only RNG device.
>
> Does test/dm/virtio.c guarantee that no virtio-rng device is bound after
> the test is run?

My understanding was that dm_test_pre_run() in test/test-main.c reset
the driver model for each dm test, which would imply that nothing is
bound at the start of the test. Have I understood this correctly?

> Best regards
>
> Heinrich
>
> >
> > Signed-off-by: Andrew Scull 
> > ---
> >   drivers/virtio/virtio_sandbox.c | 2 +-
> >   test/dm/virtio.c| 8 
> >   2 files changed, 5 insertions(+), 5 deletions(-)
> >
> > diff --git a/drivers/virtio/virtio_sandbox.c 
> > b/drivers/virtio/virtio_sandbox.c
> > index a73b123454..5484ae3a1a 100644
> > --- a/drivers/virtio/virtio_sandbox.c
> > +++ b/drivers/virtio/virtio_sandbox.c
> > @@ -161,7 +161,7 @@ static int virtio_sandbox_probe(struct udevice *udev)
> >
> >   /* fake some information for testing */
> >   priv->device_features = BIT_ULL(VIRTIO_F_VERSION_1);
> > - uc_priv->device = VIRTIO_ID_BLOCK;
> > + uc_priv->device = VIRTIO_ID_RNG;
> >   uc_priv->vendor = ('u' << 24) | ('b' << 16) | ('o' << 8) | 't';
> >
> >   return 0;
> > diff --git a/test/dm/virtio.c b/test/dm/virtio.c
> > index d054ccfaa4..769945a0d8 100644
> > --- a/test/dm/virtio.c
> > +++ b/test/dm/virtio.c
> > @@ -25,10 +25,10 @@ static int dm_test_virtio_base(struct unit_test_state 
> > *uts)
> >   ut_assertok(uclass_first_device(UCLASS_VIRTIO, ));
> >   ut_assertnonnull(bus);
> >
> > - /* check the child virtio-blk device is bound */
> > + /* check the child virtio-rng device is bound */
> >   ut_assertok(device_find_first_child(bus, ));
> >   ut_assertnonnull(dev);
> > - ut_assertok(strcmp(dev->name, "virtio-blk#0"));
> > + ut_asserteq_str("virtio-rng#0", dev->name);
> >
> >   /* check driver status */
> >   ut_assertok(virtio_get_status(dev, ));
> > @@ -54,7 +54,7 @@ static int dm_test_virtio_all_ops(struct unit_test_state 
> > *uts)
> >   ut_assertok(uclass_first_device(UCLASS_VIRTIO, ));
> >   ut_assertnonnull(bus);
> >
> > - /* check the child virtio-blk device is bound */
> > + /* check the child virtio-rng device is bound */
> >   ut_assertok(device_find_first_child(bus, ));
> >   ut_assertnonnull(dev);
> >
> > @@ -114,7 +114,7 @@ static int dm_test_virtio_remove(struct unit_test_state 
> > *uts)
> >   ut_assertok(uclass_first_device(UCLASS_VIRTIO, ));
> >   ut_assertnonnull(bus);
> >
> > - /* check the child virtio-blk device is bound */
> > + /* check the child virtio-rng device is bound */
> >   ut_assertok(device_find_first_child(bus, ));
> >   ut_assertnonnull(dev);
> >
>

Re: [PATCH 10/11] virtio: rng: Check length before copying

[Andrew Scull]

On Wed, 6 Apr 2022 at 15:18, Pierre-Clément Tosi  wrote:
>
> Hi,
>
> On Thu, Mar 31, 2022 at 10:09:48AM +, Andrew Scull wrote:
> > Check the length of data written by the device is consistent with the
> > size of the buffers to avoid out-of-bounds memory accesses in case
> > values aren't consistent.
> >
> > Signed-off-by: Andrew Scull 
> > Cc: Sughosh Ganu 
> > ---
> >  drivers/virtio/virtio_rng.c | 3 +++
> >  1 file changed, 3 insertions(+)
> >
> > diff --git a/drivers/virtio/virtio_rng.c b/drivers/virtio/virtio_rng.c
> > index 9314c0a03e..b85545c2ee 100644
> > --- a/drivers/virtio/virtio_rng.c
> > +++ b/drivers/virtio/virtio_rng.c
> > @@ -41,6 +41,9 @@ static int virtio_rng_read(struct udevice *dev, void 
> > *data, size_t len)
> >   while (!virtqueue_get_buf(priv->rng_vq, ))
> >   ;
> >
> > + if (rsize > sg.length)
> > + return -EIO;
> > +
>
> Although this patch addresses a legitimate concern, could we instead aim for
> strengthening the lower-level virtio building blocks (e.g. 
> virtqueue_get_buf())
> so that higher-level virtio device drivers such as 
> virtio-{rng,console,net,...}
> don't have to be littered with checks of this nature? Could this be achieved 
> by
> using the shadow copy introduced in [PATCH 03/11]?

There could certainly be _a_ bounds check in the vring driver, to
check that the total size written doesn't exceed the cumulative size
of the writable buffers in the descriptor chain. That would be
satisfactory for this rng driver, since there is only one buffer being
used, but if there is more than one buffer then the device driver will
still need to do checks as it accesses each of them. So it still feels
like the device driver's responsibility to do the checking, given the
current API.

> >   memcpy(ptr, buf, rsize);
> >   len -= rsize;
> >   ptr += rsize;
> > --
> > 2.35.1.1094.g7c7d902a7c-goog
> >
>
> Thanks,
>
> --
> Pierre

Re: [PATCH] squashfs: Fix compilation on big endian systems

[Pali Rohár]

On Thursday 07 April 2022 11:54:55 Miquel Raynal wrote:
> Hi Pali,
> 
> p...@kernel.org wrote on Thu, 7 Apr 2022 11:41:59 +0200:
> 
> > On Thursday 07 April 2022 09:54:21 Miquel Raynal wrote:
> > > Hi Pali,
> > > 
> > > p...@kernel.org wrote on Wed,  6 Apr 2022 23:31:53 +0200:
> > > 
> > > Would you mind explaining a little bit how this change fixes it? It
> > > does not look straightforward to me.  
> > 
> > Yes! I though that it is straightforward this change...
> > byteorder/little_endian.h defines cpu_to_le* macros for Little Endian
> > systems and byteorder/big_endian.h for Big Endian systems.
> > 
> > File asm/byteorder.h is then ARCH-specific and implements macros for the
> > current architecture (by including the correct header file).
> > 
> > So currently if you try to compile squashfs for big endian systems you
> > get compile error:
> > 
> >   In file included from ./arch/powerpc/include/asm/byteorder.h:82,
> >from include/linux/unaligned/access_ok.h:4,
> >from ./arch/powerpc/include/asm/unaligned.h:9,
> >from fs/squashfs/sqfs_filesystem.h:11,
> >from fs/squashfs/sqfs_dir.c:16:
> >   include/linux/byteorder/big_endian.h:34: warning: "__cpu_to_le32" 
> > redefined
> >#define __cpu_to_le32(x) ((__force __le32)__swab32((x)))
> > 
> >   In file included from fs/squashfs/sqfs_dir.c:10:
> >   include/linux/byteorder/little_endian.h:34: note: this is the location of 
> > the previous definition
> >#define __cpu_to_le32(x) ((__force __le32)(__u32)(x))
> > 
> > Or:
> > 
> >   In file included from fs/squashfs/sqfs.c:14:
> >   include/linux/byteorder/little_endian.h:89:21: error: redefinition of 
> > ‘__be16_to_cpup’
> >static inline __u16 __be16_to_cpup(const __be16 *p)
> >^~
> >   In file included from ./arch/powerpc/include/asm/byteorder.h:82,
> >from include/linux/unaligned/access_ok.h:4,
> >from ./arch/powerpc/include/asm/unaligned.h:9,
> >from fs/squashfs/sqfs.c:10:
> >   include/linux/byteorder/big_endian.h:89:21: note: previous definition of 
> > ‘__be16_to_cpup’ was here
> >static inline __u16 __be16_to_cpup(const __be16 *p)
> >^~
> > 
> > As some header files include correct asm/byteorder.h file and this
> > squashfs includes additional little_endian.h.
> 
> Great, thanks for the thorough explanation. Based on what you said,
> wouldn't it be cleaner to just get rid of the little_endian.h include
> rather than also use the ARCH specific byteorder.h header?

I think that this is not possible. squashfs code uses le16_to_cpu()
macro and its correct definition is provided only by arch specific
asm/byteorder.h.

> > 
> > > > Signed-off-by: Pali Rohár 
> > > > ---
> > > >  fs/squashfs/sqfs.c | 3 +--
> > > >  fs/squashfs/sqfs_dir.c | 3 +--
> > > >  2 files changed, 2 insertions(+), 4 deletions(-)
> > > > 
> > > > diff --git a/fs/squashfs/sqfs.c b/fs/squashfs/sqfs.c
> > > > index 5d9c52af80ba..41cb811c1b32 100644
> > > > --- a/fs/squashfs/sqfs.c
> > > > +++ b/fs/squashfs/sqfs.c
> > > > @@ -11,8 +11,7 @@
> > > >  #include 
> > > >  #include 
> > > >  #include 
> > > > -#include 
> > > > -#include 
> > > > +#include 
> > > >  #include 
> > > >  #include 
> > > >  #include 
> > > > diff --git a/fs/squashfs/sqfs_dir.c b/fs/squashfs/sqfs_dir.c
> > > > index a265b98fe685..ed83c90682ff 100644
> > > > --- a/fs/squashfs/sqfs_dir.c
> > > > +++ b/fs/squashfs/sqfs_dir.c
> > > > @@ -7,8 +7,7 @@
> > > >  
> > > >  #include 
> > > >  #include 
> > > > -#include 
> > > > -#include 
> > > > +#include 
> > > >  #include 
> > > >  #include 
> > > >  #include   
> > > 
> > > Cheers,
> > > Miquèl  
> 
> 
> Thanks,
> Miquèl

Re: [PATCH] squashfs: Fix compilation on big endian systems

[Miquel Raynal]

Hi Pali,

p...@kernel.org wrote on Thu, 7 Apr 2022 11:41:59 +0200:

> On Thursday 07 April 2022 09:54:21 Miquel Raynal wrote:
> > Hi Pali,
> > 
> > p...@kernel.org wrote on Wed,  6 Apr 2022 23:31:53 +0200:
> > 
> > Would you mind explaining a little bit how this change fixes it? It
> > does not look straightforward to me.  
> 
> Yes! I though that it is straightforward this change...
> byteorder/little_endian.h defines cpu_to_le* macros for Little Endian
> systems and byteorder/big_endian.h for Big Endian systems.
> 
> File asm/byteorder.h is then ARCH-specific and implements macros for the
> current architecture (by including the correct header file).
> 
> So currently if you try to compile squashfs for big endian systems you
> get compile error:
> 
>   In file included from ./arch/powerpc/include/asm/byteorder.h:82,
>from include/linux/unaligned/access_ok.h:4,
>from ./arch/powerpc/include/asm/unaligned.h:9,
>from fs/squashfs/sqfs_filesystem.h:11,
>from fs/squashfs/sqfs_dir.c:16:
>   include/linux/byteorder/big_endian.h:34: warning: "__cpu_to_le32" redefined
>#define __cpu_to_le32(x) ((__force __le32)__swab32((x)))
> 
>   In file included from fs/squashfs/sqfs_dir.c:10:
>   include/linux/byteorder/little_endian.h:34: note: this is the location of 
> the previous definition
>#define __cpu_to_le32(x) ((__force __le32)(__u32)(x))
> 
> Or:
> 
>   In file included from fs/squashfs/sqfs.c:14:
>   include/linux/byteorder/little_endian.h:89:21: error: redefinition of 
> ‘__be16_to_cpup’
>static inline __u16 __be16_to_cpup(const __be16 *p)
>^~
>   In file included from ./arch/powerpc/include/asm/byteorder.h:82,
>from include/linux/unaligned/access_ok.h:4,
>from ./arch/powerpc/include/asm/unaligned.h:9,
>from fs/squashfs/sqfs.c:10:
>   include/linux/byteorder/big_endian.h:89:21: note: previous definition of 
> ‘__be16_to_cpup’ was here
>static inline __u16 __be16_to_cpup(const __be16 *p)
>^~
> 
> As some header files include correct asm/byteorder.h file and this
> squashfs includes additional little_endian.h.

Great, thanks for the thorough explanation. Based on what you said,
wouldn't it be cleaner to just get rid of the little_endian.h include
rather than also use the ARCH specific byteorder.h header?

> 
> > > Signed-off-by: Pali Rohár 
> > > ---
> > >  fs/squashfs/sqfs.c | 3 +--
> > >  fs/squashfs/sqfs_dir.c | 3 +--
> > >  2 files changed, 2 insertions(+), 4 deletions(-)
> > > 
> > > diff --git a/fs/squashfs/sqfs.c b/fs/squashfs/sqfs.c
> > > index 5d9c52af80ba..41cb811c1b32 100644
> > > --- a/fs/squashfs/sqfs.c
> > > +++ b/fs/squashfs/sqfs.c
> > > @@ -11,8 +11,7 @@
> > >  #include 
> > >  #include 
> > >  #include 
> > > -#include 
> > > -#include 
> > > +#include 
> > >  #include 
> > >  #include 
> > >  #include 
> > > diff --git a/fs/squashfs/sqfs_dir.c b/fs/squashfs/sqfs_dir.c
> > > index a265b98fe685..ed83c90682ff 100644
> > > --- a/fs/squashfs/sqfs_dir.c
> > > +++ b/fs/squashfs/sqfs_dir.c
> > > @@ -7,8 +7,7 @@
> > >  
> > >  #include 
> > >  #include 
> > > -#include 
> > > -#include 
> > > +#include 
> > >  #include 
> > >  #include 
> > >  #include   
> > 
> > Cheers,
> > Miquèl  


Thanks,
Miquèl

[PATCH 11/11] RFC: Hack dlmalloc to poison memory

[Andrew Scull]

This is a hugely ugly hack to poison and unpoison memory allocated by
dlmalloc. It wraps every access dlmalloc makes to the metadata breifly
allow it access, taking care not to then poison the parts of the record
which overlap.

The result is very small redzones between the allocations, which has
limted value but has able to spot immediate buffer overruns.

The instrumentation is extremely intrusive and would be benefited by
more intrusions to increase redzone sizes etc.

Signed-off-by: Andrew Scull 
---
 common/dlmalloc.c | 284 --
 include/compiler.h|   1 +
 include/linux/types.h |   1 +
 3 files changed, 245 insertions(+), 41 deletions(-)

diff --git a/common/dlmalloc.c b/common/dlmalloc.c
index 11729e8c85..614f004579 100644
--- a/common/dlmalloc.c
+++ b/common/dlmalloc.c
@@ -8,6 +8,8 @@
  * as file malloc-2.6.6.c.
  */
 
+#define DEBUG
+
 #include 
 #include 
 #include 
@@ -16,6 +18,8 @@
 #define DEBUG
 #endif
 
+#include 
+
 #include 
 #include 
 
@@ -31,6 +35,17 @@ void malloc_stats();
 
 DECLARE_GLOBAL_DATA_PTR;
 
+/*
+#undef ASAN_POISON_MEMORY_REGION
+#define ASAN_POISON_MEMORY_REGION(p, s) do { \
+if ((uintptr_t)p == 0x150200c0) { \
+printf("size %lx\n", s); \
+*(int*)NULL = 9; \
+} \
+__asan_poison_memory_region(p, s); \
+} while (0)
+*/
+
 /*
   Emulation of sbrk for WIN32
   All code within the ifdef WIN32 is untested by me.
@@ -409,12 +424,26 @@ nextchunk-> 
+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
 
 /* Ptr to next physical malloc_chunk. */
 
-#define next_chunk(p) ((mchunkptr)( ((char*)(p)) + ((p)->size & ~PREV_INUSE) ))
+#define _next_chunk(p) ((mchunkptr)( ((char*)(p)) + ((p)->size & ~PREV_INUSE) 
))
+#define next_chunk(p) ({ \
+mchunkptr _ptr = (p); \
+ASAN_UNPOISON_MEMORY_REGION(((char*)_ptr) + SIZE_SZ, SIZE_SZ); \
+mchunkptr _ret = _next_chunk(_ptr); \
+ASAN_POISON_MEMORY_REGION(((char*)_ptr) + SIZE_SZ, SIZE_SZ); \
+_ret; \
+})
 
 /* Ptr to previous physical malloc_chunk */
 
-#define prev_chunk(p)\
+#define _prev_chunk(p)\
((mchunkptr)( ((char*)(p)) - ((p)->prev_size) ))
+#define prev_chunk(p) ({ \
+mchunkptr _ptr = (p); \
+ASAN_UNPOISON_MEMORY_REGION(_ptr, SIZE_SZ); \
+mchunkptr _ret = _prev_chunk(_ptr); \
+ASAN_POISON_MEMORY_REGION(_ptr, SIZE_SZ); \
+_ret; \
+})
 
 
 /* Treat space at ptr + offset as a chunk */
@@ -430,35 +459,102 @@ nextchunk-> 
+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
 
 /* extract p's inuse bit */
 
-#define inuse(p)\
+#define _inuse(p)\
 mchunkptr)(((char*)(p))+((p)->size & ~PREV_INUSE)))->size) & PREV_INUSE)
+#define inuse(p) ({ \
+mchunkptr _p = (p); \
+ASAN_UNPOISON_MEMORY_REGION(((char*)_p) + SIZE_SZ, SIZE_SZ); \
+mchunkptr _ptr = ((mchunkptr)(((char*)_p)+(_p->size & ~PREV_INUSE))); \
+ASAN_UNPOISON_MEMORY_REGION(((char*)_ptr) + SIZE_SZ, SIZE_SZ); \
+INTERNAL_SIZE_T _ret = _inuse(_p); \
+ASAN_POISON_MEMORY_REGION(((char*)_ptr) + SIZE_SZ, SIZE_SZ); \
+ASAN_POISON_MEMORY_REGION(((char*)_p) + SIZE_SZ, SIZE_SZ); \
+_ret; \
+})
 
 /* extract inuse bit of previous chunk */
 
-#define prev_inuse(p)  ((p)->size & PREV_INUSE)
+#define _prev_inuse(p)  ((p)->size & PREV_INUSE)
+#define prev_inuse(p) ({ \
+mchunkptr _ptr = (p); \
+ASAN_UNPOISON_MEMORY_REGION(((char*)_ptr) + SIZE_SZ, SIZE_SZ); \
+INTERNAL_SIZE_T _ret = _prev_inuse(_ptr); \
+ASAN_POISON_MEMORY_REGION(((char*)_ptr) + SIZE_SZ, SIZE_SZ); \
+_ret; \
+})
 
 /* check for mmap()'ed chunk */
 
-#define chunk_is_mmapped(p) ((p)->size & IS_MMAPPED)
+#define _chunk_is_mmapped(p) ((p)->size & IS_MMAPPED)
+#define chunk_is_mmapped(p) ({ \
+mchunkptr _ptr = (p); \
+ASAN_UNPOISON_MEMORY_REGION(((char*)_ptr) + SIZE_SZ, SIZE_SZ); \
+INTERNAL_SIZE_T _ret = _chunk_is_mmapped(_ptr); \
+ASAN_POISON_MEMORY_REGION(((char*)_ptr) + SIZE_SZ, SIZE_SZ); \
+_ret; \
+})
 
 /* set/clear chunk as in use without otherwise disturbing */
 
-#define set_inuse(p)\
+#define _set_inuse(p)\
 ((mchunkptr)(((char*)(p)) + ((p)->size & ~PREV_INUSE)))->size |= PREV_INUSE
-
-#define clear_inuse(p)\
+#define set_inuse(p, s) ({ \
+mchunkptr _p = (p); \
+ASAN_UNPOISON_MEMORY_REGION(((char*)_p) + SIZE_SZ, SIZE_SZ); \
+mchunkptr _ptr = ((mchunkptr)(((char*)_p)+(_p->size & ~PREV_INUSE))); \
+ASAN_UNPOISON_MEMORY_REGION(((char*)_ptr) + SIZE_SZ, SIZE_SZ); \
+_set_inuse(_p, (s)); \
+ASAN_POISON_MEMORY_REGION(((char*)_ptr) + SIZE_SZ, SIZE_SZ); \
+ASAN_POISON_MEMORY_REGION(((char*)_p) + SIZE_SZ, SIZE_SZ); \
+})
+
+#define _clear_inuse(p)\
 ((mchunkptr)(((char*)(p)) + ((p)->size & ~PREV_INUSE)))->size &= ~(PREV_INUSE)
+#define clear_inuse(p, s) ({ \
+__typeof__(p) _p = (p); \
+

Re: [PATCH] squashfs: Fix compilation on big endian systems

[Pali Rohár]

On Thursday 07 April 2022 09:54:21 Miquel Raynal wrote:
> Hi Pali,
> 
> p...@kernel.org wrote on Wed,  6 Apr 2022 23:31:53 +0200:
> 
> Would you mind explaining a little bit how this change fixes it? It
> does not look straightforward to me.

Yes! I though that it is straightforward this change...
byteorder/little_endian.h defines cpu_to_le* macros for Little Endian
systems and byteorder/big_endian.h for Big Endian systems.

File asm/byteorder.h is then ARCH-specific and implements macros for the
current architecture (by including the correct header file).

So currently if you try to compile squashfs for big endian systems you
get compile error:

  In file included from ./arch/powerpc/include/asm/byteorder.h:82,
   from include/linux/unaligned/access_ok.h:4,
   from ./arch/powerpc/include/asm/unaligned.h:9,
   from fs/squashfs/sqfs_filesystem.h:11,
   from fs/squashfs/sqfs_dir.c:16:
  include/linux/byteorder/big_endian.h:34: warning: "__cpu_to_le32" redefined
   #define __cpu_to_le32(x) ((__force __le32)__swab32((x)))

  In file included from fs/squashfs/sqfs_dir.c:10:
  include/linux/byteorder/little_endian.h:34: note: this is the location of the 
previous definition
   #define __cpu_to_le32(x) ((__force __le32)(__u32)(x))

Or:

  In file included from fs/squashfs/sqfs.c:14:
  include/linux/byteorder/little_endian.h:89:21: error: redefinition of 
‘__be16_to_cpup’
   static inline __u16 __be16_to_cpup(const __be16 *p)
   ^~
  In file included from ./arch/powerpc/include/asm/byteorder.h:82,
   from include/linux/unaligned/access_ok.h:4,
   from ./arch/powerpc/include/asm/unaligned.h:9,
   from fs/squashfs/sqfs.c:10:
  include/linux/byteorder/big_endian.h:89:21: note: previous definition of 
‘__be16_to_cpup’ was here
   static inline __u16 __be16_to_cpup(const __be16 *p)
   ^~

As some header files include correct asm/byteorder.h file and this
squashfs includes additional little_endian.h.

> > Signed-off-by: Pali Rohár 
> > ---
> >  fs/squashfs/sqfs.c | 3 +--
> >  fs/squashfs/sqfs_dir.c | 3 +--
> >  2 files changed, 2 insertions(+), 4 deletions(-)
> > 
> > diff --git a/fs/squashfs/sqfs.c b/fs/squashfs/sqfs.c
> > index 5d9c52af80ba..41cb811c1b32 100644
> > --- a/fs/squashfs/sqfs.c
> > +++ b/fs/squashfs/sqfs.c
> > @@ -11,8 +11,7 @@
> >  #include 
> >  #include 
> >  #include 
> > -#include 
> > -#include 
> > +#include 
> >  #include 
> >  #include 
> >  #include 
> > diff --git a/fs/squashfs/sqfs_dir.c b/fs/squashfs/sqfs_dir.c
> > index a265b98fe685..ed83c90682ff 100644
> > --- a/fs/squashfs/sqfs_dir.c
> > +++ b/fs/squashfs/sqfs_dir.c
> > @@ -7,8 +7,7 @@
> >  
> >  #include 
> >  #include 
> > -#include 
> > -#include 
> > +#include 
> >  #include 
> >  #include 
> >  #include 
> 
> Cheers,
> Miquèl

[PATCH 07/11] sandbox: Decouple program entry from sandbox init

[Andrew Scull]

Move the program's entry point to os.c, in preparation for a separate
fuzzing entry point to be added.

Signed-off-by: Andrew Scull 
---
 arch/sandbox/cpu/os.c   |  6 ++
 arch/sandbox/cpu/start.c|  2 +-
 arch/sandbox/include/asm/main.h | 18 ++
 3 files changed, 25 insertions(+), 1 deletion(-)
 create mode 100644 arch/sandbox/include/asm/main.h

diff --git a/arch/sandbox/cpu/os.c b/arch/sandbox/cpu/os.c
index 72a72029f2..5ea4135741 100644
--- a/arch/sandbox/cpu/os.c
+++ b/arch/sandbox/cpu/os.c
@@ -27,6 +27,7 @@
 #include 
 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -1000,3 +1001,8 @@ void os_relaunch(char *argv[])
execv(argv[0], argv);
os_exit(1);
 }
+
+int main(int argc, char *argv[])
+{
+   return sandbox_main(argc, argv);
+}
diff --git a/arch/sandbox/cpu/start.c b/arch/sandbox/cpu/start.c
index 5cb47e1156..ba67f4fbd7 100644
--- a/arch/sandbox/cpu/start.c
+++ b/arch/sandbox/cpu/start.c
@@ -451,7 +451,7 @@ void sandbox_reset(void)
os_relaunch(os_argv);
 }
 
-int main(int argc, char *argv[])
+int sandbox_main(int argc, char *argv[])
 {
struct sandbox_state *state;
void * text_base;
diff --git a/arch/sandbox/include/asm/main.h b/arch/sandbox/include/asm/main.h
new file mode 100644
index 00..7a2f0d3a8d
--- /dev/null
+++ b/arch/sandbox/include/asm/main.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2022 Google, Inc.
+ * Written by Andrew Scull 
+ */
+
+#ifndef __ASM_SANDBOX_MAIN_H
+#define __ASM_SANDBOX_MAIN_H
+
+/**
+ * sandbox_main() - main entrypoint for sandbox
+ *
+ * @argc:  the number of arguments passed to the program
+ * @argv:  array of argc+1 pointers, of which the last one is null
+ */
+int sandbox_main(int argc, char *argv[]);
+
+#endif /* __ASM_SANDBOX_MAIN_H */
-- 
2.35.1.1094.g7c7d902a7c-goog

[PATCH 09/11] sandbox: Implement fuzzing engine driver

[Andrew Scull]

Add a fuzzing engine driver for the sandbox to take inputs from
libfuzzer and expose them to the fuzz tests.

Signed-off-by: Andrew Scull 
---
 arch/Kconfig  |  2 ++
 arch/sandbox/dts/test.dts |  4 +++
 drivers/fuzzing_engine/Kconfig| 11 ++
 drivers/fuzzing_engine/Makefile   |  1 +
 .../fuzzing_engine/sandbox_fuzzing_engine.c   | 35 +++
 5 files changed, 53 insertions(+)
 create mode 100644 drivers/fuzzing_engine/sandbox_fuzzing_engine.c

diff --git a/arch/Kconfig b/arch/Kconfig
index e6191446a3..6320a98db6 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -135,6 +135,7 @@ config SANDBOX
select BZIP2
select CMD_POWEROFF
select DM
+   select DM_FUZZING_ENGINE
select DM_GPIO
select DM_I2C
select DM_KEYBOARD
@@ -170,6 +171,7 @@ config SANDBOX
imply CRC32_VERIFY
imply FAT_WRITE
imply FIRMWARE
+   imply FUZZING_ENGINE_SANDBOX
imply HASH_VERIFY
imply LZMA
imply TEE
diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts
index 48ca3e1e47..848329fda5 100644
--- a/arch/sandbox/dts/test.dts
+++ b/arch/sandbox/dts/test.dts
@@ -71,6 +71,10 @@
};
};
 
+   fuzzing-engine {
+   compatible = "sandbox,sandbox-fuzzing-engine";
+   };
+
reboot-mode0 {
compatible = "reboot-mode-gpio";
gpios = <_c 0 GPIO_ACTIVE_HIGH>, <_c 1 
GPIO_ACTIVE_HIGH>;
diff --git a/drivers/fuzzing_engine/Kconfig b/drivers/fuzzing_engine/Kconfig
index f405fc75e8..6311385222 100644
--- a/drivers/fuzzing_engine/Kconfig
+++ b/drivers/fuzzing_engine/Kconfig
@@ -4,3 +4,14 @@ config DM_FUZZING_ENGINE
help
  Enable driver model for fuzzing engine devices. This interface is
  used to get fuzzing inputs from a fuzzing engine.
+
+if DM_FUZZING_ENGINE
+
+config FUZZING_ENGINE_SANDBOX
+   bool "Sanbox fuzzing engine"
+   depends on SANDBOX
+   default y
+   help
+ Enable fuzzing engine for sandbox.
+
+endif
diff --git a/drivers/fuzzing_engine/Makefile b/drivers/fuzzing_engine/Makefile
index acd894999c..073743ba94 100644
--- a/drivers/fuzzing_engine/Makefile
+++ b/drivers/fuzzing_engine/Makefile
@@ -5,3 +5,4 @@
 #
 
 obj-$(CONFIG_DM_FUZZING_ENGINE) += fuzzing_engine-uclass.o
+obj-$(CONFIG_FUZZING_ENGINE_SANDBOX) += sandbox_fuzzing_engine.o
diff --git a/drivers/fuzzing_engine/sandbox_fuzzing_engine.c 
b/drivers/fuzzing_engine/sandbox_fuzzing_engine.c
new file mode 100644
index 00..4d187deaa4
--- /dev/null
+++ b/drivers/fuzzing_engine/sandbox_fuzzing_engine.c
@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2022 Google, Inc.
+ * Written by Andrew Scull 
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+static int get_input(struct udevice *dev,
+const uint8_t **data,
+size_t *size)
+{
+   return sandbox_fuzzing_engine_get_input(data, size);
+}
+
+static const struct dm_fuzzing_engine_ops sandbox_fuzzing_engine_ops = {
+   .get_input = get_input,
+};
+
+static const struct udevice_id sandbox_fuzzing_engine_match[] = {
+   {
+   .compatible = "sandbox,sandbox-fuzzing-engine",
+   },
+   {},
+};
+
+U_BOOT_DRIVER(sandbox_fuzzing_engine) = {
+   .name = "sandbox-fuzzing-engine",
+   .id = UCLASS_FUZZING_ENGINE,
+   .of_match = sandbox_fuzzing_engine_match,
+   .ops = _fuzzing_engine_ops,
+};
-- 
2.35.1.1094.g7c7d902a7c-goog

[PATCH 03/11] linker_lists: Rename sections to remove . prefix

[Andrew Scull]

Rename the sections used to implement linker lists so they begin with
'__u_boot_list' rather than '.u_boot_list'. The double underscore at the
start is still distinct from the single underscore used by the symbol
names.

Having a '.' in the section names conflicts with clang's ASAN
instrumentation which tries to add redzones between the linker list
elements, causing expected accesses to fail. However, clang doesn't try
to add redzones to user sections, which are names with all alphanumeric
and underscore characters.

Signed-off-by: Andrew Scull 
---
 arch/arc/cpu/u-boot.lds   |  4 ++--
 arch/arm/config.mk|  4 ++--
 arch/arm/cpu/arm926ejs/sunxi/u-boot-spl.lds   |  4 ++--
 arch/arm/cpu/armv7/sunxi/u-boot-spl.lds   |  4 ++--
 arch/arm/cpu/armv8/u-boot-spl.lds |  4 ++--
 arch/arm/cpu/armv8/u-boot.lds |  4 ++--
 arch/arm/cpu/u-boot-spl.lds   |  4 ++--
 arch/arm/cpu/u-boot.lds   |  6 ++---
 arch/arm/mach-at91/arm926ejs/u-boot-spl.lds   |  2 +-
 arch/arm/mach-at91/armv7/u-boot-spl.lds   |  2 +-
 arch/arm/mach-omap2/u-boot-spl.lds|  4 ++--
 arch/arm/mach-orion5x/u-boot-spl.lds  |  4 ++--
 arch/arm/mach-rockchip/u-boot-tpl-v8.lds  |  4 ++--
 arch/arm/mach-zynq/u-boot-spl.lds |  4 ++--
 arch/arm/mach-zynq/u-boot.lds |  4 ++--
 arch/m68k/cpu/u-boot.lds  |  4 ++--
 arch/microblaze/cpu/u-boot-spl.lds|  4 ++--
 arch/microblaze/cpu/u-boot.lds|  4 ++--
 arch/mips/config.mk   |  2 +-
 arch/mips/cpu/u-boot-spl.lds  |  4 ++--
 arch/mips/cpu/u-boot.lds  |  4 ++--
 arch/nds32/cpu/n1213/u-boot.lds   |  4 ++--
 arch/nios2/cpu/u-boot.lds |  4 ++--
 arch/powerpc/cpu/mpc83xx/u-boot.lds   |  4 ++--
 arch/powerpc/cpu/mpc85xx/u-boot-nand.lds  |  4 ++--
 arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds  |  4 ++--
 arch/powerpc/cpu/mpc85xx/u-boot-spl.lds   |  4 ++--
 arch/powerpc/cpu/mpc85xx/u-boot.lds   |  4 ++--
 arch/riscv/cpu/u-boot-spl.lds |  4 ++--
 arch/riscv/cpu/u-boot.lds |  4 ++--
 arch/sandbox/config.mk|  4 ++--
 arch/sandbox/cpu/u-boot-spl.lds   |  4 ++--
 arch/sandbox/cpu/u-boot.lds   |  4 ++--
 arch/sh/cpu/u-boot.lds|  4 ++--
 arch/x86/cpu/u-boot-64.lds|  6 ++---
 arch/x86/cpu/u-boot-spl.lds   |  6 ++---
 arch/x86/cpu/u-boot.lds   |  6 ++---
 arch/x86/lib/elf_ia32_efi.lds |  4 ++--
 arch/x86/lib/elf_x86_64_efi.lds   |  4 ++--
 arch/xtensa/cpu/u-boot.lds|  2 +-
 arch/xtensa/include/asm/ldscript.h|  4 ++--
 board/compulab/cm_t335/u-boot.lds |  4 ++--
 board/cssi/MCR3000/u-boot.lds |  4 ++--
 .../davinci/da8xxevm/u-boot-spl-da850evm.lds  |  2 +-
 board/qualcomm/dragonboard820c/u-boot.lds |  4 ++--
 board/samsung/common/exynos-uboot-spl.lds |  4 ++--
 board/synopsys/iot_devkit/u-boot.lds  |  4 ++--
 board/ti/am335x/u-boot.lds|  4 ++--
 board/vscom/baltos/u-boot.lds |  4 ++--
 doc/api/linker_lists.rst  | 22 +--
 doc/develop/commands.rst  |  4 ++--
 doc/develop/driver-model/of-plat.rst  |  4 ++--
 include/linker_lists.h| 18 +++
 53 files changed, 121 insertions(+), 121 deletions(-)

diff --git a/arch/arc/cpu/u-boot.lds b/arch/arc/cpu/u-boot.lds
index e12145c768..9f2973da65 100644
--- a/arch/arc/cpu/u-boot.lds
+++ b/arch/arc/cpu/u-boot.lds
@@ -39,8 +39,8 @@ SECTIONS
}
 
. = ALIGN(4);
-   .u_boot_list : {
-   KEEP(*(SORT(.u_boot_list*)));
+   __u_boot_list : {
+   KEEP(*(SORT(__u_boot_list*)));
}
 
. = ALIGN(4);
diff --git a/arch/arm/config.mk b/arch/arm/config.mk
index b107b1af27..b3548ce243 100644
--- a/arch/arm/config.mk
+++ b/arch/arm/config.mk
@@ -141,11 +141,11 @@ endif
 # limit ourselves to the sections we want in the .bin.
 ifdef CONFIG_ARM64
 OBJCOPYFLAGS += -j .text -j .secure_text -j .secure_data -j .rodata -j .data \
-   -j .u_boot_list -j .rela.dyn -j .got -j .got.plt \
+   -j __u_boot_list -j .rela.dyn -j .got -j .got.plt \
-j .binman_sym_table -j .text_rest
 else
 OBJCOPYFLAGS += -j .text -j .secure_text -j .secure_data -j .rodata -j .hash \
-   -j .data -j .got -j .got.plt -j .u_boot_list -j .rel.dyn \
+   -j .data -j .got -j .got.plt -j __u_boot_list -j .rel.dyn \
-j .binman_sym_table -j .text_rest
 endif
 
diff --git a/arch/arm/cpu/arm926ejs/sunxi/u-boot-spl.lds 
b/arch/arm/cpu/arm926ejs/sunxi/u-boot-spl.lds
index 9a000ac5d3..c108736811 100644

[PATCH 08/11] sandbox: Add libfuzzer integration

[Andrew Scull]

Add an implementation of LLVMFuzzerTestOneInput() that starts the
sandbox on a secondary thread and exposes a function to synchronize the
generation of fuzzing inputs with their consumption by the sandbox.

Signed-off-by: Andrew Scull 
---
 arch/sandbox/config.mk|  3 +
 arch/sandbox/cpu/os.c | 70 +++
 arch/sandbox/include/asm/fuzzing_engine.h | 25 
 3 files changed, 98 insertions(+)
 create mode 100644 arch/sandbox/include/asm/fuzzing_engine.h

diff --git a/arch/sandbox/config.mk b/arch/sandbox/config.mk
index d7ce66fb6c..5fbe1f50e3 100644
--- a/arch/sandbox/config.mk
+++ b/arch/sandbox/config.mk
@@ -19,6 +19,9 @@ SANITIZERS :=
 ifdef CONFIG_ASAN
 SANITIZERS += -fsanitize=address
 endif
+ifdef CONFIG_FUZZ
+SANITIZERS += -fsanitize=fuzzer
+endif
 KBUILD_CFLAGS  += $(SANITIZERS)
 
 cmd_u-boot__ = $(CC) -o $@ -Wl,-T u-boot.lds $(u-boot-init) \
diff --git a/arch/sandbox/cpu/os.c b/arch/sandbox/cpu/os.c
index 5ea4135741..cd45d7b6b6 100644
--- a/arch/sandbox/cpu/os.c
+++ b/arch/sandbox/cpu/os.c
@@ -8,6 +8,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -26,6 +27,7 @@
 #include 
 #include 
 
+#include 
 #include 
 #include 
 #include 
@@ -1002,7 +1004,75 @@ void os_relaunch(char *argv[])
os_exit(1);
 }
 
+
+#ifdef CONFIG_FUZZ
+static void *fuzzer_thread(void * ptr)
+{
+   char cmd[64];
+   char *argv[5] = {"./u-boot", "-T", "-c", cmd, NULL};
+   const char *fuzz_test;
+
+   /* Find which test to run from an environment variable. */
+   fuzz_test = getenv("UBOOT_SB_FUZZ_TEST");
+   if (!fuzz_test)
+   os_abort();
+
+   snprintf(cmd, sizeof(cmd), "fuzz %s", fuzz_test);
+
+   sandbox_main(4, argv);
+   os_abort();
+   return NULL;
+}
+
+static bool fuzzer_initialized = false;
+static pthread_mutex_t fuzzer_mutex = PTHREAD_MUTEX_INITIALIZER;
+static pthread_cond_t fuzzer_cond = PTHREAD_COND_INITIALIZER;
+static const uint8_t *fuzzer_data;
+static size_t fuzzer_size;
+
+int sandbox_fuzzing_engine_get_input(const uint8_t **data, size_t *size)
+{
+   if (!fuzzer_initialized)
+   return -ENOSYS;
+
+   /* Tell the main thread we need new inputs then wait for them. */
+   pthread_mutex_lock(_mutex);
+   pthread_cond_signal(_cond);
+   pthread_cond_wait(_cond, _mutex);
+   *data = fuzzer_data;
+   *size = fuzzer_size;
+   pthread_mutex_unlock(_mutex);
+   return 0;
+}
+
+int LLVMFuzzerTestOneInput(const uint8_t *data, size_t size)
+{
+   static pthread_t tid;
+
+   pthread_mutex_lock(_mutex);
+
+   /* Initialize the sandbox on another thread. */
+   if (!fuzzer_initialized) {
+   fuzzer_initialized = true;
+   if (pthread_create(, NULL, fuzzer_thread, NULL))
+   os_abort();
+   pthread_cond_wait(_cond, _mutex);
+   }
+
+   /* Hand over the input. */
+   fuzzer_data = data;
+   fuzzer_size = size;
+   pthread_cond_signal(_cond);
+
+   /* Wait for the inputs to be finished with. */
+   pthread_cond_wait(_cond, _mutex);
+   pthread_mutex_unlock(_mutex);
+
+   return 0;
+}
+#else
 int main(int argc, char *argv[])
 {
return sandbox_main(argc, argv);
 }
+#endif
diff --git a/arch/sandbox/include/asm/fuzzing_engine.h 
b/arch/sandbox/include/asm/fuzzing_engine.h
new file mode 100644
index 00..cf6396363b
--- /dev/null
+++ b/arch/sandbox/include/asm/fuzzing_engine.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2022 Google, Inc.
+ * Written by Andrew Scull 
+ */
+
+#ifndef __ASM_FUZZING_ENGINE_H
+#define __ASM_FUZZING_ENGINE_H
+
+/** Function to get fuzzing engine input data. */
+/**
+ * sandbox_fuzzing_engine_get_input() - get an input from the sandbox fuzzing
+ * engine
+ *
+ * The function will return a pointer to the input data and the size of the
+ * data pointed to. The pointer will remain valid until the next invocation of
+ * this function.
+ *
+ * @data:  output pointer to input data
+ * @size   output size of input data
+ * Return: 0 if OK, -ve on error
+ */
+int sandbox_fuzzing_engine_get_input(const uint8_t **data, size_t *size);
+
+#endif /* __ASM_FUZZING_ENGINE_H */
-- 
2.35.1.1094.g7c7d902a7c-goog

[PATCH 06/11] test: fuzz: Add framework for fuzzing

[Andrew Scull]

Add the basic infrastructure for declaring fuzz tests and a command to
invoke them.

Signed-off-by: Andrew Scull 
---
 Kconfig  |  8 +
 include/test/fuzz.h  | 51 +++
 test/Makefile|  1 +
 test/fuzz/Makefile   |  7 
 test/fuzz/cmd_fuzz.c | 82 
 5 files changed, 149 insertions(+)
 create mode 100644 include/test/fuzz.h
 create mode 100644 test/fuzz/Makefile
 create mode 100644 test/fuzz/cmd_fuzz.c

diff --git a/Kconfig b/Kconfig
index ae7e92611d..ce0a69d6aa 100644
--- a/Kconfig
+++ b/Kconfig
@@ -144,6 +144,14 @@ config ASAN
  Enables AddressSanitizer to discover out-of-bounds accesses,
  use-after-free, double-free and memory leaks.
 
+config FUZZ
+   bool "Enable fuzzing"
+   depends on DM_FUZZING_ENGINE
+   select ASAN
+   help
+ Enables the fuzzing infrastructure to generate fuzzing data and run
+  fuzz tests.
+
 config CC_HAS_ASM_INLINE
def_bool $(success,echo 'void foo(void) { asm inline (""); }' | $(CC) 
-x c - -c -o /dev/null)
 
diff --git a/include/test/fuzz.h b/include/test/fuzz.h
new file mode 100644
index 00..d4c57540eb
--- /dev/null
+++ b/include/test/fuzz.h
@@ -0,0 +1,51 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2022 Google, Inc.
+ * Written by Andrew Scull 
+ */
+
+#ifndef __TEST_FUZZ_H
+#define __TEST_FUZZ_H
+
+#include 
+#include 
+
+/**
+ * struct fuzz_test - Information about a fuzz test
+ *
+ * @name: Name of fuzz test
+ * @func: Function to call to perform fuzz test on an input
+ * @flags: Flags indicate pre-conditions for fuzz test
+ */
+struct fuzz_test {
+   const char *name;
+   int (*func)(const uint8_t * data, size_t size);
+   int flags;
+};
+
+/**
+ * FUZZ_TEST() - register a fuzz test
+ *
+ * The fuzz test function must return 0 as other values are reserved for future
+ * use.
+ *
+ * @_name: the name of the fuzz test function
+ * @_flags:an integer field that can be evaluated by the fuzzer
+ * implementation
+ */
+#define FUZZ_TEST(_name, _flags)   \
+   ll_entry_declare(struct fuzz_test, _name, fuzz_tests) = {   \
+   .name = #_name, \
+   .func = _name,  \
+   .flags = _flags,\
+   }
+
+/** Get the start of the list of fuzz tests */
+#define FUZZ_TEST_START() \
+   ll_entry_start(struct fuzz_test, fuzz_tests)
+
+/** Get the number of elements in the list of fuzz tests */
+#define FUZZ_TEST_COUNT() \
+   ll_entry_count(struct fuzz_test, fuzz_tests)
+
+#endif /* __TEST_FUZZ_H */
diff --git a/test/Makefile b/test/Makefile
index b3b2902e2e..bb2b0b5c73 100644
--- a/test/Makefile
+++ b/test/Makefile
@@ -16,6 +16,7 @@ obj-$(CONFIG_$(SPL_)CMDLINE) += cmd_ut.o
 obj-$(CONFIG_$(SPL_)CMDLINE) += command_ut.o
 obj-$(CONFIG_$(SPL_)UT_COMPRESSION) += compression.o
 obj-y += dm/
+obj-$(CONFIG_FUZZ) += fuzz/
 obj-$(CONFIG_$(SPL_)CMDLINE) += print_ut.o
 obj-$(CONFIG_$(SPL_)CMDLINE) += str_ut.o
 obj-$(CONFIG_UT_TIME) += time_ut.o
diff --git a/test/fuzz/Makefile b/test/fuzz/Makefile
new file mode 100644
index 00..03b497
--- /dev/null
+++ b/test/fuzz/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (c) 2022 Google, Inc.
+# Written by Andrew Scull 
+#
+
+obj-$(CONFIG_$(SPL_)CMDLINE) += cmd_fuzz.o
diff --git a/test/fuzz/cmd_fuzz.c b/test/fuzz/cmd_fuzz.c
new file mode 100644
index 00..0cc01dc199
--- /dev/null
+++ b/test/fuzz/cmd_fuzz.c
@@ -0,0 +1,82 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2022 Google, Inc.
+ * Written by Andrew Scull 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+static struct fuzz_test *find_fuzz_test(const char *name)
+{
+   struct fuzz_test *fuzzer = FUZZ_TEST_START();
+   size_t count = FUZZ_TEST_COUNT();
+   size_t i;
+
+   for (i = 0; i < count; ++i) {
+   if (strcmp(name, fuzzer->name) == 0)
+   return fuzzer;
+   ++fuzzer;
+   }
+
+   return NULL;
+}
+
+static struct udevice *find_fuzzing_engine(void)
+{
+   struct udevice *dev;
+
+   if (uclass_first_device(UCLASS_FUZZING_ENGINE, ))
+   return NULL;
+
+   return dev;
+}
+
+static int do_fuzz(struct cmd_tbl *cmdtp, int flag, int argc, char *const 
argv[])
+{
+   struct fuzz_test *fuzzer;
+   struct udevice *dev;
+
+   if (argc != 2)
+   return CMD_RET_USAGE;
+
+   fuzzer = find_fuzz_test(argv[1]);
+   if (!fuzzer) {
+   printf("Could not find fuzzer: %s\n", argv[1]);
+   return 1;
+   }
+
+   dev = find_fuzzing_engine();
+   if (!dev) {
+   puts("No fuzzing engine available\n");
+   return 1;
+   }
+
+   while (1) {
+

[PATCH 04/11] sandbox: Add support for Address Sanitizer

[Andrew Scull]

Add CONFIG_ASAN to build with the Address Sanitizer. This only works
with the sandbox so the config is likewise dependent. The resulting
executable will have ASAN instrumentation, including the leak detector
that can be disabled with the ASAN_OPTIONS environment variable:

   ASAN_OPTIONS=detect_leaks=0 ./u-boot

Since u-boot uses its own dlmalloc, dynamic allocations aren't
automatically instrumented, but stack variables and globals are.

Instrumentation could be added to dlmalloc to poison and unpoison memory
as it is allocated and deallocated, and to introduce redzones between
allocations. Alternatively, the sandbox may be able to play games with
the system allocator and somehow still keep the required memory
abstraction. No effort to address dynamic allocation is made by this
patch.

Signed-off-by: Andrew Scull 
---
 Kconfig   | 7 +++
 arch/sandbox/config.mk| 8 
 configs/sandbox_defconfig | 1 +
 3 files changed, 16 insertions(+)

diff --git a/Kconfig b/Kconfig
index 9dd9ec7f6d..ae7e92611d 100644
--- a/Kconfig
+++ b/Kconfig
@@ -137,6 +137,13 @@ config CC_COVERAGE
  Enabling this option will pass "--coverage" to gcc to compile
  and link code instrumented for coverage analysis.
 
+config ASAN
+   bool "Enable AddressSanitizer"
+   depends on SANDBOX
+   help
+ Enables AddressSanitizer to discover out-of-bounds accesses,
+ use-after-free, double-free and memory leaks.
+
 config CC_HAS_ASM_INLINE
def_bool $(success,echo 'void foo(void) { asm inline (""); }' | $(CC) 
-x c - -c -o /dev/null)
 
diff --git a/arch/sandbox/config.mk b/arch/sandbox/config.mk
index c42de2ff27..d7ce66fb6c 100644
--- a/arch/sandbox/config.mk
+++ b/arch/sandbox/config.mk
@@ -15,7 +15,14 @@ PLATFORM_LIBS += $(shell $(SDL_CONFIG) --libs)
 PLATFORM_CPPFLAGS += $(shell $(SDL_CONFIG) --cflags)
 endif
 
+SANITIZERS :=
+ifdef CONFIG_ASAN
+SANITIZERS += -fsanitize=address
+endif
+KBUILD_CFLAGS  += $(SANITIZERS)
+
 cmd_u-boot__ = $(CC) -o $@ -Wl,-T u-boot.lds $(u-boot-init) \
+   $(SANITIZERS) \
$(LTO_FINAL_LDFLAGS) \
-Wl,--whole-archive \
$(u-boot-main) \
@@ -24,6 +31,7 @@ cmd_u-boot__ = $(CC) -o $@ -Wl,-T u-boot.lds $(u-boot-init) \
$(PLATFORM_LIBS) -Wl,-Map -Wl,u-boot.map
 
 cmd_u-boot-spl = (cd $(obj) && $(CC) -o $(SPL_BIN) -Wl,-T u-boot-spl.lds \
+   $(SANITIZERS) \
$(LTO_FINAL_LDFLAGS) \
$(patsubst $(obj)/%,%,$(u-boot-spl-init)) \
-Wl,--whole-archive \
diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig
index 7ebeb89264..4862af07cd 100644
--- a/configs/sandbox_defconfig
+++ b/configs/sandbox_defconfig
@@ -1,3 +1,4 @@
+CONFIG_ASAN=y
 CONFIG_SYS_TEXT_BASE=0
 CONFIG_SYS_MALLOC_LEN=0x200
 CONFIG_NR_DRAM_BANKS=1
-- 
2.35.1.1094.g7c7d902a7c-goog

[PATCH 05/11] fuzzing_engine: Add fuzzing engine uclass

[Andrew Scull]

This new class of device will provide fuzzing inputs from a fuzzing
engine.

Signed-off-by: Andrew Scull 
---
 drivers/Kconfig   |  2 +
 drivers/Makefile  |  1 +
 drivers/fuzzing_engine/Kconfig|  6 +++
 drivers/fuzzing_engine/Makefile   |  7 +++
 .../fuzzing_engine/fuzzing_engine-uclass.c| 28 ++
 include/dm/uclass-id.h|  1 +
 include/fuzzing_engine.h  | 51 +++
 7 files changed, 96 insertions(+)
 create mode 100644 drivers/fuzzing_engine/Kconfig
 create mode 100644 drivers/fuzzing_engine/Makefile
 create mode 100644 drivers/fuzzing_engine/fuzzing_engine-uclass.c
 create mode 100644 include/fuzzing_engine.h

diff --git a/drivers/Kconfig b/drivers/Kconfig
index b26ca8cf70..54ad7f82fa 100644
--- a/drivers/Kconfig
+++ b/drivers/Kconfig
@@ -40,6 +40,8 @@ source "drivers/fastboot/Kconfig"
 
 source "drivers/firmware/Kconfig"
 
+source "drivers/fuzzing_engine/Kconfig"
+
 source "drivers/fpga/Kconfig"
 
 source "drivers/gpio/Kconfig"
diff --git a/drivers/Makefile b/drivers/Makefile
index 4e7cf28440..10a4a317c9 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -113,6 +113,7 @@ obj-$(CONFIG_W1) += w1/
 obj-$(CONFIG_W1_EEPROM) += w1-eeprom/
 
 obj-$(CONFIG_MACH_PIC32) += ddr/microchip/
+obj-$(CONFIG_FUZZ) += fuzzing_engine/
 obj-$(CONFIG_DM_HWSPINLOCK) += hwspinlock/
 obj-$(CONFIG_DM_RNG) += rng/
 endif
diff --git a/drivers/fuzzing_engine/Kconfig b/drivers/fuzzing_engine/Kconfig
new file mode 100644
index 00..f405fc75e8
--- /dev/null
+++ b/drivers/fuzzing_engine/Kconfig
@@ -0,0 +1,6 @@
+config DM_FUZZING_ENGINE
+   bool "Driver support for fuzzing engine devices"
+   depends on DM
+   help
+ Enable driver model for fuzzing engine devices. This interface is
+ used to get fuzzing inputs from a fuzzing engine.
diff --git a/drivers/fuzzing_engine/Makefile b/drivers/fuzzing_engine/Makefile
new file mode 100644
index 00..acd894999c
--- /dev/null
+++ b/drivers/fuzzing_engine/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (c) 2022 Google, Inc.
+# Written by Andrew Scull 
+#
+
+obj-$(CONFIG_DM_FUZZING_ENGINE) += fuzzing_engine-uclass.o
diff --git a/drivers/fuzzing_engine/fuzzing_engine-uclass.c 
b/drivers/fuzzing_engine/fuzzing_engine-uclass.c
new file mode 100644
index 00..b16f1c4cfb
--- /dev/null
+++ b/drivers/fuzzing_engine/fuzzing_engine-uclass.c
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2022 Google, Inc.
+ * Written by Andrew Scull 
+ */
+
+#define LOG_CATEGORY UCLASS_FUZZING_ENGINE
+
+#include 
+#include 
+#include 
+
+int dm_fuzzing_engine_get_input(struct udevice *dev,
+   const uint8_t **data,
+   size_t *size)
+{
+   const struct dm_fuzzing_engine_ops *ops = device_get_ops(dev);
+
+   if (!ops->get_input)
+   return -ENOSYS;
+
+   return ops->get_input(dev, data, size);
+}
+
+UCLASS_DRIVER(fuzzing_engine) = {
+   .name = "fuzzing_engine",
+   .id = UCLASS_FUZZING_ENGINE,
+};
diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h
index 0e26e1d138..b9411f1d59 100644
--- a/include/dm/uclass-id.h
+++ b/include/dm/uclass-id.h
@@ -53,6 +53,7 @@ enum uclass_id {
UCLASS_ETH, /* Ethernet device */
UCLASS_ETH_PHY, /* Ethernet PHY device */
UCLASS_FIRMWARE,/* Firmware */
+   UCLASS_FUZZING_ENGINE,  /* Fuzzing engine */
UCLASS_FS_FIRMWARE_LOADER,  /* Generic loader */
UCLASS_GPIO,/* Bank of general-purpose I/O pins */
UCLASS_HASH,/* Hash device */
diff --git a/include/fuzzing_engine.h b/include/fuzzing_engine.h
new file mode 100644
index 00..357346e93d
--- /dev/null
+++ b/include/fuzzing_engine.h
@@ -0,0 +1,51 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2022 Google, Inc.
+ * Written by Andrew Scull 
+ */
+
+#ifndef __FUZZING_ENGINE_H
+#define __FUZZING_ENGINE_H
+
+struct udevice;
+
+/**
+ * dm_fuzzing_engine_get_input() - get an input from the fuzzing engine device
+ *
+ * The function will return a pointer to the input data and the size of the
+ * data pointed to. The pointer will remain valid until the next invocation of
+ * this function.
+ *
+ * @dev:   fuzzing engine device
+ * @data:  output pointer to input data
+ * @size   output size of input data
+ * Return: 0 if OK, -ve on error
+ */
+int dm_fuzzing_engine_get_input(struct udevice *dev,
+   const uint8_t **data,
+   size_t *size);
+
+/**
+ * struct dm_fuzzing_engine_ops - operations for the fuzzing engine uclass
+ *
+ * This contains the functions implemented by a fuzzing engine device.
+ */
+struct dm_fuzzing_engine_ops {
+   /**
+* @get_input() - get an input
+*

[PATCH 02/11] sandbox: Migrate getopt section to linker list

[Andrew Scull]

Use the common infrastructure to create a linker list of the sandbox
command line flags rather than using a custom method.

The list is changed from containing pointers to containing structs and
the uses are updated accordingly.

Signed-off-by: Andrew Scull 
---
 arch/sandbox/cpu/os.c   | 21 ++---
 arch/sandbox/cpu/start.c| 10 +-
 arch/sandbox/cpu/u-boot-spl.lds |  6 --
 arch/sandbox/cpu/u-boot.lds |  6 --
 arch/sandbox/include/asm/getopt.h   | 19 ---
 arch/sandbox/include/asm/sections.h | 25 -
 6 files changed, 27 insertions(+), 60 deletions(-)

diff --git a/arch/sandbox/cpu/os.c b/arch/sandbox/cpu/os.c
index d83c862182..72a72029f2 100644
--- a/arch/sandbox/cpu/os.c
+++ b/arch/sandbox/cpu/os.c
@@ -424,9 +424,8 @@ static struct option *long_opts;
 
 int os_parse_args(struct sandbox_state *state, int argc, char *argv[])
 {
-   struct sandbox_cmdline_option **sb_opt =
-   __u_boot_sandbox_option_start();
-   size_t num_options = __u_boot_sandbox_option_count();
+   struct sandbox_cmdline_option *sb_opt = SANDBOX_CMDLINE_OPT_START();
+   size_t num_options = SANDBOX_CMDLINE_OPT_COUNT();
size_t i;
 
int hidden_short_opt;
@@ -455,17 +454,17 @@ int os_parse_args(struct sandbox_state *state, int argc, 
char *argv[])
hidden_short_opt = 0x100;
si = 0;
for (i = 0; i < num_options; ++i) {
-   long_opts[i].name = sb_opt[i]->flag;
-   long_opts[i].has_arg = sb_opt[i]->has_arg ?
+   long_opts[i].name = sb_opt[i].flag;
+   long_opts[i].has_arg = sb_opt[i].has_arg ?
required_argument : no_argument;
long_opts[i].flag = NULL;
 
-   if (sb_opt[i]->flag_short) {
-   short_opts[si++] = long_opts[i].val = 
sb_opt[i]->flag_short;
+   if (sb_opt[i].flag_short) {
+   short_opts[si++] = long_opts[i].val = 
sb_opt[i].flag_short;
if (long_opts[i].has_arg == required_argument)
short_opts[si++] = ':';
} else
-   long_opts[i].val = sb_opt[i]->flag_short = 
hidden_short_opt++;
+   long_opts[i].val = sb_opt[i].flag_short = 
hidden_short_opt++;
}
short_opts[si] = '\0';
 
@@ -480,9 +479,9 @@ int os_parse_args(struct sandbox_state *state, int argc, 
char *argv[])
 */
while ((c = getopt_long(argc, argv, short_opts, long_opts, NULL)) != 
-1) {
for (i = 0; i < num_options; ++i) {
-   if (sb_opt[i]->flag_short == c) {
-   if (sb_opt[i]->callback(state, optarg)) {
-   state->parse_err = sb_opt[i]->flag;
+   if (sb_opt[i].flag_short == c) {
+   if (sb_opt[i].callback(state, optarg)) {
+   state->parse_err = sb_opt[i].flag;
return 0;
}
break;
diff --git a/arch/sandbox/cpu/start.c b/arch/sandbox/cpu/start.c
index 13b0731ec3..5cb47e1156 100644
--- a/arch/sandbox/cpu/start.c
+++ b/arch/sandbox/cpu/start.c
@@ -58,9 +58,8 @@ static int h_compare_opt(const void *p1, const void *p2)
 int sandbox_early_getopt_check(void)
 {
struct sandbox_state *state = state_get_current();
-   struct sandbox_cmdline_option **sb_opt =
-   __u_boot_sandbox_option_start();
-   size_t num_options = __u_boot_sandbox_option_count();
+   struct sandbox_cmdline_option *sb_opt = SANDBOX_CMDLINE_OPT_START();
+   size_t num_options = SANDBOX_CMDLINE_OPT_COUNT();
size_t i;
int max_arg_len, max_noarg_len;
struct sandbox_cmdline_option **sorted_opt;
@@ -84,7 +83,7 @@ int sandbox_early_getopt_check(void)
 
max_arg_len = 0;
for (i = 0; i < num_options; ++i)
-   max_arg_len = max((int)strlen(sb_opt[i]->flag), max_arg_len);
+   max_arg_len = max((int)strlen(sb_opt[i].flag), max_arg_len);
max_noarg_len = max_arg_len + 7;
 
/* Sort the options */
@@ -94,7 +93,8 @@ int sandbox_early_getopt_check(void)
printf("No memory to sort options\n");
os_exit(1);
}
-   memcpy(sorted_opt, sb_opt, size);
+   for (i = 0; i < num_options; ++i)
+   sorted_opt[i] = _opt[i];
qsort(sorted_opt, num_options, sizeof(*sorted_opt), h_compare_opt);
 
for (i = 0; i < num_options; ++i) {
diff --git a/arch/sandbox/cpu/u-boot-spl.lds b/arch/sandbox/cpu/u-boot-spl.lds
index 6754f4ef6c..5c19d090cb 100644
--- a/arch/sandbox/cpu/u-boot-spl.lds
+++ b/arch/sandbox/cpu/u-boot-spl.lds
@@ -20,12 +20,6 @@ SECTIONS
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.priv_data*)))

[PATCH 01/11] sandbox: Set the EFI symbols in linker script

[Andrew Scull]

The sandbox doesn't populate the EFI lists so explicitly set the list
start and end symbols to indicate that the lists are empty. This
simplifies the linker scripts, removed references to non-existant
sections and removes '.' prefixed sections that conflicted with clang's
ASAN.

Signed-off-by: Andrew Scull 
---
 arch/sandbox/cpu/u-boot.lds | 32 +---
 arch/sandbox/lib/Makefile   |  2 +-
 arch/sandbox/lib/sections.c | 13 -
 3 files changed, 6 insertions(+), 41 deletions(-)
 delete mode 100644 arch/sandbox/lib/sections.c

diff --git a/arch/sandbox/cpu/u-boot.lds b/arch/sandbox/cpu/u-boot.lds
index 6d710618f5..dd675cc3d2 100644
--- a/arch/sandbox/cpu/u-boot.lds
+++ b/arch/sandbox/cpu/u-boot.lds
@@ -19,33 +19,11 @@ SECTIONS
*(.u_boot_sandbox_getopt_end)
}
 
-   .__efi_runtime_start : {
-   *(.__efi_runtime_start)
-   }
-
-   .efi_runtime : {
-   *(efi_runtime_text)
-   *(efi_runtime_data)
-   }
-
-   .__efi_runtime_stop : {
-   *(.__efi_runtime_stop)
-   }
-
-   .efi_runtime_rel_start :
-   {
-   *(.__efi_runtime_rel_start)
-   }
-
-   .efi_runtime_rel : {
-   *(.relefi_runtime_text)
-   *(.relefi_runtime_data)
-   }
-
-   .efi_runtime_rel_stop :
-   {
-   *(.__efi_runtime_rel_stop)
-   }
+   /* Sandbox has empty EFI runtime lists. */
+   __efi_runtime_start = .;
+   __efi_runtime_stop = __efi_runtime_start;
+   __efi_runtime_rel_start = .;
+   __efi_runtime_rel_stop = __efi_runtime_rel_start;
 
.dynsym :
{
diff --git a/arch/sandbox/lib/Makefile b/arch/sandbox/lib/Makefile
index a2bc5a7ee6..05f06180f8 100644
--- a/arch/sandbox/lib/Makefile
+++ b/arch/sandbox/lib/Makefile
@@ -5,7 +5,7 @@
 # (C) Copyright 2002-2006
 # Wolfgang Denk, DENX Software Engineering, w...@denx.de.
 
-obj-y  += fdt_fixup.o interrupts.o sections.o
+obj-y  += fdt_fixup.o interrupts.o
 obj-$(CONFIG_PCI)  += pci_io.o
 obj-$(CONFIG_CMD_BOOTM) += bootm.o
 obj-$(CONFIG_CMD_BOOTZ) += bootm.o
diff --git a/arch/sandbox/lib/sections.c b/arch/sandbox/lib/sections.c
deleted file mode 100644
index 2559eeea38..00
--- a/arch/sandbox/lib/sections.c
+++ /dev/null
@@ -1,13 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013 Albert ARIBAUD 
- *
- */
-#include 
-
-char __efi_runtime_start[0] __section(".__efi_runtime_start");
-char __efi_runtime_stop[0] __section(".__efi_runtime_stop");
-char __efi_runtime_rel_start[0]
-   __section(".__efi_runtime_rel_start");
-char __efi_runtime_rel_stop[0]
-   __section(".__efi_runtime_rel_stop");
-- 
2.35.1.1094.g7c7d902a7c-goog

[PATCH] tools: add boot/ to .gitignore

[Du Huanpeng]

/tools/boot/ is a build product. Add it to .gitignore

Signed-off-by: Du Huanpeng 
---
 tools/.gitignore | 1 +
 1 file changed, 1 insertion(+)

diff --git a/tools/.gitignore b/tools/.gitignore
index a88453f64d..d3a93ff294 100644
--- a/tools/.gitignore
+++ b/tools/.gitignore
@@ -36,3 +36,4 @@
 /update_octeon_header
 /version.h
 /xway-swap-bytes
+/boot
-- 
2.25.1

[PATCH] arm: mvebu: a37xx: Add support for writing Security OTP values

[Pali Rohár]

Implement write support for Security OTP values via mailbox API commands
MBOX_CMD_OTP_WRITE_32B and MBOX_CMD_OTP_WRITE.

Write support for North and South Bridge OTPs are not implemented as these
OTPs are already burned in factory with some data.

Signed-off-by: Pali Rohár 
---
This patch depends on series which implements read support for A3720 OTP:
https://patchwork.ozlabs.org/project/uboot/list/?series=287578=*

Stefan, what do you think, should be enable write support by default. Or
should it be hidden under some other CONFIG option? Becaue currently
CONFIG_CMD_FUSE enable both read and write support (or what driver
implements).
---
 arch/arm/mach-mvebu/armada3700/efuse.c | 50 --
 1 file changed, 48 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-mvebu/armada3700/efuse.c 
b/arch/arm/mach-mvebu/armada3700/efuse.c
index 50c73f36c565..07d5f394354c 100644
--- a/arch/arm/mach-mvebu/armada3700/efuse.c
+++ b/arch/arm/mach-mvebu/armada3700/efuse.c
@@ -113,6 +113,41 @@ static int rwtm_otp_read(u8 row, u32 word, u32 *data)
return res;
 }
 
+static int rwtm_otp_write(u8 row, u32 word, u32 data)
+{
+   u32 in[4];
+   int res = -EINVAL;
+
+   if (word < 2) {
+   /*
+* MBOX_CMD_OTP_WRITE_32B command is supported by Marvell
+* fuse.bin firmware and also by new CZ.NIC wtmi firmware.
+* This command writes only selected bits to OTP and does
+* not calculate ECC bits. It does not allow to write the
+* lock bit.
+*/
+   in[0] = row;
+   in[1] = word * 32;
+   in[2] = data;
+   res = mbox_do_cmd(MBOX_CMD_OTP_WRITE_32B, in, 3, NULL, 0);
+   } else if (word == 2 && !(data & ~0x1)) {
+   /*
+* MBOX_CMD_OTP_WRITE command is supported only by new CZ.NIC
+* wtmi firmware and allows to write any bit to OTP, including
+* the lock bit. It does not calculate or write ECC bits too.
+* For compatibility with Marvell fuse.bin firmware, use this
+* command only for writing the lock bit.
+*/
+   in[0] = row;
+   in[1] = 0;
+   in[2] = 0;
+   in[3] = data;
+   res = mbox_do_cmd(MBOX_CMD_OTP_WRITE, in, 4, NULL, 0);
+   }
+
+   return res;
+}
+
 /*
  * Banks 0-43 are used for accessing Security OTP (44 rows with 67 bits via 44 
banks and words 0-2)
  * Bank 44 is used for accessing North Bridge OTP (69 bits via words 0-2)
@@ -154,8 +189,19 @@ int fuse_read(u32 bank, u32 word, u32 *val)
 
 int fuse_prog(u32 bank, u32 word, u32 val)
 {
-   /* TODO: not implemented yet */
-   return -ENOSYS;
+   if (bank <= RWTM_MAX_BANK) {
+   if (word >= RWTM_ROW_WORDS)
+   return -EINVAL;
+   return rwtm_otp_write(bank, word, val);
+   } else if (bank == OTP_NB_BANK) {
+   /* TODO: not implemented yet */
+   return -ENOSYS;
+   } else if (bank == OTP_SB_BANK) {
+   /* TODO: not implemented yet */
+   return -ENOSYS;
+   } else {
+   return -EINVAL;
+   }
 }
 
 int fuse_sense(u32 bank, u32 word, u32 *val)
-- 
2.20.1

Re: [PATCH] riscv: Fix build against binutils 2.38

[Leo Liang]

Hi Alex,
On Thu, Mar 10, 2022 at 09:03:08AM +0100, Alexandre Ghiti wrote:
> Hi Leo,
> 
> On Wed, Mar 9, 2022 at 7:31 AM Leo Liang  wrote:
> >
> > Hi Alex,
> > On Thu, Mar 03, 2022 at 11:06:18AM +, Leo Liang wrote:
> > > Hi Alex,
> > > On Tue, Mar 01, 2022 at 03:21:56AM +, Leo Liang wrote:
> > > > Hi Alex,
> > > > On Mon, Feb 21, 2022 at 05:42:41PM +0100, Alexandre Ghiti wrote:
> > > > > On Sat, Feb 19, 2022 at 9:52 AM Leo Liang  
> > > > > wrote:
> > > > > >
> > > > > > Hi Alex,
> > > > > > On Thu, Feb 17, 2022 at 11:28:46AM +0100, Alexandre Ghiti wrote:
> > > > > > > Hi Leo,
> > > > > > >
> > > > > > > On Thu, Feb 17, 2022 at 10:25 AM Leo Liang 
> > > > > > >  wrote:
> > > > > > > >
> > > > > > > > Hi Alexandre,
> > > > > > > > On Fri, Jan 28, 2022 at 02:47:13PM +0100, Alexandre Ghiti wrote:
> > > > > > > > > The following description is copied from the equivalent patch 
> > > > > > > > > for the
> > > > > > > > > Linux Kernel proposed by Aurelien Jarno:
> > > > > > > > >
> > > > > > > > > From version 2.38, binutils default to ISA spec version 
> > > > > > > > > 20191213. This
> > > > > > > > > means that the csr read/write (csrr*/csrw*) instructions and 
> > > > > > > > > fence.i
> > > > > > > > > instruction has separated from the `I` extension, become two 
> > > > > > > > > standalone
> > > > > > > > > extensions: Zicsr and Zifencei. As the kernel uses those 
> > > > > > > > > instruction,
> > > > > > > > > this causes the following build failure:
> > > > > > > > >
> > > > > > > > > arch/riscv/cpu/mtrap.S: Assembler messages:
> > > > > > > > > arch/riscv/cpu/mtrap.S:65: Error: unrecognized opcode `csrr 
> > > > > > > > > a0,scause'
> > > > > > > > > arch/riscv/cpu/mtrap.S:66: Error: unrecognized opcode `csrr 
> > > > > > > > > a1,sepc'
> > > > > > > > > arch/riscv/cpu/mtrap.S:67: Error: unrecognized opcode `csrr 
> > > > > > > > > a2,stval'
> > > > > > > > > arch/riscv/cpu/mtrap.S:70: Error: unrecognized opcode `csrw 
> > > > > > > > > sepc,a0'
> > > > > > > > >
> > > > > > > > > Signed-off-by: Alexandre Ghiti 
> > > > > > > > > ---
> > > > > > > > >  arch/riscv/Makefile | 11 ++-
> > > > > > > > >  1 file changed, 10 insertions(+), 1 deletion(-)
> > > > > > > >
> > > > > > > > This patch seems to fail CI somehow.
> > > > > > > > (https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/11004)
> > > > > > > >
> > > > > > > > Could you take a look at it ?
> > > > > > >
> > > > > > > I have just tried on master (commit ab8903a24db1) and it failed 
> > > > > > > for
> > > > > > > the same reason, so this is not related to this patch. 
> > > > > > > Nevertheless,
> > > > > > > I'll try to bisect the problem :)
> > > > > > >
> > > > > > > Thanks,
> > > > > > >
> > > > > > > Alex
> > > > > > >
> > > > > >
> > > > > > Thanks for putting the effort into it!
> > > > > >
> > > > > > AFAIK, this patch does nothing related to the error message 
> > > > > > "undefined reference to `__ashldi3'" from the failed CI.
> > > > > >
> > > > > > Nonetheless, I have tried a few times myself,
> > > > > > and found that CI could pass with ab8903a24db1 but cannot pass with 
> > > > > > this patch on my side.
> > > > > > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/commits/staging
> > > > > > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines
> > > > > >
> > > > >
> > > > > To me it is an issue with the toolchain: libgcc is missing those
> > > > > symbols. If I use an Ubuntu toolchain, it fails no matter which commit
> > > > > I am on (I tested as far as v2021.10). But if I use a toolchain from
> > > > > https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/,
> > > > > it works fine.
> > > > >
> > > > > What I don't understand is how you manage to have different build
> > > > > results with the same docker image: can you confirm that you use the
> > > > > same toolchains in the following builds?
> > > > >
> > > > > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/jobs/393701
> > > > > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/jobs/393783
> > > > >
> > > >
> > > > Sorry for the late reply.
> > > > I have checked the toolchain version of these two builds,
> > > > they are using the same toolchain[1] from Tom's docker image on docker 
> > > > hub[2].
> > > >
> > > > Also the fail is reproducible using this docker image with the 
> > > > following commands:
> > > >
> > > > leo@host sudo docker run -it --name leo-test 
> > > > trini/u-boot-gitlab-ci-runner:focal-20220113-03Feb2022 /bin/bash
> > > > uboot@356268d27bf0:~$ git clone 
> > > > https://source.denx.de/u-boot/custodians/u-boot-riscv.git && cd 
> > > > u-boot-riscv
> > > > uboot@356268d27bf0:~/u-boot-riscv$ git checkout staging
> > > > uboot@356268d27bf0:~/u-boot-riscv$ export 
> > > > PATH=/opt/gcc-11.1.0-nolibc/riscv64-linux/bin:$PATH
> > > > uboot@356268d27bf0:~/u-boot-riscv$ export CROSS_COMPILE=riscv64-linux-
> > > > uboot@356268d27bf0:~/u-boot-riscv$ make qemu-riscv32_spl_defconfig
> 

Re: [PATCH v6 0/7] fpga: zynqmp: Adding support of loading authenticated images

[Michal Simek]

Hi,

On 2/7/22 12:18, Adrian Fiergolski wrote:

This patchset introduces support for the authenticated FPGA images
on ZynqMP boards, besides that introducing common way to pass the
compatible property to any fpga driver.

It bases on the initial work by Jorge Ramirez-Ortiz 
https://patchwork.ozlabs.org/project/uboot/patch/20211015091506.2602-1-jo...@foundries.io/
https://patchwork.ozlabs.org/project/uboot/patch/20211005111324.19749-3-jo...@foundries.io/

Changed in v6:
- add support for the encrypted bitfiles

Changes in v5:
- replace ifdef with if() where it's possible

Changes in v4:
- change interface to xilinx_desc->operations->open() callback.
- fix a bug from previous version of the patchset in dereferencing
   of a parent fpga_desc structure.

Changes in v3:
- remove the patch which introduced CMD_SPL_FPGA_LOAD_SECURE.
- fix mixing definitions/declarations.
- replace strcmp() calls with more secure strncmp().
- document the "u-boot,zynqmp-fpga-ddrauth" compatible string.
- fix code style by check-patch recommendations.

Changes in v2:
- add function fit_fpga_load() to simplify calls of fpga_load()
   from contexts without a compatible attribute.
- move all ZynqMP-specific logic to drivers/fpga/zynqmppl.c
- prepare for passing a "compatible" FDT property to any fpga driver.

Oleksandr Suvorov (6):
   fpga: add option for loading FPGA secure bitstreams
   fpga: add fit_fpga_load function
   fpga: xilinx: pass an address of xilinx_desc in fpga_desc
   fpga: xilinx: add missed identifier names
   fpga: xilinx: pass xilinx_desc pointer address into load() ops
   fpga: zynqmp: support loading authenticated images

Adrian Fiergolski (1):
   fpga: zynqmp: support loading encrypted bitfiles




sorry for delay.
My biggest problem with this series is that if SPL_FPGA_LOAD_SECURE is not 
enabled when this series is applied I see what we are adding 216 Bytes without 
any benefit when this option is disabled.
Please use buildman and make sure that there is only reasonable number of bytes 
added when this option is not enabled.


Thanks,
Michal

Re: [PATCH v6 2/7] fpga: add fit_fpga_load function

[Michal Simek]

On 2/7/22 12:18, Adrian Fiergolski wrote:

From: Oleksandr Suvorov 

Introduce a function which passes an fpga compatible string from
FIT images to FPGA drivers. This lets the different implementations
decide how to handle it.

Some code of Jorge Ramirez-Ortiz  is reused.

Signed-off-by: Oleksandr Suvorov 
Tested-by: Ricardo Salveti 
---
  common/spl/spl_fit.c |  6 ++
  drivers/fpga/fpga.c  | 35 ---
  include/fpga.h   |  4 
  3 files changed, 34 insertions(+), 11 deletions(-)

diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c
index 1bbf824684..0e3c2a94b6 100644
--- a/common/spl/spl_fit.c
+++ b/common/spl/spl_fit.c
@@ -588,11 +588,9 @@ static int spl_fit_upload_fpga(struct spl_fit_info *ctx, 
int node,
compatible = fdt_getprop(ctx->fit, node, "compatible", NULL);
if (!compatible)
warn_deprecated("'fpga' image without 'compatible' property");
-   else if (strcmp(compatible, "u-boot,fpga-legacy"))
-   printf("Ignoring compatible = %s property\n", compatible);
  
-	ret = fpga_load(0, (void *)fpga_image->load_addr, fpga_image->size,

-   BIT_FULL);
+   ret = fit_fpga_load(0, (void *)fpga_image->load_addr, fpga_image->size,
+   BIT_FULL, compatible);
if (ret) {
printf("%s: Cannot load the image to the FPGA\n", __func__);
return ret;
diff --git a/drivers/fpga/fpga.c b/drivers/fpga/fpga.c
index 3b0a44b242..2266c7d83a 100644
--- a/drivers/fpga/fpga.c
+++ b/drivers/fpga/fpga.c
@@ -197,9 +197,9 @@ int fpga_fsload(int devnum, const void *buf, size_t size,
 fpga_fs_info *fpga_fsinfo)
  {
int ret_val = FPGA_FAIL;   /* assume failure */
-   const fpga_desc *desc = fpga_validate(devnum, buf, size,
- (char *)__func__);
+   const fpga_desc *desc;
  
+	desc = fpga_validate(devnum, buf, size, (char *)__func__);


this is unrelated to core change.



if (desc) {
switch (desc->devtype) {
case fpga_xilinx:
@@ -225,10 +225,9 @@ int fpga_loads(int devnum, const void *buf, size_t size,
   struct fpga_secure_info *fpga_sec_info)
  {
int ret_val = FPGA_FAIL;
+   const fpga_desc *desc;
  
-	const fpga_desc *desc = fpga_validate(devnum, buf, size,

- (char *)__func__);
-
+   desc = fpga_validate(devnum, buf, size, (char *)__func__);


the same here.


if (desc) {
switch (desc->devtype) {
case fpga_xilinx:
@@ -249,15 +248,31 @@ int fpga_loads(int devnum, const void *buf, size_t size,
  }
  #endif
  
+int fit_fpga_load(int devnum, const void *buf, size_t bsize,

+ bitstream_type bstype, const char *compatible)
+{
+   fpga_desc *desc = (fpga_desc *)fpga_validate(devnum, buf, bsize,
+ (char *)__func__);


This is the first fpga_validate() call


+
+   if (!desc)
+   return FPGA_FAIL;
+   /*
+* Store the compatible string to proceed it in underlying
+* functions
+*/
+   desc->compatible = (char *)compatible;
+
+   return fpga_load(devnum, buf, bsize, bstype);


and inside fpga_load there is another fpga_validate call again.


+}


missing newline


  /*
- * Generic multiplexing code
+ * Generic multiplexing code:
+ * Each architecture must handle the mandatory FPGA DT compatible property.
   */
  int fpga_load(int devnum, const void *buf, size_t bsize, bitstream_type 
bstype)
  {
int ret_val = FPGA_FAIL;   /* assume failure */
const fpga_desc *desc = fpga_validate(devnum, buf, bsize,
  (char *)__func__);
-


unrelated.


if (desc) {
switch (desc->devtype) {
case fpga_xilinx:
@@ -270,6 +285,9 @@ int fpga_load(int devnum, const void *buf, size_t bsize, 
bitstream_type bstype)
break;
case fpga_altera:
  #if defined(CONFIG_FPGA_ALTERA)
+   if (strncmp(desc->compatible, "u-boot,fpga-legacy", 18))
+   printf("Ignoring compatible = %s property\n",
+  desc->compatible);
ret_val = altera_load(desc->devdesc, buf, bsize);
  #else
fpga_no_sup((char *)__func__, "Altera devices");
@@ -277,6 +295,9 @@ int fpga_load(int devnum, const void *buf, size_t bsize, 
bitstream_type bstype)
break;
case fpga_lattice:
  #if defined(CONFIG_FPGA_LATTICE)
+   if (strncmp(desc->compatible, "u-boot,fpga-legacy", 18))
+   printf("Ignoring compatible = %s property\n",
+  desc->compatible);
ret_val = 

Re: [PATCH] imx: power-domain: Add i.MX8MP support

[Marek Vasut]

On 4/7/22 06:01, Peng Fan (OSS) wrote:



On 2022/4/1 9:12, Marek Vasut wrote:

Add i.MX8MP power domain handling into the driver. This is based on the
Linux GPCv2 driver state which is soon to be in Linux next.


Do we really need this in U-Boot? You will also port the blk-ctrl part?
That would be lots code!


I already did sent HSIOMIX driver too, that's all we need to get USB and 
PCIe going in U-Boot, and get U-Boot working without running ATF, which 
makes new platform bring up far easier.


The "lots of code" that's in Linux is for graphics pipeline and we don't 
need that in U-Boot, so we conveniently avoid it here.

Re: [PATCH] misc: atsha204a: Fix big endian support

[Pali Rohár]

On Monday 04 April 2022 09:43:21 Stefan Roese wrote:
> On 4/3/22 00:36, Pali Rohár wrote:
> > Callers of function atsha204a_crc16() expect to return value in host cpu
> > endianity. So remove cpu_to_le16() conversion.
> > 
> > Signed-off-by: Pali Rohár 
> 
> Reviewed-by: Stefan Roese 

Hello Stefan! Would you or somebody else take this patch?

Because I have some other u-boot generic patches which touches this
driver and I'm waiting until this simple change would be merged first.

> Thanks,
> Stefan
> 
> > ---
> >   drivers/misc/atsha204a-i2c.c | 2 +-
> >   1 file changed, 1 insertion(+), 1 deletion(-)
> > 
> > diff --git a/drivers/misc/atsha204a-i2c.c b/drivers/misc/atsha204a-i2c.c
> > index b89463babb56..63fe541dade3 100644
> > --- a/drivers/misc/atsha204a-i2c.c
> > +++ b/drivers/misc/atsha204a-i2c.c
> > @@ -146,7 +146,7 @@ static u16 atsha204a_crc16(const u8 *buffer, size_t len)
> > while (len--)
> > crc = crc16_byte(crc, *buffer++);
> > -   return cpu_to_le16(crc);
> > +   return crc;
> >   }
> >   static int atsha204a_send(struct udevice *dev, const u8 *buf, u8 len)
> 
> Viele Grüße,
> Stefan Roese
> 
> -- 
> DENX Software Engineering GmbH,  Managing Director: Wolfgang Denk
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: s...@denx.de

Re: [PATCH v6 1/7] fpga: add option for loading FPGA secure bitstreams

[Michal Simek]

On 2/7/22 12:18, Adrian Fiergolski wrote:

From: Oleksandr Suvorov 

It allows using this feature without enabling the "fpga loads"
command.

Signed-off-by: Oleksandr Suvorov 
Tested-by: Ricardo Salveti 
---
  cmd/Kconfig |  3 ++-
  drivers/fpga/Kconfig| 14 ++
  drivers/fpga/fpga.c |  2 +-
  drivers/fpga/xilinx.c   |  2 +-
  drivers/fpga/zynqmppl.c |  4 ++--
  5 files changed, 20 insertions(+), 5 deletions(-)

diff --git a/cmd/Kconfig b/cmd/Kconfig
index 5e25e45fd2..604ab37f3b 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -949,8 +949,9 @@ config CMD_FPGA_LOADP
  a partial bitstream.
  
  config CMD_FPGA_LOAD_SECURE

-   bool "fpga loads - loads secure bitstreams (Xilinx only)"
+   bool "fpga loads - loads secure bitstreams"
depends on CMD_FPGA
+   select FPGA_LOAD_SECURE
help
  Enables the fpga loads command which is used to load secure
  (authenticated or encrypted or both) bitstreams on to FPGA.
diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
index dc0b3dd31b..262f95a252 100644
--- a/drivers/fpga/Kconfig
+++ b/drivers/fpga/Kconfig
@@ -85,4 +85,18 @@ config FPGA_ZYNQPL
  Enable FPGA driver for loading bitstream in BIT and BIN format
  on Xilinx Zynq devices.
  
+config FPGA_LOAD_SECURE

+   bool "Enable loading secure bitstreams"
+   depends on FPGA
+   help
+ Enables the fpga loads() functions that are used to load secure
+ (authenticated or encrypted or both) bitstreams on to FPGA.
+
+config SPL_FPGA_LOAD_SECURE
+   bool "Enable loading secure bitstreams for SPL"
+   depends on FPGA


This should be SPL_FPGA

M

Re: [PATCH v6 3/7] fpga: xilinx: pass an address of xilinx_desc in fpga_desc

[Michal Simek]

On 2/7/22 12:18, Adrian Fiergolski wrote:

From: Oleksandr Suvorov 

Pass an address of xilinx_desc pointer in an fpga_desc  to use parent


double space here.

M

Re: [PATCH v6 6/7] fpga: zynqmp: support loading authenticated images

[Michal Simek]

On 2/7/22 12:18, Adrian Fiergolski wrote:

From: Oleksandr Suvorov 

Add supporting new compatible string "u-boot,zynqmp-fpga-ddrauth" to
handle loading authenticated images (DDR).

Based on solution by Jorge Ramirez-Ortiz 
Signed-off-by: Oleksandr Suvorov 
Co-developed-by: Ricardo Salveti 
Signed-off-by: Ricardo Salveti 
Tested-by: Ricardo Salveti 
---
  boot/Kconfig  |  4 ++--
  doc/uImage.FIT/source_file_format.txt |  5 -
  drivers/fpga/zynqmppl.c   | 21 +
  3 files changed, 27 insertions(+), 3 deletions(-)

diff --git a/boot/Kconfig b/boot/Kconfig
index b83a4e8400..f7faafb29f 100644
--- a/boot/Kconfig
+++ b/boot/Kconfig
@@ -209,8 +209,8 @@ config SPL_LOAD_FIT
  1. "loadables" images, other than FDTs, which do not have a "load"
 property will not be loaded. This limitation also applies to FPGA
 images with the correct "compatible" string.
- 2. For FPGA images, only the "compatible" = "u-boot,fpga-legacy"
-loading method is supported.
+ 2. For FPGA images, the supported "compatible" list is in the
+doc/uImage.FIT/source_file_format.txt.
  3. FDTs are only loaded for images with an "os" property of "u-boot".
 "linux" images are also supported with Falcon boot mode.
  
diff --git a/doc/uImage.FIT/source_file_format.txt b/doc/uImage.FIT/source_file_format.txt

index f93ac6d1c7..461e2af2a8 100644
--- a/doc/uImage.FIT/source_file_format.txt
+++ b/doc/uImage.FIT/source_file_format.txt
@@ -184,7 +184,10 @@ the '/images' node should have the following layout:
  Mandatory for types: "firmware", and "kernel".
- compatible : compatible method for loading image.
  Mandatory for types: "fpga", and images that do not specify a load 
address.
-To use the generic fpga loading routine, use "u-boot,fpga-legacy".
+Supported compatible methods:
+"u-boot,fpga-legacy" - the generic fpga loading routine.
+"u-boot,zynqmp-fpga-ddrauth" - signed non-encrypted FPGA bitstream for
+Xilinx Zynq UltraScale+ (ZymqMP) device.
  
Optional nodes:

- hash-1 : Each hash sub-node represents separate hash or checksum
diff --git a/drivers/fpga/zynqmppl.c b/drivers/fpga/zynqmppl.c
index c7f9f4ae84..bf6f56e1c4 100644
--- a/drivers/fpga/zynqmppl.c
+++ b/drivers/fpga/zynqmppl.c
@@ -9,6 +9,7 @@
  #include 
  #include 
  #include 
+#include 
  #include 
  #include 
  #include 
@@ -210,6 +211,26 @@ static int zynqmp_load(xilinx_desc **desc_ptr, const void 
*buf, size_t bsize,
u32 ret_payload[PAYLOAD_ARG_CNT];
bool xilfpga_old = false;
xilinx_desc *desc = *desc_ptr;
+   fpga_desc *fdesc = container_of((void *)desc_ptr, fpga_desc, devdesc);
+
+   if (fdesc && fdesc->compatible &&
+   !strcmp(fdesc->compatible, "u-boot,zynqmp-fpga-ddrauth")) {
+   if (CONFIG_IS_ENABLED(FPGA_LOAD_SECURE)) {
+   struct fpga_secure_info info = { 0 };
+
+   if (!desc->operations->loads) {
+   printf("%s: Missing load operation\n", 
__func__);
+   return FPGA_FAIL;
+   }
+   /* DDR authentication */
+   info.authflag = 1;
+   info.encflag = 2;
+   return desc->operations->loads(desc, buf, bsize, );
+   } else {


Please run checkpatch on every patch. Then you would see this error.


WARNING: else is not generally useful after a break or return
#89: FILE: drivers/fpga/zynqmppl.c:229:
+   return desc->operations->loads(desc, buf, bsize, );
+   } else {

M


+   printf("No support for %s\n", fdesc->compatible);
+   return FPGA_FAIL;
+   }
+   }
  
  	if (zynqmp_firmware_version() <= PMUFW_V1_0) {

puts("WARN: PMUFW v1.0 or less is detected\n");

Re: [PATCH v6 7/7] fpga: zynqmp: support loading encrypted bitfiles

[Michal Simek]

On 2/7/22 12:18, Adrian Fiergolski wrote:

Add supporting new compatible string "u-boot,zynqmp-fpga-enc" to handle
loading encrypted bitfiles.

This feature requires encrypted FSBL,as according to UG1085:
"The CSU automatically locks out the AES key, stored in either BBRAM or eFUSEs,
  as a key source to the AES engine if the FSBL is not encrypted. This prevents
  using the BBRAM or eFUSE as the key source to the AES engine during run-time
  applications."

Signed-off-and-tested-by: Adrian Fiergolski 
---
  doc/uImage.FIT/source_file_format.txt |  2 ++
  drivers/fpga/zynqmppl.c   | 16 
  2 files changed, 14 insertions(+), 4 deletions(-)

diff --git a/doc/uImage.FIT/source_file_format.txt 
b/doc/uImage.FIT/source_file_format.txt
index 461e2af2a8..2cf77ba3e9 100644
--- a/doc/uImage.FIT/source_file_format.txt
+++ b/doc/uImage.FIT/source_file_format.txt
@@ -188,6 +188,8 @@ the '/images' node should have the following layout:
  "u-boot,fpga-legacy" - the generic fpga loading routine.
  "u-boot,zynqmp-fpga-ddrauth" - signed non-encrypted FPGA bitstream for
  Xilinx Zynq UltraScale+ (ZymqMP) device.
+"u-boot,zynqmp-fpga-enc" - encrypted FPGA bitstream for Xilinx Zynq
+UltraScale+ (ZymqMP) device.


ZynqMP

  
Optional nodes:

- hash-1 : Each hash sub-node represents separate hash or checksum
diff --git a/drivers/fpga/zynqmppl.c b/drivers/fpga/zynqmppl.c
index bf6f56e1c4..5fcca8d1b8 100644
--- a/drivers/fpga/zynqmppl.c
+++ b/drivers/fpga/zynqmppl.c
@@ -214,7 +214,9 @@ static int zynqmp_load(xilinx_desc **desc_ptr, const void 
*buf, size_t bsize,
fpga_desc *fdesc = container_of((void *)desc_ptr, fpga_desc, devdesc);
  
  	if (fdesc && fdesc->compatible &&

-   !strcmp(fdesc->compatible, "u-boot,zynqmp-fpga-ddrauth")) {
+   ( !strcmp(fdesc->compatible, "u-boot,zynqmp-fpga-ddrauth") ||
+ !strcmp(fdesc->compatible, "u-boot,zynqmp-fpga-enc") )
+ ) {


coding style and I think you should revert the logic here. You should check 
u-boot-fpga-legacy and use inverted logic if possible which should save some bytes.


And strncmp



if (CONFIG_IS_ENABLED(FPGA_LOAD_SECURE)) {
struct fpga_secure_info info = { 0 };
  
@@ -222,9 +224,15 @@ static int zynqmp_load(xilinx_desc **desc_ptr, const void *buf, size_t bsize,

printf("%s: Missing load operation\n", 
__func__);
return FPGA_FAIL;
}
-   /* DDR authentication */
-   info.authflag = 1;
-   info.encflag = 2;
+   if(!strcmp(fdesc->compatible+19, "enc")){


coding style issues and use strncmp.


+ /* Encryption using device key*/


coding style issues.


+ info.authflag = 2;
+ info.encflag = 0;


You should use macros for it.



+   } else {
+ /* DDR authentication */
+ info.authflag = 1;
+ info.encflag = 2;


ditto.


+   }
return desc->operations->loads(desc, buf, bsize, );
} else {
printf("No support for %s\n", fdesc->compatible);


M

Re: [PATCH] squashfs: Fix compilation on big endian systems

[Miquel Raynal]

Hi Pali,

p...@kernel.org wrote on Wed,  6 Apr 2022 23:31:53 +0200:

Would you mind explaining a little bit how this change fixes it? It
does not look straightforward to me.

> Signed-off-by: Pali Rohár 
> ---
>  fs/squashfs/sqfs.c | 3 +--
>  fs/squashfs/sqfs_dir.c | 3 +--
>  2 files changed, 2 insertions(+), 4 deletions(-)
> 
> diff --git a/fs/squashfs/sqfs.c b/fs/squashfs/sqfs.c
> index 5d9c52af80ba..41cb811c1b32 100644
> --- a/fs/squashfs/sqfs.c
> +++ b/fs/squashfs/sqfs.c
> @@ -11,8 +11,7 @@
>  #include 
>  #include 
>  #include 
> -#include 
> -#include 
> +#include 
>  #include 
>  #include 
>  #include 
> diff --git a/fs/squashfs/sqfs_dir.c b/fs/squashfs/sqfs_dir.c
> index a265b98fe685..ed83c90682ff 100644
> --- a/fs/squashfs/sqfs_dir.c
> +++ b/fs/squashfs/sqfs_dir.c
> @@ -7,8 +7,7 @@
>  
>  #include 
>  #include 
> -#include 
> -#include 
> +#include 
>  #include 
>  #include 
>  #include 

Cheers,
Miquèl