).
Angela Stegmaier (1):
configs: ti_omap5_common: Enable workaround for ARM errata 798870
Nishanth Menon (2):
ARM: OMAP: Change set_pl310_ctrl_reg to be generic
ARM: OMAP5 / DRA7: Setup L2 Aux Control Register with recommended
configuration
Praveen Rao (1):
ARM / OMAP5: Add workaround
to a macro and use a generic name (same as
that used in Linux for some consistency). While at that, also add
a data barrier which is necessary as per recommendation.
Signed-off-by: Nishanth Menon n...@ti.com
---
arch/arm/cpu/armv7/omap-common/lowlevel_init.S |8 +---
arch/arm/cpu/armv7/omap4
Update to existing recommendation for L2ACTLR configuration to prevent
system instability and optimize performance.
These apply to both OMAP5 and DRA7.
Reported-by: Vivek Chengalvala vchengalv...@ti.com
Signed-off-by: Nishanth Menon n...@ti.com
---
arch/arm/cpu/armv7/omap5/hwinit.c
From: Angela Stegmaier angelaba...@ti.com
Enable the workaround for ARM errata 798870 for OMAP5
and DRA7xx since they are Coretx-A15 r2.
Signed-off-by: Angela Stegmaier angelaba...@ti.com
Signed-off-by: Nishanth Menon n...@ti.com
---
include/configs/ti_omap5_common.h |4
1 file changed
.
+
+
extra EOL?
Load and Run U-Boot on keystone EVMs using CCS
=
--
Regards,
Nishanth Menon
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from V1.
--
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Nishanth Menon
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On 02/16/2015 02:56 PM, Vitaly Andrianov wrote:
On 02/16/2015 03:15 PM, Nishanth Menon wrote:
On 02/16/2015 12:22 PM, Vitaly Andrianov wrote:
Currently to flash u-boot image onto NAND or SPI NOR flash, very first
time user need to use Code Composer Studio (CCS). This is cumbersome
; then \
setenv fdtfile am43x-epos-evm.dtb; fi; \
Should we start introducing generic macros in v7_common.h ? that'd let
all network enabled platforms to uniformly provide this?
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, but not other
comments those are not related to the purpose of the patch.
Nice of you to just ignore my comments as being not related to the
purpose of the patch considering that I did provide the comments with
the complete expectation from the patch itself.
Sorry, my NAK stands.
--
---
Regards,
Nishanth
Synchronize with the implementation from v3.18 tag. This allows us to
use a standardized 64 bit ops on architectures that do not natively
support 64 bit (example: 32bit ARM)
Signed-off-by: Nishanth Menon n...@ti.com
---
include/linux/math64.h | 81 ++
lib/div64.c
initializatin every time when the
keystone2_eth_open is being called.
Signed-off-by: Vitaly Andrianov vita...@ti.com
---
Necessary for keystone 2 devices to reach to shell.
Tested-by: Nishanth Menon n...@ti.com
drivers/net/keystone_net.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions
instead.
Signed-off-by: Vitaly Andrianov vita...@ti.com
---
This patch is necesasry for Keystone2 platforms to boot to u-boot shell.
Tested-by: Nishanth Menon n...@ti.com
Tested on v2015.01 tag (which is broke).
arch/arm/cpu/armv7/keystone/ddr3.c| 5 +
arch/arm/include/asm
/sys_info.c;h=bbb65bbe7263674c2b47b97ee05a9f588ed1c58f;hb=HEAD#l265
Macro HS_DEVICE could be used?
--
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if needed.
Based on ARM errata Document revision 20.0 (13 Nov 2010)
Signed-off-by: Nishanth Menon n...@ti.com
---
README |1 +
arch/arm/cpu/armv7/cp15.c|6 ++
arch/arm/cpu/armv7/start.S | 13 +
arch/arm/include/asm/armv7.h |2 ++
4 files
omap_smc1 is now generic enough to remove duplicate
omap3_gp_romcode_call logic that omap3 introduced.
As part of this change, move to using the generic lowlevel_init.S for
omap3 as well.
Signed-off-by: Nishanth Menon n...@ti.com
---
arch/arm/cpu/armv7/omap-common/Makefile|2
430973: Stale prediction on replaced inter working branch causes
Cortex-A8 to execute in the wrong ARM/Thumb state
Impacts: Every Cortex-A8 processors with revision lower than r2p1
Work around: Set IBE to 1
Based on ARM errata Document revision 20.0 (13 Nov 2010)
Signed-off-by: Nishanth
-by: Nishanth Menon n...@ti.com
---
arch/arm/cpu/armv7/omap3/board.c| 45 ---
arch/arm/include/asm/arch-omap3/sys_proto.h |1 +
board/nokia/rx51/rx51.c | 19 ++-
include/configs/nokia_rx51.h|4 +++
4 files changed
is
around..)
branch errata-v6-master-62f3aaf89d01
Git link: https://gitorious.org/nm-kernel/u-boot-nm.git
errata-v6-master-62f3aaf89d01
Nishanth Menon (10):
ARM: Introduce erratum workaround for 798870
ARM: Introduce erratum workaround for 454179
ARM: Introduce erratum workaround
Stegmaier angelaba...@ti.com
Signed-off-by: Nishanth Menon n...@ti.com
---
arch/arm/cpu/armv7/omap5/hwinit.c |7 +++
arch/arm/include/asm/arch-omap5/sys_proto.h |3 +++
include/configs/ti_omap5_common.h |3 +++
3 files changed, 13 insertions(+)
diff --git a/arch
Monitor handling of Secure
Monitor Call(smc) is diverse. Hence an weak function is introduced
which may be overriden to implement SoC specific accessor implementation.
Based on ARM errata Document revision 18.0 (22 Nov 2013)
Signed-off-by: Nishanth Menon n...@ti.com
---
README
-off-by: Nishanth Menon n...@ti.com
---
README |1 +
arch/arm/cpu/armv7/start.S | 13 +
2 files changed, 14 insertions(+)
diff --git a/README b/README
index 82f7e10c71d6..e7e90a08145e 100644
--- a/README
+++ b/README
@@ -695,6 +695,7 @@ The following options need
This is in preperation of using generic cross OMAP code.
Signed-off-by: Nishanth Menon n...@ti.com
---
.../arm/include/asm/arch-omap3/{omap3.h = omap.h} |0
include/configs/am3517_crane.h |2 +-
include/configs/am3517_evm.h |2 +-
include
Enable the OMAP3 specific errata code for 454179, 430973, 621766
and while at it, remove legacy non-revision checked errata logic.
Signed-off-by: Nishanth Menon n...@ti.com
---
arch/arm/cpu/armv7/omap3/board.c | 31 ++-
include/configs/am3517_crane.h |4
Update to existing recommendation for L2ACTLR configuration to prevent
system instability and optimize performance.
These apply to both OMAP5 and DRA7.
Reported-by: Vivek Chengalvala vchengalv...@ti.com
Signed-off-by: Nishanth Menon n...@ti.com
---
arch/arm/cpu/armv7/omap5/hwinit.c | 16
/?t=14254216681r=1w=2
Signed-off-by: Nishanth Menon n...@ti.com
---
arch/arm/cpu/armv7/omap-common/lowlevel_init.S | 18 +++---
arch/arm/cpu/armv7/omap4/hwinit.c |4 ++--
arch/arm/include/asm/arch-omap4/sys_proto.h|4 +++-
arch/arm/include/asm
On Wed, Mar 11, 2015 at 11:00 AM, Tom Rini tr...@konsulko.com wrote:
On Wed, Mar 11, 2015 at 10:53:41AM -0500, Nishanth Menon wrote:
On Wed, Mar 11, 2015 at 10:48 AM, Tom Rini tr...@konsulko.com wrote:
On Mon, Mar 09, 2015 at 05:12:05PM -0500, Nishanth Menon wrote:
omap_smc1 is now generic
On Wed, Mar 11, 2015 at 10:48 AM, Tom Rini tr...@konsulko.com wrote:
On Mon, Mar 09, 2015 at 05:12:05PM -0500, Nishanth Menon wrote:
omap_smc1 is now generic enough to remove duplicate
omap3_gp_romcode_call logic that omap3 introduced.
As part of this change, move to using the generic
On Thu, Mar 5, 2015 at 3:36 PM, Tom Rini tr...@konsulko.com wrote:
On Thu, Mar 05, 2015 at 11:49:05AM -0600, Nishanth Menon wrote:
On 03/05/2015 08:00 AM, Matt Porter wrote:
On Tue, Mar 03, 2015 at 04:26:22PM -0600, Nishanth Menon wrote:
set_pl310_ctrl_reg does use the Secure Monitor Call
On 03/05/2015 10:40 PM, Nishanth Menon wrote:
The fifth incarnation should be proper, I hope. (skipping all the
blurb and pointing to v1 for the blurb).
Changes since v4:
- smc is back to handassembled thanks to gcc versions
- fixes in multiple call handling within cpu_init_cp15
On 03/06/2015 09:43 AM, Tom Rini wrote:
On Thu, Jan 29, 2015 at 10:25:20AM -0600, Nishanth Menon wrote:
Synchronize with the implementation from v3.18 tag. This allows us to
use a standardized 64 bit ops on architectures that do not natively
support 64 bit (example: 32bit ARM)
Signed-off
On 03/06/2015 11:08 AM, Tom Rini wrote:
On Thu, Mar 05, 2015 at 10:41:00PM -0600, Nishanth Menon wrote:
set_pl310_ctrl_reg does use the Secure Monitor Call (SMC) to setup
PL310 control register, however, that is something that is generic
enough to be used for OMAP5 generation of processors
On 03/06/2015 11:05 AM, Tom Rini wrote:
On Thu, Mar 05, 2015 at 10:41:04PM -0600, Nishanth Menon wrote:
Update to existing recommendation for L2ACTLR configuration to prevent
system instability and optimize performance.
These apply to both OMAP5 and DRA7.
Reported-by: Vivek Chengalvala
On 03/03/2015 05:10 AM, Dileep Katta wrote:
Adds the registers to get the serial number of dra7xx boards.
Serial# environment variable will be set if not done already.
This will be useful to show correct information in
fastboot devices commands.
Signed-off-by: Angela Stegmaier
to override the same. I tried to do something
like that for CP15 errata[1]
just my 2 cents.
[1] http://article.gmane.org/gmane.comp.boot-loaders.u-boot/214436
--
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/asm/pl310.h
@@ -16,6 +16,8 @@
#define L2X0_STNDBY_MODE_EN(1 0)
#define L2X0_CTRL_EN1
+#define L310_SHARED_ATT_OVERRIDE_ENABLE(1 22)
+
struct pl310_regs {
u32 pl310_cache_id;
u32 pl310_cache_type;
--
Regards,
Nishanth Menon
On Thu, Mar 12, 2015 at 10:15 AM, Fabio Estevam feste...@gmail.com wrote:
On Thu, Mar 12, 2015 at 11:43 AM, Nishanth Menon n...@ti.com wrote:
I dont think this works for OMAP4 (which also uses A9, PL310) - we use
an smc #0 with service 0x109 (I have to reconfirm) to set l2 aux_ctrl.
https
On 03/05/2015 11:56 AM, Nishanth Menon wrote:
On 03/05/2015 10:21 AM, Matt Porter wrote:
On Tue, Mar 03, 2015 at 04:26:17PM -0600, Nishanth Menon wrote:
The fourth incarnation of this series to address review comments on V3
With all the usual disclaimers and request to see V1 of the series
On Wed, Mar 11, 2015 at 10:48 AM, Tom Rini tr...@konsulko.com wrote:
On Mon, Mar 09, 2015 at 05:11:58PM -0500, Nishanth Menon wrote:
The sixth revision should be proper, I hope. (skipping all the
blurb and pointing to v1 for the blurb).
Changes since v5:
- omap_smc1 is now
=0x0040
--
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On 02/25/2015 02:55 PM, Nishanth Menon wrote:
Add workaround for Cortex-A15 ARM erratum 798870 which says
If back-to-back speculative cache line fills (fill A and fill B) are
issued from the L1 data cache of a CPU to the L2 cache, the second
request (fill B) is then cancelled, and the second
On 03/03/2015 11:08 AM, Tom Rini wrote:
On Wed, Feb 25, 2015 at 02:55:13PM -0600, Nishanth Menon wrote:
set_pl310_ctrl_reg does use the Secure Monitor Call (SMC) to setup
PL310 control register, however, that is something that is generic
enough to be used for OMAP5 generation of processors
On 02/18/2015 09:35 AM, menon.nisha...@gmail.com wrote:
On Wed, Feb 18, 2015 at 7:12 AM, Vitaly Andrianov vita...@ti.com wrote:
On 02/17/2015 05:47 PM, Nishanth Menon wrote:
On Tue, Feb 17, 2015 at 4:27 PM, Murali Karicheri m-kariche...@ti.com
wrote:
is complete the boot-loader sets
On 03/03/2015 11:12 AM, Nishanth Menon wrote:
On 03/03/2015 11:08 AM, Tom Rini wrote:
On Wed, Feb 25, 2015 at 02:55:13PM -0600, Nishanth Menon wrote:
set_pl310_ctrl_reg does use the Secure Monitor Call (SMC) to setup
PL310 control register, however, that is something that is generic
enough
if needed.
Based on ARM errata Document revision 20.0 (13 Nov 2010)
Signed-off-by: Nishanth Menon n...@ti.com
---
README |1 +
arch/arm/cpu/armv7/cp15.c|6 ++
arch/arm/cpu/armv7/start.S | 13 +
arch/arm/include/asm/armv7.h |2 ++
4 files
430973: Stale prediction on replaced inter working branch causes
Cortex-A8 to execute in the wrong ARM/Thumb state
Impacts: Every Cortex-A8 processors with revision lower than r2p1
Work around: Set IBE to 1
Based on ARM errata Document revision 20.0 (13 Nov 2010)
Signed-off-by: Nishanth
Stegmaier angelaba...@ti.com
Signed-off-by: Nishanth Menon n...@ti.com
---
arch/arm/cpu/armv7/omap5/hwinit.c |7 +++
arch/arm/include/asm/arch-omap5/sys_proto.h |4
include/configs/ti_omap5_common.h |3 +++
3 files changed, 14 insertions(+)
diff --git
Monitor handling of Secure
Monitor Call(smc) is diverse. Hence an weak function is introduced
which may be overriden to implement SoC specific accessor implementation.
Based on ARM errata Document revision 18.0 (22 Nov 2013)
Signed-off-by: Nishanth Menon n...@ti.com
---
README
omap_smc1 is now generic enough to remove duplicate
omap3_gp_romcode_call logic that omap3 introduced.
As part of this change, move to using the generic lowlevel_init.S for
omap3 as well.
Signed-off-by: Nishanth Menon n...@ti.com
---
arch/arm/cpu/armv7/omap-common/Makefile|2
for sec extension builds (NOTE: we no longer use '-march=armv5' as the
legacy comment claims).
Signed-off-by: Nishanth Menon n...@ti.com
---
arch/arm/cpu/armv7/omap-common/Makefile|3 +++
arch/arm/cpu/armv7/omap-common/lowlevel_init.S | 17 ++---
arch/arm/cpu/armv7/omap4
This is in preperation of using generic cross OMAP code.
Signed-off-by: Nishanth Menon n...@ti.com
---
.../arm/include/asm/arch-omap3/{omap3.h = omap.h} |0
include/configs/am3517_crane.h |2 +-
include/configs/am3517_evm.h |2 +-
include
Enable the OMAP3 specific errata code for 454179, 430973, 621766
and while at it, remove legacy non-revision checked errata logic.
Signed-off-by: Nishanth Menon n...@ti.com
---
arch/arm/cpu/armv7/omap3/board.c | 31 ++-
include/configs/am3517_crane.h |4
On 03/05/2015 08:00 AM, Matt Porter wrote:
On Tue, Mar 03, 2015 at 04:26:22PM -0600, Nishanth Menon wrote:
set_pl310_ctrl_reg does use the Secure Monitor Call (SMC) to setup
PL310 control register, however, that is something that is generic
enough to be used for OMAP5 generation of processors
On 03/05/2015 10:21 AM, Matt Porter wrote:
On Tue, Mar 03, 2015 at 04:26:17PM -0600, Nishanth Menon wrote:
The fourth incarnation of this series to address review comments on V3
With all the usual disclaimers and request to see V1 of the series for a
detailed blurb.. As usual additional
-off-by: Nishanth Menon n...@ti.com
---
README |1 +
arch/arm/cpu/armv7/start.S | 13 +
2 files changed, 14 insertions(+)
diff --git a/README b/README
index 484ae9ee39a8..5ee789aea627 100644
--- a/README
+++ b/README
@@ -626,6 +626,7 @@ The following options need
Update to existing recommendation for L2ACTLR configuration to prevent
system instability and optimize performance.
These apply to both OMAP5 and DRA7.
Reported-by: Vivek Chengalvala vchengalv...@ti.com
Signed-off-by: Nishanth Menon n...@ti.com
---
arch/arm/cpu/armv7/omap5/hwinit.c | 16
dont have access to other omap3 platforms to give a better coverage
Sanity check:
OMAP4Panda-ES: http://pastebin.ubuntu.com/10518971/
Nishanth Menon (10):
ARM: Introduce erratum workaround for 798870
ARM: Introduce erratum workaround for 454179
ARM: Introduce erratum workaround for 430973
-by: Nishanth Menon n...@ti.com
---
arch/arm/cpu/armv7/omap3/board.c| 45 ---
arch/arm/include/asm/arch-omap3/sys_proto.h |1 +
board/nokia/rx51/rx51.c | 19 ++-
include/configs/nokia_rx51.h|4 +++
4 files changed
?
Do I understand that Angela is ok with the same? please confirm.
Should have sent it
as RFC patch, as this is not verified due to unavailability of board.
Hmm... interesting maybe Vish can help here?
[...]
--
Regards,
Nishanth Menon
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--
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On Wed, Feb 25, 2015 at 2:27 AM, Akshay Saraswat aksha...@samsung.com wrote:
Hi Nishanth,
On 17:13-20150224, Nishanth Menon wrote:
On 13:27-20150220, Akshay Saraswat wrote:
This patch adds workaround for ARM errata 798870 which says
If back-to-back speculative cache line fills (fill
On Wed, Feb 25, 2015 at 5:02 AM, Paul Kocialkowski cont...@paulk.fr wrote:
Le mardi 24 février 2015 à 16:57 -0600, Nishanth Menon a écrit :
This is in preperation of using generic cross OMAP code.
I found it a bit confusing at first, since as far as I could see, this
series does not introduce
On 02/25/2015 05:15 AM, Paul Kocialkowski wrote:
Le mardi 24 février 2015 à 16:57 -0600, Nishanth Menon a écrit :
430973: Stale prediction on replaced inter working branch causes
Cortex-A8 to execute in the wrong ARM/Thumb state
Impacts: Everything lower than r2p1
Work around: Set IBE
omap_smc1 is now generic enough to remove duplicate
omap3_gp_romcode_call logic that omap3 introduced.
As part of this change, move to using the generic lowlevel_init.S for
omap3 as well.
Signed-off-by: Nishanth Menon n...@ti.com
---
arch/arm/cpu/armv7/omap-common/Makefile|2
-by: Nishanth Menon n...@ti.com
---
arch/arm/cpu/armv7/omap3/board.c| 45 ---
arch/arm/include/asm/arch-omap3/sys_proto.h |1 +
board/nokia/rx51/rx51.c | 19 ++-
include/configs/nokia_rx51.h|4 +++
4 files changed
Monitor handling of Secure
Monitor Call(smc) is diverse. Hence an weak function is introduced
which may be overriden to implement SoC specific accessor implementation.
Based on ARM errata Document revision 18.0 (22 Nov 2013)
Signed-off-by: Nishanth Menon n...@ti.com
---
README
Stegmaier angelaba...@ti.com
Signed-off-by: Nishanth Menon n...@ti.com
---
arch/arm/cpu/armv7/omap5/hwinit.c |7 +++
arch/arm/include/asm/arch-omap5/sys_proto.h |4
include/configs/ti_omap5_common.h |3 +++
3 files changed, 14 insertions(+)
diff --git
to a macro and use a generic name (same as
that used in Linux for some consistency). While at that, also add
a data barrier which is necessary as per recommendation.
Signed-off-by: Nishanth Menon n...@ti.com
---
arch/arm/cpu/armv7/omap-common/lowlevel_init.S | 13 -
arch/arm/cpu/armv7/omap4
Update to existing recommendation for L2ACTLR configuration to prevent
system instability and optimize performance.
These apply to both OMAP5 and DRA7.
Reported-by: Vivek Chengalvala vchengalv...@ti.com
Signed-off-by: Nishanth Menon n...@ti.com
---
arch/arm/cpu/armv7/omap5/hwinit.c | 16
Enable the OMAP3 specific errata code for 454179, 430973, 621766
and while at it, remove legacy non-revision checked errata logic.
Signed-off-by: Nishanth Menon n...@ti.com
---
arch/arm/cpu/armv7/omap3/board.c | 31 ++-
include/configs/am3517_crane.h |4
This is in preperation of using generic cross OMAP code.
Signed-off-by: Nishanth Menon n...@ti.com
---
.../arm/include/asm/arch-omap3/{omap3.h = omap.h} |0
include/configs/am3517_crane.h |2 +-
include/configs/am3517_evm.h |2 +-
include
if needed.
Based on ARM errata Document revision 20.0 (13 Nov 2010)
Signed-off-by: Nishanth Menon n...@ti.com
---
README |1 +
arch/arm/cpu/armv7/cp15.c|6 ++
arch/arm/cpu/armv7/start.S | 11 +++
arch/arm/include/asm/armv7.h |2 ++
4 files changed
/
- Rearranged the series to address generic ARM first followed by rest.
V2: http://comments.gmane.org/gmane.comp.boot-loaders.u-boot/213060
V1: http://comments.gmane.org/gmane.comp.boot-loaders.u-boot/212174
Nishanth Menon (10):
ARM: Introduce erratum workaround for 798870
ARM: Introduce erratum
430973: Stale prediction on replaced inter working branch causes
Cortex-A8 to execute in the wrong ARM/Thumb state
Impacts: Every Cortex-A8 processors with revision lower than r2p1
Work around: Set IBE to 1
Based on ARM errata Document revision 20.0 (13 Nov 2010)
Signed-off-by: Nishanth
-off-by: Nishanth Menon n...@ti.com
---
README |1 +
arch/arm/cpu/armv7/start.S | 11 +++
2 files changed, 12 insertions(+)
diff --git a/README b/README
index 484ae9ee39a8..5ee789aea627 100644
--- a/README
+++ b/README
@@ -626,6 +626,7 @@ The following options need
On 02/25/2015 01:55 PM, Kevin Hilman wrote:
Nishanth Menon n...@ti.com writes:
On 13:27-20150220, Akshay Saraswat wrote:
This patch adds workaround for ARM errata 798870 which says
If back-to-back speculative cache line fills (fill A and fill B) are
issued from the L1 data cache of a CPU
On Tue, Feb 24, 2015 at 6:02 AM, Paul Kocialkowski cont...@paulk.fr wrote:
Le lundi 23 février 2015 à 16:43 -0600, Nishanth Menon a écrit :
On Mon, Feb 23, 2015 at 4:21 PM, Tom Rini tr...@ti.com wrote:
On Mon, Feb 23, 2015 at 08:16:44PM +0100, Paul Kocialkowski wrote:
Not every version
On Thu, Feb 26, 2015 at 1:40 AM, Siarhei Siamashka
siarhei.siamas...@gmail.com wrote:
On Wed, 25 Feb 2015 14:55:08 -0600
Nishanth Menon n...@ti.com wrote:
Hi,
The third incarnation of this series to address various ideas of
previous V2 series. I will skip the full blurb and point to V1/V2
, etc).
I think we have maintained ti_ prefix for omap3,4,5 etc.. might make
sense to retain that.. but then, I am no decision maker in that regards,
I suggest posting a proposal and seeing feedback folks have w.r.t.
--
Regards,
Nishanth Menon
___
U
://pastebin.ubuntu.com/10397352/
v2015.04-rc1+ this series: http://pastebin.ubuntu.com/10397267/
(same sets of failures of build - no regressions introduced that I could see).
Angela Stegmaier (1):
configs: ti_omap5_common: Enable workaround for ARM errata 798870
Nishanth Menon (7):
ARM: OMAP: Change
Every SoC has slightly different manner of setting up access
to L2ACLR and similar registers since the Secure Monitor handling
of Secure Monitor Call(smc) is diverse. Hence an ARCH specific
macro is introduced to implement SoC specific errata workaround
implementations.
Signed-off-by: Nishanth
This is in preperation of using generic cross OMAP code.
Signed-off-by: Nishanth Menon n...@ti.com
---
.../arm/include/asm/arch-omap3/{omap3.h = omap.h} |0
include/configs/am3517_crane.h |2 +-
include/configs/am3517_evm.h |2 +-
include
to a macro and use a generic name (same as
that used in Linux for some consistency). While at that, also add
a data barrier which is necessary as per recommendation.
Signed-off-by: Nishanth Menon n...@ti.com
---
arch/arm/cpu/armv7/omap-common/lowlevel_init.S | 13 -
arch/arm/cpu/armv7/omap4
Enable the OMAP3 specific errata code for 454179, 430973, 621766
and while at it, remove legacy non-revision checked errata logic.
Signed-off-by: Nishanth Menon n...@ti.com
---
arch/arm/cpu/armv7/omap3/board.c | 16
include/configs/ti_omap3_common.h |6 ++
2 files
Update to existing recommendation for L2ACTLR configuration to prevent
system instability and optimize performance.
These apply to both OMAP5 and DRA7.
Reported-by: Vivek Chengalvala vchengalv...@ti.com
Signed-off-by: Nishanth Menon n...@ti.com
---
arch/arm/cpu/armv7/omap5/hwinit.c
On 02/24/2015 10:09 AM, Paul Kocialkowski wrote:
Le mardi 24 février 2015 à 09:22 -0600, Nishanth Menon a écrit :
On Tue, Feb 24, 2015 at 6:02 AM, Paul Kocialkowski cont...@paulk.fr wrote:
Le lundi 23 février 2015 à 16:43 -0600, Nishanth Menon a écrit :
On Mon, Feb 23, 2015 at 4:21 PM, Tom
/
--
Regards,
Nishanth Menon
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Every SoC has slightly different manner of setting up access
to L2ACLR and similar registers since the Secure Monitor handling
of Secure Monitor Call(smc) is diverse. Hence an ARCH specific
macro is introduced to implement SoC specific errata workaround
implementations.
Signed-off-by: Nishanth
-off-by: Praveen Rao p...@ti.com
Signed-off-by: Angela Stegmaier angelaba...@ti.com
Signed-off-by: Nishanth Menon n...@ti.com
---
README |1 +
arch/arm/cpu/armv7/omap5/Makefile |1 +
arch/arm/cpu/armv7/omap5/lowlevel_init.S| 46
This is in preperation of using generic cross OMAP code.
Signed-off-by: Nishanth Menon n...@ti.com
---
.../arm/include/asm/arch-omap3/{omap3.h = omap.h} |0
include/configs/am3517_crane.h |2 +-
include/configs/am3517_evm.h |2 +-
include
From: Angela Stegmaier angelaba...@ti.com
Enable the workaround for ARM errata 798870 for OMAP5
and DRA7xx since they are Coretx-A15 r2.
Signed-off-by: Angela Stegmaier angelaba...@ti.com
Signed-off-by: Nishanth Menon n...@ti.com
---
include/configs/ti_omap5_common.h |4
1 file changed
-off-by: Praveen Rao p...@ti.com
Signed-off-by: Angela Stegmaier angelaba...@ti.com
Signed-off-by: Nishanth Menon n...@ti.com
---
README |1 +
arch/arm/cpu/armv7/omap5/Makefile |1 +
arch/arm/cpu/armv7/omap5/lowlevel_init.S| 46
On 17:13-20150224, Nishanth Menon wrote:
On 13:27-20150220, Akshay Saraswat wrote:
This patch adds workaround for ARM errata 798870 which says
If back-to-back speculative cache line fills (fill A and fill B) are
issued from the L1 data cache of a CPU to the L2 cache, the second
request
).
Angela Stegmaier (1):
configs: ti_omap5_common: Enable workaround for ARM errata 798870
Nishanth Menon (7):
ARM: OMAP: Change set_pl310_ctrl_reg to be generic
ARM: OMAP3: Rename omap3.h to omap.h to be generic as all SoCs
ARM: OMAP3: Get rid of omap3_gp_romcode_call and replace
to a macro and use a generic name (same as
that used in Linux for some consistency). While at that, also add
a data barrier which is necessary as per recommendation.
Signed-off-by: Nishanth Menon n...@ti.com
---
arch/arm/cpu/armv7/omap-common/lowlevel_init.S | 13 -
arch/arm/cpu/armv7/omap4
From: Angela Stegmaier angelaba...@ti.com
Enable the workaround for ARM errata 798870 for OMAP5
and DRA7xx since they are Coretx-A15 r2.
Signed-off-by: Angela Stegmaier angelaba...@ti.com
Signed-off-by: Nishanth Menon n...@ti.com
---
include/configs/ti_omap5_common.h |4
1 file changed
Enable the OMAP3 specific errata code for 454179, 430973, 621766
and while at it, remove legacy non-revision checked errata logic.
Signed-off-by: Nishanth Menon n...@ti.com
---
arch/arm/cpu/armv7/omap3/board.c | 16
include/configs/ti_omap3_common.h |6 ++
2 files
omap_smc1 is now generic enough to remove duplicate
omap3_gp_romcode_call logic that omap3 introduced.
As part of this change, move to using the generic lowlevel_init.S for
omap3 as well.
Signed-off-by: Nishanth Menon n...@ti.com
---
arch/arm/cpu/armv7/omap-common/Makefile|2
the OMAP3 generation of processors have a wide variety of CPU
revisions, it is more logical to enforce an implementation using
revision checks.
Signed-off-by: Nishanth Menon n...@ti.com
---
README |3 +++
arch/arm/cpu/armv7/omap3/board.c|2
/?t=14254216681r=1w=2
Signed-off-by: Nishanth Menon n...@ti.com
---
change since V4:
- back to handcoding smc #0
arch/arm/cpu/armv7/omap-common/lowlevel_init.S | 18 +++---
arch/arm/cpu/armv7/omap4/hwinit.c |4 ++--
arch/arm/include/asm/arch-omap4
Monitor handling of Secure
Monitor Call(smc) is diverse. Hence an weak function is introduced
which may be overriden to implement SoC specific accessor implementation.
Based on ARM errata Document revision 18.0 (22 Nov 2013)
Signed-off-by: Nishanth Menon n...@ti.com
---
Change since V4
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