Re: [U-Boot] cadence_qspi_apb: cache issues on mach-socfpga

Goldschmidt Simon Wrote: >Marek Vasut wrote: I don't believe the patchset I submitted for DT bindings were merged in. >>> >>> I can confirm that. I'd strongly vote for them to get in as cadence_qspi >>> is otherwise not usable on mach socfpga. >>> >>> How can I ensure a tested-by from me gets

Re: [U-Boot] cadence_qspi_apb: cache issues on mach-socfpga

Goldschmidt Simon wrote: > Hi, > > I ran into the same issue with the cadence qspi driver and dcache as Jason > reported (in febuary, I think - I started to monitor U-Boot in july only). > > May I ask what's the status here? I do need fixes for this to keep > mach-socfpga running with qspi. I

[U-Boot] [PATCH 3/4] dts: k2g: Add trigger-address property to QSPI device

Add the 'cdns,trigger-address' property to the cadence QSPI device node for Texas Instruments K2G SoC devices. Signed-off-by: Jason A. Rush --- arch/arm/dts/keystone-k2g.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/dts/keystone-k2g.dtsi

[U-Boot] [PATCH 4/4] dts: stv0991: Add trigger-address property to QSPI device

Add the 'cdns,trigger-address' property to the cadence QSPI device node for the ST STV0991 application board. Signed-off-by: Jason A. Rush --- arch/arm/dts/stv0991.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/dts/stv0991.dts b/arch/arm/dts/stv0991.dts

[U-Boot] [PATCH 0/4] spi: cadence_spi: Add cdns, trigger-address DT property

This patch series addresses an issue with the indaddrtrig register on the Cadence QSPI device being programmed with the wrong value for the socfpga arch. Adopting the trigger-address DT bindings from the Linux kernel allows the indaddrtrig register to be set independently from the ahbbase as

[U-Boot] [PATCH 1/4] spi: cadence_spi: Add cdns, trigger-address DT property

The socfpga arch uses a different value for the indaddrtrig reg than the ahbbase address. Adopting the cdns,trigger-address DT bindings from the Linux kernel allows the trigger-address to be set correctly on the socfpga arch. Tested on Terasic SoCKit dev board (Altera Cyclone V) Signed-off-by:

Re: [U-Boot] [PATCH v2 2/8] Revert "spi: cadence_qspi_apb: Use 32 bit indirect read transaction when possible"

Marek Vasut wrote: > On 03/14/2017 03:23 PM, Rush, Jason A. wrote: >> Marek Vasut wrote: >>> On 03/07/2017 04:18 PM, Rush, Jason A. wrote: >>>> Marek Vasut wrote: >>>>> On 03/03/2017 04:17 PM, Rush, Jason A. wrote: >>>>>> Marek Va

Re: [U-Boot] [PATCH v2 2/8] Revert "spi: cadence_qspi_apb: Use 32 bit indirect read transaction when possible"

Marek Vasut wrote: > On 03/07/2017 04:18 PM, Rush, Jason A. wrote: >> Marek Vasut wrote: >>> On 03/03/2017 04:17 PM, Rush, Jason A. wrote: >>>> Marek Vasut wrote: >>>>> On 03/01/2017 05:36 PM, Rush, Jason A. wrote: >>>>>&g

Re: [U-Boot] [PATCH v2 2/8] Revert "spi: cadence_qspi_apb: Use 32 bit indirect read transaction when possible"

Marek Vasut wrote: > On 03/03/2017 04:17 PM, Rush, Jason A. wrote: >> Marek Vasut wrote: >>> On 03/01/2017 05:36 PM, Rush, Jason A. wrote: >>>> This reverts commit b63b46313ed29e9b0c36b3d6b9407f6eade40c8f. >>>> >>>> The Cade

Re: [U-Boot] [PATCH v2 2/8] Revert "spi: cadence_qspi_apb: Use 32 bit indirect read transaction when possible"

Marek Vasut wrote: > On 03/01/2017 05:36 PM, Rush, Jason A. wrote: >> This reverts commit b63b46313ed29e9b0c36b3d6b9407f6eade40c8f. >> >> The Cadence QSPI device does not work with caching (introduced with >> the bounce buffer in this commit) on the Altera SoC platform.

Re: [U-Boot] [PATCH v2 6/8] dts: socfpga: Add trigger-address property to QSPI device

Dinh Nguyen wrote: > Hi Jason, > > On 03/01/2017 10:38 AM, Rush, Jason A. wrote: >> Add the 'cdns,trigger-address' property to the cadence QSPI device >> node for Altera SoC devices. >> >> Signed-off-by: Jason A. Rush <jason.r...@gd-ms.com> >> ---

[U-Boot] [PATCH v2 8/8] dts: stv0991: Add trigger-address property to QSPI device

Add the 'cdns,trigger-address' property to the cadence QSPI device node for the ST STV0991 application board. Signed-off-by: Jason A. Rush --- Changed in v2: - renamed trigger-base to trigger-address arch/arm/dts/stv0991.dts | 1 + 1 file changed, 1 insertion(+) diff

[U-Boot] [PATCH v2 7/8] dts: k2g: Add trigger-address property to QSPI device

Add the 'cdns,trigger-address' property to the cadence QSPI device node for Texas Instruments K2G SoC devices. Signed-off-by: Jason A. Rush --- Changed in v2: - renamed trigger-base to trigger-address arch/arm/dts/keystone-k2g.dtsi | 1 + 1 file changed, 1 insertion(+)

[U-Boot] [PATCH v2 6/8] dts: socfpga: Add trigger-address property to QSPI device

Add the 'cdns,trigger-address' property to the cadence QSPI device node for Altera SoC devices. Signed-off-by: Jason A. Rush --- Changed in v2: - renamed trigger-base to trigger-address arch/arm/dts/socfpga.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git

[U-Boot] [PATCH v2 5/8] spi: cadence_spi: Add cdns, trigger-address DT property

The socfpga arch uses a different value for the indaddrtrig reg than the ahbbase address. Adopting the trigger-address DT bindings from the Linux kernel allows the indaddrtrig reg to be set correctly on the socfpga arch. Tested on Terasic SoCKit dev board (Altera Cyclone V) Signed-off-by: Jason

[U-Boot] [PATCH v2 4/8] spi: cadence_qspi: Cleanup register loading/accesses

Load the regbase/ahbbase 'reg' DT properties using the standard dev_get_addr_index function, and add __iomem to all register variables declarations. Signed-off-by: Jason A. Rush --- Changed in v2: None drivers/spi/cadence_qspi.c | 25 ++---

[U-Boot] [PATCH v2 3/8] spi: cadence_qspi_apb: Use 32 bit indirect write transaction when possible

From: Vignesh R According to Section 11.15.4.9.2 Indirect Write Controller of K2G SoC TRM SPRUHY8D[1], the external master is only permitted to issue 32-bit data interface writes until the last word of an indirect transfer otherwise indirect writes is known to fails sometimes.

[U-Boot] [PATCH v2 2/8] Revert "spi: cadence_qspi_apb: Use 32 bit indirect read transaction when possible"

This reverts commit b63b46313ed29e9b0c36b3d6b9407f6eade40c8f. The Cadence QSPI device does not work with caching (introduced with the bounce buffer in this commit) on the Altera SoC platform. Signed-off-by: Jason A. Rush --- Changed in v2: None

[U-Boot] [PATCH v2 1/8] Revert "spi: cadence_qspi_apb: Use 32 bit indirect write transaction when possible"

This reverts commit 57897c13de03ac0136d64641a3eab526c6810387. The Cadence QSPI device does not work with caching (introduced with the bounce buffer in this commit) on the Altera SoC platform. Signed-off-by: Jason A. Rush --- Changed in v2: None

[U-Boot] [PATCH v2 0/8] spi: cadence: Fix read/write on socfpga

This patch series addresses two problems with reads/writes not working with the Cadence QSPI device on the socfpga arch. The first issue is reads/writes to the Cadence QSPI device do not work correctly with caching enabled on the socfpga. This problem was introduced with previous commits that use

Re: [U-Boot] [PATCH] spi: cadence_qspi_apb: Add trigger-base DT bindings from Linux

R, Vignesh wrote: > On 2/28/2017 8:38 PM, Rush, Jason A. wrote: > [...] >> >> This also works. >> >> Marek - how do you feel about a patch series with the following: >> >> 1. revert commit 57897c13de03ac0136d64641a3eab526c6810387 >> spi: cadence

Re: [U-Boot] [PATCH] spi: cadence_qspi_apb: Add trigger-base DT bindings from Linux

I don't know if this message successfully sent last weekend. My mail server was undergoing maintenance, and I didn't see my original message on the u-boot mailing list archive. So I'm resending, my apologies if this is a repost. R, Vignesh wrote: > On 2/25/2017 1:25 AM, Rush, Jason A. wr

Re: [U-Boot] [PATCH] spi: cadence_qspi_apb: Add trigger-base DT bindings from Linux

R, Vignesh wrote: > On 2/24/2017 12:55 AM, Marek Vasut wrote: >> On 02/23/2017 08:22 PM, Rush, Jason A. wrote: >>> Marek Vasut wrote: >>>> On 02/22/2017 06:37 PM, Rush, Jason A. wrote: >>>>> Marek Vasut wrote: >>>>>> On 02/

Re: [U-Boot] [PATCH] spi: cadence_qspi_apb: Add trigger-base DT bindings from Linux

Marek Vasut wrote: > On 02/22/2017 06:37 PM, Rush, Jason A. wrote: >> Marek Vasut wrote: >>> On 02/21/2017 05:50 PM, Rush, Jason A. wrote: >>>> The socfpga arch uses a different value for the indaddrtrig reg than >>>> the ahbbase address. Adopting the Li

Re: [U-Boot] [PATCH] spi: cadence_qspi_apb: Add trigger-base DT bindings from Linux

Marek Vasut wrote: > On 02/21/2017 05:50 PM, Rush, Jason A. wrote: >> The socfpga arch uses a different value for the indaddrtrig reg than >> the ahbbase address. Adopting the Linux DT bindings separates the >> ahbbase and trigger-base addresses, allowing the trigger-base to

[U-Boot] [PATCH] spi: cadence_qspi_apb: Add trigger-base DT bindings from Linux

The socfpga arch uses a different value for the indaddrtrig reg than the ahbbase address. Adopting the Linux DT bindings separates the ahbbase and trigger-base addresses, allowing the trigger-base to be+ set correctly on the socfpga arch. Tested on Terasic SoCkit dev board (Altera Cyclone V)

Re: [U-Boot] socfpga qspi issues on SoCKit devkit

Marek Vasut wrote: > On 02/20/2017 05:53 PM, Rush, Jason A. wrote: >> Marek Vasut wrote: >>> On 02/20/2017 05:25 AM, Vignesh R wrote: >>>> + Marek >>> >>> Thanks, +CC Dinh and Ley >>> >>>> On Friday 17 February 2017 05:02 AM, Rus

Re: [U-Boot] socfpga qspi issues on SoCKit devkit

Marek Vasut wrote: > On 02/20/2017 05:25 AM, Vignesh R wrote: >> + Marek > > Thanks, +CC Dinh and Ley > >> On Friday 17 February 2017 05:02 AM, Rush, Jason A. wrote: >>> The QSPI NOR interface on the Altera Cyclone V SoCKit devkit (Rev B) appears >>>

[U-Boot] socfpga qspi issues on SoCKit devkit

The QSPI NOR interface on the Altera Cyclone V SoCKit devkit (Rev B) appears to be broken in the current release. I've tracked it down to working in the v2016.07 release, but broken in the the v2016.09 release. With the help of git bisect, I tracked down the commit that breaks the QSPI to the