This run is configured for baseline tests only.
flight 71957 ovmf real [real]
http://osstest.xs.citrite.net/~osstest/testlogs/logs/71957/
Perfect :-)
All tests in this flight passed as required
version targeted for testing:
ovmf 7ef0dae092afcfb6fab7e8372c78097672168c4a
baseline
flight 112536 xen-unstable real [real]
http://logs.test-lab.xenproject.org/osstest/logs/112536/
Failures :-/ but no regressions.
Regressions which are regarded as allowable (not blocking):
test-amd64-amd64-xl-qemuu-win7-amd64 17 guest-stop fail REGR. vs. 112526
Tests which did not
Hi,
On Aug 7 2017 21:22, Oleksandr Andrushchenko wrote:
From: Oleksandr Andrushchenko
This patch series adds support for Xen [1] para-virtualized
sound frontend driver. It implements the protocol from
include/xen/interface/io/sndif.h with the following
flight 112539 ovmf real [real]
http://logs.test-lab.xenproject.org/osstest/logs/112539/
Perfect :-)
All tests in this flight passed as required
version targeted for testing:
ovmf 7ef0dae092afcfb6fab7e8372c78097672168c4a
baseline version:
ovmf
From: Chao Gao
If a vIOMMU is exposed to guest, guest will configure the msi to remapping
format. The original code isn't suitable to the new format. A new pair
bind/unbind interfaces are added for this usage. This patch recognizes
this case and uses new interfaces to
This patchset is to deal with MSI interrupt remapping request when guest
updates MSI registers.
Chao Gao (3):
i386/msi: Correct mask of destination ID in MSI address
xen-pt: bind/unbind interrupt remapping format MSI
msi: Handle remappable format interrupt request
configure
From: Chao Gao
According to VT-d spec Interrupt Remapping and Interrupt Posting ->
Interrupt Remapping -> Interrupt Request Formats On Intel 64
Platforms, fields of MSI data register have changed. This patch
avoids wrongly regarding a remappable format interrupt request as
an
From: Chao Gao
According to SDM 10.11.1, only [19:12] bits of MSI address are
Destination ID, change the mask to avoid ambiguity for VT-d spec
has used the bit 4 to indicate a remappable interrupt request.
Signed-off-by: Chao Gao
Signed-off-by: Lan
From: Chao Gao
Wrap some useful status in a new structure hvm_hw_vvtd, following
the customs of vlapic, vioapic and etc. Provide two save-restore
pairs to save/restore registers and non-register status.
Signed-off-by: Chao Gao
Signed-off-by: Lan Tianyu
From: Chao Gao
When IOAPIC RTE is in remapping format, it doesn't contain the vector of
interrupt. For this case, the RTE contains an index of interrupt remapping
table where the vector of interrupt is stored. This patchs gets the vector
through a vIOMMU interface.
From: Chao Gao
In two situations, hypervisor delivers a msi to a hvm guest. One is
when qemu sends a request to hypervisor through XEN_DMOP_inject_msi.
The other is when a physical interrupt arrives and it has been bound
to a guest msi.
For the former, the msi is routed to
From: Chao Gao
Software writes to QIE fields of GCMD to enable or disable queued
invalidations. This patch emulates QIE fields of GCMD.
Signed-off-by: Chao Gao
Signed-off-by: Lan Tianyu
---
xen/drivers/passthrough/vtd/iommu.h | 3
From: Chao Gao
Software sets this field to set/update the interrupt remapping table pointer
used by hardware. The interrupt remapping table pointer is specified through
the Interrupt Remapping Table Address (IRTA_REG) register.
This patch emulates this operation and adds
From: Chao Gao
A new logic is added to build ACPI DMAR table in tool stack for a guest
with one virtual VTD and pass through it to guest via existing mechanism. If
there already are ACPI tables needed to pass through, we joint the tables.
Signed-off-by: Chao Gao
From: Chao Gao
Queued Invalidation Interface is an expanded invalidation interface with
extended capabilities. Hardware implementations report support for queued
invalidation interface through the Extended Capability Register. The queued
invalidation interface uses an
From: Chao Gao
When a remapping interrupt request arrives, remapping hardware computes the
interrupt_index per the algorithm described in VTD spec
"Interrupt Remapping Table", interprets the IRTE and generates a remapped
interrupt request.
This patch introduces
From: Chao Gao
Interrupt translation faults are non-recoverable fault. When faults
are triggered, it needs to populate fault info to Fault Recording
Registers and inject vIOMMU msi interrupt to notify guest IOMMU driver
to deal with faults.
This patch emulates hardware's
From: Chao Gao
When irq remapping is enabled, IOAPIC Redirection Entry may be in remapping
format. If that, generate an irq_remapping_request and call the common
VIOMMU abstraction's callback to handle this interrupt request. Device
model is responsible for checking the
From: Chao Gao
Software writes this field to enable/disable interrupt reampping. This patch
emulate IRES field of GCMD.
Signed-off-by: Chao Gao
Signed-off-by: Lan Tianyu
---
xen/drivers/passthrough/vtd/iommu.h | 3 ++-
From: Chao Gao
No functional change. It is a preparation for introducing new fields in
hvm_gmsi_info to manage remapping format msi bound to a physical msi.
Signed-off-by: Chao Gao
Signed-off-by: Lan Tianyu
---
From: Chao Gao
Previously, interrupt attributes can be extracted from msi message or
IOAPIC RTE. However, with interrupt remapping enabled, the attributes
are enclosed in the associated IRTE. This callback is for cases in
which the caller wants to acquire interrupt
From: Chao Gao
Introduce a new binding relationship and provide a new interface to
manage the new relationship.
Signed-off-by: Chao Gao
Signed-off-by: Lan Tianyu
---
tools/libxc/include/xenctrl.h | 17 ++
From: Chao Gao
This patch adds create/destroy/query function for the emulated VTD
and adapts it to the common VIOMMU abstraction.
Signed-off-by: Chao Gao
Signed-off-by: Lan Tianyu
---
xen/drivers/passthrough/vtd/Makefile | 7 +-
From: Chao Gao
The BIOS reports the remapping hardware units in a platform to system software
through the DMA Remapping Reporting (DMAR) ACPI table.
New fields are introduces for DMAR table. These new fields are set by
toolstack through parsing guest's config file.
From: Chao Gao
This patch adds VVTD MMIO handler to deal with MMIO access.
Signed-off-by: Chao Gao
Signed-off-by: Lan Tianyu
---
xen/drivers/passthrough/vtd/vvtd.c | 114 +
1 file changed, 114
From: Chao Gao
If guest is configured to have a vIOMMU, create it during domain construction.
Signed-off-by: Chao Gao
Signed-off-by: Lan Tianyu
---
tools/libxl/libxl_x86.c | 28
1 file changed, 28
This patch is to add irq request callback for platform implementation
to deal with irq remapping request.
Signed-off-by: Lan Tianyu
---
xen/common/viommu.c | 15 +
xen/include/asm-x86/viommu.h | 73
This patch is to introduce create, destroy and query capabilities
command for vIOMMU. vIOMMU layer will deal with requests and call
arch vIOMMU ops.
Signed-off-by: Lan Tianyu
---
xen/common/domctl.c | 3 +++
xen/common/viommu.c | 43
This patch is to add Xen virtual IOMMU doc to introduce motivation,
framework, vIOMMU hypercall and xl configuration.
Signed-off-by: Lan Tianyu
---
docs/misc/viommu.txt | 139 +++
1 file changed, 139 insertions(+)
create
From: Chao Gao
Add dmar table structure according Chapter 8 "BIOS Considerations" of
VTd spec Rev. 2.4.
VTd
spec:http://www.intel.com/content/dam/www/public/us/en/documents/product-specifications/vt-directed-io-spec.pdf
Signed-off-by: Chao Gao
This patch is to add get_irq_info callback for platform implementation
to convert irq remapping request to irq info (E,G vector, dest, dest_mode
and so on).
Signed-off-by: Lan Tianyu
---
xen/common/viommu.c | 16
xen/include/asm-x86/viommu.h | 8
From: Chao Gao
This patch adds XEN_DOMCTL_viommu_op hypercall. This hypercall
comprises three sub-command:
- query capabilities of one specific type vIOMMU emulated by Xen
- create vIOMMU in Xen hypervisor, given viommu type, register-set location
and capabilities
- destroy
From: Chao Gao
A field, viommu_info, is added to struct libxl_domain_build_info. Several
attributes can be specified by guest config file for virtual IOMMU. These
attributes are used for DMAR construction and vIOMMU creation.
Signed-off-by: Chao Gao
Change since v1:
1) Fix coding style issues
2) Add definitions for vIOMMU type and capabilities
3) Change vIOMMU kconfig and select vIOMMU default on x86
4) Put vIOMMU creation in libxl__arch_domain_create()
5) Make vIOMMU structure of tool stack more general for
flight 112535 qemu-mainline real [real]
http://logs.test-lab.xenproject.org/osstest/logs/112535/
Regressions :-(
Tests which did not succeed and are blocking,
including tests which could not be run:
test-amd64-i386-xl-qemuu-win7-amd64 16 guest-localmigrate/x10 fail REGR. vs.
112456
flight 112538 xtf real [real]
http://logs.test-lab.xenproject.org/osstest/logs/112538/
Perfect :-)
All tests in this flight passed as required
version targeted for testing:
xtf 0e04400b8575048ed0b10e4ac571c63e0769dfac
baseline version:
xtf
On 08/09/2017 06:31 PM, Munehisa Kamata wrote:
Since commit d05d7f40791c ("Merge branch 'for-4.8/core' of
git://git.kernel.dk/linux-block") and 3fc9d690936f ("Merge branch
'for-4.8/drivers' of git://git.kernel.dk/linux-block"), blkfront_resume()
has been using an index for iterating ring_info
flight 112533 linux-3.18 real [real]
http://logs.test-lab.xenproject.org/osstest/logs/112533/
Failures and problems with tests :-(
Tests which did not succeed and are blocking,
including tests which could not be run:
build-arm64-pvops 3 capture-logs broken REGR. vs. 112102
flight 112531 linux-next real [real]
http://logs.test-lab.xenproject.org/osstest/logs/112531/
Regressions :-(
Tests which did not succeed and are blocking,
including tests which could not be run:
test-amd64-i386-xl-qemuu-debianhvm-amd64 7 xen-boot fail REGR. vs. 112529
Since commit d05d7f40791c ("Merge branch 'for-4.8/core' of
git://git.kernel.dk/linux-block") and 3fc9d690936f ("Merge branch
'for-4.8/drivers' of git://git.kernel.dk/linux-block"), blkfront_resume()
has been using an index for iterating ring_info to check request when
iterating blk_shadow in an
flight 112529 linux-linus real [real]
http://logs.test-lab.xenproject.org/osstest/logs/112529/
Regressions :-(
Tests which did not succeed and are blocking,
including tests which could not be run:
test-amd64-amd64-examine 7 reboot fail REGR. vs. 110515
On 09.08.17 14:58, Jan Beulich wrote:
On 09.08.17 at 12:10, wrote:
CC "THE REST" maintainers to get an opinion on the public headers.
Please be more specific as to what you expect - the only public
header affected here is ARM-specific.
On 08/08/17 21:08, Volodymyr
On 09/08/2017 22:06, Volodymyr Babchuk wrote:
Hi Julien,
On 09.08.17 23:34, Julien Grall wrote:
On 09/08/2017 20:44, Volodymyr Babchuk wrote:
On ARMv8, one of conditional exceptions (SMC that originates
from aarch32 state) have extra field in HCR.ISS encoding:
s/aarch32/AArch32/
Hi Julien,
On 09.08.17 23:34, Julien Grall wrote:
On 09/08/2017 20:44, Volodymyr Babchuk wrote:
On ARMv8, one of conditional exceptions (SMC that originates
from aarch32 state) have extra field in HCR.ISS encoding:
s/aarch32/AArch32/
s/have/has/
And the register is called HSR and not HCR.
This run is configured for baseline tests only.
flight 71956 ovmf real [real]
http://osstest.xs.citrite.net/~osstest/testlogs/logs/71956/
Perfect :-)
All tests in this flight passed as required
version targeted for testing:
ovmf 7111e46fdebca0e03f6ddfcb029522c2fe68c74b
baseline
This run is configured for baseline tests only.
flight 71955 xen-unstable real [real]
http://osstest.xs.citrite.net/~osstest/testlogs/logs/71955/
Regressions :-(
Tests which did not succeed and are blocking,
including tests which could not be run:
build-armhf 6 xen-build
On 09/08/2017 20:44, Volodymyr Babchuk wrote:
On ARMv8 architecture SMC instruction from aarch32 state can be conditional.
s/aarch32/AArch32/. But SMC instruction are conditional even on ARMv7.
The main difference is the ARMv8 architecture allows conditional SMCs to
be trapped even if they
On 09/08/2017 20:44, Volodymyr Babchuk wrote:
According to ARM architecture reference manual (ARM DDI 0487A.k page D7-1938,
Please quote a more recent ARM ARM. In general, please use the latest
ARM ARM when sending code specific to the architecture.
Assuming this will be fixed in the next
On 09/08/2017 20:44, Volodymyr Babchuk wrote:
On ARMv8, one of conditional exceptions (SMC that originates
from aarch32 state) have extra field in HCR.ISS encoding:
s/aarch32/AArch32/
s/have/has/
And the register is called HSR and not HCR.
CCKNOWNPASS, bit [19]
Indicates whether the
Hi Volodymyr,
On 09/08/2017 20:44, Volodymyr Babchuk wrote:
Name "iss" in this case was used not exactly correctly, because this
is only part of HSR.ISS field. ARM refence manual denotes this
part of ISS as RES0 when it describes encoding for conditional
exceptions (ARM DDI 0487A.k pages
On 09/08/2017 20:26, Volodymyr Babchuk wrote:
Hi Julien,
Hi Volodymyr,
On 09.08.17 12:53, Julien Grall wrote:
Hi Volodymyr,
On 08/08/17 21:08, Volodymyr Babchuk wrote:
From: Volodymyr Babchuk
The following list of functions:
- advance_pc()
-
Name "iss" in this case was used not exactly correctly, because this
is only part of HSR.ISS field. ARM refence manual denotes this
part of ISS as RES0 when it describes encoding for conditional
exceptions (ARM DDI 0487A.k pages D7-1939 - D7-1949).
Signed-off-by: Volodymyr Babchuk
According to ARM architecture reference manual (ARM DDI 0487A.k page D7-1938,
ARM DDI 0406C.c page B3-1426), exception with unknown reason (HSR.EC == 0)
have no valid bits in HSR (apart from HSR.EC), so we can't check if that was
caused by conditional instruction. We need assume that it is
On ARMv8 architecture SMC instruction from aarch32 state can be conditional.
(ARM DDI 0487A.k page D7-1949)
Thus, we should not skip it while checking HSR.EC value.
For this type of exception special coding of HSR.ISS is used. There is
additional flag (CCKNOWNPASS) to check before perfoming
On ARMv8, one of conditional exceptions (SMC that originates
from aarch32 state) have extra field in HCR.ISS encoding:
CCKNOWNPASS, bit [19]
Indicates whether the instruction might have failed its condition
code check.
0 - The instruction was unconditional, or was conditional and
passed
Hello all,
This is second version of patch series for correct handling of SMC32
in check_conditional_instr().
After changes proposed by Julien, first patch ("arm: processor: rename iss
to res0 in hsr_cond union") does not strictly belongs to this series.
But I decided to leave it anyways, becase
On CPUFREQ_GOV_STOP in cpufreq_governor_dbs, shortcut to
return success if the governor is already stopped.
Avoid executing dbs_timer_exit, to prevent tripping an assertion
within a call to kill_timer on a timer that has not been prepared
with init_timer, if the CPUFREQ_GOV_START case has not
run
Hi Julien,
On 09.08.17 12:53, Julien Grall wrote:
Hi Volodymyr,
On 08/08/17 21:08, Volodymyr Babchuk wrote:
From: Volodymyr Babchuk
The following list of functions:
- advance_pc()
- check_conditional_instr()
- inject_undef_exception()
- inject_iabt_exception()
This infrastructure is used exclusively by the x86 do_mmu_update() hypercall.
Mapping and unmapping domain pages is probably not the slow part of that
function, but even with an opencoded caching implementation, Bloat-o-meter
reports:
function old new
This document contains our draft proposal for implementing "suspend to RAM"
support for ARM in Xen, as discussed during the last Xen ARM community call.
It covers the basic suspend to RAM mechanism based on ARM PSCI standard,
that would allow individual guests and Xen itself to suspend.
We would
On Mon, 2017-08-07 at 02:54 -0600, Jan Beulich wrote:
> > > > Dario Faggioli 07/27/17 10:01 AM
> > > > >>>
> >
> > Instead of having the CPU where a callback is queued, busy
> > looping on rcu_pending(), use a timer.
>
> Isn't this rcu_needs_cpu(), according to patch
On Wed, Aug 9, 2017 at 2:25 AM, Jan Beulich wrote:
On 09.08.17 at 03:57, wrote:
>> Avoid panic in cpufreq_gov_stop.
>
> There's no such function afaics; ...
>
>> Only execute the CPUFREQ_GOV_STOP logic if the governor has
>> actually been
On Wed, Aug 9, 2017 at 3:32 AM, Dario Faggioli
wrote:
> On Tue, 2017-08-08 at 15:55 -0700, Meng Xu wrote:
>> On Tue, Aug 8, 2017 at 3:24 PM, Dario Faggioli
>> wrote:
>> >
>> > Therefore, I think I would set extratime as on by default in both
On 09/08/17 17:56, Daniel De Graaf wrote:
> The current code was incorrectly using SECCLASS_XEN instead of
> SECCLASS_XEN2, resulting in the wrong permission being checked.
>
> GET_CPU_LEVELLING_CAPS was checking MTRR_DEL
> GET_CPU_FEATURESET was checking MTRR_READ
>
> The default XSM policy only
The current code was incorrectly using SECCLASS_XEN instead of
SECCLASS_XEN2, resulting in the wrong permission being checked.
GET_CPU_LEVELLING_CAPS was checking MTRR_DEL
GET_CPU_FEATURESET was checking MTRR_READ
The default XSM policy only allowed these permissions to dom0, so this
didn't
On 08/09/2017 03:07 AM, Juergen Gross wrote:
Add a sysctl hypercall to support setting parameters similar to
command line parameters, but at runtime. The parameters to set are
specified as a string, just like the boot parameters.
Looks good, except for one thing:
+case
flight 112537 xen-unstable-smoke real [real]
http://logs.test-lab.xenproject.org/osstest/logs/112537/
Failures :-/ but no regressions.
Tests which did not succeed, but are not blocking:
test-arm64-arm64-xl-xsm 1 build-check(1) blocked n/a
build-arm64-pvops 2
L.S.,
It seems the xen qemu-upstream tree got updated from qemu upstream last week.
Unfortunately a change breaks pci-passthrough for HVM's:
libxl: error: libxl_qmp.c:287:qmp_handle_error_response: Domain 20:received
an error message from QMP server: Unsupported bus. Bus doesn't have
flight 112532 ovmf real [real]
http://logs.test-lab.xenproject.org/osstest/logs/112532/
Perfect :-)
All tests in this flight passed as required
version targeted for testing:
ovmf 7111e46fdebca0e03f6ddfcb029522c2fe68c74b
baseline version:
ovmf
On 08/08/17 05:59, Andy Lutomirski wrote:
> Xen's raw SYSCALL entries are much less weird than native. Rather
> than fudging them to look like native entries, use the Xen-provided
> stack frame directly.
>
> This lets us eliminate entry_SYSCALL_64_after_swapgs and two uses of
> the
On 08/09/2017 03:06 AM, Juergen Gross wrote:
Modify the custom parameter parsing routines in:
xen/xsm/flask/flask_op.c
to indicate whether the parameter value was parsed successfully.
Acked-by: Daniel De Graaf
___
Xen-devel
On 09/08/17 15:00, Bruno Alvisio wrote:
> Hello,
>
> In /docs/specs/libxc-migration-stream.pandoc "x86 HVM Guest" section
> states that:
>
> "HVM\_PARAMS must precede HVM\_CONTEXT, as certain parameters can
> affect the validity of architectural state in the context." (line 679)
>
> However, from
Hello,
In /docs/specs/libxc-migration-stream.pandoc "x86 HVM Guest" section states
that:
"HVM\_PARAMS must precede HVM\_CONTEXT, as certain parameters can affect the
validity of architectural state in the context." (line 679)
However, from the code it looks like the HVM_CONTEXT record is sent
flight 112526 xen-unstable real [real]
http://logs.test-lab.xenproject.org/osstest/logs/112526/
Failures :-/ but no regressions.
Tests which did not succeed, but are not blocking:
test-arm64-arm64-libvirt-xsm 1 build-check(1) blocked n/a
test-arm64-arm64-xl 1
>>> On 09.08.17 at 14:35, wrote:
> The check is useless because pointer arithmetic ensures "info" is
> always non-zero.
>
> Replace it with an ASSERT for socket_info. The only caller of
> free_socket_resources already ensures socket_info is not NULL before
> calling it.
>
>
flight 112534 xen-unstable-smoke real [real]
http://logs.test-lab.xenproject.org/osstest/logs/112534/
Failures :-/ but no regressions.
Tests which did not succeed, but are not blocking:
test-arm64-arm64-xl-xsm 1 build-check(1) blocked n/a
build-arm64-pvops 2
flight 112527 qemu-mainline real [real]
http://logs.test-lab.xenproject.org/osstest/logs/112527/
Regressions :-(
Tests which did not succeed and are blocking,
including tests which could not be run:
test-amd64-i386-xl-qemuu-win7-amd64 16 guest-localmigrate/x10 fail REGR. vs.
112456
The check is useless because pointer arithmetic ensures "info" is
always non-zero.
Replace it with an ASSERT for socket_info. The only caller of
free_socket_resources already ensures socket_info is not NULL before
calling it.
Coverity-ID: 1416344
Signed-off-by: Wei Liu
---
Wei Liu, on mer. 09 août 2017 13:15:48 +0100, wrote:
> Some code compiled by gcc 7 requires this.
>
> Signed-off-by: Wei Liu
Reviewed-by: Samuel Thibault
> ---
> lib/math.c | 10 ++
> 1 file changed, 10 insertions(+)
>
> diff --git
flight 112528 libvirt real [real]
http://logs.test-lab.xenproject.org/osstest/logs/112528/
Failures :-/ but no regressions.
Tests which did not succeed, but are not blocking:
test-arm64-arm64-libvirt-xsm 1 build-check(1) blocked n/a
build-arm64-libvirt 1
On Tue, Aug 01, 2017 at 05:13:21PM +0200, Olaf Hering wrote:
> Ping
Acked-by: Wei Liu
I'm going to do a build test with gcc7 and push this patch.
___
Xen-devel mailing list
Xen-devel@lists.xen.org
https://lists.xen.org/xen-devel
Some code compiled by gcc 7 requires this.
Signed-off-by: Wei Liu
---
lib/math.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/lib/math.c b/lib/math.c
index 561393e..6ac8669 100644
--- a/lib/math.c
+++ b/lib/math.c
@@ -6,6 +6,7 @@
*File: math.c
>>> On 09.08.17 at 12:10, wrote:
> CC "THE REST" maintainers to get an opinion on the public headers.
Please be more specific as to what you expect - the only public
header affected here is ARM-specific.
> On 08/08/17 21:08, Volodymyr Babchuk wrote:
>> +#ifndef
Hi Andrew,
On 09/08/17 12:12, Andrew Cooper wrote:
On 09/08/17 10:52, Julien Grall wrote:
On 08/08/17 21:37, Andrew Cooper wrote:
On 08/08/2017 21:08, Volodymyr Babchuk wrote:
diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c
index 6cf9ee7..ed78b36 100644
--- a/xen/arch/arm/traps.c
Hi Volodymyr,
On 08/08/17 21:08, Volodymyr Babchuk wrote:
PSCI handling code had helper routine that checked calling convention.
It does not needed anymore, because:
- Generic handler checks that 64 bit calls can be made only by
64 bit guests.
- SMCCC requires that 64-bit handler should
Hi,
At 10:01 +0200 on 27 Jul (1501149684), Dario Faggioli wrote:
> In Xen, that is impossible, and that's particularly problematic
> when system is idle (or lightly loaded) systems, as CPUs that
> are idle may never have the chance to tell RCU about their
> quiescence, and grace periods could
title: s/psci/PSCI/
On 08/08/17 21:08, Volodymyr Babchuk wrote:
vsmc.h provides definitions to construct SMC call function number according
to SMCCC. We don't need multiple definitions for one thing, and definitions
in vsmc.h are more generic than ones used in psci.h.
So psci.h will only
On 09/08/17 10:52, Julien Grall wrote:
>
>
> On 08/08/17 21:37, Andrew Cooper wrote:
>> On 08/08/2017 21:08, Volodymyr Babchuk wrote:
>>> diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c
>>> index 6cf9ee7..ed78b36 100644
>>> --- a/xen/arch/arm/traps.c
>>> +++ b/xen/arch/arm/traps.c
>>> @@
flight 112530 xen-unstable-coverity real [real]
http://logs.test-lab.xenproject.org/osstest/logs/112530/
Perfect :-)
All tests in this flight passed as required
version targeted for testing:
xen dd050808ccc23f0a11d5596409f4245b9406a242
baseline version:
xen
On Wed, Aug 09, 2017 at 04:28:14PM +0530, Bhupinder Thakur wrote:
> Hi Julien,
>
> Thanks for the testing.
>
> On 8 August 2017 at 21:29, Julien Grall wrote:
> > Hi Bhupinder,
> >
> > I gave another and I have a couple of comments.
> >
> > Booting Linux with earlycon
Hi Volodymyr,
The title is wrong.
On 08/08/17 21:08, Volodymyr Babchuk wrote:
PSCI is part of HVC/SMC interface, so it should be handled in
appropriate place: `vsmc.c`. This patch just moves PSCI
handler calls from `traps.c` to `vsmc.c`.
PSCI is considered as two different "services" in terms
Hi Julien,
Thanks for the testing.
On 8 August 2017 at 21:29, Julien Grall wrote:
> Hi Bhupinder,
>
> I gave another and I have a couple of comments.
>
> Booting Linux with earlycon enabled take quite a while. I can see the
> characters coming slower than on the minitel.
2017-08-08 18:49 GMT+08:00 Wei Liu :
> On Sat, Aug 05, 2017 at 01:26:37AM +0800, Zhongze Liu wrote:
>> Hi Wei,
>>
>> Thank you for reviewing my patch.
>>
>> 2017-08-04 23:20 GMT+08:00 Wei Liu :
>> > I skim through this patch and have some questions.
>> >
Append the target vCPU in the messages printed by
arch_set_info_hvm_guest.
While there constify the arguments of check_segment.
Signed-off-by: Roger Pau Monné
---
Cc: Jan Beulich
Cc: Andrew Cooper
---
2017-08-08 18:56 GMT+08:00 Wei Liu :
> On Tue, Aug 08, 2017 at 11:49:35AM +0100, Wei Liu wrote:
>> On Sat, Aug 05, 2017 at 01:26:37AM +0800, Zhongze Liu wrote:
>> > Hi Wei,
>> >
>> > Thank you for reviewing my patch.
>> >
>> > 2017-08-04 23:20 GMT+08:00 Wei Liu
On Tue, 2017-08-08 at 15:55 -0700, Meng Xu wrote:
> On Tue, Aug 8, 2017 at 3:24 PM, Dario Faggioli
> wrote:
> >
> > Therefore, I think I would set extratime as on by default in both
> > Xen
> > an xl. What do you think?
> >
>
> Right now, the domain is created with
On 09/08/17 11:18, Roger Pau Monne wrote:
> Using gprintk in arch_set_info_hvm_guest doesn't make sense, since
> most of the time this function will be called from the toolstack
> domain builder or Xen itself in case of Dom0.
>
> Switch to using printk instead.
>
> Signed-off-by: Roger Pau Monné
On 09/08/17 11:18, Roger Pau Monne wrote:
> Commit 6c9abf modified the SEG macro in arch_set_info_hvm_guest and
> inverted the limit and base fields. Restore the correct order.
>
> Signed-off-by: Roger Pau Monné
Reviewed-by: Andrew Cooper
Sorry
Using gprintk in arch_set_info_hvm_guest doesn't make sense, since
most of the time this function will be called from the toolstack
domain builder or Xen itself in case of Dom0.
Switch to using printk instead.
Signed-off-by: Roger Pau Monné
---
Cc: Jan Beulich
Commit 6c9abf modified the SEG macro in arch_set_info_hvm_guest and
inverted the limit and base fields. Restore the correct order.
Signed-off-by: Roger Pau Monné
---
Cc: Jan Beulich
Cc: Andrew Cooper
---
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