Re: [XenPPC] [PATCH] Disable DPM until code is audited
-/* FIXME Do not set the NAP and DPM bits in HID0 until we have had a - * chance to audit the safe halt and idle loop code. */ +/* FIXME Do not set the NAP bit in HID0 until we have had a chance + * to audit the safe halt and idle loop code. */ hid0.bits.nap = 0; /* NAP */ -hid0.bits.dpm = 0; /* Dynamic Power Management */ +hid0.bits.dpm = 1; /* Dynamic Power Management */ hid0.bits.nhr = 1; /* Not Hard Reset */ hid0.bits.hdice_en = 1; /* enable HDEC */ This works on the JS20 in TRL. Great to hear DPM is just fine. NAP is expected to have problems on CPUs before 970MP, it needs special setup. Segher ___ Xen-ppc-devel mailing list Xen-ppc-devel@lists.xensource.com http://lists.xensource.com/xen-ppc-devel
Re: [XenPPC] [PATCH] Disable DPM until code is audited
thanks Amos! -JX On Dec 4, 2006, at 10:37 AM, Amos Waterland wrote: On Sat, Dec 02, 2006 at 10:31:11AM -0500, Jimi Xenidis wrote: The following patch results in SMP stability on Maple. Amos, Kawachiya-san, could one of you ack it with the JS20 in question? @@ -193,10 +193,10 @@ void cpu_initialize(int cpuid) mtdec(timebase_freq); mthdec(timebase_freq); -/* FIXME Do not set the NAP and DPM bits in HID0 until we have had a - * chance to audit the safe halt and idle loop code. */ +/* FIXME Do not set the NAP bit in HID0 until we have had a chance + * to audit the safe halt and idle loop code. */ hid0.bits.nap = 0; /* NAP */ -hid0.bits.dpm = 0; /* Dynamic Power Management */ +hid0.bits.dpm = 1; /* Dynamic Power Management */ hid0.bits.nhr = 1; /* Not Hard Reset */ hid0.bits.hdice_en = 1; /* enable HDEC */ This works on the JS20 in TRL. Acked-by: Amos Waterland <[EMAIL PROTECTED]> ___ Xen-ppc-devel mailing list Xen-ppc-devel@lists.xensource.com http://lists.xensource.com/xen-ppc-devel
Re: [XenPPC] [PATCH] Disable DPM until code is audited
On Sat, Dec 02, 2006 at 10:31:11AM -0500, Jimi Xenidis wrote: > The following patch results in SMP stability on Maple. Amos, > Kawachiya-san, could one of you ack it with the JS20 in question? > > @@ -193,10 +193,10 @@ void cpu_initialize(int cpuid) > mtdec(timebase_freq); > mthdec(timebase_freq); > -/* FIXME Do not set the NAP and DPM bits in HID0 until we have had a > - * chance to audit the safe halt and idle loop code. */ > +/* FIXME Do not set the NAP bit in HID0 until we have had a chance > + * to audit the safe halt and idle loop code. */ > hid0.bits.nap = 0; /* NAP */ > -hid0.bits.dpm = 0; /* Dynamic Power Management */ > +hid0.bits.dpm = 1; /* Dynamic Power Management */ > hid0.bits.nhr = 1; /* Not Hard Reset */ > hid0.bits.hdice_en = 1; /* enable HDEC */ This works on the JS20 in TRL. Acked-by: Amos Waterland <[EMAIL PROTECTED]> ___ Xen-ppc-devel mailing list Xen-ppc-devel@lists.xensource.com http://lists.xensource.com/xen-ppc-devel
Re: [XenPPC] [PATCH] Disable DPM until code is audited
Most JS20 and JS21 have DPM disabled on the board, What does this mean? SLOF/js2x enables DPM always, for example; there is no hardware override that I'm aware of. According to S9.9 of 970FX UM: Dynamic power management can be disabled in the RAS units by asserting bit[0] in the JTAG register with modifier address 0x000800. Oh okay, that's not a *hardware* disable. Well could be that it's enabled on JS2x, I dunno. which is why we have not seen any SMP problems with them. However the Maple-D and the JS20 model Amos cites both have had problems with the one of these two modes. That model seems to be the newest JS20 we've run on. Sounds like the problem manifests itself on all 970FX and no other CPUs from the 970 family. I was under the impression that we had other 970FX js20s but perhaps we do not The 2.2GHz ones are 970FX, the 1.6GHz ones are not. My question remains: did you try with NAP disabled and DPM enabled? I see, so: HID0[NAP]=1 HID0[DPM]=1 MSR[POW]=1 is NAP and is different than: HID0[NAP]=0 HID0[DPM]=1 MSR[POW]=1 which is something else? NAP=0 DPM=1 POW=whatever is what I was after. DPM is not a power-down mode; it's just (fine-grained) clock gating AFAIK, it shouldn't make anything slower ever. Sure I'll try that. Thanks! Segher ___ Xen-ppc-devel mailing list Xen-ppc-devel@lists.xensource.com http://lists.xensource.com/xen-ppc-devel
Re: [XenPPC] [PATCH] Disable DPM until code is audited
On Dec 2, 2006, at 10:18 AM, Jimi Xenidis wrote: On Dec 2, 2006, at 2:37 AM, Segher Boessenkool wrote: My question remains: did you try with NAP disabled and DPM enabled? I see, so: HID0[NAP]=1 HID0[DPM]=1 MSR[POW]=1 is NAP and is different than: HID0[NAP]=0 HID0[DPM]=1 MSR[POW]=1 which is something else? Sure I'll try that. The following patch results in SMP stability on Maple. Amos, Kawachiya-san, could one of you ack it with the JS20 in question? diff -r 0e85b389980a xen/arch/powerpc/powerpc64/ppc970.c --- a/xen/arch/powerpc/powerpc64/ppc970.c Fri Dec 01 19:11:02 2006 -0500 +++ b/xen/arch/powerpc/powerpc64/ppc970.c Sat Dec 02 10:26:50 2006 -0500 @@ -193,10 +193,10 @@ void cpu_initialize(int cpuid) mtdec(timebase_freq); mthdec(timebase_freq); -/* FIXME Do not set the NAP and DPM bits in HID0 until we have had a - * chance to audit the safe halt and idle loop code. */ +/* FIXME Do not set the NAP bit in HID0 until we have had a chance + * to audit the safe halt and idle loop code. */ hid0.bits.nap = 0; /* NAP */ -hid0.bits.dpm = 0; /* Dynamic Power Management */ +hid0.bits.dpm = 1; /* Dynamic Power Management */ hid0.bits.nhr = 1; /* Not Hard Reset */ hid0.bits.hdice_en = 1; /* enable HDEC */ ___ Xen-ppc-devel mailing list Xen-ppc-devel@lists.xensource.com http://lists.xensource.com/xen-ppc-devel
Re: [XenPPC] [PATCH] Disable DPM until code is audited
On Dec 2, 2006, at 2:37 AM, Segher Boessenkool wrote: Do not set the NAP and DPM bits in HID0 until we have had a chance to audit the safe halt and idle loop code. Not setting these bits allows the model 884241X JS20 blade in TRL to boot correctly, and possibly also the Maple in YKT. Thanks to Jimi for his help in this matter. Is the DPM change required? I never saw any problems here... NAP and other power saving modes can cause problems for sure (for example, on pre-970MP 970s, some power saving modes require flushing the L2 before entering that mode, etc.) Most JS20 and JS21 have DPM disabled on the board, What does this mean? SLOF/js2x enables DPM always, for example; there is no hardware override that I'm aware of. According to S9.9 of 970FX UM: Dynamic power management can be disabled in the RAS units by asserting bit[0] in the JTAG register with modifier address 0x000800. which is why we have not seen any SMP problems with them. However the Maple-D and the JS20 model Amos cites both have had problems with the one of these two modes. That model seems to be the newest JS20 we've run on. Sounds like the problem manifests itself on all 970FX and no other CPUs from the 970 family. I was under the impression that we had other 970FX js20s but perhaps we do not We'll have to brush up on errata before we enable this one again. Yeah; errata and other chip differences. My question remains: did you try with NAP disabled and DPM enabled? I see, so: HID0[NAP]=1 HID0[DPM]=1 MSR[POW]=1 is NAP and is different than: HID0[NAP]=0 HID0[DPM]=1 MSR[POW]=1 which is something else? Sure I'll try that. -JX ___ Xen-ppc-devel mailing list Xen-ppc-devel@lists.xensource.com http://lists.xensource.com/xen-ppc-devel
Re: [XenPPC] [PATCH] Disable DPM until code is audited
Do not set the NAP and DPM bits in HID0 until we have had a chance to audit the safe halt and idle loop code. Not setting these bits allows the model 884241X JS20 blade in TRL to boot correctly, and possibly also the Maple in YKT. Thanks to Jimi for his help in this matter. Is the DPM change required? I never saw any problems here... NAP and other power saving modes can cause problems for sure (for example, on pre-970MP 970s, some power saving modes require flushing the L2 before entering that mode, etc.) Most JS20 and JS21 have DPM disabled on the board, What does this mean? SLOF/js2x enables DPM always, for example; there is no hardware override that I'm aware of. which is why we have not seen any SMP problems with them. However the Maple-D and the JS20 model Amos cites both have had problems with the one of these two modes. That model seems to be the newest JS20 we've run on. Sounds like the problem manifests itself on all 970FX and no other CPUs from the 970 family. We'll have to brush up on errata before we enable this one again. Yeah; errata and other chip differences. My question remains: did you try with NAP disabled and DPM enabled? Segher ___ Xen-ppc-devel mailing list Xen-ppc-devel@lists.xensource.com http://lists.xensource.com/xen-ppc-devel
Re: [XenPPC] [PATCH] Disable DPM until code is audited
On Dec 1, 2006, at 6:02 PM, Segher Boessenkool wrote: Do not set the NAP and DPM bits in HID0 until we have had a chance to audit the safe halt and idle loop code. Not setting these bits allows the model 884241X JS20 blade in TRL to boot correctly, and possibly also the Maple in YKT. Thanks to Jimi for his help in this matter. Is the DPM change required? I never saw any problems here... NAP and other power saving modes can cause problems for sure (for example, on pre-970MP 970s, some power saving modes require flushing the L2 before entering that mode, etc.) Most JS20 and JS21 have DPM disabled on the board, which is why we have not seen any SMP problems with them. However the Maple-D and the JS20 model Amos cites both have had problems with the one of these two modes. That model seems to be the newest JS20 we've run on. We'll have to brush up on errata before we enable this one again. -JX ___ Xen-ppc-devel mailing list Xen-ppc-devel@lists.xensource.com http://lists.xensource.com/xen-ppc-devel
Re: [XenPPC] [PATCH] Disable DPM until code is audited
Do not set the NAP and DPM bits in HID0 until we have had a chance to audit the safe halt and idle loop code. Not setting these bits allows the model 884241X JS20 blade in TRL to boot correctly, and possibly also the Maple in YKT. Thanks to Jimi for his help in this matter. Is the DPM change required? I never saw any problems here... NAP and other power saving modes can cause problems for sure (for example, on pre-970MP 970s, some power saving modes require flushing the L2 before entering that mode, etc.) Segher ___ Xen-ppc-devel mailing list Xen-ppc-devel@lists.xensource.com http://lists.xensource.com/xen-ppc-devel
[XenPPC] [PATCH] Disable DPM until code is audited
Do not set the NAP and DPM bits in HID0 until we have had a chance to audit the safe halt and idle loop code. Not setting these bits allows the model 884241X JS20 blade in TRL to boot correctly, and possibly also the Maple in YKT. Thanks to Jimi for his help in this matter. Signed-off-by: Amos Waterland <[EMAIL PROTECTED]> --- ppc970.c |4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff -r 927f25df5154 xen/arch/powerpc/powerpc64/ppc970.c --- a/xen/arch/powerpc/powerpc64/ppc970.c Thu Nov 30 16:21:22 2006 -0500 +++ b/xen/arch/powerpc/powerpc64/ppc970.c Fri Dec 01 16:24:32 2006 -0500 @@ -193,8 +193,8 @@ void cpu_initialize(int cpuid) mtdec(timebase_freq); mthdec(timebase_freq); -hid0.bits.nap = 1; /* NAP */ -hid0.bits.dpm = 1; /* Dynamic Power Management */ +hid0.bits.nap = 0; /* NAP */ +hid0.bits.dpm = 0; /* Dynamic Power Management */ hid0.bits.nhr = 1; /* Not Hard Reset */ hid0.bits.hdice_en = 1; /* enable HDEC */ hid0.bits.en_therm = 0; /* ! Enable ext thermal ints */ ___ Xen-ppc-devel mailing list Xen-ppc-devel@lists.xensource.com http://lists.xensource.com/xen-ppc-devel
