Re: [Xenomai-core] [Adeos-main] periodic mode in adeos-ipipe for arm at91 ...
Gregory CLEMENT wrote: > 2007/6/8, Gilles Chanteperdrix <[EMAIL PROTECTED]>: > > BOUIN Alexandre wrote: > > > We (Adeneo) are working on a ARM AT91 RTAI. We encountered > > some difficulties such tsc one : in periodic mode, we reload our timer > > automatically in order to avoid reprogramming it. TC timer increments a 16 > > byte register, which is not enough for a tsc (64 bytes). tsc need to be > > emulated on ARM. > > > With oneshot mode, tsc is updating the 4 least significant > > bytes and then increments other bytes each time counter go back to zero > > value. > > > > > > With our periodic mode, timer reloads himself so we need > > to change tsc emulation by incrementing tsc like this : tsc += period. > > > We made some evolutions on ipipe which will be applied to > > a hal patch. > > > > I intend to rework I-pipe tsc emulation for arms with a free-running > > counter. In order to reduce the tsc read operations: > > - it should use the (uninterruptible) ldm instruction to load the 64 > > bits counter without masking interrupts; > > - the 64 bits counter should not be updated at each read, but only from > > time to time, the best place to do this is Linux timer interrupt. > > If 64 bits counter is not updated at each read, we still need to load > it, read the current value of free-running counter, compare it to its > last value when 64 bits counter was updated. If we don't do this we > loose granularity. > So the gain is only on not writing the 64 bits counter, or maybe I > missed something ? We can use the ldm instruction which is not interruptible and thus remove interrupt masking as well. -- Gilles Chanteperdrix. ___ Xenomai-core mailing list Xenomai-core@gna.org https://mail.gna.org/listinfo/xenomai-core
Re: [Xenomai-core] [Adeos-main] periodic mode in adeos-ipipe for arm at91 ...
Gregory CLEMENT wrote: > 2007/6/9, Gilles Chanteperdrix <[EMAIL PROTECTED]>: > > Gilles Chanteperdrix wrote: > > > BOUIN Alexandre wrote: > > > > We (Adeneo) are working on a ARM AT91 RTAI. We encountered > > some difficulties such tsc one : in periodic mode, we reload our timer > > automatically in order to avoid reprogramming it. TC timer increments a 16 > > byte register, which is not enough for a tsc (64 bytes). tsc need to be > > emulated on ARM. > > > > With oneshot mode, tsc is updating the 4 least significant > > bytes and then increments other bytes each time counter go back to zero > > value. > > > > > > > > With our periodic mode, timer reloads himself so we need > > to change tsc emulation by incrementing tsc like this : tsc += period. > > > > We made some evolutions on ipipe which will be applied to > > a hal patch. > > > > > > I intend to rework I-pipe tsc emulation for arms with a free-running > > > counter. In order to reduce the tsc read operations: > > > - it should use the (uninterruptible) ldm instruction to load the 64 > > > bits counter without masking interrupts; > > > - the 64 bits counter should not be updated at each read, but only from > > > time to time, the best place to do this is Linux timer interrupt. > > > > I never did the calculation before, but the TC free-running counter > > wraps every 40 milliseconds, so Linux timer interrupt is not often > > How do you get this 40 ms ? > For me TC free-running counter wraps every (2^16)/(MCK/32) > For AT91RM9200-EK MCK=59904000 so we get 35ms > For AT91SMA926x-EK MCK=99328000 so we get 21ms > I am wrong? It was a rough estimation. > > enough to update the 64 bits counter. The only safe place to update the > > 64 bits counter seems to be __ipipe_mach_acktimer. > > As Linux timer period is 10ms why do you think is not often enough ? Because when Linux has a lot of work to do, or when Xenomai has a lot of work to do, Linux timer may be delayed for more than 4 ticks. > > For AT91SAM926x what do you think of using PIT for emulating tsc, > (with PIT we can have a 32 bit counter) ? Good, if it helps reducing the overhead of ipipe_read_tsc. -- Gilles Chanteperdrix. ___ Xenomai-core mailing list Xenomai-core@gna.org https://mail.gna.org/listinfo/xenomai-core
Re: [Xenomai-core] [Adeos-main] periodic mode in adeos-ipipe for arm at91 ...
2007/6/8, Gilles Chanteperdrix <[EMAIL PROTECTED]>: > BOUIN Alexandre wrote: > > We (Adeneo) are working on a ARM AT91 RTAI. We encountered > some difficulties such tsc one : in periodic mode, we reload our timer > automatically in order to avoid reprogramming it. TC timer increments a 16 > byte register, which is not enough for a tsc (64 bytes). tsc need to be > emulated on ARM. > > With oneshot mode, tsc is updating the 4 least significant > bytes and then increments other bytes each time counter go back to zero value. > > > > With our periodic mode, timer reloads himself so we need to > change tsc emulation by incrementing tsc like this : tsc += period. > > We made some evolutions on ipipe which will be applied to a > hal patch. > > I intend to rework I-pipe tsc emulation for arms with a free-running > counter. In order to reduce the tsc read operations: > - it should use the (uninterruptible) ldm instruction to load the 64 > bits counter without masking interrupts; > - the 64 bits counter should not be updated at each read, but only from > time to time, the best place to do this is Linux timer interrupt. If 64 bits counter is not updated at each read, we still need to load it, read the current value of free-running counter, compare it to its last value when 64 bits counter was updated. If we don't do this we loose granularity. So the gain is only on not writing the 64 bits counter, or maybe I missed something ? -- Gregory CLEMENT Adeneo 2, chemin du Ruisseau - BP21 69136 Ecully Cedex France Tel : +33-4 72 18 08 40 ___ Xenomai-core mailing list Xenomai-core@gna.org https://mail.gna.org/listinfo/xenomai-core
Re: [Xenomai-core] [Adeos-main] periodic mode in adeos-ipipe for arm at91 ...
2007/6/9, Gilles Chanteperdrix <[EMAIL PROTECTED]>: > Gilles Chanteperdrix wrote: > > BOUIN Alexandre wrote: > > > We (Adeneo) are working on a ARM AT91 RTAI. We encountered > some difficulties such tsc one : in periodic mode, we reload our timer > automatically in order to avoid reprogramming it. TC timer increments a 16 > byte register, which is not enough for a tsc (64 bytes). tsc need to be > emulated on ARM. > > > With oneshot mode, tsc is updating the 4 least significant > bytes and then increments other bytes each time counter go back to zero value. > > > > > > With our periodic mode, timer reloads himself so we need to > change tsc emulation by incrementing tsc like this : tsc += period. > > > We made some evolutions on ipipe which will be applied to a > hal patch. > > > > I intend to rework I-pipe tsc emulation for arms with a free-running > > counter. In order to reduce the tsc read operations: > > - it should use the (uninterruptible) ldm instruction to load the 64 > > bits counter without masking interrupts; > > - the 64 bits counter should not be updated at each read, but only from > > time to time, the best place to do this is Linux timer interrupt. > > I never did the calculation before, but the TC free-running counter > wraps every 40 milliseconds, so Linux timer interrupt is not often How do you get this 40 ms ? For me TC free-running counter wraps every (2^16)/(MCK/32) For AT91RM9200-EK MCK=59904000 so we get 35ms For AT91SMA926x-EK MCK=99328000 so we get 21ms I am wrong? > enough to update the 64 bits counter. The only safe place to update the > 64 bits counter seems to be __ipipe_mach_acktimer. As Linux timer period is 10ms why do you think is not often enough ? For AT91SAM926x what do you think of using PIT for emulating tsc, (with PIT we can have a 32 bit counter) ? -- Gregory CLEMENT Adeneo 2, chemin du Ruisseau - BP21 69136 Ecully Cedex France Tel : +33-4 72 18 08 40 ___ Xenomai-core mailing list Xenomai-core@gna.org https://mail.gna.org/listinfo/xenomai-core
Re: [Xenomai-core] [Adeos-main] periodic mode in adeos-ipipe for arm at91 ...
Gilles Chanteperdrix wrote: > BOUIN Alexandre wrote: > > We (Adeneo) are working on a ARM AT91 RTAI. We encountered some > difficulties such tsc one : in periodic mode, we reload our timer > automatically in order to avoid reprogramming it. TC timer increments a 16 > byte register, which is not enough for a tsc (64 bytes). tsc need to be > emulated on ARM. > > With oneshot mode, tsc is updating the 4 least significant > bytes and then increments other bytes each time counter go back to zero > value. > > > > With our periodic mode, timer reloads himself so we need to > change tsc emulation by incrementing tsc like this : tsc += period. > > We made some evolutions on ipipe which will be applied to a hal > patch. > > I intend to rework I-pipe tsc emulation for arms with a free-running > counter. In order to reduce the tsc read operations: > - it should use the (uninterruptible) ldm instruction to load the 64 > bits counter without masking interrupts; > - the 64 bits counter should not be updated at each read, but only from > time to time, the best place to do this is Linux timer interrupt. I never did the calculation before, but the TC free-running counter wraps every 40 milliseconds, so Linux timer interrupt is not often enough to update the 64 bits counter. The only safe place to update the 64 bits counter seems to be __ipipe_mach_acktimer. -- Gilles Chanteperdrix. ___ Xenomai-core mailing list Xenomai-core@gna.org https://mail.gna.org/listinfo/xenomai-core
Re: [Xenomai-core] [Adeos-main] periodic mode in adeos-ipipe for arm at91 ...
BOUIN Alexandre wrote: > We (Adeneo) are working on a ARM AT91 RTAI. We encountered some > difficulties such tsc one : in periodic mode, we reload our timer > automatically in order to avoid reprogramming it. TC timer increments a 16 > byte register, which is not enough for a tsc (64 bytes). tsc need to be > emulated on ARM. > With oneshot mode, tsc is updating the 4 least significant > bytes and then increments other bytes each time counter go back to zero > value. > > With our periodic mode, timer reloads himself so we need to > change tsc emulation by incrementing tsc like this : tsc += period. > We made some evolutions on ipipe which will be applied to a hal > patch. I intend to rework I-pipe tsc emulation for arms with a free-running counter. In order to reduce the tsc read operations: - it should use the (uninterruptible) ldm instruction to load the 64 bits counter without masking interrupts; - the 64 bits counter should not be updated at each read, but only from time to time, the best place to do this is Linux timer interrupt. So, if you are ready to do these modifications, I will be glad to merge your patch. -- Gilles Chanteperdrix. ___ Xenomai-core mailing list Xenomai-core@gna.org https://mail.gna.org/listinfo/xenomai-core
Re: [Xenomai-core] [Adeos-main] periodic mode in adeos-ipipe for arm at91 ...
On Fri, 2007-06-08 at 16:07 +0200, BOUIN Alexandre wrote: > We (Adeneo) are working on a ARM AT91 RTAI. We > encountered some difficulties such tsc one : in > periodic mode, we reload our timer automatically in > order to avoid reprogramming it. TC timer increments a > 16 byte register, which is not enough for a tsc (64 > bytes). tsc need to be emulated on ARM. > > With oneshot mode, tsc is updating the 4 least > significant bytes and then increments other bytes each > time counter go back to zero value. > > With our periodic mode, timer reloads himself so we > need to change tsc emulation by incrementing tsc like > this : tsc += period. > > We made some evolutions on ipipe which will be applied > to a hal patch. > > Are you interrested in a such patch for a periodic > mode on ARM ? > Support for periodic mode has been recently deprecated in the I-pipe patch, and will be discontinued in future releases. > ___ > Adeos-main mailing list > [EMAIL PROTECTED] > https://mail.gna.org/listinfo/adeos-main -- Philippe. ___ Xenomai-core mailing list Xenomai-core@gna.org https://mail.gna.org/listinfo/xenomai-core
