Poul-Henning Kamp wrote: > In message <[EMAIL PROTECTED]>, Bruce Griffiths writes: > > You guys could save a lot of time if you read my paper where all > this is described in detail: > > http://phk.freebsd.dk/pubs/timecounter.pdf > > Poul
This paper addresses virtually none of the hardware design issues at all. If you actually use "latches" as shown in the diagram on page 8 where the latch sampling is enabled by the synchroniser output transition this is usually considered to be an example of bad design practice. The accepted technique would employ gated D flipflop registers where the synchroniser output transition is converted to a single clock cycle pulse employed as the enable for the gated D register which is continuously clocked by the counter (and synchroniser) clock. Bruce _______________________________________________ time-nuts mailing list -- [email protected] To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
