John Since the PIC CLK input to output pin transition delay is relatively large (50ns or more on some datasheets) it is likely to have a relatively large tempco (several hundred ps/C) so this may be the primary limiting factor unless the thermal environment is very stable. A fast external resynchronising flipflop may have a clock to output delay and associated tempco at least 10X lower than this.
Measuring the PIC clock input to PPS output delay tempco should be relatively easy if its tempco is indeed that large. Bruce _______________________________________________ time-nuts mailing list -- [email protected] To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
