Thanks Bob;
Does this mean that the 10 MHz clock needs to be somehow divided to an
integer evenly divisible by 127 seconds?
Also 8192 seems to be unfeasible as it would take 2.2 hours to
initialize sync.
On 2/16/2011 4:51 PM, Bob Camp wrote:
Hi
According to the rules, you are not allowed to reset shift register other
than by feedback during a transmission. In order for a reset to be
"transparent" it would have to always happen at the same time. Usually
that's when the register is full or empty.
A proper (MLS) PN sequence will be (2^m) -1 long. For the allowed ham
sequences that would be 2^7 -1 = 127, 2^13 -1 = 8191, or 2^19 -1 = 524287.
If they are not MLS then I'm off a bit. None of those divide into 10 MHz
very well at all, since they all are prime numbers.
If you use the shortest sequence, you would get to reset every 127 seconds
with a simple approach. You likely would do better to run a bit more math
and figure out the "right" sequence for the time you are at.
Bob
-----Original Message-----
From: [email protected] [mailto:[email protected]] On
Behalf Of Joe Leikhim
Sent: Wednesday, February 16, 2011 4:14 PM
To: [email protected]
Subject: Re: [time-nuts] PN sequence generation using GPS
For clarification;
I am investigating an experiment using GPS to create a FHSS or DSSS
project similar to those of AMRAD and described in the ARRL Spread
Spectrum Sourcebook. In those experiments, a specific shift register
sequence was used (see below), the clock was free running and a reset
tone was transmitted on irregular intervals (whenever synch was believed
to be lost) over the radio circuit.
In my experiment I would like to derive the clock directly from a GPS at
each radio and use the GPS to periodically reset the shift register
without causing a glitch or disrupting the sequence. There is mention in
the sourcebook of a relationship between clock speed, reset interval and
shift register stage length. It is this area that I am confused.
My question is: If I use a 1PPS derived reset interval, a 10 MHz clock
and the PN sequence below, will the reset interval intrude on the
sequence? If so, what reset interval or fraction of clock speed will be
least disruptive?
This is the example shift register PN sequence:
"There is some common notation for PN sequence identification. The
sequences are often generated by a shift-register using feedback. The PN
identification notation indicates which bits are modulo-2 added and fed
back to the input of the shift-register.
As an example the [7,1] sequence is generated by modulo-2 adding
register bits 1 and 7, inverting this and applying this to the input of
the shift register."
Thanks
--
Joe Leikhim
Leikhim and Associates
Communications Consultants
Oviedo, Florida
www.Leikhim.com
[email protected]
407-982-0446
WWW.LEIKHIM.COM
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