On 2/16/11 5:04 PM, Joe Leikhim wrote:
Thanks Bob;
Does this mean that the 10 MHz clock needs to be somehow divided to an
integer evenly divisible by 127 seconds?
Also 8192 seems to be unfeasible as it would take 2.2 hours to
initialize sync.
No.. your 1pps/sync loads the register with all ones... that's what the
sync is.
If you want to synchronize without "help", what you do is slide the
receiver steadily by the transmitter, slipping one chip at a time (or
offsetting the frequency slightly).
The challenge is that you need to be "close enough" as you slide by for
"long enough" to recognize that you've got sync.
Say you've got a 1023 long code (a 10 bit generator) running at 1 MHz.
Say it takes 1 millisecond to tell if you are in sync. You can try all
1023 possible relative phases in 1 second, roughly, and the average time
will be a half second.
You can do this "try all phases" by running one clock 1ppm slow,
relative to the other, or you can run them at the same speed, and drop a
pulse every code period. Depends on if you have a digital or analog
implementation.. For a digital implementation, it's often convenient to
detect when the generator register is all ones, which occurs only once a
code period.
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