On 2/16/11 1:13 PM, Joe Leikhim wrote:
For clarification; I am investigating an experiment using GPS to create a FHSS or DSSS project similar to those of AMRAD and described in the ARRL Spread Spectrum Sourcebook. In those experiments, a specific shift register sequence was used (see below), the clock was free running and a reset tone was transmitted on irregular intervals (whenever synch was believed to be lost) over the radio circuit.
Ah yes... as Robert Dixon in his textbook "Spread Spectrum Systems" points out, code tracking is easy, acquisition and synchronization is hard.
The book is worth getting, by the way.
In my experiment I would like to derive the clock directly from a GPS at each radio and use the GPS to periodically reset the shift register without causing a glitch or disrupting the sequence. There is mention in the sourcebook of a relationship between clock speed, reset interval and shift register stage length. It is this area that I am confused. My question is: If I use a 1PPS derived reset interval, a 10 MHz clock and the PN sequence below, will the reset interval intrude on the sequence? If so, what reset interval or fraction of clock speed will be least disruptive?
For most linear feedback shift registers, the longest "period" of the pattern is 2^n-1 where n is the length of the register. This is called a maximal length sequence. You can also get shorter sequences out of a register, but not longer, as long as you are doing simple feedback. That is a 7 bit register can generate a 127 bit long sequence. The "all ones" (7 1's in a row) will occur exactly once. The register can never contain all zeros. So a "reset" is usually setting the register to all ones.
An interesting property of maximal sequences is that if you have two generators of the same sequence with some relative offset, and you combine them with an XOR, the resultant is the same sequence, just shifted (called the "shift and add property").
GPS uses a class of codes generated by combining two generators with different taps. The relative phases of the generators determines which of the "Gold codes" (named for Bob Gold, who developed them with Kasami, back in the 60s) you get.
So what you could do is drive your shift register with 10 MHz, and reset to all ones once a second with your 1pps. Now.. to get transmitter and receiver lined up, you need to know the propagation delay to better than 100ns (one code period). But once you know it, it will always line up. You could do something where you "jam" a particular bit sequence into the register (rather than all ones), where you have determined the offset.
If both transmitter and receiver do their sync at the same time (allowing for propagation delay), then you don't really care if the time between syncs is an even multiple of the code length.
This is the example shift register PN sequence: "There is some common notation for PN sequence identification. The sequences are often generated by a shift-register using feedback. The PN identification notation indicates which bits are modulo-2 added and fed back to the input of the shift-register.
A better implementation, particularly if you're changing codes or using more than 2 taps, is the one where you have an XOR between each stage, and you either feed it with a zero, or with the output of the register. Arithmetically, it's the same, but it has better propagation delay characteristics with readily obtainable MSI parts (I've built many a PN generator with 74xx136 quad XORs and octal latches)
As an example the [7,1] sequence is generated by modulo-2 adding register bits 1 and 7, inverting this and applying this to the input of the shift register." Thanks
_______________________________________________ time-nuts mailing list -- [email protected] To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
