On 26 Oct, 2013, at 18:21 , Tom Van Baak <[email protected]> wrote: > Right. The key is not to use count-down timers and interrupts at all. The key > is no interrupts; nothing asynchronous. What you do is: > > 1) About once a second (it doesn't really matter), with hot cache and > interrupts disabled, record the s/w time before and after you output a pulse. > If your PC/SBC has a low-latency DTR or GPIO pin code path, you're golden.
That's perfect if it works like it seems it should. The problem with modern CPUs is finding an instruction sequence that does the read-write-read in that order, allowing each to complete before doing the next. The write is the biggest problem. Writes are often buffered, and even when you can find an instruction which stalls until it clears the buffer the write will also often be posted across the interconnect bus so there's no way for the CPU to know when the write makes it to the device, let alone make it wait until that happens. When using the CPU cycle counter as a system clock source it is common to find that the two reads in a read-write-read sequence are only a cycle or two different even when you know the write is crossing an interconnect with 10's of nanoseconds of latency (not that 10's of nanoseconds is bad...). It is usually easier to find the magic instructions to make a read-read-read work the way one expects, though even that can be a challenge. It is possible to do the same output pulse thing with a read-read-read if there is a PWM peripheral to generate the pulses. The PWM is programmed to output pulses at whatever frequency is convenient while the read-read-read sampling is used to determine the relationship between the PWM counter and the system clock. Of course, this requires a peripheral which legacy PCs often don't have. > If the CPU/PC/SBC has h/w counter/capture latches, you're all set. Then > there's no jitter and NTP should be as accurate as the ADEV(tau 1s) of the LO > that clocks the CPU and the ADEV(tau) of the external (GPS) 1PPS source. > > But h/w counter/capture is something no legacy PC has had AFAIK. If the new > breed of SBC have this capability, NTP should show a one or two orders of > magnitude jump in precision on those platforms. The TI CPU used for the Beaglebone (Black) has three. The counter being sampled is 100 MHz. Dennis Ferguson _______________________________________________ time-nuts mailing list -- [email protected] To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
