> On most CPU architectures, the low level hardware has a register that counts > on the CPU clock.
Merely counting the CPU clock is only half the requirement. Reading the clock precisely when an external event occurs is the other half. In my mind, there are three levels of NTP precision: 1) The traditional scheme, in use for decades, where a PC uses interrupts (e.g., DCD) and OS s/w acts as a crude time interval counter. This is quite limiting, but Dave Mill's worked with what he had, and it's far better than nothing. 2) The external h/w capture/counter scheme, which is what any external time interval or time-stamping counter can provide. By using external h/w instead of internal s/w you get a precise, low-jitter time comparison at every pulse. The OP was talking about the picPET, a sub-microsecond $1 time-stamping counter. But you can use a $1000 HP sub-nanosecond time interval counter if you prefer. 3) An internal h/w capture/counter scheme, which is what the latest crop of SBC offer. Here, not only is the counter tied to the CPU clock, but timestamping is pure h/w, so all problems with s/w and latency and jitter are removed from the equation. This is the ideal solution, not unlike how any GPSDO is designed. In my mind, the modern SBC architectures with single CPU clock source (could be OCXO or atomic), and real GPIO pins (instead of serial or USB ports) and a native h/w capture/compare register should allow NTP to work at the 10 to 100 ns level. If any of you could verify this, it would be time-nut worthy. /tvb _______________________________________________ time-nuts mailing list -- [email protected] To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
