I'm pretty certain the outer that the PPS interrupt handler reads in on the CPU chip. The counter counts nanoseconds but the lower digits are always zero. I don't think a PCI bus is involved
On Sun, Oct 27, 2013 at 7:08 PM, Dennis Ferguson < [email protected]> wrote: > > ... > > The rules for things like PCI cover that case. If you do something like > > write to a register to clear an interrupt request, you have to follow it > by a > > read to that register or one close to it. -- Chris Albertson Redondo Beach, California _______________________________________________ time-nuts mailing list -- [email protected] To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
