Hi Samuel,
I have yet to see where you answered what your reference frequency is
for the PLL ? ? ? ?
If you are locking a 24.576 MHz oscillator to a common house standard
like, for example, 10 MHz then you are going to have a comparison
frequency at 16 KHz. The reason is Phase Detector #2 has a max
frequency of around 4 MHz so when you get done looking for an integer
relationship it is going to be at 16 KHz. If you are trying to lock 48
KHz to 10 MHz, it will be the same thing.
Please tell us what reference frequency you are using ?
Bill....WB6BNQ
sg sg wrote:
Running my PLL design routine again for 48 kHz I realize that this is in fact
very advantageous--it greatly reduces the required capacitor size in the loop
filter. So dividers are clearly the way to go.
Samuel
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