Hi... can you share you routine for designing with this chip? I tried
using it sometime ago but the results didn´t agree much with what I
designed, so i gave up (for now... but i´ll return to it :)
Also in the datasheet it says:
13.3 Further information
For an extensive description and application example please refer to
Application note ordering number 9397 750 00078.
I never found this application note despites all my google-fu. Anyone
got it?
Daniel
Em 29/04/2014 10:23, sg sg escreveu:
Running my PLL design routine again for 48 kHz I realize that this is in fact
very advantageous--it greatly reduces the required capacitor size in the loop
filter. So dividers are clearly the way to go.
Samuel
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