Thanks again for the further discussion. This is not for studio use, I'm designing a one-off AES-to-I2S interface for evaluation of DA converter chips. The PLL provides a very low jitter master clock such that the conversion jitter is, for jitter frequencies down to some Hz, dominated by the VCXO and converter. The pulling range of the VCXO is something like +-150 ppm (spec'd for +-100 ppm) and fully sufficient for this application (the source is a high-performance audio analyzer).
It is still not fully clear to me if there is some reasonably well defined upper limit for the operation of the PS2 in the '9046, but I take it that it is more appropriate to use the word rate (48-192 kHz) for the PLL. Samuel _______________________________________________ time-nuts mailing list -- [email protected] To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
