Samuel,
On 04/28/2014 08:41 AM, sg sg wrote:
Thanks very much for your responses!
For 24.576 MHz VCXO, the fractional change in frequency will be in multiple
ppm not octaves, and I would naturally gravitate towards a simple diode DBM.
To avoid lock issues I'd still want a phase-frequency detector; the PLL bandwidth in my
case is very low (a few Hz), which makes the lock range tiny if a "phase only"
detector is used (I've run into this recently with some other project).
If you use the PI loop principle, your lock-range does not change, but
your lock speed.
24,576 MHz is 128x192 kHz which makes essentially any divide by 2^N chip
capable of the frequency a target. Is your reference signal also 24,576
MHz or some other frequency?
The source is an AK4114 AES/EBU audio receiver, which has both master clock (24.576 MHz)
and "word select" rate (48-192 kHz) outputs. Perhaps it is better to run the
PLL at the latter? Any disadvantages from this?
If you are doing a clock-recovery of the source, then you need to keep
the first PLL bandwidth to above 8 kHz, to be in compliance with the
AES3-4-2009 spec. You won't be able to handle the jitter tolerance needed.
However, the clock recovery is usually not done with the VCXO. Rather,
you use a simpler oscillator with high bandwidth, and then you use that
"raw" clock as reference to the VCXO loop. This is also compatible with
the AES3-4-2009 spec. This two-step PLL is also described and
recommended in the AES2id-2006 which is the guideline document for the
AES3 interface. As I dipped my nose into it, I noticed to my great
satisfaction that it also covers jitter peaking and jitter accumulation.
You want to keep the jitter peaking below 0,5 dB, which means keeping
the slow PLL well damped.
While we are going to revise the AES3-4 spec and AES2id, I think these
details is pretty good. Will look at the detailed wordings in AES2id if
there is additional clarifications to be done.
Cheers,
Magnus
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