Am 04.05.2016 um 10:46 schrieb Bruce Griffiths:
Integrating A Time interval to charge TAC at the front end of a capacitive
charge redistribution SAR ADC should allow a conversion time of 300ns or so..
Using 16 such TDCs should permit 1ps resolution with a 50MHz timestamp rate
without too many cascaded gates in the selection logic for the next available
TAC.
Bruce
One or two years ago I investigated a solution around a 16 Bit / 100
MSPS ADC (LTC2165), a 2C64 Coolrunner,
an Avago PHEMT as current switch and a little bit of analog voodoo. That
would have fit on a 2"*2" board.
Good enough for a 10 MHz event rate, with some easy pipelining for at
least 20 MHz.
That includes the coarse counter from the last 1pps.
But we stayed with a classical time stretcher, and my private project
pipeline is already full.
regards, Gerhard
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