Chris, I agree with you that additional HW to avoid interrupt latency is
necessary. My NTP servers with stable oscillator and HW card processing
PPS (still in use but some mainboards failed after 10 years of reliable
service) are described here:
http://archiv.cesnet.cz/doc/techzpravy/2007/ntp-server/
Vladimir
On 10/20/2016 04:38 AM, Chris Albertson wrote:
The last time I read about this it was on an ARM based board. They clocked
it with a GPSDO. I think the problem is MUCH easier if you can abandon
the PC platform.
The other story I read solved to problem by adding even more hardware and
some software changes. They moved the nanosecond counter out of the CPU
chip to a hardware counter and then the PPS signal connected to a latch.
This avoids the interrupt latency.
In most normal NTP servers the interrupt causes the CPU to snapshot its
internal nanosecond counter and store the snapshot in memory and set a flag
so the user space task can then read the value stated in RAM. This gets
you only microsecond resolution.
With special hardware the counter is latched with external hardware then
then on the interrupt handler only has read the latch and place that valuer
in RAM and set the same flag. The trouble is that EVERY routine that
reads the internal counters has to by modified to read the eternal counter.
As I remember these system ran BSD UNIX.
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