[PATCH v3 02/12] rockchip: clk: rk3066: add SCLK_OTGPHYx enable and disable

[Johan Jonker]

Add rk3066 SCLK_OTGPHYx enable and disable.

Signed-off-by: Johan Jonker <jbx6...@gmail.com>
---

        GATE(SCLK_OTGPHY0, "sclk_otgphy0", "xin24m", CLK_IGNORE_UNUSED,
                        RK2928_CLKGATE_CON(1), 5, GFLAGS),
        GATE(SCLK_OTGPHY1, "sclk_otgphy1", "xin24m", CLK_IGNORE_UNUSED,
                        RK2928_CLKGATE_CON(1), 6, GFLAGS),
---
 drivers/clk/rockchip/clk_rk3066.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/drivers/clk/rockchip/clk_rk3066.c 
b/drivers/clk/rockchip/clk_rk3066.c
index f7dea7859f74..92b435cce83e 100644
--- a/drivers/clk/rockchip/clk_rk3066.c
+++ b/drivers/clk/rockchip/clk_rk3066.c
@@ -592,6 +592,12 @@ static int rk3066_clk_enable(struct clk *clk)
        struct rk3066_clk_priv *priv = dev_get_priv(clk->dev);

        switch (clk->id) {
+       case SCLK_OTGPHY0:
+               rk_clrreg(&priv->cru->cru_clkgate_con[1], BIT(5));
+               break;
+       case SCLK_OTGPHY1:
+               rk_clrreg(&priv->cru->cru_clkgate_con[1], BIT(6));
+               break;
        case HCLK_NANDC0:
                rk_clrreg(&priv->cru->cru_clkgate_con[5], BIT(9));
                break;
@@ -611,6 +617,12 @@ static int rk3066_clk_disable(struct clk *clk)
        struct rk3066_clk_priv *priv = dev_get_priv(clk->dev);

        switch (clk->id) {
+       case SCLK_OTGPHY0:
+               rk_setreg(&priv->cru->cru_clkgate_con[1], BIT(5));
+               break;
+       case SCLK_OTGPHY1:
+               rk_setreg(&priv->cru->cru_clkgate_con[1], BIT(6));
+               break;
        case HCLK_NANDC0:
                rk_setreg(&priv->cru->cru_clkgate_con[5], BIT(9));
                break;
--
2.39.5