Add rk3188 SCLK_OTGPHYx enable and disable.
Signed-off-by: Johan Jonker <[email protected]>
---
GATE(SCLK_OTGPHY0, "sclk_otgphy0", "xin24m", CLK_IGNORE_UNUSED,
RK2928_CLKGATE_CON(1), 5, GFLAGS),
GATE(SCLK_OTGPHY1, "sclk_otgphy1", "xin24m", CLK_IGNORE_UNUSED,
RK2928_CLKGATE_CON(1), 6, GFLAGS),
---
drivers/clk/rockchip/clk_rk3188.c | 34 +++++++++++++++++++++++++++++++
1 file changed, 34 insertions(+)
diff --git a/drivers/clk/rockchip/clk_rk3188.c
b/drivers/clk/rockchip/clk_rk3188.c
index d8b03e1d7ab3..f350eac39fce 100644
--- a/drivers/clk/rockchip/clk_rk3188.c
+++ b/drivers/clk/rockchip/clk_rk3188.c
@@ -531,7 +531,41 @@ static ulong rk3188_clk_set_rate(struct clk *clk, ulong
rate)
return new_rate;
}
+static int rk3188_clk_enable(struct clk *clk)
+{
+ struct rk3188_clk_priv *priv = dev_get_priv(clk->dev);
+
+ switch (clk->id) {
+ case SCLK_OTGPHY0:
+ rk_clrreg(&priv->cru->cru_clkgate_con[1], BIT(5));
+ break;
+ case SCLK_OTGPHY1:
+ rk_clrreg(&priv->cru->cru_clkgate_con[1], BIT(6));
+ break;
+ }
+
+ return 0;
+}
+
+static int rk3188_clk_disable(struct clk *clk)
+{
+ struct rk3188_clk_priv *priv = dev_get_priv(clk->dev);
+
+ switch (clk->id) {
+ case SCLK_OTGPHY0:
+ rk_setreg(&priv->cru->cru_clkgate_con[1], BIT(5));
+ break;
+ case SCLK_OTGPHY1:
+ rk_setreg(&priv->cru->cru_clkgate_con[1], BIT(6));
+ break;
+ }
+
+ return 0;
+}
+
static struct clk_ops rk3188_clk_ops = {
+ .disable = rk3188_clk_disable,
+ .enable = rk3188_clk_enable,
.get_rate = rk3188_clk_get_rate,
.set_rate = rk3188_clk_set_rate,
};
--
2.39.5
