Convert to use the rockchip_sysreset_bind() helper to bind the rockchip_sysreset driver. Also add and use CRU base address constants based on the clock-controller addresses used in the SoC device tree.
Signed-off-by: Jonas Karlman <[email protected]> --- arch/arm/include/asm/arch-rockchip/cru_px30.h | 3 +++ drivers/clk/rockchip/clk_px30.c | 18 +++++------------- 2 files changed, 8 insertions(+), 13 deletions(-) diff --git a/arch/arm/include/asm/arch-rockchip/cru_px30.h b/arch/arm/include/asm/arch-rockchip/cru_px30.h index 408fdd666357..4db83bd90918 100644 --- a/arch/arm/include/asm/arch-rockchip/cru_px30.h +++ b/arch/arm/include/asm/arch-rockchip/cru_px30.h @@ -113,6 +113,9 @@ struct cpu_rate_table { unsigned int pclk_div; }; +#define PX30_CRU_BASE 0xff2b0000 +#define PX30_PMU_CRU_BASE 0xff2bc000 + enum { /* PLLCON0*/ PLL_BP_SHIFT = 15, diff --git a/drivers/clk/rockchip/clk_px30.c b/drivers/clk/rockchip/clk_px30.c index d143a6b85ee6..af87b150f402 100644 --- a/drivers/clk/rockchip/clk_px30.c +++ b/drivers/clk/rockchip/clk_px30.c @@ -1485,22 +1485,14 @@ static int px30_clk_of_to_plat(struct udevice *dev) static int px30_clk_bind(struct udevice *dev) { int ret; - struct udevice *sys_child; - struct sysreset_reg *priv; /* The reset driver does not have a device node, so bind it here */ - ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset", - &sys_child); - if (ret) { + ret = rockchip_sysreset_bind(dev, PX30_CRU_BASE, + offsetof(struct px30_cru, glb_rst_st), + offsetof(struct px30_cru, glb_srst_fst), + offsetof(struct px30_cru, glb_srst_snd)); + if (ret) debug("Warning: No sysreset driver: ret=%d\n", ret); - } else { - priv = malloc(sizeof(struct sysreset_reg)); - priv->glb_srst_fst_value = offsetof(struct px30_cru, - glb_srst_fst); - priv->glb_srst_snd_value = offsetof(struct px30_cru, - glb_srst_snd); - dev_set_priv(sys_child, priv); - } #if CONFIG_IS_ENABLED(RESET_ROCKCHIP) ret = offsetof(struct px30_cru, softrst_con[0]); -- 2.54.0
