https://codereview.chromium.org/284153004/diff/20001/src/arm/assembler-arm-inl.h
File src/arm/assembler-arm-inl.h (right):
https://codereview.chromium.org/284153004/diff/20001/src/arm/assembler-arm-inl.h#newcode543
src/arm/assembler-arm-inl.h:543: MemoryBarrier();
On 2014/05/16 16:02:29, Rodolph Perfetta (ARM) wrote:
Instruction prefetching is implementation defined so what you are
trying to
achieve is not guaranteed to work, as being on the same cache line
does not
guarantee being fetched atomically (though on most CPU it probably
does).
You could make it work if there was only one instruction, but with two
I don't
see a way to avoid cache maintenance. Sorry.
How about if we only need to update one of the instructions then? It is
likely that the MovT probably doesn't need to be updated for most IC
cache updates, so we can maybe get away with this if only the MovW needs
updated - is there anything else I would need to do if I was only
updating a single instruction?
As a separate note, MemoryBarrier will guarantee the write above it
will happen
before the write after but it does not guarantee they will be visible
to the
instruction side of the CPU.
Yes, I was unsure whether the kernel defined barrier function would do a
dmb and imb, or just a dmb - sounds like it's just a dmb? If so then
this is indeed useless.
https://codereview.chromium.org/284153004/
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