Oh, that may be exactly what I need, I'll try it out.
Thanks!
Franco
On 04/04/17 03:14, Andrew Martens wrote:
Hey Franco
Many of the CASPER blocks were updated a while ago so that you can use
them asynchronously i.e data does not need to be fed to the blocks on
every clock cycle. You can then run your FPGA at a higher clock rate
than the input data rate.
Regards
Andrew
On Tue, Apr 4, 2017 at 4:22 AM, Franco <francocuro...@gmail.com
<mailto:francocuro...@gmail.com>> wrote:
Hi All,
I'm working in an application where I need high frequency
resolution (~10kHz). For my model this means I need to run my ADC
at ~40MHz (and the FPGA at 5MHz). I'm not using an special memory
block, just brams. I'm using ROACH2, and ADC5G
(https://casper.berkeley.edu/wiki/ADC1x5000-8
<https://casper.berkeley.edu/wiki/ADC1x5000-8>). It is possible to
run the ADC at such low frequency? What is the minimum acceptable
frequency? I tried to find this information in the ADC datasheet,
but I haven't been successful. Also tried compiling simple models
at low frequencies, but everything below 600MHz failed.
Thanks,
Franco
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