Hello Franco,
If you're only using 1 sample at a time, you needn't use a CASPER FFT, the
Xilinx ones do the trick nicely. You can use an asynchronous 1-input PFB if
you want to as well.
You would probably need to rework your down-stream stuff though.
Regards,
James
On Tue, Apr 4, 2017 at 2:48 PM, Franco <francocuro...@gmail.com> wrote:
> Hi Jack,
>
> I though of that, but the thing is, if I only take 1 sample per clock
> cycle, I'm not sure how to use a 8 input FFT and still keep the same number
> of output channels. Maybe I could implement serial-to-parallel block, and
> read the FFT every 8 cycles, but I don't know if that's an adequate (or
> easy to implement) solution.
>
>
> I get not very informative errors when I try to compile models below
> 600MHz (I tried, 100MHz, 200MHz, ... , 500MHz):
>
> Creating block object: xps_adc5g
> Problem with block: test/asiaa_adc5g
> : An optimum PLL solution is not available!
> Backtrace 1: xps_adc5g:177
> Backtrace 2: gen_xps_files:229
> Backtrace 3: run_Callback:155
> Backtrace 4: casper_xps:86
> Backtrace 5: @(hObject,eventdata)casper_xps('run_Callback',hObject,eventd
> ata,guidata(hObject)):0
> Error using gen_xps_files (line 242)
> Error found during Object creation.
>
>
> Thanks,
>
> Franco
>
>
>
> On 03/04/17 23:39, Jack Hickish wrote:
>
> Hi Franco,
>
> I don't know the low frequency limit, but for what it's worth, you could
> always run the adc at 320 MHz and just use 1 of the 8 outputs, which also
> has the benefit of avoiding and inter-core mismatch issues, since you'd
> effectively only be using 1 core. Or run faster and only use every Nth
> sample.
>
> What error do you get when you clock below 600 MHz ADC clock?
>
> Cheers
> Jack
>
> On Mon, 3 Apr 2017, 19:22 Franco, <francocuro...@gmail.com> wrote:
>
>> Hi All,
>>
>> I'm working in an application where I need high frequency resolution
>> (~10kHz). For my model this means I need to run my ADC at ~40MHz (and the
>> FPGA at 5MHz). I'm not using an special memory block, just brams. I'm using
>> ROACH2, and ADC5G (https://casper.berkeley.edu/wiki/ADC1x5000-8). It is
>> possible to run the ADC at such low frequency? What is the minimum
>> acceptable frequency? I tried to find this information in the ADC
>> datasheet, but I haven't been successful. Also tried compiling simple
>> models at low frequencies, but everything below 600MHz failed.
>>
>> Thanks,
>>
>> Franco
>>
>>
>>
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