On Tue, 18 Feb 2003 09:43:43 -0800, "Fargusson.Alan" <[EMAIL PROTECTED]> wrote:
>I am not sure about the P4, but earlier chip did not pass the ECC bits through the >processor bus, >so you could not detect data errors between the processor and memory. This prevents >one from >getting Mainframe reliability with an Intel processor. ECC wasn't pervasive in mainframes also. I remember hearing of a problem with a 3081 which turned out to be cosmic rays (really) which occaisionally changed bits in a channel buffer cache... which had neither parity nor ECC. I worked on an Amdahl machine once (customer machine that got cooked) and the last problem was am LRA that gave bad results when the index register was used as the source. That path through the chips had shorted (because of heat) and the result was always zero. No parity/ecc there either. john alvord
