Re: [casper] Programming a ROACH2

[Adam Isaacson]

Hi Heystek,

If you want to telnet, which is another way of configuring your board, then
you need to state the port. Are you doing the following from the terminal:

1)Telnet to port 7147: "telnet  7147".

2)?progremote fpgfile.fpg

You say you can ping your board, so you should be able to connect via
casperfpga, as you mentioned above. Did you do what James suggested i.e.
try running fpga.is_connected()? if it reports "True" then you are
connected and if false then you will need to debug further. Are you sure
that the IP you are pinging is your roach2 - may sound like a silly
question, but I don't know your setup.

Kind Regards,

Adam


On Fri, Sep 30, 2016 at 3:38 PM, Heystek Grobler 
wrote:

> Hi James
>
> I will try it. Through the terminal I can ping the board, but I cant open
> a Telnet connection.
>
> When I open a ttyUSB connection to the Roach en monitor it, and try to
> upload the fga file, the Roach gives the same error "progremote"
>
> Thats why I'm confused
>
> Thanks for your help!
>
> I really appreciate it
>
> Heystek
>
>
> On Friday, 30 September 2016, James Smith  wrote:
>
>> Hello Heystek,
>>
>> Before you program the ROACH2, I'd suggest trying fpga.is_connected()
>> and fpga.est_clk_frequency() to check whether you can actually
>> communicate with the ROACH2. It might be a network cable that's been
>> unplugged by accident - that's where I've seen those errors before. The
>> fpga=casperfpga.katcp_fpga.KatcpFpga('roachname or ip_address') doesn't
>> actually throw an error if it can't connect to the ROACH2. This information
>> would at least help you narrow down the possibilities as to what's wrong
>> (i.e. whether it's the kernel on the ROACH2).
>>
>> Disclaimer: I work only on ROACH, but I'm fairly certain the procedure
>> would be the same.
>>
>> Regards,
>> James
>>
>>
>> On Fri, Sep 30, 2016 at 1:36 PM, Heystek Grobler <
>> heystekgrob...@gmail.com> wrote:
>>
>>> Good day everyone
>>>
>>> I am having difficulties programming the ROACH 2 board. I am following
>>> the instructions of CASPER tutorial one.
>>>
>>> I Have compiled the fpg file and is using the following steps from the
>>> tutorial.
>>>
>>> 1. I entered ipython into the terminal
>>> 2. import casperfpga
>>> 3. fpga=casperfpga.katcp_fpga.KatcpFpga('roachname or ip_address') with
>>> the ip address of my roach
>>> 4. fpga.upload_to_ram_and_program('your_fpgfile.fpg') with the location
>>> of the .fpga file
>>>
>>> but at point 4 I get the following error:
>>>
>>> RuntimeError  Traceback (most recent call
>>> last)
>>>  in ()
>>> > 1 fpga.upload_to_ram_and_program('/home/heystek/simulink/ai_t1
>>> /bit_files/ai_t1_2016_Sep_14_2052.fpg')
>>>
>>> /usr/local/lib/python2.7/dist-packages/casperfpga/katcp_fpga.pyc in
>>> upload_to_ram_and_program(self, filename, port, timeout, wait_complete)
>>> 442 if request_result != '':
>>> 443 raise RuntimeError('progremote request(%s) on host
>>> %s failed' %
>>> --> 444(request_result, self.host))
>>> 445
>>> 446 # start the upload thread and join
>>>
>>> RuntimeError: progremote request(Request to client 192.168.33.4 failed.)
>>> on host 192.168.33.4 failed
>>>
>>> Am I doing something wrong?
>>>
>>> I looked at the mail archives and it sugested that I update the kernel
>>> of the roach. Is this perhaps the problem? Or am I doing something wrong?
>>>
>>> Have a wonderful day.
>>>
>>> Heystek
>>>
>>
>>


-- 

Adam Isaacson

DBE: FPGA Engineer

SKA-SA

3rd Floor

The Park

Park Road

Pinelands

7405


Tel: +27215067300 (W)

Fax: +27215067375 (W)

Cell: +27825639602

Re: [casper] Programming a ROACH2

[Heystek Grobler]

Hi James

I will try it. Through the terminal I can ping the board, but I cant open a
Telnet connection.

When I open a ttyUSB connection to the Roach en monitor it, and try to
upload the fga file, the Roach gives the same error "progremote"

Thats why I'm confused

Thanks for your help!

I really appreciate it

Heystek

On Friday, 30 September 2016, James Smith  wrote:

> Hello Heystek,
>
> Before you program the ROACH2, I'd suggest trying fpga.is_connected() and
> fpga.est_clk_frequency() to check whether you can actually communicate
> with the ROACH2. It might be a network cable that's been unplugged by
> accident - that's where I've seen those errors before. The
> fpga=casperfpga.katcp_fpga.KatcpFpga('roachname or ip_address') doesn't
> actually throw an error if it can't connect to the ROACH2. This information
> would at least help you narrow down the possibilities as to what's wrong
> (i.e. whether it's the kernel on the ROACH2).
>
> Disclaimer: I work only on ROACH, but I'm fairly certain the procedure
> would be the same.
>
> Regards,
> James
>
>
> On Fri, Sep 30, 2016 at 1:36 PM, Heystek Grobler  > wrote:
>
>> Good day everyone
>>
>> I am having difficulties programming the ROACH 2 board. I am following
>> the instructions of CASPER tutorial one.
>>
>> I Have compiled the fpg file and is using the following steps from the
>> tutorial.
>>
>> 1. I entered ipython into the terminal
>> 2. import casperfpga
>> 3. fpga=casperfpga.katcp_fpga.KatcpFpga('roachname or ip_address') with
>> the ip address of my roach
>> 4. fpga.upload_to_ram_and_program('your_fpgfile.fpg') with the location
>> of the .fpga file
>>
>> but at point 4 I get the following error:
>>
>> RuntimeError  Traceback (most recent call
>> last)
>>  in ()
>> > 1 fpga.upload_to_ram_and_program('/home/heystek/simulink/ai_t1
>> /bit_files/ai_t1_2016_Sep_14_2052.fpg')
>>
>> /usr/local/lib/python2.7/dist-packages/casperfpga/katcp_fpga.pyc in
>> upload_to_ram_and_program(self, filename, port, timeout, wait_complete)
>> 442 if request_result != '':
>> 443 raise RuntimeError('progremote request(%s) on host %s
>> failed' %
>> --> 444(request_result, self.host))
>> 445
>> 446 # start the upload thread and join
>>
>> RuntimeError: progremote request(Request to client 192.168.33.4 failed.)
>> on host 192.168.33.4 failed
>>
>> Am I doing something wrong?
>>
>> I looked at the mail archives and it sugested that I update the kernel of
>> the roach. Is this perhaps the problem? Or am I doing something wrong?
>>
>> Have a wonderful day.
>>
>> Heystek
>>
>
>

Re: [casper] Programming a ROACH2

[James Smith]

Hello Heystek,

Before you program the ROACH2, I'd suggest trying fpga.is_connected() and
fpga.est_clk_frequency() to check whether you can actually communicate with
the ROACH2. It might be a network cable that's been unplugged by accident -
that's where I've seen those errors before. The
fpga=casperfpga.katcp_fpga.KatcpFpga('roachname
or ip_address') doesn't actually throw an error if it can't connect to the
ROACH2. This information would at least help you narrow down the
possibilities as to what's wrong (i.e. whether it's the kernel on the
ROACH2).

Disclaimer: I work only on ROACH, but I'm fairly certain the procedure
would be the same.

Regards,
James


On Fri, Sep 30, 2016 at 1:36 PM, Heystek Grobler 
wrote:

> Good day everyone
>
> I am having difficulties programming the ROACH 2 board. I am following the
> instructions of CASPER tutorial one.
>
> I Have compiled the fpg file and is using the following steps from the
> tutorial.
>
> 1. I entered ipython into the terminal
> 2. import casperfpga
> 3. fpga=casperfpga.katcp_fpga.KatcpFpga('roachname or ip_address') with
> the ip address of my roach
> 4. fpga.upload_to_ram_and_program('your_fpgfile.fpg') with the location
> of the .fpga file
>
> but at point 4 I get the following error:
>
> RuntimeError  Traceback (most recent call
> last)
>  in ()
> > 1 fpga.upload_to_ram_and_program('/home/heystek/simulink/ai_
> t1/bit_files/ai_t1_2016_Sep_14_2052.fpg')
>
> /usr/local/lib/python2.7/dist-packages/casperfpga/katcp_fpga.pyc in
> upload_to_ram_and_program(self, filename, port, timeout, wait_complete)
> 442 if request_result != '':
> 443 raise RuntimeError('progremote request(%s) on host %s
> failed' %
> --> 444(request_result, self.host))
> 445
> 446 # start the upload thread and join
>
> RuntimeError: progremote request(Request to client 192.168.33.4 failed.)
> on host 192.168.33.4 failed
>
> Am I doing something wrong?
>
> I looked at the mail archives and it sugested that I update the kernel of
> the roach. Is this perhaps the problem? Or am I doing something wrong?
>
> Have a wonderful day.
>
> Heystek
>

[casper] Programming a ROACH2

[Heystek Grobler]

Good day everyone

I am having difficulties programming the ROACH 2 board. I am following the
instructions of CASPER tutorial one.

I Have compiled the fpg file and is using the following steps from the
tutorial.

1. I entered ipython into the terminal
2. import casperfpga
3. fpga=casperfpga.katcp_fpga.KatcpFpga('roachname or ip_address') with the
ip address of my roach
4. fpga.upload_to_ram_and_program('your_fpgfile.fpg') with the location of
the .fpga file

but at point 4 I get the following error:

RuntimeError  Traceback (most recent call last)
 in ()
> 1 fpga.upload_to_ram_and_program('/home/heystek/
simulink/ai_t1/bit_files/ai_t1_2016_Sep_14_2052.fpg')

/usr/local/lib/python2.7/dist-packages/casperfpga/katcp_fpga.pyc in
upload_to_ram_and_program(self, filename, port, timeout, wait_complete)
442 if request_result != '':
443 raise RuntimeError('progremote request(%s) on host %s
failed' %
--> 444(request_result, self.host))
445
446 # start the upload thread and join

RuntimeError: progremote request(Request to client 192.168.33.4 failed.) on
host 192.168.33.4 failed

Am I doing something wrong?

I looked at the mail archives and it sugested that I update the kernel of
the roach. Is this perhaps the problem? Or am I doing something wrong?

Have a wonderful day.

Heystek

Re: [casper] one_Gbe timing errors

[Mike Movius]

Hi Adam,
Yes we are using the casper_xps tool flow but with a bit of a twist. The main 
design is encapsulated in a Simulink subsystem and consists of hdl 
synthesizable blocks. Hdl coder is used to generate vhdl from the design. 
Another Simulink design contains all of the yellow blocks, the system generator 
token and one Xilinx black box containing the hdl synthesized design. This 
design is then compiled using casper_xps. This allows us to use vanilla FFT’s 
and such that hdl coder generates.
Getting back to the timing error, In the design, there is a heavy lifting block 
containing a number if FFT’s and IFFT’s. If I generate this block with the 
FFT/IFFT architecture mask parameter set to radix2 the design compiles and 
meets timing. If I set this mask parameter to radix2^2 (which is supposed to be 
faster/better according to mathworks) I get the timing error in the one_GbE 
zone. As I mentioned before, the design is using only occupying 50% of the 
slices (plenty of dsp48e’s available as well)  and running at a fabric clock 
rate 125 MHz. My initial thought was this should be no problem. I believe floor 
planning is a way to deal with issues like this and adding constraints is also 
a good suggestion. The problem is I haven’t done this before. Is there any 
information you know of that explains how to floor plan? I have pulled the ngc 
files into plan ahead and pushed the green play button to implement but don’t 
know what to do from there. Also any tips on adding timing contraints would be 
appreciated. Regards, Michael Movius

From: Adam Isaacson [mailto:aisaac...@ska.ac.za]
Sent: 27 September 2016 12:13 PM
To: Mike Movius
Cc: casper@lists.berkeley.edu
Subject: Re: [casper] one_Gbe timing errors

Hi Mike,

I have had a look at this. I can definitely tell you this is not a pipe-lining 
issue (as logic levels/interconnect = 3 stages, so no need to insert flip-flops 
to reduce the timing between the paths. It is difficult for me to analyse the 
path without seeing the floor plan, but I believe you will need to reduce the 
data path delay if you want to meet timing. The best is to open your design in 
the floor planner and highlight this failing path - hopefully you will see a 
long delay for the data path routing. It may be as easy as assigning an area 
constraint in your ucf file for the MAC itself, so that the data path is 
shorter by a few ns i.e. a pblock constraint.

I am not sure if you are using the CASPER_XPS tool flow at all or if you have 
your own flavour, but maybe there are existing constraints for the 1GbE that 
you could use? I am not sure if any of this helps, but it is a start anyway :).

Kind regards,

Adam





On Fri, Sep 23, 2016 at 10:49 AM, Mike Movius 
> wrote:

Hi All,
I have a Roach2 design using the one_Gbe yellow block. I intermittently have 
timing errors in this block seemingly unrelated to the design. Below is a 
TS_mac_rx_clk timing constraint failure. The FPGA is running at 125 MHz and 
approximately 50% of the resources are currently being utilized. The design 
only sends data out of the interface. Any ideas on what is causing this or how 
to fix it?


Timing constraint: TS_mac_rx_clk = PERIOD TIMEGRP "mac_rx_clk" 125 MHz HIGH
50%;
For more information, see Period Analysis in the Timing Closure User Guide 
(UG612).

12625 paths analyzed, 2332 endpoints analyzed, 4 failing endpoints
4 timing errors detected. (4 setup errors, 0 hold errors, 0 component switching 
limit errors)
Minimum period is   8.157ns.

Slack:  -0.157ns (requirement - (data path - clock path skew + 
uncertainty))
  Source:   
fort_adm_rsp_bb_one_GbE/fort_adm_rsp_bb_one_GbE/enable_cpu_tx.cpu_buffer_tx/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/TRUE_DP.SIMPLE_PRIM36.ram
 (RAM)
  Destination:  temac_inst/temac_inst/emac_wrapper_inst/v6_emac (CPU)
  Requirement:  8.000ns
  Data Path Delay:  7.893ns (Levels of Logic = 3)
  Clock Path Skew:  -0.229ns (1.919 - 2.148)
  Source Clock: mac_mac_rx_clk rising at 0.000ns
  Destination Clock:mac_mac_rx_clk rising at 8.000ns
  Clock Uncertainty:0.035ns

  Clock Uncertainty:  0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ):  0.070ns
Total Input Jitter (TIJ):   0.000ns
Discrete Jitter (DJ):   0.000ns
Phase Error (PE):   0.000ns

  Maximum Data Path at Slow Process Corner: 
fort_adm_rsp_bb_one_GbE/fort_adm_rsp_bb_one_GbE/enable_cpu_tx.cpu_buffer_tx/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/TRUE_DP.SIMPLE_PRIM36.ram
 to temac_inst/temac_inst/emac_wrapper_inst/v6_emac
Location   Delay type Delay(ns)  Physical 
Resource