Re: [U-Boot] [PATCH] powerpc/85xx: Add basic support for P1010RDB
On Wed, 2011-05-04 at 22:53 +0530, Poonam Aggrwal wrote:
+sinclude $(obj).depend
+
+#
diff --git a/nand_spl/board/freescale/p1010rdb/nand_boot.c
b/nand_spl/board/freescale/p1010rdb/nand_boot.c
new file mode 100644
index 000..f0de279
--- /dev/null
+++ b/nand_spl/board/freescale/p1010rdb/nand_boot.c
@@ -0,0 +1,119 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ *
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+#include common.h
+#include mpc85xx.h
+#include asm/io.h
+#include ns16550.h
+#include nand.h
+#include asm/mmu.h
+#include asm/immap_85xx.h
+#include asm/fsl_ddr_sdram.h
+#include asm/fsl_law.h
+
+#define udelay(x) {int i, j; for (i = 0; i x; i++) for (j = 0; j 1;
j++); }
There were many comments on this udelay before, we should not use this
define, but use the udelay() which u-boot provides.
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Re: [U-Boot] [PATCH] powerpc/85xx: Add basic support for P1010RDB
On Wed, 2011-05-04 at 12:34 -0500, Kumar Gala wrote:
+
+#define udelay(x) {int i, j; for (i = 0; i x; i++) for (j = 0; j
1; j++); }
There were many comments on this udelay before, we should not use this
define, but use the udelay() which u-boot provides.
Is there a udelay that is defined for the nand_spl build? The problem is
doing proper time based delay in nand_spl would require a lot more code.
No special udelay defined for nand_spl. I only saw the comments on not
to define a extra udelay like that. I understood the reason but that was
one of the reasons for TPL support.
Haiying
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Re: [U-Boot] [PATCH] Fix build issues cause by LDFLAGS_FINAL changes
Dear Wolfgang, On Thu, 2011-03-31 at 16:52 +0200, Wolfgang Denk wrote: Commit 6dc1ece Introduce a new linker flag LDFLAGS_FINAL modified a number of Makefiles in a way that broke out-of-tree builds. The problem was that $(nandobj) was used before it got defined. What is out-of-tree builds? Why did LDFLAGS_FINAL patch break it? the $(nandobj) was defined in those Makefiles in that way before applying LDFLAGS_FINAL patch. Why could the out-of-tree builds passed before applying LDFLAG_FINAL patch? Thanks. Haiying ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] Fix build issues cause by LDFLAGS_FINAL changes
On Thu, 2011-03-31 at 17:37 +0200, Wolfgang Denk wrote: $(nandobj) was defined in those Makefiles in that way before applying LDFLAGS_FINAL patch. Why could the out-of-tree builds passed before applying LDFLAG_FINAL patch? Have a look at the changes introduced by your commit, and you will see. The problem is a bit buried in the changes of = into := and $(PLATFORM_LDFLAGS) into $(LDFLAGS) $(LDFLAGS_FINAL) in lines like these: -LDFLAGS= -Bstatic -T $(nandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE) $(PLATFORM_LDFLAGS) +LDFLAGS := -T $(nandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE) $(LDFLAGS) \ + $(LDFLAGS_FINAL) Oh,yes, I got it now. := will expand the variables immediately and = will delay the expansion until the new variable is referenced, which can explain the $(nandobj)worked before this patch. [It is a bit strange to append to LDFLAGS line that.] The reason I used := was because I added LDFLAGS_FINAL += -Bstatic $(LDFLAGS) in my first version of this patch, but it seems that it is not necessary to do so after I remove $(LDFLAGS) for LDFLAGS_FINAL. Thanks for pointing it out. Haiying ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] Introduce a new linker flag LDFLAGS_FINAL
On Wed, 2011-02-16 at 19:58 +0100, Wolfgang Denk wrote:
Dear Haiying Wang,
In message 1297881643.1977.28.camel@haiying-laptop you wrote:
We have some 524 PowerPC configurations in boards.cfg, and the compare
must be done for _all_ off these, i. e. there are 2 x 524 pairs of
files to be compared. Did you really do this?
it is ok to apply this patch, if you are ok with the name _FINAL?
Sorry, I did not get the 2x254 pairs of System.map and u-boot.map. Running
MAKEALL powerpc only left the last pair. Could you please show me how I
can keep the former 523 pairs?
I usually do this on the fly using shell scripting capabilities, i.e.
something like this (copying some shell functions from MAKEALL):
---
boards_by_field()
{
awk \
-v field=$1 \
-v select=$2 \
'($1 !~ /^#/ $field == select) { print $1 }' \
boards.cfg
}
boards_by_arch() { boards_by_field 2 $@ ; }
for board in $(boards_by_arch powerpc) ; do
./MAKEALL $board
cp System.map System.map.${board}.unpatched
cp u-boot.map u-boot.map.${board}.unpatched
done
...apply patch...
for board in $(boards_by_arch powerpc) ; do
./MAKEALL $board
cmp System.map.${board}.unpatched System.map || diff -u
System.map.${board}.unpatched System.map System.map.${board}.diff
cmp u-boot.map.${board}.unpatched u-boot.map || diff -u
u-boot.map.${board}.unpatched u-boot.map u-boot.map.${board}.diff
done
less *.diff
---
Your scripts works fine. Now I only get one pair of diff which are
System.map.mpc7448hpc2.diff u-boot.map.mpc7448hpc2.diff, because
mpc7448hpc2 failed to build:
Configuring for mpc7448hpc2 board...
cc1: error: AltiVec and E500 instructions cannot coexist
cc1: error: AltiVec and E500 instructions cannot coexist
lib/asm-offsets.c:1: error: AltiVec and E500 instructions cannot coexist
make: *** [lib/asm-offsets.s] Error 1
make: *** Waiting for unfinished jobs
- SUMMARY
Boards compiled: 1
Boards with warnings or errors: 1 ( mpc7448hpc2 )
--
.
Other than that, I think all the System.map and u-boot.map keep the same
before and after applying the patch.
What kind of info do you still expect to see?
Thanks.
Haiying
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Re: [U-Boot] [PATCH] Introduce a new linker flag LDFLAGS_FINAL
On Thu, 2011-02-17 at 14:28 -0500, Haiying Wang wrote: Your scripts works fine. Now I only get one pair of diff which are System.map.mpc7448hpc2.diff u-boot.map.mpc7448hpc2.diff, because mpc7448hpc2 failed to build: Configuring for mpc7448hpc2 board... cc1: error: AltiVec and E500 instructions cannot coexist cc1: error: AltiVec and E500 instructions cannot coexist lib/asm-offsets.c:1: error: AltiVec and E500 instructions cannot coexist make: *** [lib/asm-offsets.s] Error 1 make: *** Waiting for unfinished jobs - SUMMARY Boards compiled: 1 Boards with warnings or errors: 1 ( mpc7448hpc2 ) -- . Other than that, I think all the System.map and u-boot.map keep the same before and after applying the patch. Sorry, I ignored some other info just now. Not only 7448 but also some other boards failed to build, you can get the failed info from the beforepatch.txt and afterpatch.txt I sent yesterday. The final result should be: haiying@haiying-laptop:~/Opensource/Denx/u-boot$ ls -s *.diff 0 System.map.ESTEEM192E.diff 0 System.map.P2020DS.diff 0 System.map.ETX094.diff 0 System.map.sbc8641d.diff 0 System.map.LANTEC.diff 0 System.map.SPD823TS.diff 0 System.map.mpc7448hpc2.diff0 System.map.xpedite517x.diff 0 System.map.MPC8610HPCD.diff0 u-boot.map.mpc7448hpc2.diff 0 System.map.MPC8641HPCN_36BIT.diff 0 u-boot.map.MPC8610HPCD.diff 0 System.map.MPC8641HPCN.diff0 u-boot.map.MPC8641HPCN_36BIT.diff 0 System.map.mpq101.diff 0 u-boot.map.MPC8641HPCN.diff 0 System.map.P2020DS_36BIT.diff 0 u-boot.map.sbc8641d.diff 0 System.map.P2020DS_DDR2.diff 0 u-boot.map.xpedite517x.diff The above boards failed to build thus the diff files were generated but the contents are all 0. All the other boards should not have difference in System.map/u-boot.map before and after applying the LDFLAGS_FINAL patch. Haiying ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] Introduce a new linker flag LDFLAGS_FINAL
On Wed, 2011-02-16 at 19:29 +0100, Wolfgang Denk wrote: Dear Haiying Wang, In message 1297878184.1977.18.camel@haiying-laptop you wrote: I did run ./MAKEALL powerpc for all ppc board, the System.map and u-boot.map keep exactly the same before and after applying the LDFLAGS_FINAL patch. Please find the attached two txt files and System.map and u-boot.map which are the results of MAKEALL. Do you think I'm surrised that you send just one pair of these files. Does that mean that you did the compare only after the full MAKEALL run, i. e. just on the last result, for the last board? We have some 524 PowerPC configurations in boards.cfg, and the compare must be done for _all_ off these, i. e. there are 2 x 524 pairs of files to be compared. Did you really do this? it is ok to apply this patch, if you are ok with the name _FINAL? Sorry, I did not get the 2x254 pairs of System.map and u-boot.map. Running MAKEALL powerpc only left the last pair. Could you please show me how I can keep the former 523 pairs? Others appear to be happy with it, and I don't have a better proposal, so let's use this _FINAL name. Thanks. Haiying ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 4/4 v2] p1021mds: add QE and UEC support
On Tue, 2011-02-08 at 10:52 -0600, Kumar Gala wrote:
+#endif
uec = (uec_private_t *)dev-priv;
if (uec-the_first_run == 0) {
+#ifdef CONFIG_P1021
+ /* reset micrel phy for each UEC */
+ clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 11), BCSR11_ENET_MICRST);
+ udelay(200);
+ setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 11), BCSR11_ENET_MICRST);
+
Hmm, this is board specific, can we not do this in board_*_f or _r?
It did not work to do this in board_*_f/r. The board designer to me to
reset the phy before initializing it for each UEC separately. Here is
the right place to do so.
Haiying
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Re: [U-Boot] [PATCH 4/4 v2] p1021mds: add QE and UEC support
On Tue, 2011-02-08 at 12:09 -0500, Haiying Wang wrote:
On Tue, 2011-02-08 at 10:52 -0600, Kumar Gala wrote:
+#endif
uec = (uec_private_t *)dev-priv;
if (uec-the_first_run == 0) {
+#ifdef CONFIG_P1021
+ /* reset micrel phy for each UEC */
+ clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 11), BCSR11_ENET_MICRST);
+ udelay(200);
+ setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 11), BCSR11_ENET_MICRST);
+
Hmm, this is board specific, can we not do this in board_*_f or _r?
It did not work to do this in board_*_f/r. The board designer to me to
:%s/to me/told me/
reset the phy before initializing it for each UEC separately. Here is
the right place to do so.
Haiying
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[U-Boot] [PATCH 4/4 v3] p1021mds: add QE and UEC support
P1021 has some QE pins which need to be set in pmuxcr register before using QE
functions. In this patch, pin QE0 and QE3 are set for UCC1 and UCC5 in Eth mode.
QE9 and QE12 are set for MII management. QE12 needs to be released after MII
access because QE12 pin is muxed with LBCTL signal.
Signed-off-by: Haiying Wang haiying.w...@freescale.com
---
v3: change resetting micrel phy via bcsr to board specific.
arch/powerpc/cpu/mpc85xx/speed.c |4 ++
arch/powerpc/include/asm/immap_85xx.h | 13
board/freescale/p1021mds/p1021mds.c | 51 +
drivers/qe/uec.c | 41 +-
include/configs/P1021MDS.h| 44
5 files changed, 152 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c
index f2aa8d0..ae94ee8 100644
--- a/arch/powerpc/cpu/mpc85xx/speed.c
+++ b/arch/powerpc/cpu/mpc85xx/speed.c
@@ -165,10 +165,14 @@ void get_sys_info (sys_info_t * sysInfo)
#endif
#ifdef CONFIG_QE
+#ifdef CONFIG_P1021
+ sysInfo-freqQE = sysInfo-freqSystemBus;
+#else
qe_ratio = ((gur-porpllsr) MPC85xx_PORPLLSR_QE_RATIO)
MPC85xx_PORPLLSR_QE_RATIO_SHIFT;
sysInfo-freqQE = qe_ratio * CONFIG_SYS_CLK_FREQ;
#endif
+#endif
#if defined(CONFIG_FSL_LBC)
#if defined(CONFIG_SYS_LBC_LCRR)
diff --git a/arch/powerpc/include/asm/immap_85xx.h
b/arch/powerpc/include/asm/immap_85xx.h
index 99ecb83..d0fa79b 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1909,6 +1909,19 @@ typedef struct ccsr_gur {
#define MPC85xx_PMUXCR_SD_DATA 0x8000
#define MPC85xx_PMUXCR_SDHC_CD 0x4000
#define MPC85xx_PMUXCR_SDHC_WP 0x2000
+#define MPC85xx_PMUXCR_QE0 0x8000
+#define MPC85xx_PMUXCR_QE1 0x4000
+#define MPC85xx_PMUXCR_QE2 0x2000
+#define MPC85xx_PMUXCR_QE3 0x1000
+#define MPC85xx_PMUXCR_QE4 0x0800
+#define MPC85xx_PMUXCR_QE5 0x0400
+#define MPC85xx_PMUXCR_QE6 0x0200
+#define MPC85xx_PMUXCR_QE7 0x0100
+#define MPC85xx_PMUXCR_QE8 0x0080
+#define MPC85xx_PMUXCR_QE9 0x0040
+#define MPC85xx_PMUXCR_QE100x0020
+#define MPC85xx_PMUXCR_QE110x0010
+#define MPC85xx_PMUXCR_QE120x0008
u32 pmuxcr2;/* Alt. function signal multiplex control 2 */
u8 res6[8];
u32 devdisr;/* Device disable control */
diff --git a/board/freescale/p1021mds/p1021mds.c
b/board/freescale/p1021mds/p1021mds.c
index 2dfcf13..29972f8 100644
--- a/board/freescale/p1021mds/p1021mds.c
+++ b/board/freescale/p1021mds/p1021mds.c
@@ -37,6 +37,45 @@
#include tsec.h
#include netdev.h
+#ifdef CONFIG_QE
+const qe_iop_conf_t qe_iop_conf_tab[] = {
+ /* QE_MUX_MDC */
+ {1, 19, 1, 0, 1}, /* QE_MUX_MDC*/
+ /* QE_MUX_MDIO */
+ {1, 20, 3, 0, 1}, /* QE_MUX_MDIO */
+
+ /* UCC_1_MII */
+ {0, 23, 2, 0, 2}, /* CLK12 */
+ {0, 24, 2, 0, 1}, /* CLK9 */
+ {0, 7, 1, 0, 2}, /* ENET1_TXD0_SER1_TXD0 */
+ {0, 9, 1, 0, 2}, /* ENET1_TXD1_SER1_TXD1 */
+ {0, 11, 1, 0, 2}, /* ENET1_TXD2_SER1_TXD2 */
+ {0, 12, 1, 0, 2}, /* ENET1_TXD3_SER1_TXD3 */
+ {0, 6, 2, 0, 2}, /* ENET1_RXD0_SER1_RXD0 */
+ {0, 10, 2, 0, 2}, /* ENET1_RXD1_SER1_RXD1 */
+ {0, 14, 2, 0, 2}, /* ENET1_RXD2_SER1_RXD2 */
+ {0, 15, 2, 0, 2}, /* ENET1_RXD3_SER1_RXD3 */
+ {0, 5, 1, 0, 2}, /* ENET1_TX_EN_SER1_RTS_B*/
+ {0, 13, 1, 0, 2}, /* ENET1_TX_ER */
+ {0, 4, 2, 0, 2}, /* ENET1_RX_DV_SER1_CTS_B*/
+ {0, 8, 2, 0, 2}, /* ENET1_RX_ER_SER1_CD_B*/
+ {0, 17, 2, 0, 2}, /* ENET1_CRS*/
+ {0, 16, 2, 0, 2}, /* ENET1_COL*/
+
+ /* UCC_5_RMII */
+ {1, 11, 2, 0, 1}, /* CLK13 */
+ {1, 7, 1, 0, 2}, /* ENET5_TXD0_SER5_TXD0 */
+ {1, 10, 1, 0, 2}, /* ENET5_TXD1_SER5_TXD1 */
+ {1, 6, 2, 0, 2}, /* ENET5_RXD0_SER5_RXD0 */
+ {1, 9, 2, 0, 2}, /* ENET5_RXD1_SER5_RXD1 */
+ {1, 5, 1, 0, 2}, /* ENET5_TX_EN_SER5_RTS_B*/
+ {1, 4, 2, 0, 2}, /* ENET5_RX_DV_SER5_CTS_B*/
+ {1, 8, 2, 0, 2}, /* ENET5_RX_ER_SER5_CD_B*/
+
+ {0, 0, 0, 0, QE_IOP_TAB_END} /* END of table */
+};
+#endif
+
int board_early_init_f(void)
{
@@ -100,6 +139,14 @@ int board_eth_init(bd_t *bis)
tsec_eth_init(bis, tsec_info, num);
+#if defined(CONFIG_UEC_ETH)
+ /* QE0 and QE3 need to be exposed for UCC1 and UCC5 Eth mode */
+ setbits_be32(gur-pmuxcr, MPC85xx_PMUXCR_QE0);
+ setbits_be32(gur-pmuxcr, MPC85xx_PMUXCR_QE3);
+
+ uec_standard_init(bis);
+#endif
+
return pci_eth_init(bis);
}
#endif
@@ -119,5 +166,9
Re: [U-Boot] [PATCH] Introduce a new linker flag LDFLAGS_FINAL
Dear Wolfgang, On Tue, 2011-02-01 at 14:40 -0600, Scott Wood wrote: On Tue, 1 Feb 2011 21:20:50 +0100 Wolfgang Denk w...@denx.de wrote: Dear Scott Wood, In message 20110201135136.0817f...@udp111988uds.am.freescale.net you wrote: Prior to the introduction of LDFLAGS_u-boot, was LDFLAGS not what was used? So before, anything that board/cpu code adds directly to LDFLAGS (maybe they're supposed to use PLATFORM_LDFLAGS, but not all do) was used in the final link. After 8aba9dc, only things in PLATFORM_LDFLAGS plus -Bstatic and -T are used in the final link. And this is correct for all boards? By this do you mean the switch to PLATFORM_LDFLAGS in 8aba9dc, or the switch back to LDFLAGS? It's not obvious to me that the dropping of I don;t understand why you contine to talk about switch to PLATFORM_LDFLAGS in 8aba9dc. There was no such switch - at least I cannot see it. I see only a switch in your patch. This is why I'm asking. Before 8aba9dc, the flags for the final link were produced by taking the existing LDFLAGS, and adding: -Bstatic -T linkerscript $(PLATFORM_LDFLAGS) -Ttext addr. This included anything that cpu/board code added to LDFLAGS -- some architectures added --gc-sections, x86 added --cref, etc. Since the above flags are added to LDFLAGS, rather than replacing them, these flags got used in the final link. Commit 8aba9dc introduces LDFLAGS_u-boot, so that LDFLAGS is no longer the source for the flags for the final link. It generates LDFLAGS_u-boot using PLATFORM_LDFLAGS, not LDFLAGS. It converts most of the board/cpu updates to LDFLAGS into LDFLAGS_u-boot, but it missed --cref. I don't see any other LDFLAGS changes in board/cpu code, so the distinction between using LDFLAGS and PLATFORM_LDFLAGS should have no other impact on current boards. However, the patch appears to be intended to support platform linker flags that need to be used during partial link, which would involve board/cpu additions to LDFLAGS. This change would break that only if those options need to be used for partial link *only*, and cannot be used in the final link. In such a case I'd suggest using something like LDFLAGS_PARTIAL to make this explicit. But I'd be surprised if that were actually the case. If you're looking to cut down on the number of variables, it's not clear to me what PLATFORM_LDFLAGS is supposed to mean distinct from adding to LDFLAGS. -Scott Do you have time to read Scott's email and give us any further recommendation? We do need to solve the issues of partial linking caused by commit 8aba9dc. Thanks. Haiying ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] Fix NAND_SPL and ONENAND_IPL in Makefile
Dear Wolfgang, On Thu, 2011-01-27 at 09:44 -0500, haiying.w...@freescale.com wrote: From: Haiying Wang haiying.w...@freescale.com Signed-off-by: Haiying Wang haiying.w...@freescale.com Acked-by: Scott Wood scottw...@freescale.com --- Makefile | 30 ++ 1 files changed, 14 insertions(+), 16 deletions(-) diff --git a/Makefile b/Makefile index 5f93646..0d1ea5d 100644 --- a/Makefile +++ b/Makefile @@ -287,17 +287,6 @@ LDPPFLAGS += \ $(shell $(LD) --version | \ sed -ne 's/GNU ld version \([0-9][0-9]*\)\.\([0-9][0-9]*\).*/-DLD_MAJOR=\1 -DLD_MINOR=\2/p') -ifeq ($(CONFIG_NAND_U_BOOT),y) -NAND_SPL = nand_spl -U_BOOT_NAND = $(obj)u-boot-nand.bin -endif - -ifeq ($(CONFIG_ONENAND_U_BOOT),y) -ONENAND_IPL = onenand_ipl -U_BOOT_ONENAND = $(obj)u-boot-onenand.bin -ONENAND_BIN ?= $(obj)onenand_ipl/onenand-ipl-2k.bin -endif - __OBJS := $(subst $(obj),,$(OBJS)) __LIBS := $(subst $(obj),,$(LIBS)) $(subst $(obj),,$(LIBBOARD)) @@ -320,7 +309,16 @@ BOARD_SIZE_CHECK = endif # Always append ALL so that arch config.mk's can add custom ones -ALL += $(obj)u-boot.srec $(obj)u-boot.bin $(obj)System.map $(U_BOOT_NAND) $(U_BOOT_ONENAND) +ALL += $(obj)u-boot.srec $(obj)u-boot.bin $(obj)System.map + +ifeq ($(CONFIG_NAND_U_BOOT),y) +ALL += $(obj)u-boot-nand.bin +endif + +ifeq ($(CONFIG_ONENAND_U_BOOT),y) +ALL += $(obj)u-boot-onenand.bin +ONENAND_BIN ?= $(obj)onenand_ipl/onenand-ipl-2k.bin +endif all: $(ALL) @@ -401,16 +399,16 @@ $(LDSCRIPT):depend $(obj)u-boot.lds: $(LDSCRIPT) $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - $^ $@ -$(NAND_SPL): $(TIMESTAMP_FILE) $(VERSION_FILE) depend +nand_spl:$(TIMESTAMP_FILE) $(VERSION_FILE) $(obj)include/autoconf.mk $(MAKE) -C nand_spl/board/$(BOARDDIR) all -$(U_BOOT_NAND): $(NAND_SPL) $(obj)u-boot.bin +$(obj)u-boot-nand.bin: nand_spl $(obj)u-boot.bin cat $(obj)nand_spl/u-boot-spl-16k.bin $(obj)u-boot.bin $(obj)u-boot-nand.bin -$(ONENAND_IPL): $(TIMESTAMP_FILE) $(VERSION_FILE) $(obj)include/autoconf.mk +onenand_ipl: $(TIMESTAMP_FILE) $(VERSION_FILE) $(obj)include/autoconf.mk $(MAKE) -C onenand_ipl/board/$(BOARDDIR) all -$(U_BOOT_ONENAND): $(ONENAND_IPL) $(obj)u-boot.bin +$(obj)u-boot-onenand.bin:onenand_ipl $(obj)u-boot.bin cat $(ONENAND_BIN) $(obj)u-boot.bin $(obj)u-boot-onenand.bin $(VERSION_FILE): Do you have any comments on this patch? Based on your reply at http://lists.denx.de/pipermail/u-boot/2011-January/086285.html , I added the changes for ONENAND_IPL as well. Thanks. Haiying ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] powerpc: Add cpu_late_init_r to allow for initialization post env setup
On Wed, 2011-02-02 at 11:27 -0600, Kumar Gala wrote:
+void cpu_late_init_r(void)
+{
+#ifdef CONFIG_QE
+ uint qe_base = CONFIG_SYS_IMMR + 0x0008; /* QE immr base */
+ qe_init(qe_base);
+ qe_reset();
+#endif
+}
You did not move qe_reset() inside qe_init() as you recommended.:)
For NAND boot case, the microcode needs to be read from nand flash via
nand_read first, so you might add some more code like:
+void cpu_late_init_r(void)
+{
+#ifdef CONFIG_QE
+#ifdef CONFIG_SYS_QE_FW_IN_NAND
+ int ret;
+ size_t fw_length = CONFIG_SYS_QE_FW_LENGTH;
+ /* load QE firmware from NAND flash to DDR first */
+ ret = nand_read(nand_info[0],(loff_t)CONFIG_SYS_QE_FW_IN_NAND,
+ fw_length, (u_char *)CONFIG_SYS_QE_FW_ADDR);
+ if (ret ret == -EUCLEAN) {
+ printf (NAND read for QE firmware at offset %x failed %
d\n,
+ CONFIG_SYS_QE_FW_IN_NAND, ret);
+ }
+#endif
+ uint qe_base = CONFIG_SYS_IMMR + 0x0008; /* QE immr base */
+ qe_init(qe_base);
+ qe_reset();
+#endif
+}
Haiying
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Re: [U-Boot] [PATCH] Introduce a new linker flag LDFLAGS_FINAL
On Tue, 2011-02-01 at 08:34 +0100, Wolfgang Denk wrote: Can you please be more specific? I don't see where the LDFLAGS_u-boot commit (you mean 8aba9dc ?) would change any related code. The relevant hunk looks like this: @@ -204,9 +204,11 @@ endif AFLAGS := $(AFLAGS_DEBUG) -D__ASSEMBLY__ $(CPPFLAGS) -LDFLAGS += -Bstatic -T $(obj)u-boot.lds $(PLATFORM_LDFLAGS) +LDFLAGS += $(PLATFORM_LDFLAGS) + +LDFLAGS_u-boot += -Bstatic -T $(obj)u-boot.lds $(PLATFORM_LDFLAGS) ifneq ($(CONFIG_SYS_TEXT_BASE),) -LDFLAGS += -Ttext $(CONFIG_SYS_TEXT_BASE) +LDFLAGS_u-boot += -Ttext $(CONFIG_SYS_TEXT_BASE) endif # Location of a usable BFD library, where we define usable as and this does not make any changes of PLATFORM_LDFLAGS into LDFLAGS or vice versa. But PLATFORM_LDFLAGS has been changed in $(CPUDIR)/config.mk. You can see in commit 8aba9dc: --- a/arch/powerpc/config.mk +++ b/arch/powerpc/config.mk @@ -24,10 +24,10 @@ CROSS_COMPILE ?= ppc_8xx- STANDALONE_LOAD_ADDR = 0x4 - +LDFLAGS_u-boot = --gc-sections PLATFORM_RELFLAGS += -mrelocatable -ffunction-sections -fdata-sections PLATFORM_CPPFLAGS += -DCONFIG_PPC -D__powerpc__ -PLATFORM_LDFLAGS += -n --gc-sections +PLATFORM_LDFLAGS += -n Here, --gc-sections is set only for LDFLAGS_u-boot, the PLATFORM_LDFLAGS does have --gc-sections, So in toplevel config.mk: +LDFLAGS += $(PLATFORM_LDFLAGS) And later in this config.mk, @@ -259,7 +261,7 @@ $(obj)%.s: %.c # If the list of objects to link is empty, just create an empty built-in.o cmd_link_o_target = $(if $(strip $1),\ - $(LD) -r -o $@ $1 ,\ + $(LD) $(LDFLAGS) -r -o $@ $1,\ rm -f $@; $(AR) rcs $@ ) LDFLAGS is added in cmd_link_o_target which made changes to build nand_spl. Haiying ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 6/6] p1021mds: add QE and UEC support
On Tue, 2011-02-01 at 10:50 -0600, Scott Wood wrote: If it is a one time setting, there should be no problem to put it into board code. But these pin settings need to be done before any usage of phy read/write (accessing MDIO/MDC), and need to be released after the usage of phy, thus the devices connected to eLBC like NAND flash/BCSR can be accessed. If we use board code to set/release the pin, we don't know when the phy access and nand flash access will happen. Is this actually a board issue or an SoC issue? It is not a board issue. It is a SoC *feature*. Too many pins are muxed on P1021. For this case, LBCTL of eLBC is muxed with QE's CE_PB[20] which is used for MDIO signal. Haiying ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 6/6] p1021mds: add QE and UEC support
On Tue, 2011-02-01 at 13:15 -0600, Kumar Gala wrote: On Feb 1, 2011, at 11:01 AM, Haiying Wang wrote: On Tue, 2011-02-01 at 10:50 -0600, Scott Wood wrote: If it is a one time setting, there should be no problem to put it into board code. But these pin settings need to be done before any usage of phy read/write (accessing MDIO/MDC), and need to be released after the usage of phy, thus the devices connected to eLBC like NAND flash/BCSR can be accessed. If we use board code to set/release the pin, we don't know when the phy access and nand flash access will happen. Is this actually a board issue or an SoC issue? It is not a board issue. It is a SoC *feature*. Too many pins are muxed on P1021. For this case, LBCTL of eLBC is muxed with QE's CE_PB[20] which is used for MDIO signal. Haiying But its a board decision on how they want to utilize those pins and for what feature. Yes, you can say that. If the board doesn't have QE UCC ETH support at all, we won't have to add such code in QE driver. But if there is QE UCC ETH on board, we have no choice to decide which pins to use. We definitely need to use CE_PB[20] for MDIO signal, there is no other GPIO pins to use for QE's MDIO. Haiying ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 6/6] p1021mds: add QE and UEC support
On Mon, 2011-01-31 at 21:11 +0100, Wolfgang Denk wrote: +#ifdef CONFIG_P1021 + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + + /* QE9 and QE12 need to be set for enabling QE MII managment signals */ + setbits_be32(gur-pmuxcr, MPC85xx_PMUXCR_QE9); + setbits_be32(gur-pmuxcr, MPC85xx_PMUXCR_QE12); +#endif ... Can we please avoid having board specific code in common files? I wish I could, but only P1021 has such pin mux problems. If this is really necessary, it shoud be a feature-specific #define, not a board specific one. I don't know whether this *feature* will show up on other SoC. But if you insist, I can use CONFIG_QE_PIN_MUX. Thanks. Haiying ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 5/6] powerpc/85xx: do not initialize QE if QE's firmware is in nand flash
On Mon, 2011-01-31 at 21:08 +0100, Wolfgang Denk wrote: Dear haiying.w...@freescale.com, In message 1296499317-26616-6-git-send-email-haiying.w...@freescale.com you wrote: From: Haiying Wang haiying.w...@freescale.com For some board which doesn't have NOR flash and the QE's firmware(ucode) is saved in its NAND flash, we don't want call qe_init in cpu_init_r, but will call it later after nand is initialized. Is there a pressing reason to do this so early for other boards? Can not all boards initialize this later? My understanding is that QE is a cpu feature, so it is called early in cpu_init_r. As Kumar recommended before, I can move qe_init from cpu_init_r to misc_init_r for every 85xx boards with qe support. Is it acceptable to you? Haiying ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 6/6] p1021mds: add QE and UEC support
On Mon, 2011-01-31 at 15:28 -0600, Kumar Gala wrote: On Jan 31, 2011, at 2:50 PM, Haiying Wang wrote: On Mon, 2011-01-31 at 21:11 +0100, Wolfgang Denk wrote: +#ifdef CONFIG_P1021 + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + + /* QE9 and QE12 need to be set for enabling QE MII managment signals */ + setbits_be32(gur-pmuxcr, MPC85xx_PMUXCR_QE9); + setbits_be32(gur-pmuxcr, MPC85xx_PMUXCR_QE12); +#endif ... Can we please avoid having board specific code in common files? I wish I could, but only P1021 has such pin mux problems. If this is really necessary, it shoud be a feature-specific #define, not a board specific one. I don't know whether this *feature* will show up on other SoC. But if you insist, I can use CONFIG_QE_PIN_MUX. Thanks. Haiying I think pin muxing is a board level decision so it seems like board code is the right place for it. If it is a one time setting, there should be no problem to put it into board code. But these pin settings need to be done before any usage of phy read/write (accessing MDIO/MDC), and need to be released after the usage of phy, thus the devices connected to eLBC like NAND flash/BCSR can be accessed. If we use board code to set/release the pin, we don't know when the phy access and nand flash access will happen. Haiying ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 5/8 v3] P1021: add P1021MDS board support
On Fri, 2011-01-28 at 11:02 +0100, Fabian Cenedese wrote: I'm not questioning the patch, I'm just trying to understand. +#define CONFIG_MP /* Multiprocessor support */ + +#define CONFIG_PCI /* Disable PCI/PCIE */ Shouldn't that be Enable PCI? Yes, you are right. Thanks for pointing out. Haiying ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 5/8 v3] P1021: add P1021MDS board support
On Fri, 2011-01-28 at 08:49 -0600, Kumar Gala wrote:
+
+struct law_entry law_table[] = {
+#ifndef CONFIG_IN_TPL
+ SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1),
+ SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_1),
+ SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_2),
+ SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_2),
PCIe LAWs are now set by common code, you can remove these.
Fixed it in v4 patch, thanks.
Haiying
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Re: [U-Boot] [PATCH 7/7] add gc-sections to TPL boot
On Fri, 2011-01-28 at 11:36 -0600, Scott Wood wrote: On Thu, 27 Jan 2011 23:58:10 -0500 haiying.w...@freescale.com wrote: From: Haiying Wang haiying.w...@freescale.com Signed-off-by: Haiying Wang haiying.w...@freescale.com --- arch/powerpc/config.mk |4 config.mk |7 ++- 2 files changed, 10 insertions(+), 1 deletions(-) I see patch 3/8, 4/8, 5/8, and 7/7. Where are the rest? Sorry, patch 7/7 is a wrong number here. I kept the patch # as 3/8/, 4/8, 5/8, 8/8 to be consistent with the order in the patchset(v2) I submitted in last December. I thought it would be clearer to compare them with v2 version and review. Patch 1/8,2/8 have been applied by Kumar, patch 6/8, 7/8 remain the same as v2 version. This patch, is a new patch because that TPL still needs --gc-sections in linker option to do partial link. If it is preferable to have new whole set of patch, I can reorder them from 3/8-8/8 plus this one to submit. diff --git a/config.mk b/config.mk index 5147c35..d7bb07f 100644 --- a/config.mk +++ b/config.mk @@ -260,8 +260,13 @@ $(obj)%.s: %.c # # If the list of objects to link is empty, just create an empty built-in.o +ifdef CONFIG_HAS_TPL +cmd_link_o_target = $(if $(strip $1),\ + $(LD) -r -o $@ $1,\ + rm -f $@; $(AR) rcs $@ ) +else cmd_link_o_target = $(if $(strip $1),\ $(LD) $(LDFLAGS) -r -o $@ $1,\ rm -f $@; $(AR) rcs $@ ) - +endif What's going on here? For CONFIG_HAS_TPL, LDFLAGS has --gc-sections now, passing it to cmd_link_o_target here will fail in linking stage: powerpc-none-linux-gnuspe-ld: gc-sections requires either an entry or an undefined symbol Haiying ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 7/7] add gc-sections to TPL boot
On Fri, 2011-01-28 at 12:30 -0600, Scott Wood wrote: diff --git a/config.mk b/config.mk index 5147c35..d7bb07f 100644 --- a/config.mk +++ b/config.mk @@ -260,8 +260,13 @@ $(obj)%.s: %.c # # If the list of objects to link is empty, just create an empty built-in.o +ifdef CONFIG_HAS_TPL +cmd_link_o_target = $(if $(strip $1),\ + $(LD) -r -o $@ $1,\ + rm -f $@; $(AR) rcs $@ ) +else cmd_link_o_target = $(if $(strip $1),\ $(LD) $(LDFLAGS) -r -o $@ $1,\ rm -f $@; $(AR) rcs $@ ) - +endif What's going on here? For CONFIG_HAS_TPL, LDFLAGS has --gc-sections now, passing it to cmd_link_o_target here will fail in linking stage: powerpc-none-linux-gnuspe-ld: gc-sections requires either an entry or an undefined symbol I think --gc-sections should go in LDFLAGS_u-boot instead. LDFLAGS_u-boot has --gc-sections already, I did not change it. I only add --gc-sections to PLATFORM_LDFLAGS in arch/powerpc/config.mk under ifdef CONFIG_HAS_TPL In any case, I don't think we want different behavior here based on whether we have TPL. Either LDFLAGS is used in partial linking, or it's not. I don't understand why LDFLAGS was added here in patch http://lists.denx.de/pipermail/u-boot/2011-January/084705.html It says LDFLAGS sets necessary option by partial linking (use in cmd_link_o_target). But without this changing, the partial linking worked well before. Please correct me if I am wrong. So if someone can confirm LDFLAGS is not necessary to be added in cmd_link_o_target, I prefer not add it here. Thanks. Haiying ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 7/7] add gc-sections to TPL boot
On Fri, 2011-01-28 at 13:46 -0500, Haiying Wang wrote: In any case, I don't think we want different behavior here based on whether we have TPL. Either LDFLAGS is used in partial linking, or it's not. I don't understand why LDFLAGS was added here in patch http://lists.denx.de/pipermail/u-boot/2011-January/084705.html It says LDFLAGS sets necessary option by partial linking (use in cmd_link_o_target). But without this changing, the partial linking worked well before. Please correct me if I am wrong. So if someone can confirm LDFLAGS is not necessary to be added in cmd_link_o_target, I prefer not add it here. BTW, I doubt removing --gc-sections for PLATFORM_FLAGS by patch http://lists.denx.de/pipermail/u-boot/2011-January/084705.html may have the risk of building failure for nand_spl, as we encountered the message NAND bootstrap too big before For example, the size for MPC8572DS_NAND_config before applying patch: textdata bss dec hex filename 3320 520 03840 f00 nand_spl/u-boot-spl After applying that patch: textdata bss dec hex filename 3476 520 03996 f9c nand_spl/u-boot-spl Once 8572 support is getting bigger as that in BSP, the error message will be triggered. Haiying ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 5/8 v3] P1021: add P1021MDS board support
On Fri, 2011-01-28 at 13:24 -0600, Timur Tabi wrote: Haiying Wang wrote: +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 Not 0x57? That's where the NXID EEPROM almost always is. It is board specific value, isn't it? P1021MDS does use 0x52 for board eeprom. I just wanted you to be sure it wasn't a typo. Did you actual test reading and writing to the EEPROM with the 'mac' command? Yes, I did test and have used it for almost one year. :) Haiying ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 3/8 v2] Introduce the Tertiary Program loader
Dear Wolfgang, On Mon, 2011-01-24 at 23:29 +0100, Wolfgang Denk wrote: Dear Haiying Wang, In message 1295907459.2051.158.camel@haiying-laptop you wrote: It's not the name. But you use it ina few places here, buth then hard encode tpl in a number of other paces there. Which means that you cannot change TPL_BOOT to any other value, or building would break. So why do we need this variable? It follows the same usage of NAND_SPL. Ah. I see. Well, so NAND_SPL needs fixing as well :-( I fixed the NAND_SPL in this way. If it is OK for you, I will generate the patches accordingly for TPL as well. Thanks. BTW, the ./MAKEALL powerpc worked for my previous patch. Haiying From: Haiying Wang haiying.w...@freescale.com Date: Wed, 26 Jan 2011 16:03:39 -0500 Subject: [PATCH] Fix NAND_SPL in Makefile Signed-off-by: Haiying Wang haiying.w...@freescale.com --- Makefile | 16 1 files changed, 8 insertions(+), 8 deletions(-) diff --git a/Makefile b/Makefile index 5f93646..f2c6d65 100644 --- a/Makefile +++ b/Makefile @@ -287,11 +287,6 @@ LDPPFLAGS += \ $(shell $(LD) --version | \ sed -ne 's/GNU ld version \([0-9][0-9]*\)\.\([0-9][0-9]*\).*/-DLD_MAJOR=\1 -DLD_MINOR=\2/p') -ifeq ($(CONFIG_NAND_U_BOOT),y) -NAND_SPL = nand_spl -U_BOOT_NAND = $(obj)u-boot-nand.bin -endif - ifeq ($(CONFIG_ONENAND_U_BOOT),y) ONENAND_IPL = onenand_ipl U_BOOT_ONENAND = $(obj)u-boot-onenand.bin @@ -320,7 +315,11 @@ BOARD_SIZE_CHECK = endif # Always append ALL so that arch config.mk's can add custom ones -ALL += $(obj)u-boot.srec $(obj)u-boot.bin $(obj)System.map $(U_BOOT_NAND) $(U_BOOT_ONENAND) +ALL += $(obj)u-boot.srec $(obj)u-boot.bin $(obj)System.map $(U_BOOT_ONENAND) + +ifeq ($(CONFIG_NAND_U_BOOT),y) +ALL += $(obj)u-boot-nand.bin +endif all: $(ALL) @@ -401,10 +400,11 @@ $(LDSCRIPT): depend $(obj)u-boot.lds: $(LDSCRIPT) $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - $^ $@ -$(NAND_SPL): $(TIMESTAMP_FILE) $(VERSION_FILE) depend +$(obj)nand_spl:$(TIMESTAMP_FILE) $(VERSION_FILE) $(obj)include/autoconf.mk $(MAKE) -C nand_spl/board/$(BOARDDIR) all -$(U_BOOT_NAND):$(NAND_SPL) $(obj)u-boot.bin + +$(obj)u-boot-nand.bin: $(obj)nand_spl $(obj)u-boot.bin cat $(obj)nand_spl/u-boot-spl-16k.bin $(obj)u-boot.bin $(obj)u-boot-nand.bin $(ONENAND_IPL):$(TIMESTAMP_FILE) $(VERSION_FILE) $(obj)include/autoconf.mk -- 1.7.3.1.50.g1e633 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 3/8 v2] Introduce the Tertiary Program loader
On Mon, 2011-01-24 at 13:49 +0100, Wolfgang Denk wrote: +ifeq ($(CONFIG_TPL_U_BOOT),y) +TPL_BOOT = tpl +endif I don't understand what the TPL_BOOT is good for, or how it's supposed to work. TPL_BOOT works like NAND_SPL but after NAND_SPL is executed. It is a middle stage boot loader to balance the 4K nand spl limitation which can not include ddr spd code and the 256K L2 SRAM size which can not accommodate the final uboot image on some Freescale Qoriq P1 platforms. Yes, I understand what you are atempting to do. What I do not understand is what the TPL_BOOT variable in the Makefile is good for. I cannot understand the current use. Well, it was used to generate the tpl image under tpl/ directory. Maybe TPL_BOOT is a bad name here, I just thought it was too simple to use TPL. The main purpose of tpl is to initialize the ddr with spd code in l2 sram then load the final uboot image to ddr. The reason to call tpl is because it runs after spl, the Second Program Loader. My original patch used CONFIG_MIDDLE_STAGE_SRAM_BOOT but you recommended to use CONFIG_SYS_2ND_STAGE_BOOT(http://lists.denx.de/pipermail/u-boot/2010-August/075653.html). However, 2ND STAGE is not correct here since it runs after SPL. ifeq ($(CONFIG_NAND_U_BOOT),y) NAND_SPL = nand_spl U_BOOT_NAND = $(obj)u-boot-nand.bin @@ -407,8 +411,15 @@ $(obj)u-boot.lds: $(LDSCRIPT) $(NAND_SPL): $(TIMESTAMP_FILE) $(VERSION_FILE) depend $(MAKE) -C nand_spl/board/$(BOARDDIR) all -$(U_BOOT_NAND):$(NAND_SPL) $(obj)u-boot.bin - cat $(obj)nand_spl/u-boot-spl-16k.bin $(obj)u-boot.bin $(obj)u-boot-nand.bin +$(TPL_BOOT): $(TIMESTAMP_FILE) $(VERSION_FILE) depend + $(MAKE) -C tpl/board/$(BOARDDIR) all Assume CONFIG_TPL_U_BOOT is not defined, then TPL_BOOT is not defined, and this rule will probably cause a build error, doesn't it? No, I don't think there is a build error. WEell, if CONFIG_TPL_U_BOOT is not 'y', then TPL_BOOT is not defined, which results in this make rule: : $(TIMESTAMP_FILE) $(VERSION_FILE) depend $(MAKE) -C tpl/board/$(BOARDDIR) all i. e. there would be no target name befoe the semicolon. If TPL_BOOT here is not defined, the reset(after semicolon) will not be executed, just like NAND_SPL and ONENAND_IPL etc. Has this code ever been tested? Yes, I tested it on P1021MDS board, and also built for other 85xx NAND_config without error. Did you run a MAKEALL ppc, i. e. build for all PPC board, not only NAND booting versions? No, I didn't. I will do it and let you know. But I did pass the build for other 85xx non-nand booting version. + CONFIG_TPL_U_BOOT + + Builds a U-Boot image that contains a loader stub (tertiary + program loader -- TPL) that boots out of some type of RAM, + after being loaded by an SPL or similar platform-specific + mechanism. This symbol will be set in all build phases. + + CONFIG_TPL_BOOT + + This is set by the build system when compiling code to go into + the TPL. It is not set when building the code that the TPL + loads, or when building the SPL. Can we not do with a single variable definition? I did not get it. Could you please give a recommendation? Well, I see a pollution with such CONFIG_ settings. I don;t have a solution ready to recommend, but if you can find a way not to define so many different settings for a single purpose that wouldbe great. Will apply Scott's recommendation. Thanks. Haiying ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 3/8 v2] Introduce the Tertiary Program loader
On Mon, 2011-01-24 at 23:09 +0100, Wolfgang Denk wrote: Dear Haiying Wang, In message 1295906076.2051.127.camel@haiying-laptop you wrote: What I do not understand is what the TPL_BOOT variable in the Makefile is good for. I cannot understand the current use. Well, it was used to generate the tpl image under tpl/ directory. Maybe TPL_BOOT is a bad name here, I just thought it was too simple to use TPL. It's not the name. But you use it ina few places here, buth then hard encode tpl in a number of other paces there. Which means that you cannot change TPL_BOOT to any other value, or building would break. So why do we need this variable? It follows the same usage of NAND_SPL. +$(TPL_BOOT): $(TIMESTAMP_FILE) $(VERSION_FILE) depend + $(MAKE) -C tpl/board/$(BOARDDIR) all Assume CONFIG_TPL_U_BOOT is not defined, then TPL_BOOT is not defined, and this rule will probably cause a build error, doesn't it? No, I don't think there is a build error. WEell, if CONFIG_TPL_U_BOOT is not 'y', then TPL_BOOT is not defined, which results in this make rule: : $(TIMESTAMP_FILE) $(VERSION_FILE) depend $(MAKE) -C tpl/board/$(BOARDDIR) all i. e. there would be no target name befoe the semicolon. If TPL_BOOT here is not defined, the reset(after semicolon) will not be executed, just like NAND_SPL and ONENAND_IPL etc. Sorry, I cannot follow - which reset? which semicolon? Sorry, :%s/reset/rest/. The semicolon is the same one in your previous comments. I meant the part: : $(TIMESTAMP_FILE) $(VERSION_FILE) depend $(MAKE) -C tpl/board/$(BOARDDIR) all If it is as you thought, then how the platforms will be built without NAND_SPL or ONENAND_IPL is not defined? Haiying ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 4/8 v2] powerpc/85xx: add TPL_BOOT support
On Sat, 2011-01-22 at 23:12 +0100, Wolfgang Denk wrote:
You should not undo a previous copyright. I guess you mean:
Copyright 2009-2010 Freescale Semiconductor, Inc.
?
Yes. Sorry about it.
+DECLARE_GLOBAL_DATA_PTR;
Please move this up to top of file.
OK.
+unsigned long get_tbclk(void)
+{
+#ifdef CONFIG_FSL_CORENET
+ return (gd-bus_clk + 8) / 16;
+#else
+ return (gd-bus_clk + 4UL)/8UL;
+#endif
This looks inconsistent. Either this should be ... +8UL) / 16UL or
... + 4) / 8;
This part was copied from arch/powerpc/cpu/mpc85xx/cpu.c, just want too reduce
the image size without including that file(cpu.c). Will fix it.
-#ifndef CONFIG_NAND_SPL
+#if !defined(CONFIG_NAND_SPL) !defined(CONFIG_TPL_BOOT)
GOT_ENTRY(_start)
GOT_ENTRY(_start_of_vectors)
GOT_ENTRY(_end_of_vectors)
GOT_ENTRY(transfer_to_handler)
-#endif
+#endif /* !CONFIG_TPL_BOOT || !CONFIG_NAND_SPL*/
Should that be
#endif /* !CONFIG_TPL_BOOT !CONFIG_NAND_SPL*/
instead?
Yes. Thanks for pointing out.
And can we please make this consistent, i. e. as you do in the
following:
+#endif /* !CONFIG_NAND_SPL !CONFIG_TPL_BOOT */
OK.
Thanks.
Haiying
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Re: [U-Boot] [PATCH 3/8 v2] Introduce the Tertiary Program loader
On Sat, 2011-01-22 at 23:04 +0100, Wolfgang Denk wrote: diff --git a/Makefile b/Makefile index 87a383d..94af465 100644 --- a/Makefile +++ b/Makefile @@ -290,6 +290,10 @@ LDPPFLAGS += \ $(shell $(LD) --version | \ sed -ne 's/GNU ld version \([0-9][0-9]*\)\.\([0-9][0-9]*\).*/-DLD_MAJOR=\1 -DLD_MINOR=\2/p') +ifeq ($(CONFIG_TPL_U_BOOT),y) +TPL_BOOT = tpl +endif I don't understand what the TPL_BOOT is good for, or how it's supposed to work. TPL_BOOT works like NAND_SPL but after NAND_SPL is executed. It is a middle stage boot loader to balance the 4K nand spl limitation which can not include ddr spd code and the 256K L2 SRAM size which can not accommodate the final uboot image on some Freescale Qoriq P1 platforms. The main purpose of tpl is to initialize the ddr with spd code in l2 sram then load the final uboot image to ddr. The reason to call tpl is because it runs after spl, the Second Program Loader. My original patch used CONFIG_MIDDLE_STAGE_SRAM_BOOT but you recommended to use CONFIG_SYS_2ND_STAGE_BOOT(http://lists.denx.de/pipermail/u-boot/2010-August/075653.html). However, 2ND STAGE is not correct here since it runs after SPL. ifeq ($(CONFIG_NAND_U_BOOT),y) NAND_SPL = nand_spl U_BOOT_NAND = $(obj)u-boot-nand.bin @@ -407,8 +411,15 @@ $(obj)u-boot.lds: $(LDSCRIPT) $(NAND_SPL): $(TIMESTAMP_FILE) $(VERSION_FILE) depend $(MAKE) -C nand_spl/board/$(BOARDDIR) all -$(U_BOOT_NAND):$(NAND_SPL) $(obj)u-boot.bin - cat $(obj)nand_spl/u-boot-spl-16k.bin $(obj)u-boot.bin $(obj)u-boot-nand.bin +$(TPL_BOOT): $(TIMESTAMP_FILE) $(VERSION_FILE) depend + $(MAKE) -C tpl/board/$(BOARDDIR) all Assume CONFIG_TPL_U_BOOT is not defined, then TPL_BOOT is not defined, and this rule will probably cause a build error, doesn't it? No, I don't think there is a build error. Has this code ever been tested? Yes, I tested it on P1021MDS board, and also built for other 85xx NAND_config without error. ... $(MAKE) -C $(TPL_BOOT)/board/$(BOARDDIR) all ?? +NAND_SPL_OBJS-y += $(obj)nand_spl/u-boot-spl-16k.bin +NAND_SPL_OBJS-$(CONFIG_TPL_U_BOOT) += $(obj)tpl/u-boot-tpl.bin +NAND_SPL_OBJS-y += $(obj)u-boot.bin Ditto here and in the following - but how is NAND_SPL related to TPL building? These should be completely independent? It came up with Mike Frysinger's comments http://lists.denx.de/pipermail/u-boot/2010-November/082373.html . It is applied in the case that the TPL is used with nand spl build. In fact, our another usage of TPL_BOOT is for SPI/SD boot. Patch will come is this set is accepted. + CONFIG_TPL_U_BOOT + + Builds a U-Boot image that contains a loader stub (tertiary + program loader -- TPL) that boots out of some type of RAM, + after being loaded by an SPL or similar platform-specific + mechanism. This symbol will be set in all build phases. + + CONFIG_TPL_BOOT + + This is set by the build system when compiling code to go into + the TPL. It is not set when building the code that the TPL + loads, or when building the SPL. Can we not do with a single variable definition? I did not get it. Could you please give a recommendation? Thanks. Haiying ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 7/8] powerpc/85xx: do not initialize QE if QE's firmware is in nand flash
On Wed, 2010-12-01 at 08:56 -0700, Kumar Gala wrote: diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 4b8faa5..eb34378 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -369,7 +369,7 @@ int cpu_init_r(void) enable_cpc(); -#ifdef CONFIG_QE +#if defined(CONFIG_QE) !defined(CONFIG_SYS_QE_FW_IN_NAND) uint qe_base = CONFIG_SYS_IMMR + 0x0008; /* QE immr base */ qe_init(qe_base); qe_reset(); -- 1.7.3.1.50.g1e633 Any reason to just not move QE init for everyone? That was based on Wolfgang's comment: http://lists.denx.de/pipermail/u-boot/2010-August/075657.html Haiying ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 7/8] powerpc/85xx: do not initialize QE if QE's firmware is in nand flash
On Wed, 2010-12-01 at 11:50 -0700, Kumar Gala wrote: Any reason to just not move QE init for everyone? That was based on Wolfgang's comment: http://lists.denx.de/pipermail/u-boot/2010-August/075657.html Haiying I think wolfgang's gripe is about putting the code into generic board_init_r(). I think we could move it so its in misc_init_r. So we should move qe_init out from cpu_init_r, and to a misc_init_r? should misc_init_r be defined also in 83xx/85xx's cpu_init.c file? You may see my 8/8 patch in which I defined misc_init_r for P1021 in it's board c file. I just did not want to touch the existing qe_init routines for 83xx/85xx. Haiying ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [STATUS] v2010.12-rc2 released
On Tue, 2010-11-30 at 08:00 -0700, Wolfgang Denk wrote: Hello everybody. I apologise for being a bit late with this announcement: * U-Boot v2010.12-rc2 was released on Sunday, November 28. * Release v2010.12 is (still) scheduled in 13 days: on December 13, 2010. Please help testing, and check if all your relevant patches have been included. Is it possible to pull Kumar's patch: http://lists.denx.de/pipermail/u-boot/2010-November/082099.html Since 8xxx ddr spd code calls hwconfig before relocating code, the most 85xx/86xx boards which use 8xxx ddr spd can not bring up without this patch. Haiying ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 09/24 V2] arch/powerpc/*/config.mk: makeCONFIG_SYS_LDSCRIPT settings work
On Thu, 2010-11-25 at 09:00 -0700, Wolfgang Denk wrote: As we try to get rid of board specific config.mk files we must provide a way for board specific settings of the LDSCRIPT variable (path to the linker script) where needed. We now implement the following hierarchy: - Highest priority has a #define CONFIG_SYS_LDCONFIG in the board config file. - If CONFIG_SYS_LDCONFIG is not set, and the system is booting from NAND (CONFIG_NAND_U_BOOT is set), then a board specific linker script board/$(BOARDDIR)/u-boot-nand.lds gets use. u-boot-nand.lds is not in board/$(BOARDDIR) for 85xx at least, it is in $(SRCTREE)/$(CPUDIR)/ - If we are not booting from NAND, we test if a processor specific linker script arch/powerpc/cpu/$(CPU)/u-boot.lds exists; if so we use that. should we use $(CPUDIR) instead of arch/powerpc/cpu/$(CPU)? Haiying ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 09/24 V2] arch/powerpc/*/config.mk:makeCONFIG_SYS_LDSCRIPT settings work
On Thu, 2010-11-25 at 10:19 -0700, Wolfgang Denk wrote: Dear Haiying Wang, In message 1290702018.2007.4.ca...@haiying-laptop you wrote: - If CONFIG_SYS_LDCONFIG is not set, and the system is booting from NAND (CONFIG_NAND_U_BOOT is set), then a board specific linker script board/$(BOARDDIR)/u-boot-nand.lds gets use. u-boot-nand.lds is not in board/$(BOARDDIR) for 85xx at least, it is in $(SRCTREE)/$(CPUDIR)/ This is not correct - situation before applying my patches: - find * -name u-boot-nand.lds arch/powerpc/cpu/mpc85xx/u-boot-nand.lds so your patch for arch/powerpc/config.mk will not get u-boot-nand.lds for mpc85xx boards, only for the boards below. Then 85xx boards still need to get the lds from board/$(BOARDIR)/config.mk. Is that what you want? board/amcc/acadia/u-boot-nand.lds board/amcc/bamboo/u-boot-nand.lds board/amcc/canyonlands/u-boot-nand.lds board/amcc/kilauea/u-boot-nand.lds board/amcc/sequoia/u-boot-nand.lds board/esd/pmc440/u-boot-nand.lds board/samsung/smdk6400/u-boot-nand.lds - If we are not booting from NAND, we test if a processor specific linker script arch/powerpc/cpu/$(CPU)/u-boot.lds exists; if so we use that. should we use $(CPUDIR) instead of arch/powerpc/cpu/$(CPU)? I'm not sure if CPUDIR is defined at that time. Did you try it out? CPUDIR is defined in config.mk, I tried it for 85xx/p1 boards and it worked. Haiying ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 15/24 V2] 83xx: Cleanup for partial linking and--gc-sections
On Thu, 2010-11-25 at 09:00 -0700, Wolfgang Denk wrote: Signed-off-by: Wolfgang Denk w...@denx.de Cc: Kim Phillips kim.phill...@freescale.com --- Kim, allthough the 83xx boards appear to build fine at first glance, some (or all?) of the NAND boot images are 4 GB in size. Could you please have a look what's going wrong there? Thanks. Kim, if it's OK with you I will pull this directly. arch/powerpc/cpu/mpc83xx/u-boot.lds | 53 ++ 1 files changed, 10 insertions(+), 43 deletions(-) I think the u-boot.lds in nand_spl/board/freescale/mpc83xx/ needs to have the fix as well. Haiying ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 15/24 V2] 83xx: Cleanup for partial linking and--gc-sections
On Thu, 2010-11-25 at 11:32 -0700, Wolfgang Denk wrote: Dear Haiying Wang, In message 1290709405.2007.16.ca...@haiying-laptop you wrote: I think the u-boot.lds in nand_spl/board/freescale/mpc83xx/ needs to have the fix as well. Which fix do you mean? I see two such files: nand_spl/board/freescale/mpc8313erdb/u-boot.lds nand_spl/board/freescale/mpc8315erdb/u-boot.lds They are identical and look sane to me. OK, we can drop the *(.eh_frame) line, but it doesn't hurt either. Which exact fix do you have in mind? I mean: - *(.got2) + KEEP(*(.got2)) ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 09/24 V2] arch/powerpc/*/config.mk:makeCONFIG_SYS_LDSCRIPT settings work
On Thu, 2010-11-25 at 11:28 -0700, Wolfgang Denk wrote: Dear Haiying Wang, In message 1290708988.2007.13.ca...@haiying-laptop you wrote: u-boot-nand.lds is not in board/$(BOARDDIR) for 85xx at least, it is in $(SRCTREE)/$(CPUDIR)/ This is not correct - situation before applying my patches: - find * -name u-boot-nand.lds arch/powerpc/cpu/mpc85xx/u-boot-nand.lds Oops, sorry. I missed that one, even though I was looking for it :-( so your patch for arch/powerpc/config.mk will not get u-boot-nand.lds for mpc85xx boards, only for the boards below. Then 85xx boards still need to get the lds from board/$(BOARDIR)/config.mk. Is that what you want? No, not really. But actually I was just cleaning up probems where ran into them, not trying to perform a more general cleanup [*]. The situation is that the relevant 85xx boards appeare to have their own config.mk files which explicitly set LDSCRIPT to the value they need (which is indeed different from the default that gets set up ib arch/powerpc/config.mk: arch/powerpc/config.mk: LDSCRIPT := $(SRCTREE)/$(CONFIG_BOARDDIR)/u-boot-nand.lds board/freescale/mpc8536ds/config.mk: LDSCRIPT := $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds board/freescale/mpc8569mds/config.mk: LDSCRIPT := $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds board/freescale/p1_p2_rdb/config.mk: LDSCRIPT := $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds So it seems my patches do not have any impact on the building of 85xx systems. Or am I missing something? No, your patch doesn't have impact on them. I just wonder if you wanted to apply your patch for 85xx board.:) Haiying ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 3/7] Add support for third program loader
On Tue, 2010-11-23 at 13:57 -0700, Wolfgang Denk wrote: Dear Haiying Wang, Does CONFIG_TPL_UBOOT make sense to you if I replace CONFIG_SYS_TPL_BOOT with it? I cannot answer this. Don't understand any of this. Maybe you can re-think this again and try to make it less complex, and the add a description of the then used new variables to the README. We need this documentation anyway. Maybe I can understand this documentation then, and provide better comment. Sorry, Sorry for the unclear statement in patch. A new patch is sending out soon to only address the changes in Makefile and add the description in README. Thanks. Haiying ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] patch for gc-sections
On Thu, 2010-11-04 at 14:22 -0400, Haiying Wang wrote: On Thu, 2010-11-04 at 09:36 -0700, Peter Tyser wrote: Glad to hear. I'll submit an official patch shortly. Just to make sure, have you tried running one of the nand-spl images after the patch I sent yesterday? It'd be good to get confirmation that the -gc-sections doesn't have any accidental side effects as I wasn't able to test it. Because of the second bug, I can not test it based on the top of the uboot tree. I just use 2010.06 version plus your two patches, and run the nand-spl image on MPC8569MDS board. Only NAND boot... transfering control is printed out in the terminal. It means the final u-boot image doesn't work. Then I make changes to u-boot-nand.lds and u-boot-nand_spl.lds, following the changes you made for u-boot.lds, I get the first u-boot line U-Boot 2010.06... printed out which means the final u-boot image can work a little bit. But nothing else is showed up in terminal. Do you have any idea on how to make changes to u-boot-nand/_spl.lds? I figured out the problem now. The bootpg was removed by --gc-section as well, so I need to add KEEP for it in u-boot-nand.lds. Patch will come out, I tested on MPC8569MDS board against top of the tree. Haiying ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] nand spl build with wrong CONFIG_SYS_TEXT_BASE
Dear Wolfgang, On Mon, 2010-11-08 at 16:36 -0700, Wolfgang Denk wrote: Dear Haiying Wang, Why it looks broken? I do need CONFIG_NAND defined for 8536DS nand build. For building nand uboot, 2 images are needed, one is 4K nand_spl Yes. But there is also MPC8536DS and MPC8536DS_36BIT and MPC8536DS_SDCARD and MPC8536DS_SPIFLASH which do NOT define CONFIG_NAND, but they too need a definition of CONFIG_SYS_TEXT_BASE. MPC8536DS/_36BIT/_SDCARD/_SPIFLASH are in parallel with _NAND. I understand they all need their CONFIG_SYS_TEXT_BASE. But here we talk about the MPC8536DS_NAND_config which need two uboot images, each should have its own CONFIG_SYS_TEXT_BASE. e.g. in u-boot/Makefile $(U_BOOT_NAND): $(NAND_SPL) $(obj)u-boot.bin cat $(obj)nand_spl/u-boot-spl-16k.bin $(obj)u-boot.bin $(obj)u-boot-nand.bin u-boot-spl-16k.bin needs 0xfff0 as CONFIG_SYS_TEXT_BASE u-boot.bin needs 0xf8f82000 as CONFIG_SYS_TEXT_BASE Well, I guess it also showed where the previous definition came from?. Yes, it showed the first definition of CONFIG_SYS_TEXT_BASE in my example code which is 0xfff0 in MPC8536DS.h was redefined. But in fact, I need that value instead of 0xf8f82000 for nand spl. You did not answer my question. The error message shows _where_ the previous definition came from. Please check this. OK, the error message is: In file included from /home/haiying/Opensource/Kumar/u-boot-mpc85xx/include/config.h:5, from ns16550.c:7: /home/haiying/Opensource/Kumar/u-boot-mpc85xx/include/configs/MPC8536DS.h:40:1: warning: CONFIG_SYS_TEXT_BASE redefined Here are the lines in MPC8536DS.h(using git diff result, so that the changes I made can be seen clearly) diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index 8b8f467..0eb3072 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -36,8 +36,12 @@ 36: #ifdef CONFIG_NAND 37: #define CONFIG_NAND_U_BOOT 1 38: #define CONFIG_RAMBOOT_NAND1 39:+#ifdef CONFIG_NAND_SPL 40:+#define CONFIG_SYS_TEXT_BASE 0xfff0 41:+#else 42: #define CONFIG_SYS_TEXT_BASE 0xf8f82000 43: #endif 44: +#endif CONFIG_NAND was used for the final uboot image, and CONFIG_NAND_SPL was used for nand_spl image. However, after that commit, the CONFIG_NAND combined the usage of CONFIG_MK_NAND and CONFIG_NAND. Right. Why would we need two different defines for the same thing? I need two different defines for generating the different image, which are under the same CONFIG_NAND defines now. Try to find out where that redefine is coming from, and fix that. And fix the ,NAND flag in boards.cfg if this is not what you want. The redefine came from the define of CONFIG_SYS_TEXT_BASE for nand_spl. Sorry, but this makes no sense. If the code looks as above, there is always at most one define of CONFIG_SYS_TEXT_BASE in the board config file (actually it's missing for boards that don't define CONFIG_NAND). Yes, now the problem is only one define of CONFIG_SYS_TEXT_BASE is allowed for one board config,i.e CONFIG_NAND, but two images need to be generated for nand boot, one is u-boot-spl.bin, the other is u-boot.bin. They need different CONFIG_SYS_TEXT_BASE. Haiying ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] nand spl build with wrong CONFIG_SYS_TEXT_BASE
On Tue, 2010-11-09 at 09:23 -0700, Wolfgang Denk wrote: Dear Haiying Wang, Is this all the error messages you get? Normally tehre should be another message, for example: [filename]:[lineno]:[column]: warning: this is the location of the previous definition or, if there was a -DCONFIG_SYS_TEXT_BASE=... on the command line: command-line: warning: this is the location of the previous definition It is in one of the error messages, there are others for the same error. Here is the total message when building tlb.c for nand_spl: powerpc-none-linux-gnuspe-gcc -g -Os -mrelocatable -fPIC -meabi -ffunction-sections -fdata-sections -D__KERNEL__ -DCONFIG_SYS_TEXT_BASE=0xf8f82000 -DRESET_VECTOR_ADDRESS=0xeffc -I/home/haiying/u-boot-mpc85xx/include -fno-builtin -ffreestanding -nostdinc -isystem /opt/freescale/usr/local/gcc-4.3.74-eglibc-2.8.74-dp-2/powerpc-none-linux-gnuspe/lib/gcc/powerpc-none-linux-gnuspe/4.3.2/include -pipe -DCONFIG_PPC -D__powerpc__ -ffixed-r2 -Wa,-me500 -msoft-float -mno-string -mspe=yes -mno-spe -Wall -Wstrict-prototypes -fno-stack-protector -DCONFIG_NAND_SPL -c -o tlb.o tlb.c In file included from /home/haiying/u-boot-mpc85xx/include/config.h:5, from /home/haiying/u-boot-mpc85xx/include/common.h:37, from tlb.c:26: /home/haiying/u-boot-mpc85xx/include/configs/MPC8536DS.h:40:1: warning: CONFIG_SYS_TEXT_BASE redefined command-line: warning: this is the location of the previous definition Here are the lines in MPC8536DS.h(using git diff result, so that the changes I made can be seen clearly)ing This doesn't help, as it doesn't show where the other definition is coming from. The other definition comes from include/autoconf.mk, I think. Haiy ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] nand spl build with wrong CONFIG_SYS_TEXT_BASE
On Tue, 2010-11-09 at 14:11 -0700, Wolfgang Denk wrote: Dear Scott Wood, In message 20101109143747.685f9...@udp111988uds.am.freescale.net you wrote: I don't see how #ifdef NAND_SPL #define CONFIG_SYS_TEXT_BASE xxx #else #define CONFIG_SYS_TEXT_BASE yyy #endif is more of a maintenance problem than #define CONFIG_SYS_TEXT_BASE_SPL xxx #define CONFIG_SYS_TEXT_BASE yyy followed by multiple instances of #ifdef NAND_SPL do something with CONFIG_SYS_TEXT_BASE_SPL #else do something with CONFIG_SYS_TEXT_BASE #endif Assuming that your code really needs to know the start address of the image, it should probably do something like this instead: #ifdef NAND_SPL #define CONFIG_SYS_TEXT_BASE xxx #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE #else #define CONFIG_SYS_TEXT_BASE yyy #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE #endif This doesn't make sense if there is still one autoconfig.mk. The value for CONFIG_SYS_TEXT_BASE will always be yyy for NAND_SPL. Haiying ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] nand spl build with wrong CONFIG_SYS_TEXT_BASE
Dear Wolfgang, On Sun, 2010-11-07 at 14:31 -0700, Wolfgang Denk wrote: Dear Haiying Wang, In message 1288970062.1855.44.ca...@haiying-laptop you wrote: Wolfgang's latest commit to change all TEXT_BASE to CONFIG_SYS_TEXT_BASE breaks the build for nand_spl. He defined CONFIG_SYS_TEXT_BASE in board Which board(s) / configuration(s) are you talkign about? I meant freescale 8536/8569/p1_p2 boards, and their NAND_config build. header file for CONFIG_NAND, and renamed TEXT_BASE to CONFIG_SYS_TEXT_BASE in nand_spl/board/.../Makefile. Then for u-boot-spl, the CONFIG_SYS_TEXT_BASE is always the value defined in header file, which is, for example, 0xf8f82000 for MPC8536/8569/p1_p2/, not the one defined in nand-spl's Makefile, which is 0xfff0. Thus it It is fundamentally broken to define such settings in a Makefile. They do not belong there, an never did. If you take for example the MPC8536DS_NAND configuration, this defines CONFIG_NAND as indication for the NAND booting config option, so it should be trivial to add some #ifdef CONFIG_NAND #define CONFIG_SYS_TEXT_BASE ... #else #define CONFIG_SYS_TEXT_BASE ... #endif to the respective board config file(s). Before sending last email, I modified the CONFIG_SYS_TEXT_BASE in 8536DS header file like this: #ifdef CONFIG_NAND #ifdef CONFIG_NAND_SPL #define CONFIG_SYS_TEXT_BASE 0xfff0 #else #define CONFIG_SYS_TEXT_BASE 0xf8f82000 #endif #endif but still get 0xf8f82000 for NAND SPL image, which should have 0xfff0 as its CONFIG_SYS_TEXT_BASE. And build log showed me warning: CONFIG_SYS_TEXT_BASE redefined In fact, your change above seems no meaning for NAND _SPL because NAND_SPL also has CONFIG_NAND defined. Can you take a look at it? Defining CONFIG_SYS_TEXT_BASE in header file does impact the TEXT_BASE defined in Makefile for nand_spl. Please remove any such defines from Makefiles. You meant the CONFIG_SYS_TEXT_BASE can only be defined in board header files? But you change all the TEXT_BASE to CONFIG_SYS_TEXT_BASE in the Makefile or config.mk for almost all boards under nand_spl, which I guess you were OK with it.:) I did not understand why old way to define TEXT_BASE in Makefile worked but changing it to CONFIG_SYS_TEXT_BASE doesn't work any more. And as you pointed out, defining CONFIG_SYS_TEXT_BASE in header file is the right way, but it did not work for nans_spl for now. Thanks. Haiying ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] nand spl build with wrong CONFIG_SYS_TEXT_BASE
On Mon, 2010-11-08 at 09:30 -0700, Wolfgang Denk wrote: Dear Haiying Wang, In message 1289230710.1900.27.ca...@haiying-laptop you wrote: Before sending last email, I modified the CONFIG_SYS_TEXT_BASE in 8536DS header file like this: #ifdef CONFIG_NAND #ifdef CONFIG_NAND_SPL #define CONFIG_SYS_TEXT_BASE 0xfff0 #else #define CONFIG_SYS_TEXT_BASE 0xf8f82000 #endif #endif This looks broken to me. If you have CONFIG_NAND not defined you have no CONFIG_SYS_TEXT_BASE definition at all. Why it looks broken? I do need CONFIG_NAND defined for 8536DS nand build. For building nand uboot, 2 images are needed, one is 4K nand_spl which should have CONFIG_SYS_TEXT_BASE at 0xfff0, the other is the final uboot image which has CONFIG_SYS_TEXT_BASE at 0xf8f82000. Both CONFIG_SYS_TEXT_BASE are now under the define of CONFIG_NAND. but still get 0xf8f82000 for NAND SPL image, which should have 0xfff0 as its CONFIG_SYS_TEXT_BASE. And build log showed me warning: CONFIG_SYS_TEXT_BASE redefined Well, I guess it also showed where the previous definition came from? Yes, it showed the first definition of CONFIG_SYS_TEXT_BASE in my example code which is 0xfff0 in MPC8536DS.h was redefined. But in fact, I need that value instead of 0xf8f82000 for nand spl. In fact, your change above seems no meaning for NAND _SPL because NAND_SPL also has CONFIG_NAND defined. Well, then your bord entry in boards.cfg makes no sense. The NAND-booting board configurations auto-define CONFIG_NAND. If this is not what you want then please feel free to change it. Yes, 8356DS's board entry in boards.cfg does make sense. It has CONFIG_NAND defined for MPC8536DS_NAND_config. Again, CONFIG_NAND means two stage uboot image needs to be generated, each of them has different CONFIG_SYS_TEXT_BASE. I think the previous uboot(before your commit to change CONFIG_MK to CONFIG_), CONFIG_MK_NAND was used for NAND_booting board configuration, CONFIG_NAND was used for the final uboot image, and CONFIG_NAND_SPL was used for nand_spl image. However, after that commit, the CONFIG_NAND combined the usage of CONFIG_MK_NAND and CONFIG_NAND. Please remove any such defines from Makefiles. You meant the CONFIG_SYS_TEXT_BASE can only be defined in board header files? But you change all the TEXT_BASE to CONFIG_SYS_TEXT_BASE in the Makefile or config.mk for almost all boards under nand_spl, which I guess you were OK with it.:) If there is any such code left, it should be cleaned up. Yes, there is such code. I did not understand why old way to define TEXT_BASE in Makefile worked but changing it to CONFIG_SYS_TEXT_BASE doesn't work any more. And as you pointed out, defining CONFIG_SYS_TEXT_BASE in header file is the right way, but it did not work for nans_spl for now. Try to find out where that redefine is coming from, and fix that. And fix the ,NAND flag in boards.cfg if this is not what you want. The redefine came from the define of CONFIG_SYS_TEXT_BASE for nand_spl. In summary, the problem is how the 2 uboot images(nand_spl and final uboot image) can get different CONFIG_SYS_TEXT_BASE under the shared CONFIG_NAND. Haiying ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] nand spl build with wrong CONFIG_SYS_TEXT_BASE
Hi Scott, Wolfgang's latest commit to change all TEXT_BASE to CONFIG_SYS_TEXT_BASE breaks the build for nand_spl. He defined CONFIG_SYS_TEXT_BASE in board header file for CONFIG_NAND, and renamed TEXT_BASE to CONFIG_SYS_TEXT_BASE in nand_spl/board/.../Makefile. Then for u-boot-spl, the CONFIG_SYS_TEXT_BASE is always the value defined in header file, which is, for example, 0xf8f82000 for MPC8536/8569/p1_p2/, not the one defined in nand-spl's Makefile, which is 0xfff0. Thus it causes the nand_spl image has wrong address from 0xf8f82000. When PAD_TO 0xfff01000, the final u-boot-spl-16k.bin will be 112M bytes. I think 83xx nand_spl might have the similar problem, but as I built 8315erdb's nand, it failed for some other multiple define for undef errors. Can you take a look at it? Defining CONFIG_SYS_TEXT_BASE in header file does impact the TEXT_BASE defined in Makefile for nand_spl. Thanks. Haiying ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] patch for gc-sections
On Wed, 2010-11-03 at 13:38 -0700, Peter Tyser wrote: I'd guess none of the functions in the SPL binary are referenced in the linker script or linker command line, so the linker thinks none of them are necessary and removes them. Can you try the following patch: I did a quick compile test, and it seemed to work, as well as stripped out a few unused functions. Thanks for your patch, it did work to generate the binary, however, there are two problems: 1. The u-boot size for nand_spl is not cut down as expected. /* before apply your new patch */ 29292 2010-11-04 09:29 nand_spl/u-boot-spl 0 2010-11-04 09:29 nand_spl/u-boot-spl-16k.bin 0 2010-11-04 09:29 nand_spl/u-boot-spl.bin 13931 2010-11-04 09:29 nand_spl/u-boot-spl.map /* After apply your new patch */ 35636 2010-11-04 09:49 nand_spl/u-boot-spl 116912128 2010-11-04 09:49 nand_spl/u-boot-spl-16k.bin 4096 2010-11-04 09:49 nand_spl/u-boot-spl.bin 16381 2010-11-04 09:49 nand_spl/u-boot-spl.map /* Remove your two patches(remove gc-section patch and this new patch */ 34094 2010-11-04 09:51 nand_spl/u-boot-spl 116912128 2010-11-04 09:51 nand_spl/u-boot-spl-16k.bin 4096 2010-11-04 09:51 nand_spl/u-boot-spl.bin 14097 2010-11-04 09:51 nand_spl/u-boot-spl.map 2.the u-boot-spl.bin is 4096 bytes, and u-boot-spl-16.bin which should be padded to 4K bytes is 116912128 bytes. You can take a look at nand_spl/board/freescale/mpc8536ds/Makefile to see how u-boot-spl.bin/u-boot-spl-16k.bin is generated. I don't know which patch(not your gc-section for sure) cause this problem. I just reset my git tree to 2010.06, the size is: 33512 2010-11-04 10:07 nand_spl/u-boot-spl 4096 2010-11-04 10:07 nand_spl/u-boot-spl-16k.bin 4096 2010-11-04 10:07 nand_spl/u-boot-spl.bin 14037 2010-11-04 10:07 nand_spl/u-boot-spl.map So we need to find out the cause for the huge u-boot-spl-16k.bin. Anyway, thanks for taking care of this. Haiying ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] patch for gc-sections
On Thu, 2010-11-04 at 08:45 -0700, Peter Tyser wrote: Can you explain what you mean? The binary needs to be 4K, right? So it can't be trimmed down. But there should be more available space in that 4K region, eg (all tests on MPC8536DS_NAND_config): /* After apply my patch sent yesterday */ pty...@petert u-boot $ size after/u-boot-spl textdata bss dec hex filename 3440 460 03900 f3c after/u-boot-spl /* Remove my two patches(remove gc-section patch and this new patch) */ pty...@petert u-boot $ size before/u-boot-spl textdata bss dec hex filename 3620 460 04080 ff0 before/u-boot-spl Yes, you are right, the size is down. I only noticed the u-boot-spl size by using ls -l, not via size. Now I get the same result as yours. It is very good to see this trim-down size because I know some board developers are fighting with the 4k limitation of the nand-spl size. Are you going to submit your new patch to upstream? Btw, the filesize I see here is smaller than yours, I guess you are using the most updated gcc version. I am using gcc-4.3.2. I batted an eye when I saw the 112M file to, but it looks like that is unrelated to my change: It is not related to your change, I see it happens on 2010.09 which doesn't have your change. Something between 2010.06 and 2010.09 makes this happen. Thanks. Haiying ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] patch for gc-sections
On Thu, 2010-11-04 at 09:36 -0700, Peter Tyser wrote: Glad to hear. I'll submit an official patch shortly. Just to make sure, have you tried running one of the nand-spl images after the patch I sent yesterday? It'd be good to get confirmation that the -gc-sections doesn't have any accidental side effects as I wasn't able to test it. Because of the second bug, I can not test it based on the top of the uboot tree. I just use 2010.06 version plus your two patches, and run the nand-spl image on MPC8569MDS board. Only NAND boot... transfering control is printed out in the terminal. It means the final u-boot image doesn't work. Then I make changes to u-boot-nand.lds and u-boot-nand_spl.lds, following the changes you made for u-boot.lds, I get the first u-boot line U-Boot 2010.06... printed out which means the final u-boot image can work a little bit. But nothing else is showed up in terminal. Do you have any idea on how to make changes to u-boot-nand/_spl.lds? Thanks. Haiying ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] patch for gc-sections
Peter, Do you have any idea on why your commit: commit fbe53f59bd40b3b1ab66dc98859e26589d64d1b7 Author: Peter Tyser pty...@xes-inc.com Date: Wed Sep 29 14:05:56 2010 -0500 85xx: Use gc-sections to reduce image size which made change to : --- a/arch/powerpc/cpu/mpc85xx/config.mk +++ b/arch/powerpc/cpu/mpc85xx/config.mk @@ -25,6 +25,10 @@ PLATFORM_RELFLAGS += -fPIC -meabi PLATFORM_CPPFLAGS += -ffixed-r2 -Wa,-me500 -msoft-float -mno-string +# Enable gc-sections to enable generation of smaller images. +PLATFORM_LDFLAGS += --gc-sections +PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections makes the u-boot-spl.bin, u-boot-spl-16k.bin to 0 bytes? At least I tried to build MPC8536DS_NAND_config, MPC8569MDS_NAND_config, P1021MDS_NAND_config, and got 0 bytes of those nand_spl binaries for them all. Thanks. Haiying ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/3] mpc8569mds: fix CONFIG_ENV_SIZE
On Wed, 2010-29-09 at 20:25 +0200, Wolfgang Denk wrote: You submitted the same patch series twice, without any version ID in the subject, and without any other indication about possible changes. I am so sorry for sending the patchset twice. I did not add smtp-server at the first time, then I thought the patches were lost since the same thing happened in last month. Obviously I was wrong. Is there any difference between both patch series, and if so, what is it? No difference. Haiying ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 3/7] Add support for SRAM Boot
On Mon, 2010-16-08 at 12:23 +0200, Wolfgang Denk wrote: Dear Haiying Wang, In message 1281945897.24612.17.ca...@localhost.localdomain you wrote: Once CONFIG_MIDDLE_STAGE_SRAM_BOOT is defined, CONFIG_SRAM_BOOT is enabled to generate u-boot-sram.bin which will run in the l2/l3 sram. This middle stage uboot will init ddr sdram with ddr spd code and load the final uboot image to ddr and start from there. It is useful for the silicons which have small l2/l3 size under the two scenarios: 1. NAND boot. The 4k NAND SPL uboot can not enable the spd ddr code to initialize the ddr because of the 4k size limitation, and the l2/l3 as SRAM also is not large enough to acoommodate the final uboot image. 2. SD/eSPI boot. we don't want to statically init ddr in SD/eSPI's configuration part, but l2/l3 as SRAM is small for final uboot. The concept may be useful for other situations as well, so we should try and make this as generic as possible. First, the name CONFIG_MIDDLE_STAGE_SRAM_BOOT is too long and too specific to your case. Please use a more generic name, for example CONFIG_SYS_2ND_STAGE_BOOT or similar (I don't think this is a user configurable option, hence the CONFIG_SYS_) OK. will rename it. This patch has nand boot support, SD/eSPI support will be submited later. Because ddr spd code calls some functions defined the files in common/ and lib/,#ifndef CONFIG_SRAM_BOOT is used in those files to keep the sram uboot size as small as possible. Line too long. will fix it. Signed-off-by: Haiying Wang haiying.w...@freescale.com --- Makefile | 18 ++- arch/powerpc/cpu/mpc85xx/cpu_init_nand.c | 31 +++- arch/powerpc/cpu/mpc85xx/sram_boot/Makefile| 190 arch/powerpc/cpu/mpc85xx/sram_boot/sram_boot.c | 76 .../cpu/mpc85xx/sram_boot/u-boot-sram-boot.lds | 101 +++ The code for this should not live in some specific 85xx directory, but instead be generalized similar to what we have with nand_spl. Should we let it structured as $(TOPDIR)/sram_boot/board/freescale? At least current, the above code is mostly only used for 85xx. The only common part I can tell is the changes in Makefile. ... --- a/Makefile +++ b/Makefile ... +$(SRAM_BOOT): $(TIMESTAMP_FILE) $(VERSION_FILE) $(obj)include/autoconf.mk + $(MAKE) -C $(CPUDIR)/sram_boot all + +$(U_BOOT_NAND_SRAM): $(NAND_SPL) $(SRAM_BOOT) $(obj)u-boot.bin + cat $(obj)nand_spl/u-boot-spl-16k.bin $(obj)$(CPUDIR)/u-boot-sram.bin $(obj)u-boot.bin $(obj)u-boot-nand.bin We really need bette rnames here, too. Does SRAM_BOOT/sram_boot sound bad? :) ... diff --git a/arch/powerpc/cpu/mpc85xx/sram_boot/Makefile b/arch/powerpc/cpu/mpc85xx/sram_boot/Makefile new file mode 100644 index 000..7c86095 --- /dev/null +++ b/arch/powerpc/cpu/mpc85xx/sram_boot/Makefile @@ -0,0 +1,190 @@ +# +# Copyright (C) 2010 Freescale Semiconductor, Inc. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of the GNU General Public License as published by the Free +# Software Foundation; either version 2 of the License, or (at your option) +# any later version. +# + +SRAM_BOOT := y + +include $(TOPDIR)/config.mk + +LDSCRIPT= $(TOPDIR)/$(CPUDIR)/sram_boot/u-boot-sram-boot.lds +LDFLAGS= -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS) +AFLAGS += -DCONFIG_SRAM_BOOT +CFLAGS += -DCONFIG_SRAM_BOOT + +SOBJS = start.o ticks.o ppcstring.o +COBJS = cache.o cpu_init_early.o cpu_init_nand.o fsl_law.o law.o speed.o \ + sram_boot.o ns16550.o tlb.o tlb_table.o string.o hwconfig.o ddr.o \ + time.o time_lib.o ddr-gen3.o ddr_spd.o ctype.o div64.o console.o \ + cmd_nvedit.o env_common.o env_nand.o vsprintf.o display_options.o You do not want to duplicate all this stuff here. This makes no sense. Also, it is unmaintainable. For this case, I need to call some functions like getenv, hwconfig, printf, strcmp etc. which are needed in ddr spd code, but I don't want to link the libs for those file because if so, the 2nd stage uboot will be larger. It might also not be a good idea to copy all those functions into some new files which are really duplicate. I agree it is unmaintainable here. As Scott pointed, we need to find a better way. Any suggestion? diff --git a/arch/powerpc/cpu/mpc85xx/sram_boot/sram_boot.c b/arch/powerpc/cpu/mpc85xx/sram_boot/sram_boot.c new file mode 100644 index 000..7b90eee --- /dev/null +++ b/arch/powerpc/cpu/mpc85xx/sram_boot/sram_boot.c ... +const char *board_hwconfig = foo:bar=baz; +const char *cpu_hwconfig = foo:bar=baz; This does not exactly look like useful values to me. The only use is to make board_hwconfig and cpu_hwconfig from sbss to sdata section
Re: [U-Boot] [PATCH 4/7] powerpc/p1021: Add P1021MDS board support
On Mon, 2010-16-08 at 12:33 +0200, Wolfgang Denk wrote: --- /dev/null +++ b/board/freescale/p1021mds/bcsr.h @@ -0,0 +1,18 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + * + */ + +#ifndef __BCSR_H_ +#define __BCSR_H_ + +#include common.h + +/*BCSR Utils functions*/ +void reset_p1021mds_micrel_phy(void); +#endif /* __BCSR_H_ */ Please avoid adding a new header file just for this single prototype. This was copied from mpc8568mds/mpc8569mds. If it is not allowed anymore, I can remove it. Why do you need a separate one anyway? Because it is p1021mds board specific reset routine. Why cannot you implement this in reset_phy() ? reset_phy() is a one time reset and called after eth_initialize(). But the board designer told me to reset phy for each UEC port before initializing it, otherwise the phy can not work properly. Haiying ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 6/7] powerpc/qe: supports loading QE firmware from nand flash
On Mon, 2010-16-08 at 12:40 +0200, Wolfgang Denk wrote:
Dear Haiying Wang,
In message 1281947090.24612.23.ca...@localhost.localdomain you wrote:
and because some platforms need to load QE firmware from NAND flash(no NOR
flash), it makes qe_init to be called after nand_init.
Signed-off-by: Haiying Wang haiying.w...@freescale.com
---
arch/powerpc/cpu/mpc83xx/cpu_init.c |8
arch/powerpc/cpu/mpc85xx/cpu_init.c |8
arch/powerpc/lib/board.c| 31 +++
3 files changed, 31 insertions(+), 16 deletions(-)
Please do not throw such stuff into common code. Use board /
architecture specific implementations instead (say, provide some
misc_init_r() or so).
QE is not a misc feature for the SOCs with QE. It actually makes more
sense to enable it in cpu init code. But P1021 doesn't have ROM in QE,
and P1021mds doesn't have NOR flash on board, so I move this cpu feature
to board.c. How about re-spin this patch as:
---
arch/powerpc/cpu/mpc85xx/cpu_init.c |2 +-
arch/powerpc/lib/board.c| 15 +++
2 files changed, 16 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c
b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 1fbc0cc..1021575 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -369,7 +369,7 @@ int cpu_init_r(void)
enable_cpc();
-#ifdef CONFIG_QE
+#if defined(CONFIG_QE) !defined(CONFIG_SYS_QE_FW_IN_NAND)
uint qe_base = CONFIG_SYS_IMMR + 0x0008; /* QE immr base */
qe_init(qe_base);
qe_reset();
diff --git a/arch/powerpc/lib/board.c b/arch/powerpc/lib/board.c
index 0e00d86..aae6e23 100644
--- a/arch/powerpc/lib/board.c
+++ b/arch/powerpc/lib/board.c
@@ -783,6 +783,21 @@ void board_init_r (gd_t *id, ulong dest_addr)
nand_init();/* go init the NAND */
#endif
+ /* QE needs to be initialized after nand_init because some boards have
+* to save QE firmware in NAND flash.
+*/
+#if defined(CONFIG_QE) defined(CONFIG_SYS_QE_FW_IN_NAND)
+#ifdef CONFIG_SYS_QE_FW_IN_NAND
+ /* load QE firmware from NAND flash to DDR first */
+ ret = nand_read(nand_info[0], (loff_t)CONFIG_SYS_QE_FW_IN_NAND,
+ fw_length, (u_char *)CONFIG_SYS_QE_FW_ADDR);
+
+ if (ret ret == -EUCLEAN) {
+ printf (NAND read for QE firmware at offset %x failed %d\n,
+ (loff_t)CONFIG_SYS_QE_FW_IN_NAND, ret);
+ }
+#endif /* CONFIG_QE CONFIG_SYS_QE_FW_IN_NAND */
+
/* relocate environment function pointers etc. */
env_relocate ();
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[U-Boot] [PATCH] common/cmd_mmc.c: fix a bug
introduced by commit cc9f607beb49d4d3556c326efb83a0a51784e484, it causes: cmd_mmc.c:136:2: warning: missing terminating character cmd_mmc.c:133: error: missing terminating character make[1]: *** [cmd_mmc.o] Error 1 Signed-off-by: Haiying Wang haiying.w...@freescale.com --- common/cmd_mmc.c |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/common/cmd_mmc.c b/common/cmd_mmc.c index a6ed6a8..c0b30d8 100644 --- a/common/cmd_mmc.c +++ b/common/cmd_mmc.c @@ -133,7 +133,7 @@ int do_mmcinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) U_BOOT_CMD( mmcinfo, 2, 0, do_mmcinfo, display MMC info, - dev num\n + dev num\n - device number of the device to dislay info of\n ); -- 1.7.0 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 0/7] patch set for P1021MDS support
On Mon, 2010-16-08 at 07:42 +0200, Wolfgang Denk wrote: Dear Haiying Wang, Please keep in mind that patches shall be submitted against the mainline repository, NOPT against any custodian branches. This is to make sure everybody can apply and test these without addinitional compatibility issues. Ok, will send patch against mainline. It's odd that my patches sent with this [PATCH 0/7] did not show up in the maillist, including the three 8569 patches I sent last week. Any patch after this mail is against mainline. Thanks. Haiying ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/7] nand_spl: remove static for nand_load
so it can be called in other file.
Signed-off-by: Haiying Wang haiying.w...@freescale.com
---
nand_spl/nand_boot_fsl_elbc.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/nand_spl/nand_boot_fsl_elbc.c b/nand_spl/nand_boot_fsl_elbc.c
index 9547d44..efac293 100644
--- a/nand_spl/nand_boot_fsl_elbc.c
+++ b/nand_spl/nand_boot_fsl_elbc.c
@@ -47,7 +47,7 @@ static void nand_wait(void)
}
}
-static void nand_load(unsigned int offs, int uboot_size, uchar *dst)
+void nand_load(unsigned int offs, int uboot_size, uchar *dst)
{
fsl_lbc_t *regs = LBC_BASE_ADDR;
uchar *buf = (uchar *)CONFIG_SYS_NAND_BASE;
--
1.7.0
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[U-Boot] [PATCH 3/7] Add support for SRAM Boot
Once CONFIG_MIDDLE_STAGE_SRAM_BOOT is defined, CONFIG_SRAM_BOOT is enabled to
generate u-boot-sram.bin which will run in the l2/l3 sram. This middle stage
uboot will init ddr sdram with ddr spd code and load the final uboot image to
ddr and start from there. It is useful for the silicons which have small l2/l3
size under the two scenarios:
1. NAND boot. The 4k NAND SPL uboot can not enable the spd ddr code to
initialize the ddr because of the 4k size limitation, and the l2/l3 as SRAM also
is not large enough to acoommodate the final uboot image.
2. SD/eSPI boot. we don't want to statically init ddr in SD/eSPI's configuration
part, but l2/l3 as SRAM is small for final uboot.
This patch has nand boot support, SD/eSPI support will be submited later.
Because ddr spd code calls some functions defined the files in common/ and
lib/,#ifndef CONFIG_SRAM_BOOT is used in those files to keep the sram uboot
size as
small as possible.
Signed-off-by: Haiying Wang haiying.w...@freescale.com
---
Makefile | 18 ++-
arch/powerpc/cpu/mpc85xx/cpu_init_nand.c | 31 +++-
arch/powerpc/cpu/mpc85xx/sram_boot/Makefile| 190
arch/powerpc/cpu/mpc85xx/sram_boot/sram_boot.c | 76
.../cpu/mpc85xx/sram_boot/u-boot-sram-boot.lds | 101 +++
arch/powerpc/cpu/mpc85xx/start.S |8 +-
common/cmd_nvedit.c|8 +-
common/console.c |4 +
common/env_common.c|4 +
common/env_nand.c |3 +-
lib/display_options.c |2 +
lib/string.c | 10 +
lib/vsprintf.c |2 +
13 files changed, 450 insertions(+), 7 deletions(-)
create mode 100644 arch/powerpc/cpu/mpc85xx/sram_boot/Makefile
create mode 100644 arch/powerpc/cpu/mpc85xx/sram_boot/sram_boot.c
create mode 100644 arch/powerpc/cpu/mpc85xx/sram_boot/u-boot-sram-boot.lds
diff --git a/Makefile b/Makefile
index 4f1cb1b..b1d92b7 100644
--- a/Makefile
+++ b/Makefile
@@ -280,10 +280,18 @@ LDPPFLAGS += \
$(shell $(LD) --version | \
sed -ne 's/GNU ld version
\([0-9][0-9]*\)\.\([0-9][0-9]*\).*/-DLD_MAJOR=\1 -DLD_MINOR=\2/p')
+ifeq ($(CONFIG_MIDDLE_STAGE_SRAM_BOOT),y)
+SRAM_BOOT = sram_boot
+endif
+
ifeq ($(CONFIG_NAND_U_BOOT),y)
NAND_SPL = nand_spl
+ifeq ($(CONFIG_MIDDLE_STAGE_SRAM_BOOT),y)
+U_BOOT_NAND_SRAM = $(obj)u-boot-nand.bin
+else
U_BOOT_NAND = $(obj)u-boot-nand.bin
endif
+endif
ifeq ($(CONFIG_ONENAND_U_BOOT),y)
ONENAND_IPL = onenand_ipl
@@ -298,7 +306,7 @@ __LIBS := $(subst $(obj),,$(LIBS)) $(subst
$(obj),,$(LIBBOARD))
#
# Always append ALL so that arch config.mk's can add custom ones
-ALL += $(obj)u-boot.srec $(obj)u-boot.bin $(obj)System.map $(U_BOOT_NAND)
$(U_BOOT_ONENAND)
+ALL += $(obj)u-boot.srec $(obj)u-boot.bin $(obj)System.map $(U_BOOT_NAND)
$(U_BOOT_ONENAND) $(U_BOOT_NAND_SRAM)
all: $(ALL)
@@ -382,6 +390,12 @@ $(NAND_SPL): $(TIMESTAMP_FILE) $(VERSION_FILE)
$(obj)include/autoconf.mk
$(U_BOOT_NAND):$(NAND_SPL) $(obj)u-boot.bin
cat $(obj)nand_spl/u-boot-spl-16k.bin $(obj)u-boot.bin
$(obj)u-boot-nand.bin
+$(SRAM_BOOT): $(TIMESTAMP_FILE) $(VERSION_FILE) $(obj)include/autoconf.mk
+ $(MAKE) -C $(CPUDIR)/sram_boot all
+
+$(U_BOOT_NAND_SRAM): $(NAND_SPL) $(SRAM_BOOT) $(obj)u-boot.bin
+ cat $(obj)nand_spl/u-boot-spl-16k.bin
$(obj)$(CPUDIR)/u-boot-sram.bin $(obj)u-boot.bin $(obj)u-boot-nand.bin
+
$(ONENAND_IPL):$(TIMESTAMP_FILE) $(VERSION_FILE)
$(obj)include/autoconf.mk
$(MAKE) -C onenand_ipl/board/$(BOARDDIR) all
@@ -2459,6 +2473,7 @@ clean:
@rm -f $(obj)include/bmp_logo.h
@rm -f $(obj)nand_spl/{u-boot.lds,u-boot-spl,u-boot-spl.map,System.map}
@rm -f $(obj)onenand_ipl/onenand-{ipl,ipl.bin,ipl.map}
+ @rm -f $(obj)$(CPUDIR)/{u-boot-sram,u-boot-sram.map}
@rm -f $(ONENAND_BIN)
@rm -f $(obj)onenand_ipl/u-boot.lds
@rm -f $(TIMESTAMP_FILE) $(VERSION_FILE)
@@ -2482,6 +2497,7 @@ clobber: clean
@rm -f $(obj)include/asm/proc $(obj)include/asm/arch $(obj)include/asm
@[ ! -d $(obj)nand_spl ] || find $(obj)nand_spl -name * -type l
-print | xargs rm -f
@[ ! -d $(obj)onenand_ipl ] || find $(obj)onenand_ipl -name * -type l
-print | xargs rm -f
+ @[ ! -d $(obj)board/freescale ] || find $(obj)board/freescale -name *
-type l -print | xargs rm -f
ifeq ($(OBJTREE),$(SRCTREE))
mrproper \
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c
b/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c
index 8fb27ab..ff09bea 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c
@@ -40,7 +40,8 @@ void
[U-Boot] [PATCH 2/7] powerpc/85xx: do not reloc l2srbar if CONFIG_FLASH_BASE is not defined
This fixes the compiling error for the board which doesn't have NOR flash
(so CONFIG_FLASH_BASE is not defined)
Signed-off-by: Haiying Wang haiying.w...@freescale.com
---
arch/powerpc/cpu/mpc85xx/cpu_init.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c
b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 2c3be6d..1fbc0cc 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -327,7 +327,7 @@ int cpu_init_r(void)
if (l2cache-l2ctl MPC85xx_L2CTL_L2E) {
puts(already enabled);
l2srbar = l2cache-l2srbar0;
-#ifdef CONFIG_SYS_INIT_L2_ADDR
+#if defined(CONFIG_SYS_INIT_L2_ADDR) defined(CONFIG_SYS_FLASH_BASE)
if (l2cache-l2ctl MPC85xx_L2CTL_L2SRAM_ENTIRE
l2srbar = CONFIG_SYS_FLASH_BASE) {
l2srbar = CONFIG_SYS_INIT_L2_ADDR;
--
1.7.0
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[U-Boot] [PATCH 4/7] powerpc/p1021: Add P1021MDS board support
This patch supports P1021MDS NAND boot with the following features:
* Boot from NAND flash with SRAM BOOT support.(No NOR flash on this board)
* SPD DDR Initialization
Signed-off-by: Haiying Wang haiying.w...@freescale.com
Signed-off-by: Mohit Kumar mohit.ku...@freescale.com
Signed-off-by: Yu.Liu yu@freescale.com
---
MAKEALL |1 +
Makefile |4 +
board/freescale/p1021mds/Makefile | 38 ++
board/freescale/p1021mds/bcsr.c | 22 +
board/freescale/p1021mds/bcsr.h | 18 +
board/freescale/p1021mds/config.mk| 24 ++
board/freescale/p1021mds/ddr.c| 148 +++
board/freescale/p1021mds/law.c| 24 ++
board/freescale/p1021mds/p1021mds.c | 122 ++
board/freescale/p1021mds/pci.c| 91 +
board/freescale/p1021mds/tlb.c| 72
include/configs/P1021MDS.h| 536 +
nand_spl/board/freescale/p1021mds/Makefile| 117 ++
nand_spl/board/freescale/p1021mds/nand_boot.c | 59 +++
14 files changed, 1276 insertions(+), 0 deletions(-)
create mode 100644 board/freescale/p1021mds/Makefile
create mode 100644 board/freescale/p1021mds/bcsr.c
create mode 100644 board/freescale/p1021mds/bcsr.h
create mode 100644 board/freescale/p1021mds/config.mk
create mode 100644 board/freescale/p1021mds/ddr.c
create mode 100644 board/freescale/p1021mds/law.c
create mode 100644 board/freescale/p1021mds/p1021mds.c
create mode 100644 board/freescale/p1021mds/pci.c
create mode 100644 board/freescale/p1021mds/tlb.c
create mode 100644 include/configs/P1021MDS.h
create mode 100644 nand_spl/board/freescale/p1021mds/Makefile
create mode 100644 nand_spl/board/freescale/p1021mds/nand_boot.c
diff --git a/MAKEALL b/MAKEALL
index b34ae33..f14c955 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -428,6 +428,7 @@ LIST_85xx= \
P2020RDB_NAND \
P2020RDB_SDCARD \
P2020RDB_SPIFLASH \
+ P1021MDS_NAND \
P4080DS \
PM854 \
PM856 \
diff --git a/Makefile b/Makefile
index b1d92b7..7bfa733 100644
--- a/Makefile
+++ b/Makefile
@@ -1809,6 +1809,10 @@ P2020RDB_SDCARD_config \
P2020RDB_SPIFLASH_config: unconfig
@$(MKCONFIG) -n $@ -t $@ P1_P2_RDB powerpc mpc85xx p1_p2_rdb freescale
+P1021MDS_config \
+P1021MDS_NAND_config: unconfig
+ @$(MKCONFIG) -n $@ -t $@ P1021MDS powerpc mpc85xx p1021mds freescale
+
sbc8540_config \
sbc8540_33_config \
sbc8540_66_config: unconfig
diff --git a/board/freescale/p1021mds/Makefile
b/board/freescale/p1021mds/Makefile
new file mode 100644
index 000..bb744f0
--- /dev/null
+++ b/board/freescale/p1021mds/Makefile
@@ -0,0 +1,38 @@
+#
+# Copyright (C) 2010 Freescale Semiconductor, Inc.
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of the GNU General Public License as published by the Free
+# Software Foundation; either version 2 of the License, or (at your option)
+# any later version.
+
+include $(TOPDIR)/config.mk
+
+LIB= $(obj)lib$(BOARD).a
+
+COBJS-y+= $(BOARD).o
+COBJS-y+= bcsr.o
+COBJS-y+= law.o
+COBJS-y+= tlb.o
+COBJS-y+= pci.o
+
+SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS-y))
+SOBJS := $(addprefix $(obj),$(SOBJS-y))
+
+$(LIB):$(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+ rm -f $(OBJS) $(SOBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#
diff --git a/board/freescale/p1021mds/bcsr.c b/board/freescale/p1021mds/bcsr.c
new file mode 100644
index 000..6daf690
--- /dev/null
+++ b/board/freescale/p1021mds/bcsr.c
@@ -0,0 +1,22 @@
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ *
+ */
+
+#include common.h
+#include asm/io.h
+
+#include bcsr.h
+
+#define BCSR11_ENET_MICRST 0x20
+
+void reset_p1021mds_micrel_phy(void)
+{
+ clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 11), BCSR11_ENET_MICRST);
+ setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 11), BCSR11_ENET_MICRST);
+}
diff --git a/board/freescale/p1021mds/bcsr.h b/board/freescale/p1021mds/bcsr.h
new file mode 100644
index 000..f3e47d4
--- /dev/null
+++ b/board/freescale/p1021mds/bcsr.h
@@ -0,0 +1,18 @@
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc
[U-Boot] [PATCH 5/7] powerpc/p1021: Add more P1021 defines
Signed-off-by: Haiying Wang haiying.w...@freescale.com
---
arch/powerpc/include/asm/immap_85xx.h |6 ++
arch/powerpc/include/asm/immap_qe.h |7 ++-
2 files changed, 12 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/include/asm/immap_85xx.h
b/arch/powerpc/include/asm/immap_85xx.h
index c1382c8..5eeb93a 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1962,6 +1962,12 @@ typedef struct ccsr_gur {
u8 res10b[76];
par_io_t qe_par_io[7];
u8 res10c[1600];
+#elif defined(CONFIG_P1021)
+ u8 res10b1[12];
+ u32 iovselsr;
+ u8 res10b2[60];
+ par_io_t qe_par_io[3];
+ u8 res10c[1496];
#else
u8 res10b[1868];
#endif
diff --git a/arch/powerpc/include/asm/immap_qe.h
b/arch/powerpc/include/asm/immap_qe.h
index 531cfc8..a523876 100644
--- a/arch/powerpc/include/asm/immap_qe.h
+++ b/arch/powerpc/include/asm/immap_qe.h
@@ -588,6 +588,9 @@ typedef struct qe_immap {
#elif defined(CONFIG_MPC8569)
u8 muram[0x2]; /* 0x1_ - 0x3_ Multi-user RAM */
u8 res17[0x1]; /* 0x3_ - 0x4_ */
+#elif defined(CONFIG_P1021)
+ u8 muram[0x06000]; /* 0x1_ - 0x1_6000 Multi-user RAM */
+ u8 res17[0x1a000]; /* 0x1_6000 - 0x3_ */
#else
u8 muram[0xC000]; /* 0x11 - 0x11C000 Multi-user RAM */
u8 res17[0x24000]; /* 0x11C000 - 0x14 */
@@ -601,13 +604,15 @@ extern qe_map_t *qe_immr;
#define QE_MURAM_SIZE 0x1UL
#elif defined(CONFIG_MPC8569)
#define QE_MURAM_SIZE 0x2UL
+#elif defined(CONFIG_P1021)
+#define QE_MURAM_SIZE 0x6000UL
#elif defined(CONFIG_MPC8360)
#define QE_MURAM_SIZE 0xc000UL
#elif defined(CONFIG_MPC832x)
#define QE_MURAM_SIZE 0x4000UL
#endif
-#if defined(CONFIG_MPC8323)
+#if defined(CONFIG_MPC8323) || defined(CONFIG_P1021)
#define MAX_QE_RISC 1
#define QE_NUM_OF_SNUM 28
#elif defined(CONFIG_MPC8569)
--
1.7.0
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[U-Boot] [PATCH 6/7] powerpc/qe: supports loading QE firmware from nand flash
and because some platforms need to load QE firmware from NAND flash(no NOR
flash), it makes qe_init to be called after nand_init.
Signed-off-by: Haiying Wang haiying.w...@freescale.com
---
arch/powerpc/cpu/mpc83xx/cpu_init.c |8
arch/powerpc/cpu/mpc85xx/cpu_init.c |8
arch/powerpc/lib/board.c| 31 +++
3 files changed, 31 insertions(+), 16 deletions(-)
diff --git a/arch/powerpc/cpu/mpc83xx/cpu_init.c
b/arch/powerpc/cpu/mpc83xx/cpu_init.c
index 83cba93..6d40037 100644
--- a/arch/powerpc/cpu/mpc83xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc83xx/cpu_init.c
@@ -34,8 +34,6 @@ DECLARE_GLOBAL_DATA_PTR;
extern qe_iop_conf_t qe_iop_conf_tab[];
extern void qe_config_iopin(u8 port, u8 pin, int dir,
int open_drain, int assign);
-extern void qe_init(uint qe_base);
-extern void qe_reset(void);
static void config_qe_ioports(void)
{
@@ -333,12 +331,6 @@ void cpu_init_f (volatile immap_t * im)
int cpu_init_r (void)
{
-#ifdef CONFIG_QE
- uint qe_base = CONFIG_SYS_IMMR + 0x0010; /* QE immr base */
-
- qe_init(qe_base);
- qe_reset();
-#endif
return 0;
}
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c
b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 1fbc0cc..f799773 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -44,8 +44,6 @@ DECLARE_GLOBAL_DATA_PTR;
extern qe_iop_conf_t qe_iop_conf_tab[];
extern void qe_config_iopin(u8 port, u8 pin, int dir,
int open_drain, int assign);
-extern void qe_init(uint qe_base);
-extern void qe_reset(void);
static void config_qe_ioports(void)
{
@@ -369,12 +367,6 @@ int cpu_init_r(void)
enable_cpc();
-#ifdef CONFIG_QE
- uint qe_base = CONFIG_SYS_IMMR + 0x0008; /* QE immr base */
- qe_init(qe_base);
- qe_reset();
-#endif
-
#if defined(CONFIG_SYS_HAS_SERDES)
/* needs to be in ram since code uses global static vars */
fsl_serdes_init();
diff --git a/arch/powerpc/lib/board.c b/arch/powerpc/lib/board.c
index 0e00d86..3fa865d 100644
--- a/arch/powerpc/lib/board.c
+++ b/arch/powerpc/lib/board.c
@@ -87,6 +87,15 @@
#include miiphy.h
#endif
+#ifdef CONFIG_QE
+#ifdef CONFIG_SYS_QE_FW_IN_NAND
+#include nand.h
+#include asm/errno.h
+#endif
+extern void qe_init(uint qe_base);
+extern void qe_reset(void);
+#endif
+
#ifdef CONFIG_SYS_UPDATE_FLASH_SIZE
extern int update_flash_size (int flash_size);
#endif
@@ -631,6 +640,10 @@ void board_init_r (gd_t *id, ulong dest_addr)
char *s;
bd_t *bd;
ulong malloc_start;
+#ifdef CONFIG_SYS_QE_FW_IN_NAND
+ int ret;
+ size_t fw_length = CONFIG_SYS_QE_FW_LENGTH;
+#endif
#ifndef CONFIG_SYS_NO_FLASH
ulong flash_size;
@@ -783,6 +796,24 @@ void board_init_r (gd_t *id, ulong dest_addr)
nand_init();/* go init the NAND */
#endif
+ /* QE needs to be initialized after nand_init because some boards have
+* to save QE firmware in NAND flash.
+*/
+#ifdef CONFIG_QE
+#ifdef CONFIG_SYS_QE_FW_IN_NAND
+ /* load QE firmware from NAND flash to DDR first */
+ ret = nand_read(nand_info[0], (loff_t)CONFIG_SYS_QE_FW_IN_NAND,
+ fw_length, (u_char *)CONFIG_SYS_QE_FW_ADDR);
+
+ if (ret ret == -EUCLEAN) {
+ printf (NAND read for QE firmware at offset %x failed %d\n,
+ (loff_t)CONFIG_SYS_QE_FW_IN_NAND, ret);
+ }
+#endif /* CONFIG_SYS_QE_FW_IN_NAND */
+ qe_init(CONFIG_SYS_IMMR + 0x0008);
+ qe_reset();
+#endif /* CONFIG_QE */
+
/* relocate environment function pointers etc. */
env_relocate ();
--
1.7.0
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[U-Boot] [PATCH 7/7] powerpc/p1021mds: add QE and UEC support
P1021 has some QE pins which need to be set in pmuxcr register before using QE
functions. In this patch, pin QE0 and QE3 are set for UCC1 and UCC5 in Eth mode.
QE9 and QE12 are set for MII management. QE12 needs to be released after MII
access because QE12 pin is muxed with LBCTL signal.
Signed-off-by: Haiying Wang haiying.w...@freescale.com
---
arch/powerpc/cpu/mpc85xx/speed.c |4 ++
arch/powerpc/include/asm/immap_85xx.h | 13
board/freescale/p1021mds/p1021mds.c | 54 +
drivers/qe/uec.c | 36 ++
include/configs/P1021MDS.h| 44 ++
5 files changed, 151 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c
index dd4c6b3..6f1aa7b 100644
--- a/arch/powerpc/cpu/mpc85xx/speed.c
+++ b/arch/powerpc/cpu/mpc85xx/speed.c
@@ -163,10 +163,14 @@ void get_sys_info (sys_info_t * sysInfo)
#endif
#ifdef CONFIG_QE
+#ifdef CONFIG_P1021
+ sysInfo-freqQE = sysInfo-freqSystemBus;
+#else
qe_ratio = ((gur-porpllsr) MPC85xx_PORPLLSR_QE_RATIO)
MPC85xx_PORPLLSR_QE_RATIO_SHIFT;
sysInfo-freqQE = qe_ratio * CONFIG_SYS_CLK_FREQ;
#endif
+#endif
#if defined(CONFIG_SYS_LBC_LCRR)
/* We will program LCRR to this value later */
diff --git a/arch/powerpc/include/asm/immap_85xx.h
b/arch/powerpc/include/asm/immap_85xx.h
index 5eeb93a..896014b 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1923,6 +1923,19 @@ typedef struct ccsr_gur {
#define MPC85xx_PMUXCR_SD_DATA 0x8000
#define MPC85xx_PMUXCR_SDHC_CD 0x4000
#define MPC85xx_PMUXCR_SDHC_WP 0x2000
+#define MPC85xx_PMUXCR_QE0 0x8000
+#define MPC85xx_PMUXCR_QE1 0x4000
+#define MPC85xx_PMUXCR_QE2 0x2000
+#define MPC85xx_PMUXCR_QE3 0x1000
+#define MPC85xx_PMUXCR_QE4 0x0800
+#define MPC85xx_PMUXCR_QE5 0x0400
+#define MPC85xx_PMUXCR_QE6 0x0200
+#define MPC85xx_PMUXCR_QE7 0x0100
+#define MPC85xx_PMUXCR_QE8 0x0080
+#define MPC85xx_PMUXCR_QE9 0x0040
+#define MPC85xx_PMUXCR_QE100x0020
+#define MPC85xx_PMUXCR_QE110x0010
+#define MPC85xx_PMUXCR_QE120x0008
u32 pmuxcr2;/* Alt. function signal multiplex control 2 */
u8 res6[8];
u32 devdisr;/* Device disable control */
diff --git a/board/freescale/p1021mds/p1021mds.c
b/board/freescale/p1021mds/p1021mds.c
index c61c902..9297d0c 100644
--- a/board/freescale/p1021mds/p1021mds.c
+++ b/board/freescale/p1021mds/p1021mds.c
@@ -24,6 +24,48 @@
#include tsec.h
#include netdev.h
+#include bcsr.h
+
+#ifdef CONFIG_QE
+const qe_iop_conf_t qe_iop_conf_tab[] = {
+ /* QE_MUX_MDC */
+ {1, 19, 1, 0, 1}, /* QE_MUX_MDC */
+
+ /* QE_MUX_MDIO */
+ {1, 20, 3, 0, 1}, /* QE_MUX_MDIO */
+
+ /* UCC_1_MII */
+ {0, 23, 2, 0, 2}, /* CLK12 */
+ {0, 24, 2, 0, 1}, /* CLK9 */
+ {0, 7, 1, 0, 2}, /* ENET1_TXD0_SER1_TXD0 */
+ {0, 9, 1, 0, 2}, /* ENET1_TXD1_SER1_TXD1 */
+ {0, 11, 1, 0, 2}, /* ENET1_TXD2_SER1_TXD2 */
+ {0, 12, 1, 0, 2}, /* ENET1_TXD3_SER1_TXD3 */
+ {0, 6, 2, 0, 2}, /* ENET1_RXD0_SER1_RXD0 */
+ {0, 10, 2, 0, 2}, /* ENET1_RXD1_SER1_RXD1 */
+ {0, 14, 2, 0, 2}, /* ENET1_RXD2_SER1_RXD2 */
+ {0, 15, 2, 0, 2}, /* ENET1_RXD3_SER1_RXD3 */
+ {0, 5, 1, 0, 2}, /* ENET1_TX_EN_SER1_RTS_B*/
+ {0, 13, 1, 0, 2}, /* ENET1_TX_ER */
+ {0, 4, 2, 0, 2}, /* ENET1_RX_DV_SER1_CTS_B*/
+ {0, 8, 2, 0, 2}, /* ENET1_RX_ER_SER1_CD_B*/
+ {0, 17, 2, 0, 2}, /* ENET1_CRS*/
+ {0, 16, 2, 0, 2}, /* ENET1_COL*/
+
+ /* UCC_5_RMII */
+ {1, 11, 2, 0, 1}, /* CLK13 */
+ {1, 7, 1, 0, 2}, /* ENET5_TXD0_SER5_TXD0 */
+ {1, 10, 1, 0, 2}, /* ENET5_TXD1_SER5_TXD1 */
+ {1, 6, 2, 0, 2}, /* ENET5_RXD0_SER5_RXD0 */
+ {1, 9, 2, 0, 2}, /* ENET5_RXD1_SER5_RXD1 */
+ {1, 5, 1, 0, 2}, /* ENET5_TX_EN_SER5_RTS_B*/
+ {1, 4, 2, 0, 2}, /* ENET5_RX_DV_SER5_CTS_B*/
+ {1, 8, 2, 0, 2}, /* ENET5_RX_ER_SER5_CD_B*/
+
+ {0, 0, 0, 0, QE_IOP_TAB_END} /* END of table */
+};
+#endif
+
const char *board_hwconfig = foo:bar=baz;
const char *cpu_hwconfig = foo:bar=baz;
@@ -88,6 +130,14 @@ int board_eth_init(bd_t *bis)
tsec_eth_init(bis, tsec_info, num);
+#if defined(CONFIG_UEC_ETH)
+ /* QE0 and QE3 need to be exposed for UCC1 and UCC5 Eth mode */
+ setbits_be32(gur-pmuxcr, MPC85xx_PMUXCR_QE0);
+ setbits_be32(gur-pmuxcr, MPC85xx_PMUXCR_QE3);
+
+ uec_standard_init(bis);
+#endif
+
return
Re: [U-Boot] [PATCH 2/7] powerpc/85xx: do not reloc l2srbar if CONFIG_FLASH_BASE is not defined
On Mon, 2010-16-08 at 12:11 +0200, Wolfgang Denk wrote:
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c
b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 2c3be6d..1fbc0cc 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -327,7 +327,7 @@ int cpu_init_r(void)
if (l2cache-l2ctl MPC85xx_L2CTL_L2E) {
puts(already enabled);
l2srbar = l2cache-l2srbar0;
-#ifdef CONFIG_SYS_INIT_L2_ADDR
+#if defined(CONFIG_SYS_INIT_L2_ADDR) defined(CONFIG_SYS_FLASH_BASE)
if (l2cache-l2ctl MPC85xx_L2CTL_L2SRAM_ENTIRE
l2srbar = CONFIG_SYS_FLASH_BASE) {
Does this commit not break systems which have CONFIG_SYS_FLASH_BASE
defined, but with l2srbar CONFIG_SYS_FLASH_BASE ?
I did not see it breaks the system in that case. It only affects the system
without CONFIG_SYS_FLASH_BASE defined. :)
Haiying
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Re: [U-Boot] [PATCH 1/7] nand_spl: remove static for nand_load
On Mon, 2010-16-08 at 12:09 +0200, Wolfgang Denk wrote: Dear Haiying Wang, In message 1281945721.24612.11.ca...@localhost.localdomain you wrote: so it can be called in other file. Signed-off-by: Haiying Wang haiying.w...@freescale.com --- nand_spl/nand_boot_fsl_elbc.c |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) That commit should be squashed with the other one that actually makes use of this. Will squash this one with patch 3/7 for sram boot. Thanks. Haiying ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 0/7] patch set for P1021MDS support
The patchset supports SRAM boot, P1021MDS NAND boot, P1021MDS QE/UEC, it is against the git://git.denx.de/u-boot-mpc85xx. Thanks. Haiying ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 03/14 v2] MPC85xx: Fix some settings for MPC8569MDS board
- Increase the size of malloc to 512KB because MPC8569MDS needs more memory for malloc to support up to eight Ethernet interfaces. - Move Environment address out of uboot thus the saved environment variables will not be erased after u-boot is re-programmed. Signed-off-by: Haiying Wang haiying.w...@freescale.com --- v2 change: remove the CLK_IN change since Dave submitted in another patch include/configs/MPC8569MDS.h |6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-) diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h index 64a82dd..21a7adf 100644 --- a/include/configs/MPC8569MDS.h +++ b/include/configs/MPC8569MDS.h @@ -194,7 +194,7 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET #define CONFIG_SYS_MONITOR_LEN (256 * 1024)/* Reserve 256 kB for Mon */ -#define CONFIG_SYS_MALLOC_LEN (128 * 1024)/* Reserved for malloc */ +#define CONFIG_SYS_MALLOC_LEN (512 * 1024)/* Reserved for malloc */ /* Serial Port */ #define CONFIG_CONS_INDEX 1 @@ -327,9 +327,9 @@ extern unsigned long get_clock_freq(void); * Environment */ #define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_ADDR(CONFIG_SYS_MONITOR_BASE + 0x4) +#define CONFIG_ENV_ADDR(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) #define CONFIG_ENV_SECT_SIZE 0x2 /* 256K(one sector) for env */ -#define CONFIG_ENV_SIZE0x2000 +#define CONFIG_ENV_SIZECONFIG_ENV_SECT_SIZE #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ -- 1.6.0.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 10/14 v4] Update the number of ethxaddr in reading system eeprom
We support up to 8 mac addresses in system eeprom, so we define the macro
MAX_NUM_PORTS to limit the mac_count to 8, and update the number of ethxaddr
according to mac_count.
Signed-off-by: Haiying Wang haiying.w...@freescale.com
---
v4 change: white space clean up
board/freescale/common/sys_eeprom.c | 23 ++-
1 files changed, 18 insertions(+), 5 deletions(-)
diff --git a/board/freescale/common/sys_eeprom.c
b/board/freescale/common/sys_eeprom.c
index 988cb94..ae5304a 100644
--- a/board/freescale/common/sys_eeprom.c
+++ b/board/freescale/common/sys_eeprom.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2006, 2008 Freescale Semiconductor
+ * Copyright 2006, 2008-2009 Freescale Semiconductor
* York Sun (york...@freescale.com)
* Haiying Wang (haiying.w...@freescale.com)
* Timur Tabi (ti...@freescale.com)
@@ -34,6 +34,8 @@
#error Please define either CONFIG_SYS_I2C_EEPROM_CCID or
CONFIG_SYS_I2C_EEPROM_NXID
#endif
+#define MAX_NUM_PORTS 8 /* This value must be 8 as defined in doc */
+
/**
* static eeprom: EEPROM layout for CCID or NXID formats
*
@@ -50,7 +52,7 @@ static struct __attribute__ ((__packed__)) eeprom {
u8 res_0[40]; /* 0x18 - 0x3f Reserved */
u8 mac_count; /* 0x40Number of MAC addresses */
u8 mac_flag; /* 0x41MAC table flags */
- u8 mac[8][6]; /* 0x42 - 0x71 MAC addresses */
+ u8 mac[MAX_NUM_PORTS][6]; /* 0x42 - 0x71 MAC addresses */
u32 crc; /* 0x72CRC32 checksum */
#endif
#ifdef CONFIG_SYS_I2C_EEPROM_NXID
@@ -66,7 +68,7 @@ static struct __attribute__ ((__packed__)) eeprom {
u8 res_1[21]; /* 0x2b - 0x3f Reserved */
u8 mac_count; /* 0x40Number of MAC addresses */
u8 mac_flag; /* 0x41MAC table flags */
- u8 mac[8][6]; /* 0x42 - 0x71 MAC addresses */
+ u8 mac[MAX_NUM_PORTS][6]; /* 0x42 - 0x71 MAC addresses */
u32 crc; /* 0x72CRC32 checksum */
#endif
} e;
@@ -119,7 +121,8 @@ static void show_eeprom(void)
e.date[3] 0x80 ? PM : );
/* Show MAC addresses */
- for (i = 0; i min(e.mac_count, 8); i++) {
+ for (i = 0; i min(e.mac_count, MAX_NUM_PORTS); i++) {
+
u8 *p = e.mac[i];
printf(Eth%u: %02x:%02x:%02x:%02x:%02x:%02x\n, i,
@@ -404,7 +407,17 @@ int mac_read_from_eeprom(void)
}
}
- for (i = 0; i min(4, e.mac_count); i++) {
+ /* Check the number of MAC addresses which is limited to
+* MAX_NUM_PORTS.
+*/
+ if (e.mac_count MAX_NUM_PORTS) {
+ printf(Warning: The number of MAC addresses is greater
+than %u, force it to %u.\n, MAX_NUM_PORTS,
+ MAX_NUM_PORTS);
+ e.mac_count = MAX_NUM_PORTS;
+ }
+
+ for (i = 0; i e.mac_count; i++) {
if (memcmp(e.mac[i], \0\0\0\0\0\0, 6)
memcmp(e.mac[i], \xFF\xFF\xFF\xFF\xFF\xFF, 6)) {
char ethaddr[18];
--
1.6.0.2
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[U-Boot] [PATCH 11/14 v2] Pass in uec_info struct through uec_initialize
The uec driver contains code to hard code configuration information for the uec
ethernet controllers. This patch creates an array of uec_info structures, which
are then parsed by the corresponding driver instance to determine configuration.
It also creates function uec_standard_init() to initialize all UEC interfaces
for 83xx and 85xx.
Signed-off-by: Haiying Wang haiying.w...@freescale.com
---
v2 change: Use the loop according to Wolfgang's comments on May 20th.
cpu/mpc83xx/cpu.c | 20 +
cpu/mpc85xx/cpu.c | 21 +
drivers/qe/uec.c | 225 +
drivers/qe/uec.h | 21 +
4 files changed, 65 insertions(+), 222 deletions(-)
diff --git a/cpu/mpc83xx/cpu.c b/cpu/mpc83xx/cpu.c
index 876f5c7..c4331ae 100644
--- a/cpu/mpc83xx/cpu.c
+++ b/cpu/mpc83xx/cpu.c
@@ -367,24 +367,10 @@ int dma_xfer(void *dest, u32 count, void *src)
*/
int cpu_eth_init(bd_t *bis)
{
-#if defined(CONFIG_UEC_ETH1)
- uec_initialize(0);
-#endif
-#if defined(CONFIG_UEC_ETH2)
- uec_initialize(1);
-#endif
-#if defined(CONFIG_UEC_ETH3)
- uec_initialize(2);
-#endif
-#if defined(CONFIG_UEC_ETH4)
- uec_initialize(3);
-#endif
-#if defined(CONFIG_UEC_ETH5)
- uec_initialize(4);
-#endif
-#if defined(CONFIG_UEC_ETH6)
- uec_initialize(5);
+#if defined(CONFIG_UEC_ETH)
+ uec_standard_init(bis);
#endif
+
#if defined(CONFIG_TSEC_ENET)
tsec_standard_init(bis);
#endif
diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c
index b812d88..0b1ba33 100644
--- a/cpu/mpc85xx/cpu.c
+++ b/cpu/mpc85xx/cpu.c
@@ -381,24 +381,11 @@ int cpu_eth_init(bd_t *bis)
#if defined(CONFIG_ETHER_ON_FCC)
fec_initialize(bis);
#endif
-#if defined(CONFIG_UEC_ETH1)
- uec_initialize(0);
-#endif
-#if defined(CONFIG_UEC_ETH2)
- uec_initialize(1);
-#endif
-#if defined(CONFIG_UEC_ETH3)
- uec_initialize(2);
-#endif
-#if defined(CONFIG_UEC_ETH4)
- uec_initialize(3);
-#endif
-#if defined(CONFIG_UEC_ETH5)
- uec_initialize(4);
-#endif
-#if defined(CONFIG_UEC_ETH6)
- uec_initialize(5);
+
+#if defined(CONFIG_UEC_ETH)
+ uec_standard_init(bis);
#endif
+
#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_MPC85XX_FEC)
tsec_standard_init(bis);
#endif
diff --git a/drivers/qe/uec.c b/drivers/qe/uec.c
index d02c8c9..0b4a6e7 100644
--- a/drivers/qe/uec.c
+++ b/drivers/qe/uec.c
@@ -31,176 +31,34 @@
#include uec_phy.h
#include miiphy.h
+static uec_info_t uec_info[] = {
#ifdef CONFIG_UEC_ETH1
-static uec_info_t eth1_uec_info = {
- .uf_info= {
- .ucc_num= CONFIG_SYS_UEC1_UCC_NUM,
- .rx_clock = CONFIG_SYS_UEC1_RX_CLK,
- .tx_clock = CONFIG_SYS_UEC1_TX_CLK,
- .eth_type = CONFIG_SYS_UEC1_ETH_TYPE,
- },
-#if (CONFIG_SYS_UEC1_ETH_TYPE == FAST_ETH)
- .num_threads_tx = UEC_NUM_OF_THREADS_1,
- .num_threads_rx = UEC_NUM_OF_THREADS_1,
-#else
- .num_threads_tx = UEC_NUM_OF_THREADS_4,
- .num_threads_rx = UEC_NUM_OF_THREADS_4,
-#endif
-#if (MAX_QE_RISC == 4)
- .risc_tx= QE_RISC_ALLOCATION_FOUR_RISCS,
- .risc_rx= QE_RISC_ALLOCATION_FOUR_RISCS,
-#else
- .risc_tx= QE_RISC_ALLOCATION_RISC1_AND_RISC2,
- .risc_rx= QE_RISC_ALLOCATION_RISC1_AND_RISC2,
-#endif
- .tx_bd_ring_len = 16,
- .rx_bd_ring_len = 16,
- .phy_address= CONFIG_SYS_UEC1_PHY_ADDR,
- .enet_interface = CONFIG_SYS_UEC1_INTERFACE_MODE,
-};
+ STD_UEC_INFO(1),/* UEC1 */
#endif
#ifdef CONFIG_UEC_ETH2
-static uec_info_t eth2_uec_info = {
- .uf_info= {
- .ucc_num= CONFIG_SYS_UEC2_UCC_NUM,
- .rx_clock = CONFIG_SYS_UEC2_RX_CLK,
- .tx_clock = CONFIG_SYS_UEC2_TX_CLK,
- .eth_type = CONFIG_SYS_UEC2_ETH_TYPE,
- },
-#if (CONFIG_SYS_UEC2_ETH_TYPE == FAST_ETH)
- .num_threads_tx = UEC_NUM_OF_THREADS_1,
- .num_threads_rx = UEC_NUM_OF_THREADS_1,
-#else
- .num_threads_tx = UEC_NUM_OF_THREADS_4,
- .num_threads_rx = UEC_NUM_OF_THREADS_4,
-#endif
-#if (MAX_QE_RISC == 4)
- .risc_tx= QE_RISC_ALLOCATION_FOUR_RISCS,
- .risc_rx= QE_RISC_ALLOCATION_FOUR_RISCS,
-#else
- .risc_tx= QE_RISC_ALLOCATION_RISC1_AND_RISC2,
- .risc_rx= QE_RISC_ALLOCATION_RISC1_AND_RISC2,
-#endif
- .tx_bd_ring_len = 16,
- .rx_bd_ring_len = 16,
- .phy_address= CONFIG_SYS_UEC2_PHY_ADDR,
- .enet_interface = CONFIG_SYS_UEC2_INTERFACE_MODE,
-};
+ STD_UEC_INFO(2),/* UEC2 */
#endif
#ifdef CONFIG_UEC_ETH3
-static uec_info_t eth3_uec_info
[U-Boot] [PATCH 12/14 v2] drivers/qe: add sgmii support in for UEC driver
Signed-off-by: Haiying Wang haiying.w...@freescale.com
---
v2 change: Adjust the code according to the change in patch 11/15
drivers/qe/uec.c | 17 +
drivers/qe/uec.h | 31 +--
2 files changed, 46 insertions(+), 2 deletions(-)
diff --git a/drivers/qe/uec.c b/drivers/qe/uec.c
index 0b4a6e7..3686575 100644
--- a/drivers/qe/uec.c
+++ b/drivers/qe/uec.c
@@ -379,6 +379,10 @@ static int uec_set_mac_if_mode(uec_private_t *uec,
enet_interface_e if_mode)
maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
upsmr |= (UPSMR_R10M | UPSMR_RMM);
break;
+ case ENET_1000_SGMII:
+ maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
+ upsmr |= UPSMR_SGMM;
+ break;
default:
return -EINVAL;
break;
@@ -1078,6 +1082,18 @@ static int uec_startup(uec_private_t *uec)
out_be32(uec_regs-utbipar, utbipar);
+ /* Configure the TBI for SGMII operation */
+ if (uec-uec_info-enet_interface == ENET_1000_SGMII) {
+ uec_write_phy_reg(uec-dev, uec_regs-utbipar,
+ ENET_TBI_MII_ANA, TBIANA_SETTINGS);
+
+ uec_write_phy_reg(uec-dev, uec_regs-utbipar,
+ ENET_TBI_MII_TBICON, TBICON_CLK_SELECT);
+
+ uec_write_phy_reg(uec-dev, uec_regs-utbipar,
+ ENET_TBI_MII_CR, TBICR_SETTINGS);
+ }
+
/* Allocate Tx BDs */
length = ((uec_info-tx_bd_ring_len * SIZEOFBD) /
UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT) *
@@ -1333,6 +1349,7 @@ int uec_initialize(bd_t *bis, uec_info_t *uec_info)
devlist[uec_info-uf_info.ucc_num] = dev;
uec-uec_info = uec_info;
+ uec-dev = dev;
sprintf(dev-name, FSL UEC%d, uec_info-uf_info.ucc_num);
dev-iobase = 0;
diff --git a/drivers/qe/uec.h b/drivers/qe/uec.h
index 6c408d1..1568310 100644
--- a/drivers/qe/uec.h
+++ b/drivers/qe/uec.h
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2006 Freescale Semiconductor, Inc.
+ * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
*
* Dave Liu dave...@freescale.com
* based on source code of Shlomi Gridish
@@ -47,6 +47,7 @@
#define UPSMR_CAM 0x0400 /* CAM Address Matching */
#define UPSMR_BRO 0x0200 /* Broadcast Address */
#define UPSMR_RES1 0x2000 /* Reserved feild - must be 1*/
+#define UPSMR_SGMM 0x0020 /* SGMII mode*/
#define UPSMR_INIT_VALUE (UPSMR_HSE | UPSMR_RES1)
@@ -621,6 +622,31 @@ typedef enum enet_tbi_mii_reg {
ENET_TBI_MII_TBICON= 0x11
} enet_tbi_mii_reg_e;
+/* TBI MDIO register bit fields*/
+#define TBICON_CLK_SELECT 0x0020
+#define TBIANA_ASYMMETRIC_PAUSE0x0100
+#define TBIANA_SYMMETRIC_PAUSE 0x0080
+#define TBIANA_HALF_DUPLEX 0x0040
+#define TBIANA_FULL_DUPLEX 0x0020
+#define TBICR_PHY_RESET0x8000
+#define TBICR_ANEG_ENABLE 0x1000
+#define TBICR_RESTART_ANEG 0x0200
+#define TBICR_FULL_DUPLEX 0x0100
+#define TBICR_SPEED1_SET 0x0040
+
+#define TBIANA_SETTINGS ( \
+ TBIANA_ASYMMETRIC_PAUSE \
+ | TBIANA_SYMMETRIC_PAUSE \
+ | TBIANA_FULL_DUPLEX \
+ )
+
+#define TBICR_SETTINGS ( \
+ TBICR_PHY_RESET \
+ | TBICR_ANEG_ENABLE \
+ | TBICR_FULL_DUPLEX \
+ | TBICR_SPEED1_SET \
+ )
+
/* UEC number of threads
*/
typedef enum uec_num_of_threads {
@@ -645,7 +671,8 @@ typedef enum enet_interface {
ENET_1000_RGMII_ID,
ENET_1000_RGMII_RXID,
ENET_1000_TBI,
- ENET_1000_RTBI
+ ENET_1000_RTBI,
+ ENET_1000_SGMII
} enet_interface_e;
/* UEC initialization info struct
--
1.6.0.2
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[U-Boot] [PATCH] drivers/qe: Rename the camel-case identifiers in uec
Rename riscRx/riscTx to risc_rx/risc_tx to comply with Codingstyle.
Signed-off-by: Haiying Wang haiying.w...@freescale.com
---
This patch should be applied before the 15 patches I sent out yesterday
drivers/qe/uec.c | 32
drivers/qe/uec.h |4 ++--
2 files changed, 18 insertions(+), 18 deletions(-)
diff --git a/drivers/qe/uec.c b/drivers/qe/uec.c
index bba3ef2..e67c0ba 100644
--- a/drivers/qe/uec.c
+++ b/drivers/qe/uec.c
@@ -46,8 +46,8 @@ static uec_info_t eth1_uec_info = {
.num_threads_tx = UEC_NUM_OF_THREADS_4,
.num_threads_rx = UEC_NUM_OF_THREADS_4,
#endif
- .riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
- .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
+ .risc_tx= QE_RISC_ALLOCATION_RISC1_AND_RISC2,
+ .risc_rx= QE_RISC_ALLOCATION_RISC1_AND_RISC2,
.tx_bd_ring_len = 16,
.rx_bd_ring_len = 16,
.phy_address= CONFIG_SYS_UEC1_PHY_ADDR,
@@ -69,8 +69,8 @@ static uec_info_t eth2_uec_info = {
.num_threads_tx = UEC_NUM_OF_THREADS_4,
.num_threads_rx = UEC_NUM_OF_THREADS_4,
#endif
- .riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
- .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
+ .risc_tx= QE_RISC_ALLOCATION_RISC1_AND_RISC2,
+ .risc_rx= QE_RISC_ALLOCATION_RISC1_AND_RISC2,
.tx_bd_ring_len = 16,
.rx_bd_ring_len = 16,
.phy_address= CONFIG_SYS_UEC2_PHY_ADDR,
@@ -92,8 +92,8 @@ static uec_info_t eth3_uec_info = {
.num_threads_tx = UEC_NUM_OF_THREADS_4,
.num_threads_rx = UEC_NUM_OF_THREADS_4,
#endif
- .riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
- .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
+ .risc_tx= QE_RISC_ALLOCATION_RISC1_AND_RISC2,
+ .risc_rx= QE_RISC_ALLOCATION_RISC1_AND_RISC2,
.tx_bd_ring_len = 16,
.rx_bd_ring_len = 16,
.phy_address= CONFIG_SYS_UEC3_PHY_ADDR,
@@ -115,8 +115,8 @@ static uec_info_t eth4_uec_info = {
.num_threads_tx = UEC_NUM_OF_THREADS_4,
.num_threads_rx = UEC_NUM_OF_THREADS_4,
#endif
- .riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
- .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
+ .risc_tx= QE_RISC_ALLOCATION_RISC1_AND_RISC2,
+ .risc_rx= QE_RISC_ALLOCATION_RISC1_AND_RISC2,
.tx_bd_ring_len = 16,
.rx_bd_ring_len = 16,
.phy_address= CONFIG_SYS_UEC4_PHY_ADDR,
@@ -138,8 +138,8 @@ static uec_info_t eth5_uec_info = {
.num_threads_tx = UEC_NUM_OF_THREADS_4,
.num_threads_rx = UEC_NUM_OF_THREADS_4,
#endif
- .riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
- .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
+ .risc_tx= QE_RISC_ALLOCATION_RISC1_AND_RISC2,
+ .risc_rx= QE_RISC_ALLOCATION_RISC1_AND_RISC2,
.tx_bd_ring_len = 16,
.rx_bd_ring_len = 16,
.phy_address= CONFIG_SYS_UEC5_PHY_ADDR,
@@ -161,8 +161,8 @@ static uec_info_t eth6_uec_info = {
.num_threads_tx = UEC_NUM_OF_THREADS_4,
.num_threads_rx = UEC_NUM_OF_THREADS_4,
#endif
- .riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
- .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
+ .risc_tx= QE_RISC_ALLOCATION_RISC1_AND_RISC2,
+ .risc_rx= QE_RISC_ALLOCATION_RISC1_AND_RISC2,
.tx_bd_ring_len = 16,
.rx_bd_ring_len = 16,
.phy_address= CONFIG_SYS_UEC6_PHY_ADDR,
@@ -1020,7 +1020,7 @@ static int uec_issue_init_enet_rxtx_cmd(uec_private_t
*uec,
/* Init Rx global parameter pointer */
p_init_enet_param-rgftgfrxglobal |= uec-rx_glbl_pram_offset |
-(u32)uec_info-riscRx;
+(u32)uec_info-risc_rx;
/* Init Rx threads */
for (i = 0; i (thread_rx + 1); i++) {
@@ -1038,13 +1038,13 @@ static int uec_issue_init_enet_rxtx_cmd(uec_private_t
*uec,
}
entry_val = ((u32)snum ENET_INIT_PARAM_SNUM_SHIFT) |
-init_enet_offset | (u32)uec_info-riscRx;
+init_enet_offset | (u32)uec_info-risc_rx;
p_init_enet_param-rxthread[i] = entry_val;
}
/* Init Tx global parameter pointer
[U-Boot] [PATCH 06/15 v2] drivers/qe: Change QE RISC ALLOCATION to support 4 RISCs
Also define the QE_RISC_ALLOCATION_RISCs to MACROs instead of using enum, and
define MAX_QE_RISC for QE based silicons.
Signed-off-by: Haiying Wang haiying.w...@freescale.com
Acked-by: Timur Tabi ti...@freescale.com
---
v2 change: rename riscRx and riscTx to risc_rx and risc_tx
drivers/qe/qe.c|3 ---
drivers/qe/qe.h| 17 +++--
drivers/qe/uec.c | 32 +++-
drivers/qe/uec.h |4 ++--
include/asm-ppc/immap_qe.h |8
5 files changed, 52 insertions(+), 12 deletions(-)
diff --git a/drivers/qe/qe.c b/drivers/qe/qe.c
index f114fe0..30fe726 100644
--- a/drivers/qe/qe.c
+++ b/drivers/qe/qe.c
@@ -258,9 +258,6 @@ int qe_set_mii_clk_src(int ucc_num)
return 0;
}
-/* The maximum number of RISCs we support */
-#define MAX_QE_RISC 2
-
/* Firmware information stored here for qe_get_firmware_info() */
static struct qe_firmware_info qe_firmware_info;
diff --git a/drivers/qe/qe.h b/drivers/qe/qe.h
index d78edba..2128f56 100644
--- a/drivers/qe/qe.h
+++ b/drivers/qe/qe.h
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2006 Freescale Semiconductor, Inc.
+ * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
*
* Dave Liu dave...@freescale.com
* based on source code of Shlomi Gridish
@@ -46,11 +46,16 @@ typedef struct qe_snum {
/* QE RISC allocation
*/
-typedef enum qe_risc_allocation {
- QE_RISC_ALLOCATION_RISC1= 1, /* RISC 1 */
- QE_RISC_ALLOCATION_RISC2= 2, /* RISC 2 */
- QE_RISC_ALLOCATION_RISC1_AND_RISC2 = 3 /* RISC 1 or RISC 2 */
-} qe_risc_allocation_e;
+#defineQE_RISC_ALLOCATION_RISC10x1 /* RISC 1 */
+#defineQE_RISC_ALLOCATION_RISC20x2 /* RISC 2 */
+#defineQE_RISC_ALLOCATION_RISC30x4 /* RISC 3 */
+#defineQE_RISC_ALLOCATION_RISC40x8 /* RISC 4 */
+#defineQE_RISC_ALLOCATION_RISC1_AND_RISC2
(QE_RISC_ALLOCATION_RISC1 | \
+QE_RISC_ALLOCATION_RISC2)
+#defineQE_RISC_ALLOCATION_FOUR_RISCS (QE_RISC_ALLOCATION_RISC1 | \
+QE_RISC_ALLOCATION_RISC2 | \
+QE_RISC_ALLOCATION_RISC3 | \
+QE_RISC_ALLOCATION_RISC4)
/* QE CECR commands for UCC fast.
*/
diff --git a/drivers/qe/uec.c b/drivers/qe/uec.c
index bba3ef2..eadcc2c 100644
--- a/drivers/qe/uec.c
+++ b/drivers/qe/uec.c
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2006 Freescale Semiconductor, Inc.
+ * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
*
* Dave Liu dave...@freescale.com
*
@@ -46,8 +46,13 @@ static uec_info_t eth1_uec_info = {
.num_threads_tx = UEC_NUM_OF_THREADS_4,
.num_threads_rx = UEC_NUM_OF_THREADS_4,
#endif
+#if (MAX_QE_RISC == 4)
+ .risc_tx= QE_RISC_ALLOCATION_FOUR_RISCS,
+ .risc_rx= QE_RISC_ALLOCATION_FOUR_RISCS,
+#else
.risc_tx= QE_RISC_ALLOCATION_RISC1_AND_RISC2,
.risc_rx= QE_RISC_ALLOCATION_RISC1_AND_RISC2,
+#endif
.tx_bd_ring_len = 16,
.rx_bd_ring_len = 16,
.phy_address= CONFIG_SYS_UEC1_PHY_ADDR,
@@ -69,8 +74,13 @@ static uec_info_t eth2_uec_info = {
.num_threads_tx = UEC_NUM_OF_THREADS_4,
.num_threads_rx = UEC_NUM_OF_THREADS_4,
#endif
+#if (MAX_QE_RISC == 4)
+ .risc_tx= QE_RISC_ALLOCATION_FOUR_RISCS,
+ .risc_rx= QE_RISC_ALLOCATION_FOUR_RISCS,
+#else
.risc_tx= QE_RISC_ALLOCATION_RISC1_AND_RISC2,
.risc_rx= QE_RISC_ALLOCATION_RISC1_AND_RISC2,
+#endif
.tx_bd_ring_len = 16,
.rx_bd_ring_len = 16,
.phy_address= CONFIG_SYS_UEC2_PHY_ADDR,
@@ -92,8 +102,13 @@ static uec_info_t eth3_uec_info = {
.num_threads_tx = UEC_NUM_OF_THREADS_4,
.num_threads_rx = UEC_NUM_OF_THREADS_4,
#endif
+#if (MAX_QE_RISC == 4)
+ .risc_tx= QE_RISC_ALLOCATION_FOUR_RISCS,
+ .risc_rx= QE_RISC_ALLOCATION_FOUR_RISCS,
+#else
.risc_tx= QE_RISC_ALLOCATION_RISC1_AND_RISC2,
.risc_rx= QE_RISC_ALLOCATION_RISC1_AND_RISC2,
+#endif
.tx_bd_ring_len = 16,
.rx_bd_ring_len = 16,
.phy_address= CONFIG_SYS_UEC3_PHY_ADDR,
@@ -115,8 +130,13 @@ static uec_info_t eth4_uec_info = {
.num_threads_tx = UEC_NUM_OF_THREADS_4,
.num_threads_rx = UEC_NUM_OF_THREADS_4,
#endif
+#if (MAX_QE_RISC == 4)
+ .risc_tx= QE_RISC_ALLOCATION_FOUR_RISCS,
+ .risc_rx
[U-Boot] [PATCH 10/15 v2] Update the number of ethxaddr in reading system eeprom
We support up to 8 mac addresses in system eeprom, so we define the macro
MAX_NUM_PORTS to limit the mac_count to 8, and update the number of ethxaddr
according to mac_count.
Signed-off-by: Haiying Wang haiying.w...@freescale.com
---
v2 change: define MAC_NUM_PORTS to limit the mac_count
board/freescale/common/sys_eeprom.c | 16 +---
1 files changed, 13 insertions(+), 3 deletions(-)
diff --git a/board/freescale/common/sys_eeprom.c
b/board/freescale/common/sys_eeprom.c
index 988cb94..671eb00 100644
--- a/board/freescale/common/sys_eeprom.c
+++ b/board/freescale/common/sys_eeprom.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2006, 2008 Freescale Semiconductor
+ * Copyright 2006, 2008-2009 Freescale Semiconductor
* York Sun (york...@freescale.com)
* Haiying Wang (haiying.w...@freescale.com)
* Timur Tabi (ti...@freescale.com)
@@ -34,6 +34,8 @@
#error Please define either CONFIG_SYS_I2C_EEPROM_CCID or
CONFIG_SYS_I2C_EEPROM_NXID
#endif
+#define MAX_NUM_PORTS 8
+
/**
* static eeprom: EEPROM layout for CCID or NXID formats
*
@@ -119,7 +121,8 @@ static void show_eeprom(void)
e.date[3] 0x80 ? PM : );
/* Show MAC addresses */
- for (i = 0; i min(e.mac_count, 8); i++) {
+ for (i = 0; i min(e.mac_count, MAX_NUM_PORTS); i++) {
+
u8 *p = e.mac[i];
printf(Eth%u: %02x:%02x:%02x:%02x:%02x:%02x\n, i,
@@ -404,7 +407,14 @@ int mac_read_from_eeprom(void)
}
}
- for (i = 0; i min(4, e.mac_count); i++) {
+ /* Check the number of MAC address which is limited to MAX_NUM_PORTS */
+ if (e.mac_count MAX_NUM_PORTS) {
+ printf(Warning: The number of MAC address is greater
+than MAX_NUM_PORTS, force it to MAX_NUM_PORTS.\n);
+ e.mac_count = MAX_NUM_PORTS;
+ }
+
+ for (i = 0; i e.mac_count; i++) {
if (memcmp(e.mac[i], \0\0\0\0\0\0, 6)
memcmp(e.mac[i], \xFF\xFF\xFF\xFF\xFF\xFF, 6)) {
char ethaddr[18];
--
1.6.0.2
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[U-Boot] [PATCH 10/15 v3] Update the number of ethxaddr in reading system eeprom
We support up to 8 mac addresses in system eeprom, so we define the macro
MAX_NUM_PORTS to limit the mac_count to 8, and update the number of ethxaddr
according to mac_count.
Signed-off-by: Haiying Wang haiying.w...@freescale.com
---
v3 change: Modify printf info and replace 8 with MAX_NUM_PORTS for array mac[]
board/freescale/common/sys_eeprom.c | 23 ++-
1 files changed, 18 insertions(+), 5 deletions(-)
diff --git a/board/freescale/common/sys_eeprom.c
b/board/freescale/common/sys_eeprom.c
index 988cb94..ba44b6b 100644
--- a/board/freescale/common/sys_eeprom.c
+++ b/board/freescale/common/sys_eeprom.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2006, 2008 Freescale Semiconductor
+ * Copyright 2006, 2008-2009 Freescale Semiconductor
* York Sun (york...@freescale.com)
* Haiying Wang (haiying.w...@freescale.com)
* Timur Tabi (ti...@freescale.com)
@@ -34,6 +34,8 @@
#error Please define either CONFIG_SYS_I2C_EEPROM_CCID or
CONFIG_SYS_I2C_EEPROM_NXID
#endif
+#define MAX_NUM_PORTS 8 /* This value must be 8 as defined in doc */
+
/**
* static eeprom: EEPROM layout for CCID or NXID formats
*
@@ -50,7 +52,7 @@ static struct __attribute__ ((__packed__)) eeprom {
u8 res_0[40]; /* 0x18 - 0x3f Reserved */
u8 mac_count; /* 0x40Number of MAC addresses */
u8 mac_flag; /* 0x41MAC table flags */
- u8 mac[8][6]; /* 0x42 - 0x71 MAC addresses */
+ u8 mac[MAX_NUM_PORTS][6]; /* 0x42 - 0x71 MAC addresses */
u32 crc; /* 0x72CRC32 checksum */
#endif
#ifdef CONFIG_SYS_I2C_EEPROM_NXID
@@ -66,7 +68,7 @@ static struct __attribute__ ((__packed__)) eeprom {
u8 res_1[21]; /* 0x2b - 0x3f Reserved */
u8 mac_count; /* 0x40Number of MAC addresses */
u8 mac_flag; /* 0x41MAC table flags */
- u8 mac[8][6]; /* 0x42 - 0x71 MAC addresses */
+ u8 mac[MAX_NUM_PORTS][6]; /* 0x42 - 0x71 MAC addresses */
u32 crc; /* 0x72CRC32 checksum */
#endif
} e;
@@ -119,7 +121,8 @@ static void show_eeprom(void)
e.date[3] 0x80 ? PM : );
/* Show MAC addresses */
- for (i = 0; i min(e.mac_count, 8); i++) {
+ for (i = 0; i min(e.mac_count, MAX_NUM_PORTS); i++) {
+
u8 *p = e.mac[i];
printf(Eth%u: %02x:%02x:%02x:%02x:%02x:%02x\n, i,
@@ -404,7 +407,17 @@ int mac_read_from_eeprom(void)
}
}
- for (i = 0; i min(4, e.mac_count); i++) {
+ /* Check the number of MAC addresses which is limited to
+* MAX_NUM_PORTS.
+*/
+ if (e.mac_count MAX_NUM_PORTS) {
+ printf(Warning: The number of MAC addresses is greater
+than %u, force it to %u.\n, MAX_NUM_PORTS,
+ MAX_NUM_PORTS);
+ e.mac_count = MAX_NUM_PORTS;
+ }
+
+ for (i = 0; i e.mac_count; i++) {
if (memcmp(e.mac[i], \0\0\0\0\0\0, 6)
memcmp(e.mac[i], \xFF\xFF\xFF\xFF\xFF\xFF, 6)) {
char ethaddr[18];
--
1.6.0.2
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[U-Boot] [PATCH 08/15] MPC85xx: Add UEC3 and UEC4 support for MPC8569MDS
Signed-off-by: Haiying Wang haiying.w...@freescale.com
---
board/freescale/mpc8569mds/bcsr.c |4
board/freescale/mpc8569mds/mpc8569mds.c | 30 ++
include/configs/MPC8569MDS.h| 23 +++
3 files changed, 57 insertions(+), 0 deletions(-)
diff --git a/board/freescale/mpc8569mds/bcsr.c
b/board/freescale/mpc8569mds/bcsr.c
index 5adffc2..f133732 100644
--- a/board/freescale/mpc8569mds/bcsr.c
+++ b/board/freescale/mpc8569mds/bcsr.c
@@ -41,6 +41,10 @@ void enable_8569mds_qe_mdio()
BCSR7_UCC1_GETH_EN | BCSR7_UCC1_RGMII_EN);
setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 8),
BCSR8_UCC2_GETH_EN | BCSR8_UCC2_RGMII_EN);
+ setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 9),
+ BCSR9_UCC3_GETH_EN | BCSR9_UCC3_RGMII_EN);
+ setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 10),
+ BCSR10_UCC4_GETH_EN | BCSR10_UCC4_RGMII_EN);
}
void disable_8569mds_brd_eeprom_write_protect()
diff --git a/board/freescale/mpc8569mds/mpc8569mds.c
b/board/freescale/mpc8569mds/mpc8569mds.c
index 7e6cfb7..387ecad 100644
--- a/board/freescale/mpc8569mds/mpc8569mds.c
+++ b/board/freescale/mpc8569mds/mpc8569mds.c
@@ -77,6 +77,36 @@ const qe_iop_conf_t qe_iop_conf_tab[] = {
{2, 3, 2, 0, 1}, /* ENET2_GRXCLK */
{2, 2, 1, 0, 2}, /* ENET2_GTXCLK */
+ /* UCC_3_RGMII */
+ {2, 11, 2, 0, 1}, /* CLK12 */
+ {0, 29, 1, 0, 2}, /* ENET3_TXD0_SER3_TXD0 */
+ {0, 30, 1, 0, 3}, /* ENET3_TXD1_SER3_TXD1 */
+ {0, 31, 1, 0, 2}, /* ENET3_TXD2_SER3_TXD2 */
+ {1, 0, 1, 0, 3}, /* ENET3_TXD3_SER3_TXD3 */
+ {1, 3, 2, 0, 3}, /* ENET3_RXD0_SER3_RXD0 */
+ {1, 4, 2, 0, 1}, /* ENET3_RXD1_SER3_RXD1 */
+ {1, 5, 2, 0, 2}, /* ENET3_RXD2_SER3_RXD2 */
+ {1, 6, 2, 0, 3}, /* ENET3_RXD3_SER3_RXD3 */
+ {1, 1, 1, 0, 1}, /* ENET3_TX_EN_SER3_RTS_B*/
+ {1, 9, 2, 0, 3}, /* ENET3_RX_DV_SER3_CTS_B*/
+ {2, 9, 2, 0, 2}, /* ENET3_GRXCLK */
+ {2, 25, 1, 0, 2}, /* ENET3_GTXCLK */
+
+ /* UCC_4_RGMII */
+ {2, 16, 2, 0, 3}, /* CLK17 */
+ {1, 12, 1, 0, 2}, /* ENET4_TXD0_SER4_TXD0 */
+ {1, 13, 1, 0, 2}, /* ENET4_TXD1_SER4_TXD1 */
+ {1, 14, 1, 0, 1}, /* ENET4_TXD2_SER4_TXD2 */
+ {1, 15, 1, 0, 2}, /* ENET4_TXD3_SER4_TXD3 */
+ {1, 18, 2, 0, 2}, /* ENET4_RXD0_SER4_RXD0 */
+ {1, 19, 2, 0, 1}, /* ENET4_RXD1_SER4_RXD1 */
+ {1, 20, 2, 0, 1}, /* ENET4_RXD2_SER4_RXD2 */
+ {1, 21, 2, 0, 2}, /* ENET4_RXD3_SER4_RXD3 */
+ {1, 16, 1, 0, 2}, /* ENET4_TX_EN_SER4_RTS_B*/
+ {1, 24, 2, 0, 3}, /* ENET4_RX_DV_SER4_CTS_B*/
+ {2, 17, 2, 0, 2}, /* ENET4_GRXCLK */
+ {2, 24, 1, 0, 2}, /* ENET4_GTXCLK */
+
/* UART1 is muxed with QE PortF bit [9-12].*/
{5, 12, 2, 0, 3}, /* UART1_SIN */
{5, 9, 1, 0, 3}, /* UART1_SOUT */
diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h
index c87e51d..7208c78 100644
--- a/include/configs/MPC8569MDS.h
+++ b/include/configs/MPC8569MDS.h
@@ -313,6 +313,29 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_SYS_UEC2_INTERFACE_MODE ENET_1000_RGMII_ID
#endif
+#define CONFIG_UEC_ETH3 /* GETH3 */
+#define CONFIG_HAS_ETH2
+
+#ifdef CONFIG_UEC_ETH3
+#define CONFIG_SYS_UEC3_UCC_NUM2 /* UCC3 */
+#define CONFIG_SYS_UEC3_RX_CLK QE_CLK_NONE
+#define CONFIG_SYS_UEC3_TX_CLK QE_CLK12
+#define CONFIG_SYS_UEC3_ETH_TYPE GIGA_ETH
+#define CONFIG_SYS_UEC3_PHY_ADDR 2
+#define CONFIG_SYS_UEC3_INTERFACE_MODE ENET_1000_RGMII_ID
+#endif
+
+#define CONFIG_UEC_ETH4 /* GETH4 */
+#define CONFIG_HAS_ETH3
+
+#ifdef CONFIG_UEC_ETH4
+#define CONFIG_SYS_UEC4_UCC_NUM3 /* UCC4 */
+#define CONFIG_SYS_UEC4_RX_CLK QE_CLK_NONE
+#define CONFIG_SYS_UEC4_TX_CLK QE_CLK17
+#define CONFIG_SYS_UEC4_ETH_TYPE GIGA_ETH
+#define CONFIG_SYS_UEC4_PHY_ADDR 3
+#define CONFIG_SYS_UEC4_INTERFACE_MODE ENET_1000_RGMII_ID
+#endif
#endif /* CONFIG_QE */
#if defined(CONFIG_PCI)
--
1.6.0.2
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[U-Boot] [PATCH 15/15] 85xx: Fix the wrong BCSR address of MPC8569MDS
From: Dave Liu dave...@freescale.com
The BCSR17[7] = 1 will unlock the write protect of FLASH.
The WP# pin only controls the write protect of top/bottom sector,
That is why we can save env, but we can't write the first sector
before the patch.
Signed-off-by: Dave Liu dave...@freescale.com
Signed-off-by: Haiying Wang haiying.w...@freescale.com
---
board/freescale/mpc8569mds/bcsr.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/board/freescale/mpc8569mds/bcsr.c
b/board/freescale/mpc8569mds/bcsr.c
index b895b4e..a936edb 100644
--- a/board/freescale/mpc8569mds/bcsr.c
+++ b/board/freescale/mpc8569mds/bcsr.c
@@ -27,7 +27,7 @@
void enable_8569mds_flash_write()
{
- setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 11), BCSR17_FLASH_nWP);
+ setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 17), BCSR17_FLASH_nWP);
}
void disable_8569mds_flash_write()
--
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[U-Boot] [PATCH 02/15] MPC85xx: Fix MURAM size for MPC8569
MPC8569 has 128K bytes MURAM.
Signed-off-by: Haiying Wang haiying.w...@freescale.com
---
include/asm-ppc/immap_qe.h |9 +++--
1 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/include/asm-ppc/immap_qe.h b/include/asm-ppc/immap_qe.h
index 66a4735..55667ca 100644
--- a/include/asm-ppc/immap_qe.h
+++ b/include/asm-ppc/immap_qe.h
@@ -582,9 +582,12 @@ typedef struct qe_immap {
u8 res14[0x300];
u8 res15[0x3A00];
u8 res16[0x8000]; /* 0x108000 - 0x11 */
-#if defined(CONFIG_MPC8568)||defined(CONFIG_MPC8569)
+#if defined(CONFIG_MPC8568)
u8 muram[0x1]; /* 0x1_ - 0x2_ Multi-user RAM */
u8 res17[0x2]; /* 0x2_ - 0x4_ */
+#elif defined(CONFIG_MPC8569)
+ u8 muram[0x2]; /* 0x1_ - 0x3_ Multi-user RAM */
+ u8 res17[0x1]; /* 0x3_ - 0x4_ */
#else
u8 muram[0xC000]; /* 0x11 - 0x11C000 Multi-user RAM */
u8 res17[0x24000]; /* 0x11C000 - 0x14 */
@@ -594,8 +597,10 @@ typedef struct qe_immap {
extern qe_map_t *qe_immr;
-#if defined(CONFIG_MPC8568) || defined(CONFIG_MPC8569)
+#if defined(CONFIG_MPC8568)
#define QE_MURAM_SIZE 0x1UL
+#elif defined(CONFIG_MPC8569)
+#define QE_MURAM_SIZE 0x2UL
#elif defined(CONFIG_MPC8360)
#define QE_MURAM_SIZE 0xc000UL
#elif defined(CONFIG_MPC832X)
--
1.6.0.2
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[U-Boot] [PATCH 03/15] MPC85xx: Fix some settings for MPC8569MDS board
- Change the CONFIG_SYS_CLK_FREQ and CONFIG_DDR_CLK_FREQ to since the on-board oscillator's freq is 66.666MHz. - Increase the size of malloc to 512KB because MPC8569MDS needs more memory for malloc to support up to eight Ethernet interfaces. - Move Environment address out of uboot thus the saved environment variables will not be erased after u-boot is re-programmed. Signed-off-by: Haiying Wang haiying.w...@freescale.com Signed-off-by: Dave Liu dave...@freescale.com --- include/configs/MPC8569MDS.h | 10 +- 1 files changed, 5 insertions(+), 5 deletions(-) diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h index b0af5dc..ea996ff 100644 --- a/include/configs/MPC8569MDS.h +++ b/include/configs/MPC8569MDS.h @@ -55,8 +55,8 @@ extern unsigned long get_clock_freq(void); #endif /* Replace a call to get_clock_freq (after it is implemented)*/ -#define CONFIG_SYS_CLK_FREQ6600 -#define CONFIG_DDR_CLK_FREQ6600 +#define CONFIG_SYS_CLK_FREQ +#define CONFIG_DDR_CLK_FREQCONFIG_SYS_CLK_FREQ /* * These can be toggled for performance analysis, otherwise use default. @@ -194,7 +194,7 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET #define CONFIG_SYS_MONITOR_LEN (256 * 1024)/* Reserve 256 kB for Mon */ -#define CONFIG_SYS_MALLOC_LEN (128 * 1024)/* Reserved for malloc */ +#define CONFIG_SYS_MALLOC_LEN (512 * 1024)/* Reserved for malloc */ /* Serial Port */ #define CONFIG_CONS_INDEX 1 @@ -327,9 +327,9 @@ extern unsigned long get_clock_freq(void); * Environment */ #define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_ADDR(CONFIG_SYS_MONITOR_BASE + 0x4) +#define CONFIG_ENV_ADDR(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) #define CONFIG_ENV_SECT_SIZE 0x2 /* 256K(one sector) for env */ -#define CONFIG_ENV_SIZE0x2000 +#define CONFIG_ENV_SIZECONFIG_ENV_SECT_SIZE #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ -- 1.6.0.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 07/15] drivers/qe: Add more SNUM number for QE
Some QE chips like 8569 need more SNUM numbers for supporting 4 UECs in RGMII-
1000 mode.
Signed-off-by: Haiying Wang haiying.w...@freescale.com
Acked-by: Timur Tabi ti...@freescale.com
---
drivers/qe/qe.c| 15 ---
drivers/qe/qe.h|1 -
include/asm-ppc/immap_qe.h |5 -
3 files changed, 16 insertions(+), 5 deletions(-)
diff --git a/drivers/qe/qe.c b/drivers/qe/qe.c
index 30fe726..beeb189 100644
--- a/drivers/qe/qe.c
+++ b/drivers/qe/qe.c
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2006 Freescale Semiconductor, Inc.
+ * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
*
* Dave Liu dave...@freescale.com
* based on source code of Shlomi Gridish
@@ -108,14 +108,23 @@ static void qe_sdma_init(void)
out_be32(p-sdmr, QE_SDMR_GLB_1_MSK | (0x3 QE_SDMR_CEN_SHIFT));
}
-static u8 thread_snum[QE_NUM_OF_SNUM] = {
+/* This table is a list of the serial numbers of the Threads, taken from the
+ * SNUM Table chart in the QE Reference Manual. The order is not important,
+ * we just need to know what the SNUMs are for the threads.
+ */
+static u8 thread_snum[] = {
0x04, 0x05, 0x0c, 0x0d,
0x14, 0x15, 0x1c, 0x1d,
0x24, 0x25, 0x2c, 0x2d,
0x34, 0x35, 0x88, 0x89,
0x98, 0x99, 0xa8, 0xa9,
0xb8, 0xb9, 0xc8, 0xc9,
- 0xd8, 0xd9, 0xe8, 0xe9
+ 0xd8, 0xd9, 0xe8, 0xe9,
+ 0x08, 0x09, 0x18, 0x19,
+ 0x28, 0x29, 0x38, 0x39,
+ 0x48, 0x49, 0x58, 0x59,
+ 0x68, 0x69, 0x78, 0x79,
+ 0x80, 0x81
};
static void qe_snums_init(void)
diff --git a/drivers/qe/qe.h b/drivers/qe/qe.h
index 2128f56..faad43c 100644
--- a/drivers/qe/qe.h
+++ b/drivers/qe/qe.h
@@ -25,7 +25,6 @@
#include common.h
-#define QE_NUM_OF_SNUM 28
#define QE_NUM_OF_BRGS 16
#define UCC_MAX_NUM8
diff --git a/include/asm-ppc/immap_qe.h b/include/asm-ppc/immap_qe.h
index 7613b5c..6e7f392 100644
--- a/include/asm-ppc/immap_qe.h
+++ b/include/asm-ppc/immap_qe.h
@@ -3,7 +3,7 @@
* The Internal Memory Map for devices with QE on them. This
* is the superset of all QE devices (8360, etc.).
*
- * Copyright (c) 2006 Freescale Semiconductor, Inc.
+ * Copyright (c) 2006-2009 Freescale Semiconductor, Inc.
* Author: Shlomi Gridih grid...@freescale.com
*
* This program is free software; you can redistribute it and/or modify it
@@ -609,10 +609,13 @@ extern qe_map_t *qe_immr;
#if defined(CONFIG_MPC8323)
#define MAX_QE_RISC 1
+#define QE_NUM_OF_SNUM 28
#elif defined(CONFIG_MPC8569)
#define MAX_QE_RISC 4
+#define QE_NUM_OF_SNUM 46
#else
#define MAX_QE_RISC2
+#define QE_NUM_OF_SNUM 28
#endif
#endif /* __IMMAP_QE_H__ */
--
1.6.0.2
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[U-Boot] [PATCH 05/15] MPC85xx: Add UART1 support for MPC8569MDS
MPC8569 UART1 signals are muxed with PortF bit[9-12], we need to define
those pins before using UART1.
Signed-off-by: Haiying Wang haiying.w...@freescale.com
---
board/freescale/mpc8569mds/mpc8569mds.c |6 ++
1 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/board/freescale/mpc8569mds/mpc8569mds.c
b/board/freescale/mpc8569mds/mpc8569mds.c
index 129c58c..7e6cfb7 100644
--- a/board/freescale/mpc8569mds/mpc8569mds.c
+++ b/board/freescale/mpc8569mds/mpc8569mds.c
@@ -77,6 +77,12 @@ const qe_iop_conf_t qe_iop_conf_tab[] = {
{2, 3, 2, 0, 1}, /* ENET2_GRXCLK */
{2, 2, 1, 0, 2}, /* ENET2_GTXCLK */
+ /* UART1 is muxed with QE PortF bit [9-12].*/
+ {5, 12, 2, 0, 3}, /* UART1_SIN */
+ {5, 9, 1, 0, 3}, /* UART1_SOUT */
+ {5, 10, 2, 0, 3}, /* UART1_CTS_B */
+ {5, 11, 1, 0, 2}, /* UART1_RTS_B */
+
{0, 0, 0, 0, QE_IOP_TAB_END} /* END of table */
};
--
1.6.0.2
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[U-Boot] [PATCH 06/15] drivers/qe: Change QE RISC ALLOCATION to support 4 RISCs
Also define the QE_RISC_ALLOCATION_RISCs to MACROs instead of using enum, and
define MAX_QE_RISC for QE based silicons.
Signed-off-by: Haiying Wang haiying.w...@freescale.com
Acked-by: Timur Tabi ti...@freescale.com
---
drivers/qe/qe.c|3 ---
drivers/qe/qe.h| 17 +++--
drivers/qe/uec.c | 32 +++-
drivers/qe/uec.h |4 ++--
include/asm-ppc/immap_qe.h |8
5 files changed, 52 insertions(+), 12 deletions(-)
diff --git a/drivers/qe/qe.c b/drivers/qe/qe.c
index f114fe0..30fe726 100644
--- a/drivers/qe/qe.c
+++ b/drivers/qe/qe.c
@@ -258,9 +258,6 @@ int qe_set_mii_clk_src(int ucc_num)
return 0;
}
-/* The maximum number of RISCs we support */
-#define MAX_QE_RISC 2
-
/* Firmware information stored here for qe_get_firmware_info() */
static struct qe_firmware_info qe_firmware_info;
diff --git a/drivers/qe/qe.h b/drivers/qe/qe.h
index d78edba..2128f56 100644
--- a/drivers/qe/qe.h
+++ b/drivers/qe/qe.h
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2006 Freescale Semiconductor, Inc.
+ * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
*
* Dave Liu dave...@freescale.com
* based on source code of Shlomi Gridish
@@ -46,11 +46,16 @@ typedef struct qe_snum {
/* QE RISC allocation
*/
-typedef enum qe_risc_allocation {
- QE_RISC_ALLOCATION_RISC1= 1, /* RISC 1 */
- QE_RISC_ALLOCATION_RISC2= 2, /* RISC 2 */
- QE_RISC_ALLOCATION_RISC1_AND_RISC2 = 3 /* RISC 1 or RISC 2 */
-} qe_risc_allocation_e;
+#defineQE_RISC_ALLOCATION_RISC10x1 /* RISC 1 */
+#defineQE_RISC_ALLOCATION_RISC20x2 /* RISC 2 */
+#defineQE_RISC_ALLOCATION_RISC30x4 /* RISC 3 */
+#defineQE_RISC_ALLOCATION_RISC40x8 /* RISC 4 */
+#defineQE_RISC_ALLOCATION_RISC1_AND_RISC2
(QE_RISC_ALLOCATION_RISC1 | \
+QE_RISC_ALLOCATION_RISC2)
+#defineQE_RISC_ALLOCATION_FOUR_RISCS (QE_RISC_ALLOCATION_RISC1 | \
+QE_RISC_ALLOCATION_RISC2 | \
+QE_RISC_ALLOCATION_RISC3 | \
+QE_RISC_ALLOCATION_RISC4)
/* QE CECR commands for UCC fast.
*/
diff --git a/drivers/qe/uec.c b/drivers/qe/uec.c
index bba3ef2..eadcc2c 100644
--- a/drivers/qe/uec.c
+++ b/drivers/qe/uec.c
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2006 Freescale Semiconductor, Inc.
+ * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
*
* Dave Liu dave...@freescale.com
*
@@ -46,8 +46,13 @@ static uec_info_t eth1_uec_info = {
.num_threads_tx = UEC_NUM_OF_THREADS_4,
.num_threads_rx = UEC_NUM_OF_THREADS_4,
#endif
+#if (MAX_QE_RISC == 4)
+ .riscTx = QE_RISC_ALLOCATION_FOUR_RISCS,
+ .riscRx = QE_RISC_ALLOCATION_FOUR_RISCS,
+#else
.riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
.riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
+#endif
.tx_bd_ring_len = 16,
.rx_bd_ring_len = 16,
.phy_address= CONFIG_SYS_UEC1_PHY_ADDR,
@@ -69,8 +74,13 @@ static uec_info_t eth2_uec_info = {
.num_threads_tx = UEC_NUM_OF_THREADS_4,
.num_threads_rx = UEC_NUM_OF_THREADS_4,
#endif
+#if (MAX_QE_RISC == 4)
+ .riscTx = QE_RISC_ALLOCATION_FOUR_RISCS,
+ .riscRx = QE_RISC_ALLOCATION_FOUR_RISCS,
+#else
.riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
.riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
+#endif
.tx_bd_ring_len = 16,
.rx_bd_ring_len = 16,
.phy_address= CONFIG_SYS_UEC2_PHY_ADDR,
@@ -92,8 +102,13 @@ static uec_info_t eth3_uec_info = {
.num_threads_tx = UEC_NUM_OF_THREADS_4,
.num_threads_rx = UEC_NUM_OF_THREADS_4,
#endif
+#if (MAX_QE_RISC == 4)
+ .riscTx = QE_RISC_ALLOCATION_FOUR_RISCS,
+ .riscRx = QE_RISC_ALLOCATION_FOUR_RISCS,
+#else
.riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
.riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
+#endif
.tx_bd_ring_len = 16,
.rx_bd_ring_len = 16,
.phy_address= CONFIG_SYS_UEC3_PHY_ADDR,
@@ -115,8 +130,13 @@ static uec_info_t eth4_uec_info = {
.num_threads_tx = UEC_NUM_OF_THREADS_4,
.num_threads_rx = UEC_NUM_OF_THREADS_4,
#endif
+#if (MAX_QE_RISC == 4)
+ .riscTx = QE_RISC_ALLOCATION_FOUR_RISCS,
+ .riscRx = QE_RISC_ALLOCATION_FOUR_RISCS,
+#else
.riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
.riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
+#endif
[U-Boot] [PATCH 12/15] drivers/qe: add sgmii support in for UEC driver
Signed-off-by: Haiying Wang haiying.w...@freescale.com
---
drivers/qe/uec.c | 17 +
drivers/qe/uec.h | 31 +--
2 files changed, 46 insertions(+), 2 deletions(-)
diff --git a/drivers/qe/uec.c b/drivers/qe/uec.c
index deeb947..7649f9f 100644
--- a/drivers/qe/uec.c
+++ b/drivers/qe/uec.c
@@ -577,6 +577,10 @@ static int uec_set_mac_if_mode(uec_private_t *uec,
enet_interface_e if_mode)
maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
upsmr |= (UPSMR_R10M | UPSMR_RMM);
break;
+ case ENET_1000_SGMII:
+ maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
+ upsmr |= UPSMR_SGMM;
+ break;
default:
return -EINVAL;
break;
@@ -1276,6 +1280,18 @@ static int uec_startup(uec_private_t *uec)
out_be32(uec_regs-utbipar, utbipar);
+ /* Configure the TBI for SGMII operation */
+ if (uec-uec_info-enet_interface == ENET_1000_SGMII) {
+ uec_write_phy_reg(uec-dev, uec_regs-utbipar,
+ ENET_TBI_MII_ANA, TBIANA_SETTINGS);
+
+ uec_write_phy_reg(uec-dev, uec_regs-utbipar,
+ ENET_TBI_MII_TBICON, TBICON_CLK_SELECT);
+
+ uec_write_phy_reg(uec-dev, uec_regs-utbipar,
+ ENET_TBI_MII_CR, TBICR_SETTINGS);
+ }
+
/* Allocate Tx BDs */
length = ((uec_info-tx_bd_ring_len * SIZEOFBD) /
UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT) *
@@ -1565,6 +1581,7 @@ int uec_initialize(int index)
devlist[index] = dev;
uec-uec_info = uec_info;
+ uec-dev = dev;
sprintf(dev-name, FSL UEC%d, index);
dev-iobase = 0;
diff --git a/drivers/qe/uec.h b/drivers/qe/uec.h
index 411f0d2..5497b06 100644
--- a/drivers/qe/uec.h
+++ b/drivers/qe/uec.h
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2006 Freescale Semiconductor, Inc.
+ * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
*
* Dave Liu dave...@freescale.com
* based on source code of Shlomi Gridish
@@ -47,6 +47,7 @@
#define UPSMR_CAM 0x0400 /* CAM Address Matching */
#define UPSMR_BRO 0x0200 /* Broadcast Address */
#define UPSMR_RES1 0x2000 /* Reserved feild - must be 1*/
+#define UPSMR_SGMM 0x0020 /* SGMII mode*/
#define UPSMR_INIT_VALUE (UPSMR_HSE | UPSMR_RES1)
@@ -621,6 +622,31 @@ typedef enum enet_tbi_mii_reg {
ENET_TBI_MII_TBICON= 0x11
} enet_tbi_mii_reg_e;
+/* TBI MDIO register bit fields*/
+#define TBICON_CLK_SELECT 0x0020
+#define TBIANA_ASYMMETRIC_PAUSE0x0100
+#define TBIANA_SYMMETRIC_PAUSE 0x0080
+#define TBIANA_HALF_DUPLEX 0x0040
+#define TBIANA_FULL_DUPLEX 0x0020
+#define TBICR_PHY_RESET0x8000
+#define TBICR_ANEG_ENABLE 0x1000
+#define TBICR_RESTART_ANEG 0x0200
+#define TBICR_FULL_DUPLEX 0x0100
+#define TBICR_SPEED1_SET 0x0040
+
+#define TBIANA_SETTINGS ( \
+ TBIANA_ASYMMETRIC_PAUSE \
+ | TBIANA_SYMMETRIC_PAUSE \
+ | TBIANA_FULL_DUPLEX \
+ )
+
+#define TBICR_SETTINGS ( \
+ TBICR_PHY_RESET \
+ | TBICR_ANEG_ENABLE \
+ | TBICR_FULL_DUPLEX \
+ | TBICR_SPEED1_SET \
+ )
+
/* UEC number of threads
*/
typedef enum uec_num_of_threads {
@@ -645,7 +671,8 @@ typedef enum enet_interface {
ENET_1000_RGMII_ID,
ENET_1000_RGMII_RXID,
ENET_1000_TBI,
- ENET_1000_RTBI
+ ENET_1000_RTBI,
+ ENET_1000_SGMII
} enet_interface_e;
/* UEC initialization info struct
--
1.6.0.2
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[U-Boot] [PATCH 00/15] patchset for QE UEC and MPC8569MDS
Here is the patchset for adding new features for QE UEC and MPC8569MDS board. Please review this patchset and ignore the one(9 patches) I sent out some weeks ago, since there are some update in the new patches. Thanks. Haiying ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 09/15] MPC85xx: Add RMII support for MPC8569MDS
This patch supports UCC working at RMII mode on PIB board, fixup fdt blob to
support rmii in kernel. It also changes the name of enable_mpc8569mds_qe_mdio to
enalbe_mpc8569mds_qe_uec which is more accurate.
Signed-off-by: Haiying Wang haiying.w...@freescale.com
---
board/freescale/mpc8569mds/bcsr.c | 15 +-
board/freescale/mpc8569mds/bcsr.h |2 +-
board/freescale/mpc8569mds/mpc8569mds.c | 96 ++-
include/configs/MPC8569MDS.h| 38 +++-
4 files changed, 144 insertions(+), 7 deletions(-)
diff --git a/board/freescale/mpc8569mds/bcsr.c
b/board/freescale/mpc8569mds/bcsr.c
index f133732..b895b4e 100644
--- a/board/freescale/mpc8569mds/bcsr.c
+++ b/board/freescale/mpc8569mds/bcsr.c
@@ -35,8 +35,9 @@ void disable_8569mds_flash_write()
clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 17), BCSR17_FLASH_nWP);
}
-void enable_8569mds_qe_mdio()
+void enable_8569mds_qe_uec()
{
+#if defined(CONFIG_SYS_UCC_RGMII_MODE)
setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 7),
BCSR7_UCC1_GETH_EN | BCSR7_UCC1_RGMII_EN);
setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 8),
@@ -45,6 +46,18 @@ void enable_8569mds_qe_mdio()
BCSR9_UCC3_GETH_EN | BCSR9_UCC3_RGMII_EN);
setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 10),
BCSR10_UCC4_GETH_EN | BCSR10_UCC4_RGMII_EN);
+#elif defined(CONFIG_SYS_UCC_RMII_MODE)
+ /* Set UCC1-4 working at RMII mode */
+ clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 7),
+ BCSR7_UCC1_GETH_EN | BCSR7_UCC1_RGMII_EN);
+ clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 8),
+ BCSR8_UCC2_GETH_EN | BCSR8_UCC2_RGMII_EN);
+ clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 9),
+ BCSR9_UCC3_GETH_EN | BCSR9_UCC3_RGMII_EN);
+ clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 10),
+ BCSR10_UCC4_GETH_EN | BCSR10_UCC4_RGMII_EN);
+ setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 9), BCSR9_UCC3_RMII_EN);
+#endif
}
void disable_8569mds_brd_eeprom_write_protect()
diff --git a/board/freescale/mpc8569mds/bcsr.h
b/board/freescale/mpc8569mds/bcsr.h
index 8efe9bd..e5d63c7 100644
--- a/board/freescale/mpc8569mds/bcsr.h
+++ b/board/freescale/mpc8569mds/bcsr.h
@@ -76,7 +76,7 @@
void enable_8569mds_flash_write(void);
void disable_8569mds_flash_write(void);
-void enable_8569mds_qe_mdio(void);
+void enable_8569mds_qe_uec(void);
void disable_8569mds_brd_eeprom_write_protect(void);
#endif /* __BCSR_H_ */
diff --git a/board/freescale/mpc8569mds/mpc8569mds.c
b/board/freescale/mpc8569mds/mpc8569mds.c
index 387ecad..1e7526a 100644
--- a/board/freescale/mpc8569mds/mpc8569mds.c
+++ b/board/freescale/mpc8569mds/mpc8569mds.c
@@ -47,6 +47,7 @@ const qe_iop_conf_t qe_iop_conf_tab[] = {
/* QE_MUX_MDIO */
{2, 30, 3, 0, 2}, /* QE_MUX_MDIO */
+#if defined(CONFIG_SYS_UCC_RGMII_MODE)
/* UCC_1_RGMII */
{2, 11, 2, 0, 1}, /* CLK12 */
{0, 0, 1, 0, 3}, /* ENET1_TXD0_SER1_TXD0 */
@@ -107,6 +108,44 @@ const qe_iop_conf_t qe_iop_conf_tab[] = {
{2, 17, 2, 0, 2}, /* ENET4_GRXCLK */
{2, 24, 1, 0, 2}, /* ENET4_GTXCLK */
+#elif defined(CONFIG_SYS_UCC_RMII_MODE)
+ /* UCC_1_RMII */
+ {2, 15, 2, 0, 1}, /* CLK16 */
+ {0, 0, 1, 0, 3}, /* ENET1_TXD0_SER1_TXD0 */
+ {0, 1, 1, 0, 3}, /* ENET1_TXD1_SER1_TXD1 */
+ {0, 6, 2, 0, 3}, /* ENET1_RXD0_SER1_RXD0 */
+ {0, 7, 2, 0, 1}, /* ENET1_RXD1_SER1_RXD1 */
+ {0, 4, 1, 0, 2}, /* ENET1_TX_EN_SER1_RTS_B*/
+ {0, 12, 2, 0, 3}, /* ENET1_RX_DV_SER1_CTS_B*/
+
+ /* UCC_2_RMII */
+ {2, 15, 2, 0, 1}, /* CLK16 */
+ {0, 14, 1, 0, 2}, /* ENET2_TXD0_SER2_TXD0 */
+ {0, 15, 1, 0, 2}, /* ENET2_TXD1_SER2_TXD1 */
+ {0, 20, 2, 0, 2}, /* ENET2_RXD0_SER2_RXD0 */
+ {0, 21, 2, 0, 1}, /* ENET2_RXD1_SER2_RXD1 */
+ {0, 18, 1, 0, 2}, /* ENET2_TX_EN_SER2_RTS_B*/
+ {0, 26, 2, 0, 3}, /* ENET2_RX_DV_SER2_CTS_B*/
+
+ /* UCC_3_RMII */
+ {2, 15, 2, 0, 1}, /* CLK16 */
+ {0, 29, 1, 0, 2}, /* ENET3_TXD0_SER3_TXD0 */
+ {0, 30, 1, 0, 3}, /* ENET3_TXD1_SER3_TXD1 */
+ {1, 3, 2, 0, 3}, /* ENET3_RXD0_SER3_RXD0 */
+ {1, 4, 2, 0, 1}, /* ENET3_RXD1_SER3_RXD1 */
+ {1, 1, 1, 0, 1}, /* ENET3_TX_EN_SER3_RTS_B*/
+ {1, 9, 2, 0, 3}, /* ENET3_RX_DV_SER3_CTS_B*/
+
+ /* UCC_4_RMII */
+ {2, 15, 2, 0, 1}, /* CLK16 */
+ {1, 12, 1, 0, 2}, /* ENET4_TXD0_SER4_TXD0 */
+ {1, 13, 1, 0, 2}, /* ENET4_TXD1_SER4_TXD1 */
+ {1, 18, 2, 0, 2}, /* ENET4_RXD0_SER4_RXD0 */
+ {1, 19, 2, 0, 1}, /* ENET4_RXD1_SER4_RXD1 */
+ {1, 16, 1, 0, 2}, /* ENET4_TX_EN_SER4_RTS_B*/
+ {1, 24, 2, 0, 3}, /* ENET4_RX_DV_SER4_CTS_B*/
+#endif
+
/* UART1 is muxed with QE
[U-Boot] [PATCH 11/15] MPC85xx: update uec to support up to 8 UECs in QE
Signed-off-by: Haiying Wang haiying.w...@freescale.com
---
cpu/mpc85xx/cpu.c |6 +
cpu/mpc85xx/fdt.c |4 ++-
drivers/qe/uec.c | 66 -
3 files changed, 74 insertions(+), 2 deletions(-)
diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c
index b812d88..eb2aeec 100644
--- a/cpu/mpc85xx/cpu.c
+++ b/cpu/mpc85xx/cpu.c
@@ -399,6 +399,12 @@ int cpu_eth_init(bd_t *bis)
#if defined(CONFIG_UEC_ETH6)
uec_initialize(5);
#endif
+#if defined(CONFIG_UEC_ETH7)
+ uec_initialize(6);
+#endif
+#if defined(CONFIG_UEC_ETH8)
+ uec_initialize(7);
+#endif
#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_MPC85XX_FEC)
tsec_standard_init(bis);
#endif
diff --git a/cpu/mpc85xx/fdt.c b/cpu/mpc85xx/fdt.c
index 26a8f48..720c645 100644
--- a/cpu/mpc85xx/fdt.c
+++ b/cpu/mpc85xx/fdt.c
@@ -279,7 +279,9 @@ void ft_cpu_setup(void *blob, bd_t *bd)
fdt_fixup_crypto_node(blob, 0);
#if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) ||\
-defined(CONFIG_HAS_ETH2) || defined(CONFIG_HAS_ETH3)
+defined(CONFIG_HAS_ETH2) || defined(CONFIG_HAS_ETH3) ||\
+defined(CONFIG_HAS_ETH4) || defined(CONFIG_HAS_ETH5) ||\
+defined(CONFIG_HAS_ETH6) || defined(CONFIG_HAS_ETH7)
fdt_fixup_ethernet(blob);
fdt_add_enet_stashing(blob);
diff --git a/drivers/qe/uec.c b/drivers/qe/uec.c
index eadcc2c..deeb947 100644
--- a/drivers/qe/uec.c
+++ b/drivers/qe/uec.c
@@ -199,8 +199,64 @@ static uec_info_t eth6_uec_info = {
.enet_interface = CONFIG_SYS_UEC6_INTERFACE_MODE,
};
#endif
+#ifdef CONFIG_UEC_ETH7
+static uec_info_t eth7_uec_info = {
+ .uf_info= {
+ .ucc_num= CONFIG_SYS_UEC7_UCC_NUM,
+ .rx_clock = CONFIG_SYS_UEC7_RX_CLK,
+ .tx_clock = CONFIG_SYS_UEC7_TX_CLK,
+ .eth_type = CONFIG_SYS_UEC7_ETH_TYPE,
+ },
+#if (CONFIG_SYS_UEC7_ETH_TYPE == FAST_ETH)
+ .num_threads_tx = UEC_NUM_OF_THREADS_1,
+ .num_threads_rx = UEC_NUM_OF_THREADS_1,
+#else
+ .num_threads_tx = UEC_NUM_OF_THREADS_4,
+ .num_threads_rx = UEC_NUM_OF_THREADS_4,
+#endif
+#if (MAX_QE_RISC == 4)
+ .riscTx = QE_RISC_ALLOCATION_FOUR_RISCS,
+ .riscRx = QE_RISC_ALLOCATION_FOUR_RISCS,
+#else
+ .riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
+ .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
+#endif
+ .tx_bd_ring_len = 16,
+ .rx_bd_ring_len = 16,
+ .phy_address= CONFIG_SYS_UEC7_PHY_ADDR,
+ .enet_interface = CONFIG_SYS_UEC7_INTERFACE_MODE,
+};
+#endif
+#ifdef CONFIG_UEC_ETH8
+static uec_info_t eth8_uec_info = {
+ .uf_info= {
+ .ucc_num= CONFIG_SYS_UEC8_UCC_NUM,
+ .rx_clock = CONFIG_SYS_UEC8_RX_CLK,
+ .tx_clock = CONFIG_SYS_UEC8_TX_CLK,
+ .eth_type = CONFIG_SYS_UEC8_ETH_TYPE,
+ },
+#if (CONFIG_SYS_UEC8_ETH_TYPE == FAST_ETH)
+ .num_threads_tx = UEC_NUM_OF_THREADS_1,
+ .num_threads_rx = UEC_NUM_OF_THREADS_1,
+#else
+ .num_threads_tx = UEC_NUM_OF_THREADS_4,
+ .num_threads_rx = UEC_NUM_OF_THREADS_4,
+#endif
+#if (MAX_QE_RISC == 4)
+ .riscTx = QE_RISC_ALLOCATION_FOUR_RISCS,
+ .riscRx = QE_RISC_ALLOCATION_FOUR_RISCS,
+#else
+ .riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
+ .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
+#endif
+ .tx_bd_ring_len = 16,
+ .rx_bd_ring_len = 16,
+ .phy_address= CONFIG_SYS_UEC8_PHY_ADDR,
+ .enet_interface = CONFIG_SYS_UEC8_INTERFACE_MODE,
+};
+#endif
-#define MAXCONTROLLERS (6)
+#define MAXCONTROLLERS (8)
static struct eth_device *devlist[MAXCONTROLLERS];
@@ -1493,6 +1549,14 @@ int uec_initialize(int index)
#ifdef CONFIG_UEC_ETH6
uec_info = eth6_uec_info;
#endif
+ } else if (index == 6) {
+#ifdef CONFIG_UEC_ETH7
+ uec_info = eth7_uec_info;
+#endif
+ } else if (index == 7) {
+#ifdef CONFIG_UEC_ETH8
+ uec_info = eth8_uec_info;
+#endif
} else {
printf(%s: index is illegal.\n, __FUNCTION__);
return -EINVAL;
--
1.6.0.2
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[U-Boot] [PATCH 04/15] MPC85xx: Add PIB support at CS4/CS5 for MPC8569MDS
Signed-off-by: Haiying Wang haiying.w...@freescale.com Signed-off-by: Yu Liu yu@freescale.com --- include/configs/MPC8569MDS.h | 10 +- 1 files changed, 9 insertions(+), 1 deletions(-) diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h index ea996ff..c87e51d 100644 --- a/include/configs/MPC8569MDS.h +++ b/include/configs/MPC8569MDS.h @@ -156,10 +156,18 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_BR0_PRELIM 0xfe000801 #defineCONFIG_SYS_OR0_PRELIM 0xfe000ff7 -/*Chip slelect 1 - BCSR*/ +/*Chip select 1 - BCSR*/ #define CONFIG_SYS_BR1_PRELIM 0xf8000801 #defineCONFIG_SYS_OR1_PRELIM 0xe9f7 +/*Chip select 4 - PIB*/ +#define CONFIG_SYS_BR4_PRELIM 0xf8008801 +#define CONFIG_SYS_OR4_PRELIM 0xe9f7 + +/*Chip select 5 - PIB*/ +#define CONFIG_SYS_BR5_PRELIM 0xf8010801 +#define CONFIG_SYS_OR5_PRELIM 0xe9f7 + #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */ #undef CONFIG_SYS_FLASH_CHECKSUM -- 1.6.0.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 01/15] MPC85xx: Add QE clk support
Signed-off-by: Haiying Wang haiying.w...@freescale.com
Acked-by: Timur Tabi ti...@freescale.com
---
cpu/mpc85xx/cpu.c|4
cpu/mpc85xx/speed.c | 15 ++-
include/asm-ppc/immap_85xx.h |2 ++
include/e500.h |1 +
4 files changed, 21 insertions(+), 1 deletions(-)
diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c
index ef976a4..b812d88 100644
--- a/cpu/mpc85xx/cpu.c
+++ b/cpu/mpc85xx/cpu.c
@@ -184,6 +184,10 @@ int checkcpu (void)
printf(CPM: %s MHz\n, strmhz(buf1, sysinfo.freqSystemBus));
#endif
+#ifdef CONFIG_QE
+ printf( QE:%-4s MHz\n, strmhz(buf1, sysinfo.freqQE));
+#endif
+
puts(L1:D-cache 32 kB enabled\n I-cache 32 kB enabled\n);
return 0;
diff --git a/cpu/mpc85xx/speed.c b/cpu/mpc85xx/speed.c
index b0f47e0..286b6b2 100644
--- a/cpu/mpc85xx/speed.c
+++ b/cpu/mpc85xx/speed.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2004 Freescale Semiconductor.
+ * Copyright 2004, 2007-2009 Freescale Semiconductor Inc.
* (C) Copyright 2003 Motorola Inc.
* Xianghua Xiao, (x.x...@motorola.com)
*
@@ -40,6 +40,9 @@ void get_sys_info (sys_info_t * sysInfo)
uint plat_ratio,e500_ratio,half_freqSystemBus;
uint lcrr_div;
int i;
+#ifdef CONFIG_QE
+ u32 qe_ratio;
+#endif
plat_ratio = (gur-porpllsr) 0x003e;
plat_ratio = 1;
@@ -65,6 +68,12 @@ void get_sys_info (sys_info_t * sysInfo)
}
#endif
+#ifdef CONFIG_QE
+ qe_ratio = ((gur-porpllsr) MPC85xx_PORPLLSR_QE_RATIO)
+MPC85xx_PORPLLSR_QE_RATIO_SHIFT;
+ sysInfo-freqQE = qe_ratio * CONFIG_SYS_CLK_FREQ;
+#endif
+
#if defined(CONFIG_SYS_LBC_LCRR)
/* We will program LCRR to this value later */
lcrr_div = CONFIG_SYS_LBC_LCRR LCRR_CLKDIV;
@@ -112,6 +121,10 @@ int get_clocks (void)
gd-mem_clk = sys_info.freqDDRBus;
gd-lbc_clk = sys_info.freqLocalBus;
+#ifdef CONFIG_QE
+ gd-qe_clk = sys_info.freqQE;
+ gd-brg_clk = gd-qe_clk / 2;
+#endif
/*
* The base clock for I2C depends on the actual SOC. Unfortunately,
* there is no pattern that can be used to determine the frequency, so
diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h
index 0810b8e..a4d25cd 100644
--- a/include/asm-ppc/immap_85xx.h
+++ b/include/asm-ppc/immap_85xx.h
@@ -1581,6 +1581,8 @@ typedef struct ccsr_gur {
#define MPC85xx_PORPLLSR_DDR_RATIO 0x3e00
#define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT 9
#endif
+#define MPC85xx_PORPLLSR_QE_RATIO 0x3e00
+#define MPC85xx_PORPLLSR_QE_RATIO_SHIFT25
uintporbmsr;/* 0xe0004 - POR boot mode status register */
#define MPC85xx_PORBMSR_HA 0x0007
uintporimpscr; /* 0xe0008 - POR I/O impedance status and
control register */
diff --git a/include/e500.h b/include/e500.h
index 4c5eeb7..84b580d 100644
--- a/include/e500.h
+++ b/include/e500.h
@@ -18,6 +18,7 @@ typedef struct
unsigned long freqSystemBus;
unsigned long freqDDRBus;
unsigned long freqLocalBus;
+ unsigned long freqQE;
} MPC85xx_SYS_INFO;
#endif /* _ASMLANGUAGE */
--
1.6.0.2
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[U-Boot] [PATCH 13/15] MPC85xx: Add UEC6 and UEC8 at SGMII mode for MPC8569MDS
On MPC8569MDS board, UCC6 and UCC8 can be configured to work at SGMII mode via UEM on PB board. Since MPC8569 supports up to 4 Gigabit Ethernet ports, we disable UEC6 and UEC8 by default. Signed-off-by: Haiying Wang haiying.w...@freescale.com --- include/configs/MPC8569MDS.h | 25 + 1 files changed, 25 insertions(+), 0 deletions(-) diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h index 81df4c8..62507fe 100644 --- a/include/configs/MPC8569MDS.h +++ b/include/configs/MPC8569MDS.h @@ -366,6 +366,31 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_UEC4_INTERFACE_MODE ENET_100_RMII #endif /* CONFIG_SYS_UCC_RGMII_MODE */ #endif /* CONFIG_UEC_ETH4 */ + +#undef CONFIG_UEC_ETH6 /* GETH6 */ +#define CONFIG_HAS_ETH5 + +#ifdef CONFIG_UEC_ETH6 +#define CONFIG_SYS_UEC6_UCC_NUM5 /* UCC6 */ +#define CONFIG_SYS_UEC6_RX_CLK QE_CLK_NONE +#define CONFIG_SYS_UEC6_TX_CLK QE_CLK_NONE +#define CONFIG_SYS_UEC6_ETH_TYPE GIGA_ETH +#define CONFIG_SYS_UEC6_PHY_ADDR 4 +#define CONFIG_SYS_UEC6_INTERFACE_MODE ENET_1000_SGMII +#endif /* CONFIG_UEC_ETH6 */ + +#undef CONFIG_UEC_ETH8 /* GETH8 */ +#define CONFIG_HAS_ETH7 + +#ifdef CONFIG_UEC_ETH8 +#define CONFIG_SYS_UEC8_UCC_NUM7 /* UCC8 */ +#define CONFIG_SYS_UEC8_RX_CLK QE_CLK_NONE +#define CONFIG_SYS_UEC8_TX_CLK QE_CLK_NONE +#define CONFIG_SYS_UEC8_ETH_TYPE GIGA_ETH +#define CONFIG_SYS_UEC8_PHY_ADDR 6 +#define CONFIG_SYS_UEC8_INTERFACE_MODE ENET_1000_SGMII +#endif /* CONFIG_UEC_ETH8 */ + #endif /* CONFIG_QE */ #if defined(CONFIG_PCI) -- 1.6.0.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 14/15] MPC85xx: Add README for MPC8569MDS
Signed-off-by: Haiying Wang haiying.w...@freescale.com --- doc/README.mpc8569mds | 78 + 1 files changed, 78 insertions(+), 0 deletions(-) create mode 100644 doc/README.mpc8569mds diff --git a/doc/README.mpc8569mds b/doc/README.mpc8569mds new file mode 100644 index 000..d9112b6 --- /dev/null +++ b/doc/README.mpc8569mds @@ -0,0 +1,78 @@ +Overview + +MPC8569MDS is composed of two boards - PB (Processor Board) and PIB (Platform +I/O Board). The mpc8569 PowerTM processor is mounted on PB board. + +Building U-boot +--- + make MPC8569MDS_config + make + +Memory Map +-- +0x_ 0x7fff_ DDR 2G +0xa000_ 0xbfff_ PCIe MEM512MB +0xe000_ 0xe00f_ CCSRBAR 1M +0xe280_ 0xe2ff_ PCIe I/O8M +0xc000_ 0xdfff_ SRIO512MB +0xf000_ 0xf3ff_ SDRAM 64MB +0xf800_ 0xf800_7fff BCSR32KB +0xf800_8000 0xf800_ PIB (CS4) 32KB +0xf801_ 0xf801_7fff PIB (CS5) 32KB +0xfe00_ 0x_ Flash 32MB + + +Flashing u-boot Images +--- + +Use the following commands to program u-boot image into flash: + + = tftp 100 u-boot.bin + = protect off all + = erase fff8 + = cp.b 100 fff8 8 + + +Setting the correct MAC addresses +--- +The command - mac, is introduced to set on-board system EEPROM in the format +defined in board/freescale/common/sys_eeprom.c. we must set all 8 MAC +addresses for the MPC8569MDS's 8 Ethernet ports and save it by mac save when +we first get the board. The commands are as follows: + = mac i NXID /* Set NXID to this EEPROM */ + = mac e 01 /* Set Errata, this value is not defined by hardware + designer, we can set whatever we want */ + = mac n a0 /* Set Serial Number. This is not defined by hardware + designer, we can set whatever we want */ + = mac date 09051208 /* Set the date in YYMMDDhhmmss format */ + + = mac p 8 /* Set the number of mac ports, it should be 8 */ + = mac 0 xx:xx:xx:xx:xx:xx /* xx:xx:xx:xx:xx:xx should be the real mac + address, you can refer to the value on + the sticker of the rear side of the board +*/ + . + = mac 7 xx:xx:xx:xx:xx:xx + = mac read + = mac save + +After resetting the board, the ethxaddrs will be filled with the mac addresses +if such environment variables are blank(never been set before). If the ethxaddr +has been set but we want to update it, we can use the following commands: + = setenv ethxaddr /* x = none,1,2,3,4,5,6,7 */ + = save + = reset + + +Programming the ucode to flash +- +MPC8569 doesn't have ROM in QE, so we must upload the microcode(ucode) to QE's +IRAM so that the QE can work. The ucode binary can be downloaded from +http://opensource.freescale.com/firmware/, and it must be programmed to +the address 0xfff in the flash. Otherwise, the QE can't work and uboot +hangs at Net: + + +Please note the above two steps(setting mac addresses and programming ucode) are +very important to get the board booting up and working properly. + -- 1.6.0.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 10/15] Update the number of ethxaddr in reading system eeprom
We support up to 8 mac addresses in system eeprom, so we'd limit the mac_count
to 8, and update the number of ethxaddr if there is more than 4 ethernet ports.
Signed-off-by: Haiying Wang haiying.w...@freescale.com
---
board/freescale/common/sys_eeprom.c | 11 +--
1 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/board/freescale/common/sys_eeprom.c
b/board/freescale/common/sys_eeprom.c
index 988cb94..d71a5e4 100644
--- a/board/freescale/common/sys_eeprom.c
+++ b/board/freescale/common/sys_eeprom.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2006, 2008 Freescale Semiconductor
+ * Copyright 2006, 2008-2009 Freescale Semiconductor
* York Sun (york...@freescale.com)
* Haiying Wang (haiying.w...@freescale.com)
* Timur Tabi (ti...@freescale.com)
@@ -404,7 +404,14 @@ int mac_read_from_eeprom(void)
}
}
- for (i = 0; i min(4, e.mac_count); i++) {
+ /* Check the number of MAC address which is limited to 8 */
+ if (e.mac_count 8) {
+ printf(Warning: The number of MAC address is greater
+than 8, force it to 8.\n);
+ e.mac_count = 8;
+ }
+
+ for (i = 0; i e.mac_count; i++) {
if (memcmp(e.mac[i], \0\0\0\0\0\0, 6)
memcmp(e.mac[i], \xFF\xFF\xFF\xFF\xFF\xFF, 6)) {
char ethaddr[18];
--
1.6.0.2
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[U-Boot] [PATCH 1/9 v2] MPC85xx: Add QE clk support for mpc85xx platforms
Signed-off-by: Haiying Wang haiying.w...@freescale.com
Acked-by: Timur Tabi ti...@freescale.com
---
v2 change: Fix the indention issue pointed by Scott, and add Acked-by.
cpu/mpc85xx/cpu.c|4
cpu/mpc85xx/speed.c | 13 +
include/asm-ppc/immap_85xx.h |2 ++
include/e500.h |1 +
4 files changed, 20 insertions(+), 0 deletions(-)
diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c
index ef976a4..b812d88 100644
--- a/cpu/mpc85xx/cpu.c
+++ b/cpu/mpc85xx/cpu.c
@@ -184,6 +184,10 @@ int checkcpu (void)
printf(CPM: %s MHz\n, strmhz(buf1, sysinfo.freqSystemBus));
#endif
+#ifdef CONFIG_QE
+ printf( QE:%-4s MHz\n, strmhz(buf1, sysinfo.freqQE));
+#endif
+
puts(L1:D-cache 32 kB enabled\n I-cache 32 kB enabled\n);
return 0;
diff --git a/cpu/mpc85xx/speed.c b/cpu/mpc85xx/speed.c
index b0f47e0..16dbe76 100644
--- a/cpu/mpc85xx/speed.c
+++ b/cpu/mpc85xx/speed.c
@@ -40,6 +40,9 @@ void get_sys_info (sys_info_t * sysInfo)
uint plat_ratio,e500_ratio,half_freqSystemBus;
uint lcrr_div;
int i;
+#ifdef CONFIG_QE
+ u32 qe_ratio;
+#endif
plat_ratio = (gur-porpllsr) 0x003e;
plat_ratio = 1;
@@ -65,6 +68,12 @@ void get_sys_info (sys_info_t * sysInfo)
}
#endif
+#ifdef CONFIG_QE
+ qe_ratio = ((gur-porpllsr) MPC85xx_PORPLLSR_QE_RATIO)
+MPC85xx_PORPLLSR_QE_RATIO_SHIFT;
+ sysInfo-freqQE = qe_ratio * CONFIG_SYS_CLK_FREQ;
+#endif
+
#if defined(CONFIG_SYS_LBC_LCRR)
/* We will program LCRR to this value later */
lcrr_div = CONFIG_SYS_LBC_LCRR LCRR_CLKDIV;
@@ -112,6 +121,10 @@ int get_clocks (void)
gd-mem_clk = sys_info.freqDDRBus;
gd-lbc_clk = sys_info.freqLocalBus;
+#ifdef CONFIG_QE
+ gd-qe_clk = sys_info.freqQE;
+ gd-brg_clk = gd-qe_clk / 2;
+#endif
/*
* The base clock for I2C depends on the actual SOC. Unfortunately,
* there is no pattern that can be used to determine the frequency, so
diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h
index 0810b8e..a4d25cd 100644
--- a/include/asm-ppc/immap_85xx.h
+++ b/include/asm-ppc/immap_85xx.h
@@ -1581,6 +1581,8 @@ typedef struct ccsr_gur {
#define MPC85xx_PORPLLSR_DDR_RATIO 0x3e00
#define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT 9
#endif
+#define MPC85xx_PORPLLSR_QE_RATIO 0x3e00
+#define MPC85xx_PORPLLSR_QE_RATIO_SHIFT25
uintporbmsr;/* 0xe0004 - POR boot mode status register */
#define MPC85xx_PORBMSR_HA 0x0007
uintporimpscr; /* 0xe0008 - POR I/O impedance status and
control register */
diff --git a/include/e500.h b/include/e500.h
index 4c5eeb7..84b580d 100644
--- a/include/e500.h
+++ b/include/e500.h
@@ -18,6 +18,7 @@ typedef struct
unsigned long freqSystemBus;
unsigned long freqDDRBus;
unsigned long freqLocalBus;
+ unsigned long freqQE;
} MPC85xx_SYS_INFO;
#endif /* _ASMLANGUAGE */
--
1.6.0.2
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[U-Boot] [PATCH 2/9] MPC85xx: Change QE RISC ALLOCATION to support 4 RISCs
Also define the QE_RISC_ALLOCATION_RISCs to MACROs instead of using enum, and
define MAX_QE_RISC for QE based silicons.
Signed-off-by: Haiying Wang haiying.w...@freescale.com
---
drivers/qe/qe.c|3 ---
drivers/qe/qe.h| 15 ++-
drivers/qe/uec.c | 30 ++
drivers/qe/uec.h |4 ++--
include/asm-ppc/immap_qe.h |8
5 files changed, 50 insertions(+), 10 deletions(-)
diff --git a/drivers/qe/qe.c b/drivers/qe/qe.c
index ea5a14b..a8e9399 100644
--- a/drivers/qe/qe.c
+++ b/drivers/qe/qe.c
@@ -257,9 +257,6 @@ int qe_set_mii_clk_src(int ucc_num)
return 0;
}
-/* The maximum number of RISCs we support */
-#define MAX_QE_RISC 2
-
/* Firmware information stored here for qe_get_firmware_info() */
static struct qe_firmware_info qe_firmware_info;
diff --git a/drivers/qe/qe.h b/drivers/qe/qe.h
index d78edba..1eb0a74 100644
--- a/drivers/qe/qe.h
+++ b/drivers/qe/qe.h
@@ -46,11 +46,16 @@ typedef struct qe_snum {
/* QE RISC allocation
*/
-typedef enum qe_risc_allocation {
- QE_RISC_ALLOCATION_RISC1= 1, /* RISC 1 */
- QE_RISC_ALLOCATION_RISC2= 2, /* RISC 2 */
- QE_RISC_ALLOCATION_RISC1_AND_RISC2 = 3 /* RISC 1 or RISC 2 */
-} qe_risc_allocation_e;
+#defineQE_RISC_ALLOCATION_RISC10x1 /* RISC 1 */
+#defineQE_RISC_ALLOCATION_RISC20x2 /* RISC 2 */
+#defineQE_RISC_ALLOCATION_RISC30x4 /* RISC 3 */
+#defineQE_RISC_ALLOCATION_RISC40x8 /* RISC 4 */
+#defineQE_RISC_ALLOCATION_RISC1_AND_RISC2
(QE_RISC_ALLOCATION_RISC1 | \
+QE_RISC_ALLOCATION_RISC2)
+#defineQE_RISC_ALLOCATION_FOUR_RISCS (QE_RISC_ALLOCATION_RISC1 | \
+QE_RISC_ALLOCATION_RISC2 | \
+QE_RISC_ALLOCATION_RISC3 | \
+QE_RISC_ALLOCATION_RISC4)
/* QE CECR commands for UCC fast.
*/
diff --git a/drivers/qe/uec.c b/drivers/qe/uec.c
index bba3ef2..119e3d3 100644
--- a/drivers/qe/uec.c
+++ b/drivers/qe/uec.c
@@ -46,8 +46,13 @@ static uec_info_t eth1_uec_info = {
.num_threads_tx = UEC_NUM_OF_THREADS_4,
.num_threads_rx = UEC_NUM_OF_THREADS_4,
#endif
+#if (MAX_QE_RISC == 4)
+ .riscTx = QE_RISC_ALLOCATION_FOUR_RISCS,
+ .riscRx = QE_RISC_ALLOCATION_FOUR_RISCS,
+#else
.riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
.riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
+#endif
.tx_bd_ring_len = 16,
.rx_bd_ring_len = 16,
.phy_address= CONFIG_SYS_UEC1_PHY_ADDR,
@@ -69,8 +74,13 @@ static uec_info_t eth2_uec_info = {
.num_threads_tx = UEC_NUM_OF_THREADS_4,
.num_threads_rx = UEC_NUM_OF_THREADS_4,
#endif
+#if (MAX_QE_RISC == 4)
+ .riscTx = QE_RISC_ALLOCATION_FOUR_RISCS,
+ .riscRx = QE_RISC_ALLOCATION_FOUR_RISCS,
+#else
.riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
.riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
+#endif
.tx_bd_ring_len = 16,
.rx_bd_ring_len = 16,
.phy_address= CONFIG_SYS_UEC2_PHY_ADDR,
@@ -92,8 +102,13 @@ static uec_info_t eth3_uec_info = {
.num_threads_tx = UEC_NUM_OF_THREADS_4,
.num_threads_rx = UEC_NUM_OF_THREADS_4,
#endif
+#if (MAX_QE_RISC == 4)
+ .riscTx = QE_RISC_ALLOCATION_FOUR_RISCS,
+ .riscRx = QE_RISC_ALLOCATION_FOUR_RISCS,
+#else
.riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
.riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
+#endif
.tx_bd_ring_len = 16,
.rx_bd_ring_len = 16,
.phy_address= CONFIG_SYS_UEC3_PHY_ADDR,
@@ -115,8 +130,13 @@ static uec_info_t eth4_uec_info = {
.num_threads_tx = UEC_NUM_OF_THREADS_4,
.num_threads_rx = UEC_NUM_OF_THREADS_4,
#endif
+#if (MAX_QE_RISC == 4)
+ .riscTx = QE_RISC_ALLOCATION_FOUR_RISCS,
+ .riscRx = QE_RISC_ALLOCATION_FOUR_RISCS,
+#else
.riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
.riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
+#endif
.tx_bd_ring_len = 16,
.rx_bd_ring_len = 16,
.phy_address= CONFIG_SYS_UEC4_PHY_ADDR,
@@ -138,8 +158,13 @@ static uec_info_t eth5_uec_info = {
.num_threads_tx = UEC_NUM_OF_THREADS_4,
.num_threads_rx = UEC_NUM_OF_THREADS_4,
#endif
+#if (MAX_QE_RISC == 4)
+ .riscTx = QE_RISC_ALLOCATION_FOUR_RISCS,
+ .riscRx
[U-Boot] [PATCH 5/9] MPC85xx: Increase the size of malloc for MPC8569MDS board
MPC8569MDS board needs more memory for malloc because it will support four Ethernet interfaces. Signed-off-by: Haiying Wang haiying.w...@freescale.com --- include/configs/MPC8569MDS.h |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h index 2cba98f..b7296f5 100644 --- a/include/configs/MPC8569MDS.h +++ b/include/configs/MPC8569MDS.h @@ -202,7 +202,7 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET #define CONFIG_SYS_MONITOR_LEN (256 * 1024)/* Reserve 256 kB for Mon */ -#define CONFIG_SYS_MALLOC_LEN (128 * 1024)/* Reserved for malloc */ +#define CONFIG_SYS_MALLOC_LEN (256 * 1024)/* Reserved for malloc */ /* Serial Port */ #define CONFIG_CONS_INDEX 1 -- 1.6.0.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 4/9] MPC85xx: Add PIB support at CS4/CS5 for MPC8569MDS board
Signed-off-by: Haiying Wang haiying.w...@freescale.com Signed-off-by: Yu Liu yu@freescale.com --- include/configs/MPC8569MDS.h | 10 +- 1 files changed, 9 insertions(+), 1 deletions(-) diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h index b0af5dc..2cba98f 100644 --- a/include/configs/MPC8569MDS.h +++ b/include/configs/MPC8569MDS.h @@ -156,10 +156,18 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_BR0_PRELIM 0xfe000801 #defineCONFIG_SYS_OR0_PRELIM 0xfe000ff7 -/*Chip slelect 1 - BCSR*/ +/*Chip select 1 - BCSR*/ #define CONFIG_SYS_BR1_PRELIM 0xf8000801 #defineCONFIG_SYS_OR1_PRELIM 0xe9f7 +/*Chip select 4 - PIB*/ +#define CONFIG_SYS_BR4_PRELIM 0xf8008801 +#define CONFIG_SYS_OR4_PRELIM 0xe9f7 + +/*Chip select 5 - PIB*/ +#define CONFIG_SYS_BR5_PRELIM 0xf8010801 +#define CONFIG_SYS_OR5_PRELIM 0xe9f7 + #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */ #undef CONFIG_SYS_FLASH_CHECKSUM -- 1.6.0.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/9] MPC85xx: Add QE clk support for mpc85xx platforms
Signed-off-by: Haiying Wang haiying.w...@freescale.com
---
cpu/mpc85xx/cpu.c|4
cpu/mpc85xx/speed.c | 13 +
include/asm-ppc/immap_85xx.h |2 ++
include/e500.h |1 +
4 files changed, 20 insertions(+), 0 deletions(-)
diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c
index ef976a4..b812d88 100644
--- a/cpu/mpc85xx/cpu.c
+++ b/cpu/mpc85xx/cpu.c
@@ -184,6 +184,10 @@ int checkcpu (void)
printf(CPM: %s MHz\n, strmhz(buf1, sysinfo.freqSystemBus));
#endif
+#ifdef CONFIG_QE
+ printf( QE:%-4s MHz\n, strmhz(buf1, sysinfo.freqQE));
+#endif
+
puts(L1:D-cache 32 kB enabled\n I-cache 32 kB enabled\n);
return 0;
diff --git a/cpu/mpc85xx/speed.c b/cpu/mpc85xx/speed.c
index b0f47e0..16dbe76 100644
--- a/cpu/mpc85xx/speed.c
+++ b/cpu/mpc85xx/speed.c
@@ -40,6 +40,9 @@ void get_sys_info (sys_info_t * sysInfo)
uint plat_ratio,e500_ratio,half_freqSystemBus;
uint lcrr_div;
int i;
+#ifdef CONFIG_QE
+ u32 qe_ratio;
+#endif
plat_ratio = (gur-porpllsr) 0x003e;
plat_ratio = 1;
@@ -65,6 +68,12 @@ void get_sys_info (sys_info_t * sysInfo)
}
#endif
+#ifdef CONFIG_QE
+ qe_ratio = ((gur-porpllsr) MPC85xx_PORPLLSR_QE_RATIO)
+MPC85xx_PORPLLSR_QE_RATIO_SHIFT;
+ sysInfo-freqQE = qe_ratio * CONFIG_SYS_CLK_FREQ;
+#endif
+
#if defined(CONFIG_SYS_LBC_LCRR)
/* We will program LCRR to this value later */
lcrr_div = CONFIG_SYS_LBC_LCRR LCRR_CLKDIV;
@@ -112,6 +121,10 @@ int get_clocks (void)
gd-mem_clk = sys_info.freqDDRBus;
gd-lbc_clk = sys_info.freqLocalBus;
+#ifdef CONFIG_QE
+ gd-qe_clk = sys_info.freqQE;
+ gd-brg_clk = gd-qe_clk / 2;
+#endif
/*
* The base clock for I2C depends on the actual SOC. Unfortunately,
* there is no pattern that can be used to determine the frequency, so
diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h
index 0810b8e..a4d25cd 100644
--- a/include/asm-ppc/immap_85xx.h
+++ b/include/asm-ppc/immap_85xx.h
@@ -1581,6 +1581,8 @@ typedef struct ccsr_gur {
#define MPC85xx_PORPLLSR_DDR_RATIO 0x3e00
#define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT 9
#endif
+#define MPC85xx_PORPLLSR_QE_RATIO 0x3e00
+#define MPC85xx_PORPLLSR_QE_RATIO_SHIFT25
uintporbmsr;/* 0xe0004 - POR boot mode status register */
#define MPC85xx_PORBMSR_HA 0x0007
uintporimpscr; /* 0xe0008 - POR I/O impedance status and
control register */
diff --git a/include/e500.h b/include/e500.h
index 4c5eeb7..84b580d 100644
--- a/include/e500.h
+++ b/include/e500.h
@@ -18,6 +18,7 @@ typedef struct
unsigned long freqSystemBus;
unsigned long freqDDRBus;
unsigned long freqLocalBus;
+ unsigned long freqQE;
} MPC85xx_SYS_INFO;
#endif /* _ASMLANGUAGE */
--
1.6.0.2
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[U-Boot] [PATCH 7/9] MPC85xx: Add UEC3 and UEC4 support for MPC8569MDS board
Signed-off-by: Haiying Wang haiying.w...@freescale.com
---
board/freescale/mpc8569mds/bcsr.c |4
board/freescale/mpc8569mds/mpc8569mds.c | 30 ++
include/configs/MPC8569MDS.h| 23 +++
3 files changed, 57 insertions(+), 0 deletions(-)
diff --git a/board/freescale/mpc8569mds/bcsr.c
b/board/freescale/mpc8569mds/bcsr.c
index 5adffc2..f133732 100644
--- a/board/freescale/mpc8569mds/bcsr.c
+++ b/board/freescale/mpc8569mds/bcsr.c
@@ -41,6 +41,10 @@ void enable_8569mds_qe_mdio()
BCSR7_UCC1_GETH_EN | BCSR7_UCC1_RGMII_EN);
setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 8),
BCSR8_UCC2_GETH_EN | BCSR8_UCC2_RGMII_EN);
+ setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 9),
+ BCSR9_UCC3_GETH_EN | BCSR9_UCC3_RGMII_EN);
+ setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 10),
+ BCSR10_UCC4_GETH_EN | BCSR10_UCC4_RGMII_EN);
}
void disable_8569mds_brd_eeprom_write_protect()
diff --git a/board/freescale/mpc8569mds/mpc8569mds.c
b/board/freescale/mpc8569mds/mpc8569mds.c
index cb56106..c72fbcf 100644
--- a/board/freescale/mpc8569mds/mpc8569mds.c
+++ b/board/freescale/mpc8569mds/mpc8569mds.c
@@ -77,6 +77,36 @@ const qe_iop_conf_t qe_iop_conf_tab[] = {
{2, 3, 2, 0, 1}, /* ENET2_GRXCLK */
{2, 2, 1, 0, 2}, /* ENET2_GTXCLK */
+ /* UCC_3_RGMII */
+ {2, 11, 2, 0, 1}, /* CLK12 */
+ {0, 29, 1, 0, 2}, /* ENET3_TXD0_SER3_TXD0 */
+ {0, 30, 1, 0, 3}, /* ENET3_TXD1_SER3_TXD1 */
+ {0, 31, 1, 0, 2}, /* ENET3_TXD2_SER3_TXD2 */
+ {1, 0, 1, 0, 3}, /* ENET3_TXD3_SER3_TXD3 */
+ {1, 3, 2, 0, 3}, /* ENET3_RXD0_SER3_RXD0 */
+ {1, 4, 2, 0, 1}, /* ENET3_RXD1_SER3_RXD1 */
+ {1, 5, 2, 0, 2}, /* ENET3_RXD2_SER3_RXD2 */
+ {1, 6, 2, 0, 3}, /* ENET3_RXD3_SER3_RXD3 */
+ {1, 1, 1, 0, 1}, /* ENET3_TX_EN_SER3_RTS_B*/
+ {1, 9, 2, 0, 3}, /* ENET3_RX_DV_SER3_CTS_B*/
+ {2, 9, 2, 0, 2}, /* ENET3_GRXCLK */
+ {2, 25, 1, 0, 2}, /* ENET3_GTXCLK */
+
+ /* UCC_4_RGMII */
+ {2, 16, 2, 0, 3}, /* CLK17 */
+ {1, 12, 1, 0, 2}, /* ENET4_TXD0_SER4_TXD0 */
+ {1, 13, 1, 0, 2}, /* ENET4_TXD1_SER4_TXD1 */
+ {1, 14, 1, 0, 1}, /* ENET4_TXD2_SER4_TXD2 */
+ {1, 15, 1, 0, 2}, /* ENET4_TXD3_SER4_TXD3 */
+ {1, 18, 2, 0, 2}, /* ENET4_RXD0_SER4_RXD0 */
+ {1, 19, 2, 0, 1}, /* ENET4_RXD1_SER4_RXD1 */
+ {1, 20, 2, 0, 1}, /* ENET4_RXD2_SER4_RXD2 */
+ {1, 21, 2, 0, 2}, /* ENET4_RXD3_SER4_RXD3 */
+ {1, 16, 1, 0, 2}, /* ENET4_TX_EN_SER4_RTS_B*/
+ {1, 24, 2, 0, 3}, /* ENET4_RX_DV_SER4_CTS_B*/
+ {2, 17, 2, 0, 2}, /* ENET4_GRXCLK */
+ {2, 24, 1, 0, 2}, /* ENET4_GTXCLK */
+
/* UART1 is muxed with QE PortF bit [9-12].*/
{5, 12, 2, 0, 3}, /* UART1_SIN */
{5, 9, 1, 0, 3}, /* UART1_SOUT */
diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h
index b7296f5..cef44a6 100644
--- a/include/configs/MPC8569MDS.h
+++ b/include/configs/MPC8569MDS.h
@@ -313,6 +313,29 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_SYS_UEC2_INTERFACE_MODE ENET_1000_RGMII_ID
#endif
+#define CONFIG_UEC_ETH3 /* GETH3 */
+#define CONFIG_HAS_ETH2
+
+#ifdef CONFIG_UEC_ETH3
+#define CONFIG_SYS_UEC3_UCC_NUM2 /* UCC3 */
+#define CONFIG_SYS_UEC3_RX_CLK QE_CLK_NONE
+#define CONFIG_SYS_UEC3_TX_CLK QE_CLK12
+#define CONFIG_SYS_UEC3_ETH_TYPE GIGA_ETH
+#define CONFIG_SYS_UEC3_PHY_ADDR 2
+#define CONFIG_SYS_UEC3_INTERFACE_MODE ENET_1000_RGMII_ID
+#endif
+
+#define CONFIG_UEC_ETH4 /* GETH4 */
+#define CONFIG_HAS_ETH3
+
+#ifdef CONFIG_UEC_ETH4
+#define CONFIG_SYS_UEC4_UCC_NUM3 /* UCC4 */
+#define CONFIG_SYS_UEC4_RX_CLK QE_CLK_NONE
+#define CONFIG_SYS_UEC4_TX_CLK QE_CLK17
+#define CONFIG_SYS_UEC4_ETH_TYPE GIGA_ETH
+#define CONFIG_SYS_UEC4_PHY_ADDR 3
+#define CONFIG_SYS_UEC4_INTERFACE_MODE ENET_1000_RGMII_ID
+#endif
#endif /* CONFIG_QE */
#if defined(CONFIG_PCI)
--
1.6.0.2
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[U-Boot] [PATCH 6/9] MPC85xx: Add UART1 support for MPC8569MDS board
MPC8569 UART1 signals are muxed with PortF bit[9-12], we need to define
those pins before using UART1.
Signed-off-by: Haiying Wang haiying.w...@freescale.com
---
board/freescale/mpc8569mds/mpc8569mds.c |6 ++
1 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/board/freescale/mpc8569mds/mpc8569mds.c
b/board/freescale/mpc8569mds/mpc8569mds.c
index 53fef43..cb56106 100644
--- a/board/freescale/mpc8569mds/mpc8569mds.c
+++ b/board/freescale/mpc8569mds/mpc8569mds.c
@@ -77,6 +77,12 @@ const qe_iop_conf_t qe_iop_conf_tab[] = {
{2, 3, 2, 0, 1}, /* ENET2_GRXCLK */
{2, 2, 1, 0, 2}, /* ENET2_GTXCLK */
+ /* UART1 is muxed with QE PortF bit [9-12].*/
+ {5, 12, 2, 0, 3}, /* UART1_SIN */
+ {5, 9, 1, 0, 3}, /* UART1_SOUT */
+ {5, 10, 2, 0, 3}, /* UART1_CTS_B */
+ {5, 11, 1, 0, 2}, /* UART1_RTS_B */
+
{0, 0, 0, 0, QE_IOP_TAB_END} /* END of table */
};
--
1.6.0.2
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[U-Boot] [PATCH 3/9] MPC85xx: Set the correct MURAM size for MPC8569
MPC8569 has 128K bytes MURAM.
Signed-off-by: Haiying Wang haiying.w...@freescale.com
---
include/asm-ppc/immap_qe.h |9 +++--
1 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/include/asm-ppc/immap_qe.h b/include/asm-ppc/immap_qe.h
index 9530b29..7613b5c 100644
--- a/include/asm-ppc/immap_qe.h
+++ b/include/asm-ppc/immap_qe.h
@@ -582,9 +582,12 @@ typedef struct qe_immap {
u8 res14[0x300];
u8 res15[0x3A00];
u8 res16[0x8000]; /* 0x108000 - 0x11 */
-#if defined(CONFIG_MPC8568)||defined(CONFIG_MPC8569)
+#if defined(CONFIG_MPC8568)
u8 muram[0x1]; /* 0x1_ - 0x2_ Multi-user RAM */
u8 res17[0x2]; /* 0x2_ - 0x4_ */
+#elif defined(CONFIG_MPC8569)
+ u8 muram[0x2]; /* 0x1_ - 0x3_ Multi-user RAM */
+ u8 res17[0x1]; /* 0x3_ - 0x4_ */
#else
u8 muram[0xC000]; /* 0x11 - 0x11C000 Multi-user RAM */
u8 res17[0x24000]; /* 0x11C000 - 0x14 */
@@ -594,8 +597,10 @@ typedef struct qe_immap {
extern qe_map_t *qe_immr;
-#if defined(CONFIG_MPC8568) || defined(CONFIG_MPC8569)
+#if defined(CONFIG_MPC8568)
#define QE_MURAM_SIZE 0x1UL
+#elif defined(CONFIG_MPC8569)
+#define QE_MURAM_SIZE 0x2UL
#elif defined(CONFIG_MPC8360)
#define QE_MURAM_SIZE 0xc000UL
#elif defined(CONFIG_MPC832X)
--
1.6.0.2
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[U-Boot] [PATCH 8/9] MPC85xx: Add RMII support for MPC8569MDS board
This patch supports UCC working at RMII mode on PIB board, fixup fdt blob to
support rmii in kernel. It also changes the name of enable_mpc8569mds_qe_mdio to
enalbe_mpc8569mds_qe_uec which is more accurate.
Signed-off-by: Haiying Wang haiying.w...@freescale.com
---
board/freescale/mpc8569mds/bcsr.c | 15 +-
board/freescale/mpc8569mds/bcsr.h |2 +-
board/freescale/mpc8569mds/mpc8569mds.c | 96 ++-
include/configs/MPC8569MDS.h| 38 +++-
4 files changed, 144 insertions(+), 7 deletions(-)
diff --git a/board/freescale/mpc8569mds/bcsr.c
b/board/freescale/mpc8569mds/bcsr.c
index f133732..b895b4e 100644
--- a/board/freescale/mpc8569mds/bcsr.c
+++ b/board/freescale/mpc8569mds/bcsr.c
@@ -35,8 +35,9 @@ void disable_8569mds_flash_write()
clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 17), BCSR17_FLASH_nWP);
}
-void enable_8569mds_qe_mdio()
+void enable_8569mds_qe_uec()
{
+#if defined(CONFIG_SYS_UCC_RGMII_MODE)
setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 7),
BCSR7_UCC1_GETH_EN | BCSR7_UCC1_RGMII_EN);
setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 8),
@@ -45,6 +46,18 @@ void enable_8569mds_qe_mdio()
BCSR9_UCC3_GETH_EN | BCSR9_UCC3_RGMII_EN);
setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 10),
BCSR10_UCC4_GETH_EN | BCSR10_UCC4_RGMII_EN);
+#elif defined(CONFIG_SYS_UCC_RMII_MODE)
+ /* Set UCC1-4 working at RMII mode */
+ clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 7),
+ BCSR7_UCC1_GETH_EN | BCSR7_UCC1_RGMII_EN);
+ clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 8),
+ BCSR8_UCC2_GETH_EN | BCSR8_UCC2_RGMII_EN);
+ clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 9),
+ BCSR9_UCC3_GETH_EN | BCSR9_UCC3_RGMII_EN);
+ clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 10),
+ BCSR10_UCC4_GETH_EN | BCSR10_UCC4_RGMII_EN);
+ setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 9), BCSR9_UCC3_RMII_EN);
+#endif
}
void disable_8569mds_brd_eeprom_write_protect()
diff --git a/board/freescale/mpc8569mds/bcsr.h
b/board/freescale/mpc8569mds/bcsr.h
index 8efe9bd..e5d63c7 100644
--- a/board/freescale/mpc8569mds/bcsr.h
+++ b/board/freescale/mpc8569mds/bcsr.h
@@ -76,7 +76,7 @@
void enable_8569mds_flash_write(void);
void disable_8569mds_flash_write(void);
-void enable_8569mds_qe_mdio(void);
+void enable_8569mds_qe_uec(void);
void disable_8569mds_brd_eeprom_write_protect(void);
#endif /* __BCSR_H_ */
diff --git a/board/freescale/mpc8569mds/mpc8569mds.c
b/board/freescale/mpc8569mds/mpc8569mds.c
index c72fbcf..4e4ec1a 100644
--- a/board/freescale/mpc8569mds/mpc8569mds.c
+++ b/board/freescale/mpc8569mds/mpc8569mds.c
@@ -47,6 +47,7 @@ const qe_iop_conf_t qe_iop_conf_tab[] = {
/* QE_MUX_MDIO */
{2, 30, 3, 0, 2}, /* QE_MUX_MDIO */
+#if defined(CONFIG_SYS_UCC_RGMII_MODE)
/* UCC_1_RGMII */
{2, 11, 2, 0, 1}, /* CLK12 */
{0, 0, 1, 0, 3}, /* ENET1_TXD0_SER1_TXD0 */
@@ -107,6 +108,44 @@ const qe_iop_conf_t qe_iop_conf_tab[] = {
{2, 17, 2, 0, 2}, /* ENET4_GRXCLK */
{2, 24, 1, 0, 2}, /* ENET4_GTXCLK */
+#elif defined(CONFIG_SYS_UCC_RMII_MODE)
+ /* UCC_1_RMII */
+ {2, 15, 2, 0, 1}, /* CLK16 */
+ {0, 0, 1, 0, 3}, /* ENET1_TXD0_SER1_TXD0 */
+ {0, 1, 1, 0, 3}, /* ENET1_TXD1_SER1_TXD1 */
+ {0, 6, 2, 0, 3}, /* ENET1_RXD0_SER1_RXD0 */
+ {0, 7, 2, 0, 1}, /* ENET1_RXD1_SER1_RXD1 */
+ {0, 4, 1, 0, 2}, /* ENET1_TX_EN_SER1_RTS_B*/
+ {0, 12, 2, 0, 3}, /* ENET1_RX_DV_SER1_CTS_B*/
+
+ /* UCC_2_RMII */
+ {2, 15, 2, 0, 1}, /* CLK16 */
+ {0, 14, 1, 0, 2}, /* ENET2_TXD0_SER2_TXD0 */
+ {0, 15, 1, 0, 2}, /* ENET2_TXD1_SER2_TXD1 */
+ {0, 20, 2, 0, 2}, /* ENET2_RXD0_SER2_RXD0 */
+ {0, 21, 2, 0, 1}, /* ENET2_RXD1_SER2_RXD1 */
+ {0, 18, 1, 0, 2}, /* ENET2_TX_EN_SER2_RTS_B*/
+ {0, 26, 2, 0, 3}, /* ENET2_RX_DV_SER2_CTS_B*/
+
+ /* UCC_3_RMII */
+ {2, 15, 2, 0, 1}, /* CLK16 */
+ {0, 29, 1, 0, 2}, /* ENET3_TXD0_SER3_TXD0 */
+ {0, 30, 1, 0, 3}, /* ENET3_TXD1_SER3_TXD1 */
+ {1, 3, 2, 0, 3}, /* ENET3_RXD0_SER3_RXD0 */
+ {1, 4, 2, 0, 1}, /* ENET3_RXD1_SER3_RXD1 */
+ {1, 1, 1, 0, 1}, /* ENET3_TX_EN_SER3_RTS_B*/
+ {1, 9, 2, 0, 3}, /* ENET3_RX_DV_SER3_CTS_B*/
+
+ /* UCC_4_RMII */
+ {2, 15, 2, 0, 1}, /* CLK16 */
+ {1, 12, 1, 0, 2}, /* ENET4_TXD0_SER4_TXD0 */
+ {1, 13, 1, 0, 2}, /* ENET4_TXD1_SER4_TXD1 */
+ {1, 18, 2, 0, 2}, /* ENET4_RXD0_SER4_RXD0 */
+ {1, 19, 2, 0, 1}, /* ENET4_RXD1_SER4_RXD1 */
+ {1, 16, 1, 0, 2}, /* ENET4_TX_EN_SER4_RTS_B*/
+ {1, 24, 2, 0, 3}, /* ENET4_RX_DV_SER4_CTS_B*/
+#endif
+
/* UART1 is muxed with QE
[U-Boot] [PATCH 9/9] MPC85xx: Add more SNUM number for QE
Some QE chips like 8569 need more SNUM numbers for supporting 4 UECs in RGMII-
1000 mode.
Signed-off-by: Haiying Wang haiying.w...@freescale.com
---
drivers/qe/qe.c| 13 +++--
drivers/qe/qe.h|1 -
include/asm-ppc/immap_qe.h |3 +++
3 files changed, 14 insertions(+), 3 deletions(-)
diff --git a/drivers/qe/qe.c b/drivers/qe/qe.c
index a8e9399..6232c85 100644
--- a/drivers/qe/qe.c
+++ b/drivers/qe/qe.c
@@ -108,14 +108,23 @@ static void qe_sdma_init(void)
out_be32(p-sdmr, QE_SDMR_GLB_1_MSK | (0x3 QE_SDMR_CEN_SHIFT));
}
-static u8 thread_snum[QE_NUM_OF_SNUM] = {
+/* This table is a list of the serial numbers of the Threads, taken from the
+ * SNUM Table chart in the QE Reference Manual. The order is not important,
+ * we just need to know what the SNUMs are for the threads.
+ */
+static u8 thread_snum[] = {
0x04, 0x05, 0x0c, 0x0d,
0x14, 0x15, 0x1c, 0x1d,
0x24, 0x25, 0x2c, 0x2d,
0x34, 0x35, 0x88, 0x89,
0x98, 0x99, 0xa8, 0xa9,
0xb8, 0xb9, 0xc8, 0xc9,
- 0xd8, 0xd9, 0xe8, 0xe9
+ 0xd8, 0xd9, 0xe8, 0xe9,
+ 0x08, 0x09, 0x18, 0x19,
+ 0x28, 0x29, 0x38, 0x39,
+ 0x48, 0x49, 0x58, 0x59,
+ 0x68, 0x69, 0x78, 0x79,
+ 0x80, 0x81
};
static void qe_snums_init(void)
diff --git a/drivers/qe/qe.h b/drivers/qe/qe.h
index 1eb0a74..d4ccec0 100644
--- a/drivers/qe/qe.h
+++ b/drivers/qe/qe.h
@@ -25,7 +25,6 @@
#include common.h
-#define QE_NUM_OF_SNUM 28
#define QE_NUM_OF_BRGS 16
#define UCC_MAX_NUM8
diff --git a/include/asm-ppc/immap_qe.h b/include/asm-ppc/immap_qe.h
index 7613b5c..1446734 100644
--- a/include/asm-ppc/immap_qe.h
+++ b/include/asm-ppc/immap_qe.h
@@ -609,10 +609,13 @@ extern qe_map_t *qe_immr;
#if defined(CONFIG_MPC8323)
#define MAX_QE_RISC 1
+#define QE_NUM_OF_SNUM 28
#elif defined(CONFIG_MPC8569)
#define MAX_QE_RISC 4
+#define QE_NUM_OF_SNUM 46
#else
#define MAX_QE_RISC2
+#define QE_NUM_OF_SNUM 28
#endif
#endif /* __IMMAP_QE_H__ */
--
1.6.0.2
___
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